arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #ifdef CONFIG_ACPI
  34 #include <acpi/acpi_bus.h>
  35 #endif
  36
  37 #include <asm/io.h>
  38 #include <asm/smp.h>
  39 #include <asm/desc.h>
  40 #include <asm/proto.h>
  41 #include <asm/mach_apic.h>
  42 #include <asm/acpi.h>
  43 #include <asm/dma.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 /*
  62  * # of IRQ routing registers
  63  */
  64 int nr_ioapic_registers[MAX_IO_APICS];
  65
  66 /*
  67  * Rough estimation of how many shared IRQs there are, can
  68  * be changed anytime.
  69  */
  70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  72
  73 /*
  74  * This is performance-critical, we want to do it O(1)
  75  *
  76  * the indexing order of this array favors 1:1 mappings
  77  * between pins and IRQs.
  78  */
  79
  80 static struct irq_pin_list {
  81         short apic, pin, next;
  82 } irq_2_pin[PIN_MAP_SIZE];
  83
  84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  85 #ifdef CONFIG_PCI_MSI
  86 #define vector_to_irq(vector)   \
  87         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  88 #else
  89 #define vector_to_irq(vector)   (vector)
  90 #endif
  91
  92 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  93                                                                         \
  94 {                                                                       \
  95         int pin;                                                        \
  96         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  97                                                                         \
  98         BUG_ON(irq >= NR_IRQS);                                         \
  99         for (;;) {                                                      \
 100                 unsigned int reg;                                       \
 101                 pin = entry->pin;                                       \
 102                 if (pin == -1)                                          \
 103                         break;                                          \
 104                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 105                 reg ACTION;                                             \
 106                 io_apic_modify(entry->apic, reg);                       \
 107                 if (!entry->next)                                       \
 108                         break;                                          \
 109                 entry = irq_2_pin + entry->next;                        \
 110         }                                                               \
 111         FINAL;                                                          \
 112 }
 113
 114 #ifdef CONFIG_SMP
 115 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 116 {
 117         unsigned long flags;
 118         unsigned int dest;
 119         cpumask_t tmp;
 120
 121         cpus_and(tmp, mask, cpu_online_map);
 122         if (cpus_empty(tmp))
 123                 tmp = TARGET_CPUS;
 124
 125         cpus_and(mask, tmp, CPU_MASK_ALL);
 126
 127         dest = cpu_mask_to_apicid(mask);
 128
 129         /*
 130          * Only the high 8 bits are valid.
 131          */
 132         dest = SET_APIC_LOGICAL_ID(dest);
 133
 134         spin_lock_irqsave(&ioapic_lock, flags);
 135         __DO_ACTION(1, = dest, )
 136         set_irq_info(irq, mask);
 137         spin_unlock_irqrestore(&ioapic_lock, flags);
 138 }
 139 #endif
 140
 141 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 142
 143 /*
 144  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 145  * shared ISA-space IRQs, so we have to support them. We are super
 146  * fast in the common case, and fast for shared ISA-space IRQs.
 147  */
 148 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 149 {
 150         static int first_free_entry = NR_IRQS;
 151         struct irq_pin_list *entry = irq_2_pin + irq;
 152
 153         BUG_ON(irq >= NR_IRQS);
 154         while (entry->next)
 155                 entry = irq_2_pin + entry->next;
 156
 157         if (entry->pin != -1) {
 158                 entry->next = first_free_entry;
 159                 entry = irq_2_pin + entry->next;
 160                 if (++first_free_entry >= PIN_MAP_SIZE)
 161                         panic("io_apic.c: ran out of irq_2_pin entries!");
 162         }
 163         entry->apic = apic;
 164         entry->pin = pin;
 165 }
 166
 167
 168 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 169                                                                         \
 170         static void name##_IO_APIC_irq (unsigned int irq)               \
 171         __DO_ACTION(R, ACTION, FINAL)
 172
 173 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 174                                                 /* mask = 1 */
 175 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 176                                                 /* mask = 0 */
 177
 178 static void mask_IO_APIC_irq (unsigned int irq)
 179 {
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&ioapic_lock, flags);
 183         __mask_IO_APIC_irq(irq);
 184         spin_unlock_irqrestore(&ioapic_lock, flags);
 185 }
 186
 187 static void unmask_IO_APIC_irq (unsigned int irq)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&ioapic_lock, flags);
 192         __unmask_IO_APIC_irq(irq);
 193         spin_unlock_irqrestore(&ioapic_lock, flags);
 194 }
 195
 196 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 197 {
 198         struct IO_APIC_route_entry entry;
 199         unsigned long flags;
 200
 201         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 202         spin_lock_irqsave(&ioapic_lock, flags);
 203         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 204         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 205         spin_unlock_irqrestore(&ioapic_lock, flags);
 206         if (entry.delivery_mode == dest_SMI)
 207                 return;
 208         /*
 209          * Disable it in the IO-APIC irq-routing table:
 210          */
 211         memset(&entry, 0, sizeof(entry));
 212         entry.mask = 1;
 213         spin_lock_irqsave(&ioapic_lock, flags);
 214         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 215         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 216         spin_unlock_irqrestore(&ioapic_lock, flags);
 217 }
 218
 219 static void clear_IO_APIC (void)
 220 {
 221         int apic, pin;
 222
 223         for (apic = 0; apic < nr_ioapics; apic++)
 224                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 225                         clear_IO_APIC_pin(apic, pin);
 226 }
 227
 228 /*
 229  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 230  * specific CPU-side IRQs.
 231  */
 232
 233 #define MAX_PIRQS 8
 234 static int pirq_entries [MAX_PIRQS];
 235 static int pirqs_enabled;
 236 int skip_ioapic_setup;
 237 int ioapic_force;
 238
 239 /* dummy parsing: see setup.c */
 240
 241 static int __init disable_ioapic_setup(char *str)
 242 {
 243         skip_ioapic_setup = 1;
 244         return 1;
 245 }
 246
 247 static int __init enable_ioapic_setup(char *str)
 248 {
 249         ioapic_force = 1;
 250         skip_ioapic_setup = 0;
 251         return 1;
 252 }
 253
 254 __setup("noapic", disable_ioapic_setup);
 255 __setup("apic", enable_ioapic_setup);
 256
 257 static int __init setup_disable_8254_timer(char *s)
 258 {
 259         timer_over_8254 = -1;
 260         return 1;
 261 }
 262 static int __init setup_enable_8254_timer(char *s)
 263 {
 264         timer_over_8254 = 2;
 265         return 1;
 266 }
 267
 268 __setup("disable_8254_timer", setup_disable_8254_timer);
 269 __setup("enable_8254_timer", setup_enable_8254_timer);
 270
 271 #include <asm/pci-direct.h>
 272 #include <linux/pci_ids.h>
 273 #include <linux/pci.h>
 274
 275
 276 #ifdef CONFIG_ACPI
 277
 278 static int nvidia_hpet_detected __initdata;
 279
 280 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
 281 {
 282         nvidia_hpet_detected = 1;
 283         return 0;
 284 }
 285 #endif
 286
 287 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 288    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 289    Use pci direct infrastructure because this runs before the PCI subsystem.
 290
 291    Can be overwritten with "apic"
 292
 293    And another hack to disable the IOMMU on VIA chipsets.
 294
 295    ... and others. Really should move this somewhere else.
 296
 297    Kludge-O-Rama. */
 298 void __init check_ioapic(void)
 299 {
 300         int num,slot,func;
 301         /* Poor man's PCI discovery */
 302         for (num = 0; num < 32; num++) {
 303                 for (slot = 0; slot < 32; slot++) {
 304                         for (func = 0; func < 8; func++) {
 305                                 u32 class;
 306                                 u32 vendor;
 307                                 u8 type;
 308                                 class = read_pci_config(num,slot,func,
 309                                                         PCI_CLASS_REVISION);
 310                                 if (class == 0xffffffff)
 311                                         break;
 312
 313                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 314                                         continue;
 315
 316                                 vendor = read_pci_config(num, slot, func,
 317                                                          PCI_VENDOR_ID);
 318                                 vendor &= 0xffff;
 319                                 switch (vendor) {
 320                                 case PCI_VENDOR_ID_VIA:
 321 #ifdef CONFIG_GART_IOMMU
 322                                         if ((end_pfn > MAX_DMA32_PFN ||
 323                                              force_iommu) &&
 324                                             !iommu_aperture_allowed) {
 325                                                 printk(KERN_INFO
 326     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 327                                                 iommu_aperture_disabled = 1;
 328                                         }
 329 #endif
 330                                         return;
 331                                 case PCI_VENDOR_ID_NVIDIA:
 332 #ifdef CONFIG_ACPI
 333                                         /*
 334                                          * All timer overrides on Nvidia are
 335                                          * wrong unless HPET is enabled.
 336                                          */
 337                                         nvidia_hpet_detected = 0;
 338                                         acpi_table_parse(ACPI_HPET,
 339                                                         nvidia_hpet_check);
 340                                         if (nvidia_hpet_detected == 0) {
 341                                                 acpi_skip_timer_override = 1;
 342                                                 printk(KERN_INFO "Nvidia board "
 343                                                     "detected. Ignoring ACPI "
 344                                                     "timer override.\n");
 345                                         }
 346 #endif
 347                                         /* RED-PEN skip them on mptables too? */
 348                                         return;
 349
 350                                 /* This should be actually default, but
 351                                    for 2.6.16 let's do it for ATI only where
 352                                    it's really needed. */
 353                                 case PCI_VENDOR_ID_ATI:
 354                                         if (timer_over_8254 == 1) {
 355                                                 timer_over_8254 = 0;
 356                                         printk(KERN_INFO
 357                 "ATI board detected. Disabling timer routing over 8254.\n");
 358                                         }
 359                                         return;
 360                                 }
 361
 362
 363                                 /* No multi-function device? */
 364                                 type = read_pci_config_byte(num,slot,func,
 365                                                             PCI_HEADER_TYPE);
 366                                 if (!(type & 0x80))
 367                                         break;
 368                         }
 369                 }
 370         }
 371 }
 372
 373 static int __init ioapic_pirq_setup(char *str)
 374 {
 375         int i, max;
 376         int ints[MAX_PIRQS+1];
 377
 378         get_options(str, ARRAY_SIZE(ints), ints);
 379
 380         for (i = 0; i < MAX_PIRQS; i++)
 381                 pirq_entries[i] = -1;
 382
 383         pirqs_enabled = 1;
 384         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 385         max = MAX_PIRQS;
 386         if (ints[0] < MAX_PIRQS)
 387                 max = ints[0];
 388
 389         for (i = 0; i < max; i++) {
 390                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 391                 /*
 392                  * PIRQs are mapped upside down, usually.
 393                  */
 394                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 395         }
 396         return 1;
 397 }
 398
 399 __setup("pirq=", ioapic_pirq_setup);
 400
 401 /*
 402  * Find the IRQ entry number of a certain pin.
 403  */
 404 static int find_irq_entry(int apic, int pin, int type)
 405 {
 406         int i;
 407
 408         for (i = 0; i < mp_irq_entries; i++)
 409                 if (mp_irqs[i].mpc_irqtype == type &&
 410                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 411                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 412                     mp_irqs[i].mpc_dstirq == pin)
 413                         return i;
 414
 415         return -1;
 416 }
 417
 418 /*
 419  * Find the pin to which IRQ[irq] (ISA) is connected
 420  */
 421 static int __init find_isa_irq_pin(int irq, int type)
 422 {
 423         int i;
 424
 425         for (i = 0; i < mp_irq_entries; i++) {
 426                 int lbus = mp_irqs[i].mpc_srcbus;
 427
 428                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 429                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 430                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 431                     (mp_irqs[i].mpc_irqtype == type) &&
 432                     (mp_irqs[i].mpc_srcbusirq == irq))
 433
 434                         return mp_irqs[i].mpc_dstirq;
 435         }
 436         return -1;
 437 }
 438
 439 static int __init find_isa_irq_apic(int irq, int type)
 440 {
 441         int i;
 442
 443         for (i = 0; i < mp_irq_entries; i++) {
 444                 int lbus = mp_irqs[i].mpc_srcbus;
 445
 446                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 447                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 448                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 449                     (mp_irqs[i].mpc_irqtype == type) &&
 450                     (mp_irqs[i].mpc_srcbusirq == irq))
 451                         break;
 452         }
 453         if (i < mp_irq_entries) {
 454                 int apic;
 455                 for(apic = 0; apic < nr_ioapics; apic++) {
 456                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 457                                 return apic;
 458                 }
 459         }
 460
 461         return -1;
 462 }
 463
 464 /*
 465  * Find a specific PCI IRQ entry.
 466  * Not an __init, possibly needed by modules
 467  */
 468 static int pin_2_irq(int idx, int apic, int pin);
 469
 470 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 471 {
 472         int apic, i, best_guess = -1;
 473
 474         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 475                 bus, slot, pin);
 476         if (mp_bus_id_to_pci_bus[bus] == -1) {
 477                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 478                 return -1;
 479         }
 480         for (i = 0; i < mp_irq_entries; i++) {
 481                 int lbus = mp_irqs[i].mpc_srcbus;
 482
 483                 for (apic = 0; apic < nr_ioapics; apic++)
 484                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 485                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 486                                 break;
 487
 488                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 489                     !mp_irqs[i].mpc_irqtype &&
 490                     (bus == lbus) &&
 491                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 492                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 493
 494                         if (!(apic || IO_APIC_IRQ(irq)))
 495                                 continue;
 496
 497                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 498                                 return irq;
 499                         /*
 500                          * Use the first all-but-pin matching entry as a
 501                          * best-guess fuzzy result for broken mptables.
 502                          */
 503                         if (best_guess < 0)
 504                                 best_guess = irq;
 505                 }
 506         }
 507         BUG_ON(best_guess >= NR_IRQS);
 508         return best_guess;
 509 }
 510
 511 /*
 512  * EISA Edge/Level control register, ELCR
 513  */
 514 static int EISA_ELCR(unsigned int irq)
 515 {
 516         if (irq < 16) {
 517                 unsigned int port = 0x4d0 + (irq >> 3);
 518                 return (inb(port) >> (irq & 7)) & 1;
 519         }
 520         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 521         return 0;
 522 }
 523
 524 /* EISA interrupts are always polarity zero and can be edge or level
 525  * trigger depending on the ELCR value.  If an interrupt is listed as
 526  * EISA conforming in the MP table, that means its trigger type must
 527  * be read in from the ELCR */
 528
 529 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 530 #define default_EISA_polarity(idx)      (0)
 531
 532 /* ISA interrupts are always polarity zero edge triggered,
 533  * when listed as conforming in the MP table. */
 534
 535 #define default_ISA_trigger(idx)        (0)
 536 #define default_ISA_polarity(idx)       (0)
 537
 538 /* PCI interrupts are always polarity one level triggered,
 539  * when listed as conforming in the MP table. */
 540
 541 #define default_PCI_trigger(idx)        (1)
 542 #define default_PCI_polarity(idx)       (1)
 543
 544 /* MCA interrupts are always polarity zero level triggered,
 545  * when listed as conforming in the MP table. */
 546
 547 #define default_MCA_trigger(idx)        (1)
 548 #define default_MCA_polarity(idx)       (0)
 549
 550 static int __init MPBIOS_polarity(int idx)
 551 {
 552         int bus = mp_irqs[idx].mpc_srcbus;
 553         int polarity;
 554
 555         /*
 556          * Determine IRQ line polarity (high active or low active):
 557          */
 558         switch (mp_irqs[idx].mpc_irqflag & 3)
 559         {
 560                 case 0: /* conforms, ie. bus-type dependent polarity */
 561                 {
 562                         switch (mp_bus_id_to_type[bus])
 563                         {
 564                                 case MP_BUS_ISA: /* ISA pin */
 565                                 {
 566                                         polarity = default_ISA_polarity(idx);
 567                                         break;
 568                                 }
 569                                 case MP_BUS_EISA: /* EISA pin */
 570                                 {
 571                                         polarity = default_EISA_polarity(idx);
 572                                         break;
 573                                 }
 574                                 case MP_BUS_PCI: /* PCI pin */
 575                                 {
 576                                         polarity = default_PCI_polarity(idx);
 577                                         break;
 578                                 }
 579                                 case MP_BUS_MCA: /* MCA pin */
 580                                 {
 581                                         polarity = default_MCA_polarity(idx);
 582                                         break;
 583                                 }
 584                                 default:
 585                                 {
 586                                         printk(KERN_WARNING "broken BIOS!!\n");
 587                                         polarity = 1;
 588                                         break;
 589                                 }
 590                         }
 591                         break;
 592                 }
 593                 case 1: /* high active */
 594                 {
 595                         polarity = 0;
 596                         break;
 597                 }
 598                 case 2: /* reserved */
 599                 {
 600                         printk(KERN_WARNING "broken BIOS!!\n");
 601                         polarity = 1;
 602                         break;
 603                 }
 604                 case 3: /* low active */
 605                 {
 606                         polarity = 1;
 607                         break;
 608                 }
 609                 default: /* invalid */
 610                 {
 611                         printk(KERN_WARNING "broken BIOS!!\n");
 612                         polarity = 1;
 613                         break;
 614                 }
 615         }
 616         return polarity;
 617 }
 618
 619 static int MPBIOS_trigger(int idx)
 620 {
 621         int bus = mp_irqs[idx].mpc_srcbus;
 622         int trigger;
 623
 624         /*
 625          * Determine IRQ trigger mode (edge or level sensitive):
 626          */
 627         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 628         {
 629                 case 0: /* conforms, ie. bus-type dependent */
 630                 {
 631                         switch (mp_bus_id_to_type[bus])
 632                         {
 633                                 case MP_BUS_ISA: /* ISA pin */
 634                                 {
 635                                         trigger = default_ISA_trigger(idx);
 636                                         break;
 637                                 }
 638                                 case MP_BUS_EISA: /* EISA pin */
 639                                 {
 640                                         trigger = default_EISA_trigger(idx);
 641                                         break;
 642                                 }
 643                                 case MP_BUS_PCI: /* PCI pin */
 644                                 {
 645                                         trigger = default_PCI_trigger(idx);
 646                                         break;
 647                                 }
 648                                 case MP_BUS_MCA: /* MCA pin */
 649                                 {
 650                                         trigger = default_MCA_trigger(idx);
 651                                         break;
 652                                 }
 653                                 default:
 654                                 {
 655                                         printk(KERN_WARNING "broken BIOS!!\n");
 656                                         trigger = 1;
 657                                         break;
 658                                 }
 659                         }
 660                         break;
 661                 }
 662                 case 1: /* edge */
 663                 {
 664                         trigger = 0;
 665                         break;
 666                 }
 667                 case 2: /* reserved */
 668                 {
 669                         printk(KERN_WARNING "broken BIOS!!\n");
 670                         trigger = 1;
 671                         break;
 672                 }
 673                 case 3: /* level */
 674                 {
 675                         trigger = 1;
 676                         break;
 677                 }
 678                 default: /* invalid */
 679                 {
 680                         printk(KERN_WARNING "broken BIOS!!\n");
 681                         trigger = 0;
 682                         break;
 683                 }
 684         }
 685         return trigger;
 686 }
 687
 688 static inline int irq_polarity(int idx)
 689 {
 690         return MPBIOS_polarity(idx);
 691 }
 692
 693 static inline int irq_trigger(int idx)
 694 {
 695         return MPBIOS_trigger(idx);
 696 }
 697
 698 static int next_irq = 16;
 699
 700 /*
 701  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 702  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 703  * from ACPI, which can reach 800 in large boxen.
 704  *
 705  * Compact the sparse GSI space into a sequential IRQ series and reuse
 706  * vectors if possible.
 707  */
 708 int gsi_irq_sharing(int gsi)
 709 {
 710         int i, tries, vector;
 711
 712         BUG_ON(gsi >= NR_IRQ_VECTORS);
 713
 714         if (platform_legacy_irq(gsi))
 715                 return gsi;
 716
 717         if (gsi_2_irq[gsi] != 0xFF)
 718                 return (int)gsi_2_irq[gsi];
 719
 720         tries = NR_IRQS;
 721   try_again:
 722         vector = assign_irq_vector(gsi);
 723
 724         /*
 725          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 726          * use of vector and if found, return that IRQ.  However, we never want
 727          * to share legacy IRQs, which usually have a different trigger mode
 728          * than PCI.
 729          */
 730         for (i = 0; i < NR_IRQS; i++)
 731                 if (IO_APIC_VECTOR(i) == vector)
 732                         break;
 733         if (platform_legacy_irq(i)) {
 734                 if (--tries >= 0) {
 735                         IO_APIC_VECTOR(i) = 0;
 736                         goto try_again;
 737                 }
 738                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 739         }
 740         if (i < NR_IRQS) {
 741                 gsi_2_irq[gsi] = i;
 742                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 743                                 gsi, vector, i);
 744                 return i;
 745         }
 746
 747         i = next_irq++;
 748         BUG_ON(i >= NR_IRQS);
 749         gsi_2_irq[gsi] = i;
 750         IO_APIC_VECTOR(i) = vector;
 751         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 752                         gsi, vector, i);
 753         return i;
 754 }
 755
 756 static int pin_2_irq(int idx, int apic, int pin)
 757 {
 758         int irq, i;
 759         int bus = mp_irqs[idx].mpc_srcbus;
 760
 761         /*
 762          * Debugging check, we are in big trouble if this message pops up!
 763          */
 764         if (mp_irqs[idx].mpc_dstirq != pin)
 765                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 766
 767         switch (mp_bus_id_to_type[bus])
 768         {
 769                 case MP_BUS_ISA: /* ISA pin */
 770                 case MP_BUS_EISA:
 771                 case MP_BUS_MCA:
 772                 {
 773                         irq = mp_irqs[idx].mpc_srcbusirq;
 774                         break;
 775                 }
 776                 case MP_BUS_PCI: /* PCI pin */
 777                 {
 778                         /*
 779                          * PCI IRQs are mapped in order
 780                          */
 781                         i = irq = 0;
 782                         while (i < apic)
 783                                 irq += nr_ioapic_registers[i++];
 784                         irq += pin;
 785                         irq = gsi_irq_sharing(irq);
 786                         break;
 787                 }
 788                 default:
 789                 {
 790                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 791                         irq = 0;
 792                         break;
 793                 }
 794         }
 795         BUG_ON(irq >= NR_IRQS);
 796
 797         /*
 798          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 799          */
 800         if ((pin >= 16) && (pin <= 23)) {
 801                 if (pirq_entries[pin-16] != -1) {
 802                         if (!pirq_entries[pin-16]) {
 803                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 804                         } else {
 805                                 irq = pirq_entries[pin-16];
 806                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 807                                                 pin-16, irq);
 808                         }
 809                 }
 810         }
 811         BUG_ON(irq >= NR_IRQS);
 812         return irq;
 813 }
 814
 815 static inline int IO_APIC_irq_trigger(int irq)
 816 {
 817         int apic, idx, pin;
 818
 819         for (apic = 0; apic < nr_ioapics; apic++) {
 820                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 821                         idx = find_irq_entry(apic,pin,mp_INT);
 822                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 823                                 return irq_trigger(idx);
 824                 }
 825         }
 826         /*
 827          * nonexistent IRQs are edge default
 828          */
 829         return 0;
 830 }
 831
 832 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 833 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 834
 835 int assign_irq_vector(int irq)
 836 {
 837         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 838         int vector;
 839
 840         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 841
 842         spin_lock(&vector_lock);
 843
 844         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
 845                 spin_unlock(&vector_lock);
 846                 return IO_APIC_VECTOR(irq);
 847         }
 848 next:
 849         current_vector += 8;
 850         if (current_vector == IA32_SYSCALL_VECTOR)
 851                 goto next;
 852
 853         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 854                 /* If we run out of vectors on large boxen, must share them. */
 855                 offset = (offset + 1) % 8;
 856                 current_vector = FIRST_DEVICE_VECTOR + offset;
 857         }
 858
 859         vector = current_vector;
 860         vector_irq[vector] = irq;
 861         if (irq != AUTO_ASSIGN)
 862                 IO_APIC_VECTOR(irq) = vector;
 863
 864         spin_unlock(&vector_lock);
 865
 866         return vector;
 867 }
 868
 869 extern void (*interrupt[NR_IRQS])(void);
 870 static struct hw_interrupt_type ioapic_level_type;
 871 static struct hw_interrupt_type ioapic_edge_type;
 872
 873 #define IOAPIC_AUTO     -1
 874 #define IOAPIC_EDGE     0
 875 #define IOAPIC_LEVEL    1
 876
 877 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 878 {
 879         unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
 880
 881         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 882                         trigger == IOAPIC_LEVEL)
 883                 irq_desc[idx].handler = &ioapic_level_type;
 884         else
 885                 irq_desc[idx].handler = &ioapic_edge_type;
 886         set_intr_gate(vector, interrupt[idx]);
 887 }
 888
 889 static void __init setup_IO_APIC_irqs(void)
 890 {
 891         struct IO_APIC_route_entry entry;
 892         int apic, pin, idx, irq, first_notcon = 1, vector;
 893         unsigned long flags;
 894
 895         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 896
 897         for (apic = 0; apic < nr_ioapics; apic++) {
 898         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 899
 900                 /*
 901                  * add it to the IO-APIC irq-routing table:
 902                  */
 903                 memset(&entry,0,sizeof(entry));
 904
 905                 entry.delivery_mode = INT_DELIVERY_MODE;
 906                 entry.dest_mode = INT_DEST_MODE;
 907                 entry.mask = 0;                         /* enable IRQ */
 908                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 909
 910                 idx = find_irq_entry(apic,pin,mp_INT);
 911                 if (idx == -1) {
 912                         if (first_notcon) {
 913                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 914                                 first_notcon = 0;
 915                         } else
 916                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 917                         continue;
 918                 }
 919
 920                 entry.trigger = irq_trigger(idx);
 921                 entry.polarity = irq_polarity(idx);
 922
 923                 if (irq_trigger(idx)) {
 924                         entry.trigger = 1;
 925                         entry.mask = 1;
 926                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 927                 }
 928
 929                 irq = pin_2_irq(idx, apic, pin);
 930                 add_pin_to_irq(irq, apic, pin);
 931
 932                 if (!apic && !IO_APIC_IRQ(irq))
 933                         continue;
 934
 935                 if (IO_APIC_IRQ(irq)) {
 936                         vector = assign_irq_vector(irq);
 937                         entry.vector = vector;
 938
 939                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 940                         if (!apic && (irq < 16))
 941                                 disable_8259A_irq(irq);
 942                 }
 943                 spin_lock_irqsave(&ioapic_lock, flags);
 944                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 945                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 946                 set_native_irq_info(irq, TARGET_CPUS);
 947                 spin_unlock_irqrestore(&ioapic_lock, flags);
 948         }
 949         }
 950
 951         if (!first_notcon)
 952                 apic_printk(APIC_VERBOSE," not connected.\n");
 953 }
 954
 955 /*
 956  * Set up the 8259A-master output pin as broadcast to all
 957  * CPUs.
 958  */
 959 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 960 {
 961         struct IO_APIC_route_entry entry;
 962         unsigned long flags;
 963
 964         memset(&entry,0,sizeof(entry));
 965
 966         disable_8259A_irq(0);
 967
 968         /* mask LVT0 */
 969         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 970
 971         /*
 972          * We use logical delivery to get the timer IRQ
 973          * to the first CPU.
 974          */
 975         entry.dest_mode = INT_DEST_MODE;
 976         entry.mask = 0;                                 /* unmask IRQ now */
 977         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 978         entry.delivery_mode = INT_DELIVERY_MODE;
 979         entry.polarity = 0;
 980         entry.trigger = 0;
 981         entry.vector = vector;
 982
 983         /*
 984          * The timer IRQ doesn't have to know that behind the
 985          * scene we have a 8259A-master in AEOI mode ...
 986          */
 987         irq_desc[0].handler = &ioapic_edge_type;
 988
 989         /*
 990          * Add it to the IO-APIC irq-routing table:
 991          */
 992         spin_lock_irqsave(&ioapic_lock, flags);
 993         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 994         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 995         spin_unlock_irqrestore(&ioapic_lock, flags);
 996
 997         enable_8259A_irq(0);
 998 }
 999
1000 void __init UNEXPECTED_IO_APIC(void)
1001 {
1002 }
1003
1004 void __apicdebuginit print_IO_APIC(void)
1005 {
1006         int apic, i;
1007         union IO_APIC_reg_00 reg_00;
1008         union IO_APIC_reg_01 reg_01;
1009         union IO_APIC_reg_02 reg_02;
1010         unsigned long flags;
1011
1012         if (apic_verbosity == APIC_QUIET)
1013                 return;
1014
1015         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1016         for (i = 0; i < nr_ioapics; i++)
1017                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1018                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1019
1020         /*
1021          * We are a bit conservative about what we expect.  We have to
1022          * know about every hardware change ASAP.
1023          */
1024         printk(KERN_INFO "testing the IO APIC.......................\n");
1025
1026         for (apic = 0; apic < nr_ioapics; apic++) {
1027
1028         spin_lock_irqsave(&ioapic_lock, flags);
1029         reg_00.raw = io_apic_read(apic, 0);
1030         reg_01.raw = io_apic_read(apic, 1);
1031         if (reg_01.bits.version >= 0x10)
1032                 reg_02.raw = io_apic_read(apic, 2);
1033         spin_unlock_irqrestore(&ioapic_lock, flags);
1034
1035         printk("\n");
1036         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1037         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1038         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1039         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1040                 UNEXPECTED_IO_APIC();
1041
1042         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1043         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1044         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1045                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1046                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1047                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1048                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1049                 (reg_01.bits.entries != 0x2E) &&
1050                 (reg_01.bits.entries != 0x3F) &&
1051                 (reg_01.bits.entries != 0x03)
1052         )
1053                 UNEXPECTED_IO_APIC();
1054
1055         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1056         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1057         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1058                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1059                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1060                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1061                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1062                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1063         )
1064                 UNEXPECTED_IO_APIC();
1065         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1066                 UNEXPECTED_IO_APIC();
1067
1068         if (reg_01.bits.version >= 0x10) {
1069                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1070                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1071                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1072                         UNEXPECTED_IO_APIC();
1073         }
1074
1075         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1076
1077         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1078                           " Stat Dest Deli Vect:   \n");
1079
1080         for (i = 0; i <= reg_01.bits.entries; i++) {
1081                 struct IO_APIC_route_entry entry;
1082
1083                 spin_lock_irqsave(&ioapic_lock, flags);
1084                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1085                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1086                 spin_unlock_irqrestore(&ioapic_lock, flags);
1087
1088                 printk(KERN_DEBUG " %02x %03X %02X  ",
1089                         i,
1090                         entry.dest.logical.logical_dest,
1091                         entry.dest.physical.physical_dest
1092                 );
1093
1094                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1095                         entry.mask,
1096                         entry.trigger,
1097                         entry.irr,
1098                         entry.polarity,
1099                         entry.delivery_status,
1100                         entry.dest_mode,
1101                         entry.delivery_mode,
1102                         entry.vector
1103                 );
1104         }
1105         }
1106         if (use_pci_vector())
1107                 printk(KERN_INFO "Using vector-based indexing\n");
1108         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1109         for (i = 0; i < NR_IRQS; i++) {
1110                 struct irq_pin_list *entry = irq_2_pin + i;
1111                 if (entry->pin < 0)
1112                         continue;
1113                 if (use_pci_vector() && !platform_legacy_irq(i))
1114                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1115                 else
1116                         printk(KERN_DEBUG "IRQ%d ", i);
1117                 for (;;) {
1118                         printk("-> %d:%d", entry->apic, entry->pin);
1119                         if (!entry->next)
1120                                 break;
1121                         entry = irq_2_pin + entry->next;
1122                 }
1123                 printk("\n");
1124         }
1125
1126         printk(KERN_INFO ".................................... done.\n");
1127
1128         return;
1129 }
1130
1131 #if 0
1132
1133 static __apicdebuginit void print_APIC_bitfield (int base)
1134 {
1135         unsigned int v;
1136         int i, j;
1137
1138         if (apic_verbosity == APIC_QUIET)
1139                 return;
1140
1141         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1142         for (i = 0; i < 8; i++) {
1143                 v = apic_read(base + i*0x10);
1144                 for (j = 0; j < 32; j++) {
1145                         if (v & (1<<j))
1146                                 printk("1");
1147                         else
1148                                 printk("0");
1149                 }
1150                 printk("\n");
1151         }
1152 }
1153
1154 void __apicdebuginit print_local_APIC(void * dummy)
1155 {
1156         unsigned int v, ver, maxlvt;
1157
1158         if (apic_verbosity == APIC_QUIET)
1159                 return;
1160
1161         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1162                 smp_processor_id(), hard_smp_processor_id());
1163         v = apic_read(APIC_ID);
1164         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1165         v = apic_read(APIC_LVR);
1166         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1167         ver = GET_APIC_VERSION(v);
1168         maxlvt = get_maxlvt();
1169
1170         v = apic_read(APIC_TASKPRI);
1171         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1172
1173         v = apic_read(APIC_ARBPRI);
1174         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1175                 v & APIC_ARBPRI_MASK);
1176         v = apic_read(APIC_PROCPRI);
1177         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1178
1179         v = apic_read(APIC_EOI);
1180         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1181         v = apic_read(APIC_RRR);
1182         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1183         v = apic_read(APIC_LDR);
1184         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1185         v = apic_read(APIC_DFR);
1186         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1187         v = apic_read(APIC_SPIV);
1188         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1189
1190         printk(KERN_DEBUG "... APIC ISR field:\n");
1191         print_APIC_bitfield(APIC_ISR);
1192         printk(KERN_DEBUG "... APIC TMR field:\n");
1193         print_APIC_bitfield(APIC_TMR);
1194         printk(KERN_DEBUG "... APIC IRR field:\n");
1195         print_APIC_bitfield(APIC_IRR);
1196
1197         v = apic_read(APIC_ESR);
1198         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1199
1200         v = apic_read(APIC_ICR);
1201         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1202         v = apic_read(APIC_ICR2);
1203         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1204
1205         v = apic_read(APIC_LVTT);
1206         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1207
1208         if (maxlvt > 3) {                       /* PC is LVT#4. */
1209                 v = apic_read(APIC_LVTPC);
1210                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1211         }
1212         v = apic_read(APIC_LVT0);
1213         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1214         v = apic_read(APIC_LVT1);
1215         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1216
1217         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1218                 v = apic_read(APIC_LVTERR);
1219                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1220         }
1221
1222         v = apic_read(APIC_TMICT);
1223         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1224         v = apic_read(APIC_TMCCT);
1225         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1226         v = apic_read(APIC_TDCR);
1227         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1228         printk("\n");
1229 }
1230
1231 void print_all_local_APICs (void)
1232 {
1233         on_each_cpu(print_local_APIC, NULL, 1, 1);
1234 }
1235
1236 void __apicdebuginit print_PIC(void)
1237 {
1238         unsigned int v;
1239         unsigned long flags;
1240
1241         if (apic_verbosity == APIC_QUIET)
1242                 return;
1243
1244         printk(KERN_DEBUG "\nprinting PIC contents\n");
1245
1246         spin_lock_irqsave(&i8259A_lock, flags);
1247
1248         v = inb(0xa1) << 8 | inb(0x21);
1249         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1250
1251         v = inb(0xa0) << 8 | inb(0x20);
1252         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1253
1254         outb(0x0b,0xa0);
1255         outb(0x0b,0x20);
1256         v = inb(0xa0) << 8 | inb(0x20);
1257         outb(0x0a,0xa0);
1258         outb(0x0a,0x20);
1259
1260         spin_unlock_irqrestore(&i8259A_lock, flags);
1261
1262         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1263
1264         v = inb(0x4d1) << 8 | inb(0x4d0);
1265         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1266 }
1267
1268 #endif  /*  0  */
1269
1270 static void __init enable_IO_APIC(void)
1271 {
1272         union IO_APIC_reg_01 reg_01;
1273         int i8259_apic, i8259_pin;
1274         int i, apic;
1275         unsigned long flags;
1276
1277         for (i = 0; i < PIN_MAP_SIZE; i++) {
1278                 irq_2_pin[i].pin = -1;
1279                 irq_2_pin[i].next = 0;
1280         }
1281         if (!pirqs_enabled)
1282                 for (i = 0; i < MAX_PIRQS; i++)
1283                         pirq_entries[i] = -1;
1284
1285         /*
1286          * The number of IO-APIC IRQ registers (== #pins):
1287          */
1288         for (apic = 0; apic < nr_ioapics; apic++) {
1289                 spin_lock_irqsave(&ioapic_lock, flags);
1290                 reg_01.raw = io_apic_read(apic, 1);
1291                 spin_unlock_irqrestore(&ioapic_lock, flags);
1292                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1293         }
1294         for(apic = 0; apic < nr_ioapics; apic++) {
1295                 int pin;
1296                 /* See if any of the pins is in ExtINT mode */
1297                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1298                         struct IO_APIC_route_entry entry;
1299                         spin_lock_irqsave(&ioapic_lock, flags);
1300                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1301                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1302                         spin_unlock_irqrestore(&ioapic_lock, flags);
1303
1304
1305                         /* If the interrupt line is enabled and in ExtInt mode
1306                          * I have found the pin where the i8259 is connected.
1307                          */
1308                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1309                                 ioapic_i8259.apic = apic;
1310                                 ioapic_i8259.pin  = pin;
1311                                 goto found_i8259;
1312                         }
1313                 }
1314         }
1315  found_i8259:
1316         /* Look to see what if the MP table has reported the ExtINT */
1317         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1318         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1319         /* Trust the MP table if nothing is setup in the hardware */
1320         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1321                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1322                 ioapic_i8259.pin  = i8259_pin;
1323                 ioapic_i8259.apic = i8259_apic;
1324         }
1325         /* Complain if the MP table and the hardware disagree */
1326         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1327                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1328         {
1329                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1330         }
1331
1332         /*
1333          * Do not trust the IO-APIC being empty at bootup
1334          */
1335         clear_IO_APIC();
1336 }
1337
1338 /*
1339  * Not an __init, needed by the reboot code
1340  */
1341 void disable_IO_APIC(void)
1342 {
1343         /*
1344          * Clear the IO-APIC before rebooting:
1345          */
1346         clear_IO_APIC();
1347
1348         /*
1349          * If the i8259 is routed through an IOAPIC
1350          * Put that IOAPIC in virtual wire mode
1351          * so legacy interrupts can be delivered.
1352          */
1353         if (ioapic_i8259.pin != -1) {
1354                 struct IO_APIC_route_entry entry;
1355                 unsigned long flags;
1356
1357                 memset(&entry, 0, sizeof(entry));
1358                 entry.mask            = 0; /* Enabled */
1359                 entry.trigger         = 0; /* Edge */
1360                 entry.irr             = 0;
1361                 entry.polarity        = 0; /* High */
1362                 entry.delivery_status = 0;
1363                 entry.dest_mode       = 0; /* Physical */
1364                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1365                 entry.vector          = 0;
1366                 entry.dest.physical.physical_dest =
1367                                         GET_APIC_ID(apic_read(APIC_ID));
1368
1369                 /*
1370                  * Add it to the IO-APIC irq-routing table:
1371                  */
1372                 spin_lock_irqsave(&ioapic_lock, flags);
1373                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1374                         *(((int *)&entry)+1));
1375                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1376                         *(((int *)&entry)+0));
1377                 spin_unlock_irqrestore(&ioapic_lock, flags);
1378         }
1379
1380         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1381 }
1382
1383 /*
1384  * function to set the IO-APIC physical IDs based on the
1385  * values stored in the MPC table.
1386  *
1387  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1388  */
1389
1390 static void __init setup_ioapic_ids_from_mpc (void)
1391 {
1392         union IO_APIC_reg_00 reg_00;
1393         int apic;
1394         int i;
1395         unsigned char old_id;
1396         unsigned long flags;
1397
1398         /*
1399          * Set the IOAPIC ID to the value stored in the MPC table.
1400          */
1401         for (apic = 0; apic < nr_ioapics; apic++) {
1402
1403                 /* Read the register 0 value */
1404                 spin_lock_irqsave(&ioapic_lock, flags);
1405                 reg_00.raw = io_apic_read(apic, 0);
1406                 spin_unlock_irqrestore(&ioapic_lock, flags);
1407
1408                 old_id = mp_ioapics[apic].mpc_apicid;
1409
1410
1411                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1412
1413
1414                 /*
1415                  * We need to adjust the IRQ routing table
1416                  * if the ID changed.
1417                  */
1418                 if (old_id != mp_ioapics[apic].mpc_apicid)
1419                         for (i = 0; i < mp_irq_entries; i++)
1420                                 if (mp_irqs[i].mpc_dstapic == old_id)
1421                                         mp_irqs[i].mpc_dstapic
1422                                                 = mp_ioapics[apic].mpc_apicid;
1423
1424                 /*
1425                  * Read the right value from the MPC table and
1426                  * write it into the ID register.
1427                  */
1428                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1429                                 mp_ioapics[apic].mpc_apicid);
1430
1431                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1432                 spin_lock_irqsave(&ioapic_lock, flags);
1433                 io_apic_write(apic, 0, reg_00.raw);
1434                 spin_unlock_irqrestore(&ioapic_lock, flags);
1435
1436                 /*
1437                  * Sanity check
1438                  */
1439                 spin_lock_irqsave(&ioapic_lock, flags);
1440                 reg_00.raw = io_apic_read(apic, 0);
1441                 spin_unlock_irqrestore(&ioapic_lock, flags);
1442                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1443                         printk("could not set ID!\n");
1444                 else
1445                         apic_printk(APIC_VERBOSE," ok.\n");
1446         }
1447 }
1448
1449 /*
1450  * There is a nasty bug in some older SMP boards, their mptable lies
1451  * about the timer IRQ. We do the following to work around the situation:
1452  *
1453  *      - timer IRQ defaults to IO-APIC IRQ
1454  *      - if this function detects that timer IRQs are defunct, then we fall
1455  *        back to ISA timer IRQs
1456  */
1457 static int __init timer_irq_works(void)
1458 {
1459         unsigned long t1 = jiffies;
1460
1461         local_irq_enable();
1462         /* Let ten ticks pass... */
1463         mdelay((10 * 1000) / HZ);
1464
1465         /*
1466          * Expect a few ticks at least, to be sure some possible
1467          * glue logic does not lock up after one or two first
1468          * ticks in a non-ExtINT mode.  Also the local APIC
1469          * might have cached one ExtINT interrupt.  Finally, at
1470          * least one tick may be lost due to delays.
1471          */
1472
1473         /* jiffies wrap? */
1474         if (jiffies - t1 > 4)
1475                 return 1;
1476         return 0;
1477 }
1478
1479 /*
1480  * In the SMP+IOAPIC case it might happen that there are an unspecified
1481  * number of pending IRQ events unhandled. These cases are very rare,
1482  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1483  * better to do it this way as thus we do not have to be aware of
1484  * 'pending' interrupts in the IRQ path, except at this point.
1485  */
1486 /*
1487  * Edge triggered needs to resend any interrupt
1488  * that was delayed but this is now handled in the device
1489  * independent code.
1490  */
1491
1492 /*
1493  * Starting up a edge-triggered IO-APIC interrupt is
1494  * nasty - we need to make sure that we get the edge.
1495  * If it is already asserted for some reason, we need
1496  * return 1 to indicate that is was pending.
1497  *
1498  * This is not complete - we should be able to fake
1499  * an edge even if it isn't on the 8259A...
1500  */
1501
1502 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1503 {
1504         int was_pending = 0;
1505         unsigned long flags;
1506
1507         spin_lock_irqsave(&ioapic_lock, flags);
1508         if (irq < 16) {
1509                 disable_8259A_irq(irq);
1510                 if (i8259A_irq_pending(irq))
1511                         was_pending = 1;
1512         }
1513         __unmask_IO_APIC_irq(irq);
1514         spin_unlock_irqrestore(&ioapic_lock, flags);
1515
1516         return was_pending;
1517 }
1518
1519 /*
1520  * Once we have recorded IRQ_PENDING already, we can mask the
1521  * interrupt for real. This prevents IRQ storms from unhandled
1522  * devices.
1523  */
1524 static void ack_edge_ioapic_irq(unsigned int irq)
1525 {
1526         move_irq(irq);
1527         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1528                                         == (IRQ_PENDING | IRQ_DISABLED))
1529                 mask_IO_APIC_irq(irq);
1530         ack_APIC_irq();
1531 }
1532
1533 /*
1534  * Level triggered interrupts can just be masked,
1535  * and shutting down and starting up the interrupt
1536  * is the same as enabling and disabling them -- except
1537  * with a startup need to return a "was pending" value.
1538  *
1539  * Level triggered interrupts are special because we
1540  * do not touch any IO-APIC register while handling
1541  * them. We ack the APIC in the end-IRQ handler, not
1542  * in the start-IRQ-handler. Protection against reentrance
1543  * from the same interrupt is still provided, both by the
1544  * generic IRQ layer and by the fact that an unacked local
1545  * APIC does not accept IRQs.
1546  */
1547 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1548 {
1549         unmask_IO_APIC_irq(irq);
1550
1551         return 0; /* don't check for pending */
1552 }
1553
1554 static void end_level_ioapic_irq (unsigned int irq)
1555 {
1556         move_irq(irq);
1557         ack_APIC_irq();
1558 }
1559
1560 #ifdef CONFIG_PCI_MSI
1561 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1562 {
1563         int irq = vector_to_irq(vector);
1564
1565         return startup_edge_ioapic_irq(irq);
1566 }
1567
1568 static void ack_edge_ioapic_vector(unsigned int vector)
1569 {
1570         int irq = vector_to_irq(vector);
1571
1572         move_native_irq(vector);
1573         ack_edge_ioapic_irq(irq);
1574 }
1575
1576 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1577 {
1578         int irq = vector_to_irq(vector);
1579
1580         return startup_level_ioapic_irq (irq);
1581 }
1582
1583 static void end_level_ioapic_vector (unsigned int vector)
1584 {
1585         int irq = vector_to_irq(vector);
1586
1587         move_native_irq(vector);
1588         end_level_ioapic_irq(irq);
1589 }
1590
1591 static void mask_IO_APIC_vector (unsigned int vector)
1592 {
1593         int irq = vector_to_irq(vector);
1594
1595         mask_IO_APIC_irq(irq);
1596 }
1597
1598 static void unmask_IO_APIC_vector (unsigned int vector)
1599 {
1600         int irq = vector_to_irq(vector);
1601
1602         unmask_IO_APIC_irq(irq);
1603 }
1604
1605 #ifdef CONFIG_SMP
1606 static void set_ioapic_affinity_vector (unsigned int vector,
1607                                         cpumask_t cpu_mask)
1608 {
1609         int irq = vector_to_irq(vector);
1610
1611         set_native_irq_info(vector, cpu_mask);
1612         set_ioapic_affinity_irq(irq, cpu_mask);
1613 }
1614 #endif // CONFIG_SMP
1615 #endif // CONFIG_PCI_MSI
1616
1617 /*
1618  * Level and edge triggered IO-APIC interrupts need different handling,
1619  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1620  * handled with the level-triggered descriptor, but that one has slightly
1621  * more overhead. Level-triggered interrupts cannot be handled with the
1622  * edge-triggered handler, without risking IRQ storms and other ugly
1623  * races.
1624  */
1625
1626 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1627         .typename = "IO-APIC-edge",
1628         .startup        = startup_edge_ioapic,
1629         .shutdown       = shutdown_edge_ioapic,
1630         .enable         = enable_edge_ioapic,
1631         .disable        = disable_edge_ioapic,
1632         .ack            = ack_edge_ioapic,
1633         .end            = end_edge_ioapic,
1634 #ifdef CONFIG_SMP
1635         .set_affinity = set_ioapic_affinity,
1636 #endif
1637 };
1638
1639 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1640         .typename = "IO-APIC-level",
1641         .startup        = startup_level_ioapic,
1642         .shutdown       = shutdown_level_ioapic,
1643         .enable         = enable_level_ioapic,
1644         .disable        = disable_level_ioapic,
1645         .ack            = mask_and_ack_level_ioapic,
1646         .end            = end_level_ioapic,
1647 #ifdef CONFIG_SMP
1648         .set_affinity = set_ioapic_affinity,
1649 #endif
1650 };
1651
1652 static inline void init_IO_APIC_traps(void)
1653 {
1654         int irq;
1655
1656         /*
1657          * NOTE! The local APIC isn't very good at handling
1658          * multiple interrupts at the same interrupt level.
1659          * As the interrupt level is determined by taking the
1660          * vector number and shifting that right by 4, we
1661          * want to spread these out a bit so that they don't
1662          * all fall in the same interrupt level.
1663          *
1664          * Also, we've got to be careful not to trash gate
1665          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1666          */
1667         for (irq = 0; irq < NR_IRQS ; irq++) {
1668                 int tmp = irq;
1669                 if (use_pci_vector()) {
1670                         if (!platform_legacy_irq(tmp))
1671                                 if ((tmp = vector_to_irq(tmp)) == -1)
1672                                         continue;
1673                 }
1674                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1675                         /*
1676                          * Hmm.. We don't have an entry for this,
1677                          * so default to an old-fashioned 8259
1678                          * interrupt if we can..
1679                          */
1680                         if (irq < 16)
1681                                 make_8259A_irq(irq);
1682                         else
1683                                 /* Strange. Oh, well.. */
1684                                 irq_desc[irq].handler = &no_irq_type;
1685                 }
1686         }
1687 }
1688
1689 static void enable_lapic_irq (unsigned int irq)
1690 {
1691         unsigned long v;
1692
1693         v = apic_read(APIC_LVT0);
1694         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1695 }
1696
1697 static void disable_lapic_irq (unsigned int irq)
1698 {
1699         unsigned long v;
1700
1701         v = apic_read(APIC_LVT0);
1702         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1703 }
1704
1705 static void ack_lapic_irq (unsigned int irq)
1706 {
1707         ack_APIC_irq();
1708 }
1709
1710 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1711
1712 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1713         .typename = "local-APIC-edge",
1714         .startup = NULL, /* startup_irq() not used for IRQ0 */
1715         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1716         .enable = enable_lapic_irq,
1717         .disable = disable_lapic_irq,
1718         .ack = ack_lapic_irq,
1719         .end = end_lapic_irq,
1720 };
1721
1722 static void setup_nmi (void)
1723 {
1724         /*
1725          * Dirty trick to enable the NMI watchdog ...
1726          * We put the 8259A master into AEOI mode and
1727          * unmask on all local APICs LVT0 as NMI.
1728          *
1729          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1730          * is from Maciej W. Rozycki - so we do not have to EOI from
1731          * the NMI handler or the timer interrupt.
1732          */
1733         printk(KERN_INFO "activating NMI Watchdog ...");
1734
1735         enable_NMI_through_LVT0(NULL);
1736
1737         printk(" done.\n");
1738 }
1739
1740 /*
1741  * This looks a bit hackish but it's about the only one way of sending
1742  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1743  * not support the ExtINT mode, unfortunately.  We need to send these
1744  * cycles as some i82489DX-based boards have glue logic that keeps the
1745  * 8259A interrupt line asserted until INTA.  --macro
1746  */
1747 static inline void unlock_ExtINT_logic(void)
1748 {
1749         int apic, pin, i;
1750         struct IO_APIC_route_entry entry0, entry1;
1751         unsigned char save_control, save_freq_select;
1752         unsigned long flags;
1753
1754         pin  = find_isa_irq_pin(8, mp_INT);
1755         apic = find_isa_irq_apic(8, mp_INT);
1756         if (pin == -1)
1757                 return;
1758
1759         spin_lock_irqsave(&ioapic_lock, flags);
1760         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1761         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1762         spin_unlock_irqrestore(&ioapic_lock, flags);
1763         clear_IO_APIC_pin(apic, pin);
1764
1765         memset(&entry1, 0, sizeof(entry1));
1766
1767         entry1.dest_mode = 0;                   /* physical delivery */
1768         entry1.mask = 0;                        /* unmask IRQ now */
1769         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1770         entry1.delivery_mode = dest_ExtINT;
1771         entry1.polarity = entry0.polarity;
1772         entry1.trigger = 0;
1773         entry1.vector = 0;
1774
1775         spin_lock_irqsave(&ioapic_lock, flags);
1776         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1777         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1778         spin_unlock_irqrestore(&ioapic_lock, flags);
1779
1780         save_control = CMOS_READ(RTC_CONTROL);
1781         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1782         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1783                    RTC_FREQ_SELECT);
1784         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1785
1786         i = 100;
1787         while (i-- > 0) {
1788                 mdelay(10);
1789                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1790                         i -= 10;
1791         }
1792
1793         CMOS_WRITE(save_control, RTC_CONTROL);
1794         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1795         clear_IO_APIC_pin(apic, pin);
1796
1797         spin_lock_irqsave(&ioapic_lock, flags);
1798         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1799         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1800         spin_unlock_irqrestore(&ioapic_lock, flags);
1801 }
1802
1803 int timer_uses_ioapic_pin_0;
1804
1805 /*
1806  * This code may look a bit paranoid, but it's supposed to cooperate with
1807  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1808  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1809  * fanatically on his truly buggy board.
1810  *
1811  * FIXME: really need to revamp this for modern platforms only.
1812  */
1813 static inline void check_timer(void)
1814 {
1815         int apic1, pin1, apic2, pin2;
1816         int vector;
1817
1818         /*
1819          * get/set the timer IRQ vector:
1820          */
1821         disable_8259A_irq(0);
1822         vector = assign_irq_vector(0);
1823         set_intr_gate(vector, interrupt[0]);
1824
1825         /*
1826          * Subtle, code in do_timer_interrupt() expects an AEOI
1827          * mode for the 8259A whenever interrupts are routed
1828          * through I/O APICs.  Also IRQ0 has to be enabled in
1829          * the 8259A which implies the virtual wire has to be
1830          * disabled in the local APIC.
1831          */
1832         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1833         init_8259A(1);
1834         if (timer_over_8254 > 0)
1835                 enable_8259A_irq(0);
1836
1837         pin1  = find_isa_irq_pin(0, mp_INT);
1838         apic1 = find_isa_irq_apic(0, mp_INT);
1839         pin2  = ioapic_i8259.pin;
1840         apic2 = ioapic_i8259.apic;
1841
1842         if (pin1 == 0)
1843                 timer_uses_ioapic_pin_0 = 1;
1844
1845         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1846                 vector, apic1, pin1, apic2, pin2);
1847
1848         if (pin1 != -1) {
1849                 /*
1850                  * Ok, does IRQ0 through the IOAPIC work?
1851                  */
1852                 unmask_IO_APIC_irq(0);
1853                 if (!no_timer_check && timer_irq_works()) {
1854                         nmi_watchdog_default();
1855                         if (nmi_watchdog == NMI_IO_APIC) {
1856                                 disable_8259A_irq(0);
1857                                 setup_nmi();
1858                                 enable_8259A_irq(0);
1859                         }
1860                         if (disable_timer_pin_1 > 0)
1861                                 clear_IO_APIC_pin(0, pin1);
1862                         return;
1863                 }
1864                 clear_IO_APIC_pin(apic1, pin1);
1865                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1866                                 "connected to IO-APIC\n");
1867         }
1868
1869         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1870                                 "through the 8259A ... ");
1871         if (pin2 != -1) {
1872                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1873                         apic2, pin2);
1874                 /*
1875                  * legacy devices should be connected to IO APIC #0
1876                  */
1877                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1878                 if (timer_irq_works()) {
1879                         apic_printk(APIC_VERBOSE," works.\n");
1880                         nmi_watchdog_default();
1881                         if (nmi_watchdog == NMI_IO_APIC) {
1882                                 setup_nmi();
1883                         }
1884                         return;
1885                 }
1886                 /*
1887                  * Cleanup, just in case ...
1888                  */
1889                 clear_IO_APIC_pin(apic2, pin2);
1890         }
1891         apic_printk(APIC_VERBOSE," failed.\n");
1892
1893         if (nmi_watchdog == NMI_IO_APIC) {
1894                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1895                 nmi_watchdog = 0;
1896         }
1897
1898         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1899
1900         disable_8259A_irq(0);
1901         irq_desc[0].handler = &lapic_irq_type;
1902         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1903         enable_8259A_irq(0);
1904
1905         if (timer_irq_works()) {
1906                 apic_printk(APIC_VERBOSE," works.\n");
1907                 return;
1908         }
1909         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1910         apic_printk(APIC_VERBOSE," failed.\n");
1911
1912         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1913
1914         init_8259A(0);
1915         make_8259A_irq(0);
1916         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1917
1918         unlock_ExtINT_logic();
1919
1920         if (timer_irq_works()) {
1921                 apic_printk(APIC_VERBOSE," works.\n");
1922                 return;
1923         }
1924         apic_printk(APIC_VERBOSE," failed :(.\n");
1925         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1926 }
1927
1928 static int __init notimercheck(char *s)
1929 {
1930         no_timer_check = 1;
1931         return 1;
1932 }
1933 __setup("no_timer_check", notimercheck);
1934
1935 /*
1936  *
1937  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1938  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1939  *   Linux doesn't really care, as it's not actually used
1940  *   for any interrupt handling anyway.
1941  */
1942 #define PIC_IRQS        (1<<2)
1943
1944 void __init setup_IO_APIC(void)
1945 {
1946         enable_IO_APIC();
1947
1948         if (acpi_ioapic)
1949                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1950         else
1951                 io_apic_irqs = ~PIC_IRQS;
1952
1953         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1954
1955         /*
1956          * Set up the IO-APIC IRQ routing table.
1957          */
1958         if (!acpi_ioapic)
1959                 setup_ioapic_ids_from_mpc();
1960         sync_Arb_IDs();
1961         setup_IO_APIC_irqs();
1962         init_IO_APIC_traps();
1963         check_timer();
1964         if (!acpi_ioapic)
1965                 print_IO_APIC();
1966 }
1967
1968 struct sysfs_ioapic_data {
1969         struct sys_device dev;
1970         struct IO_APIC_route_entry entry[0];
1971 };
1972 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1973
1974 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1975 {
1976         struct IO_APIC_route_entry *entry;
1977         struct sysfs_ioapic_data *data;
1978         unsigned long flags;
1979         int i;
1980
1981         data = container_of(dev, struct sysfs_ioapic_data, dev);
1982         entry = data->entry;
1983         spin_lock_irqsave(&ioapic_lock, flags);
1984         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1985                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1986                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1987         }
1988         spin_unlock_irqrestore(&ioapic_lock, flags);
1989
1990         return 0;
1991 }
1992
1993 static int ioapic_resume(struct sys_device *dev)
1994 {
1995         struct IO_APIC_route_entry *entry;
1996         struct sysfs_ioapic_data *data;
1997         unsigned long flags;
1998         union IO_APIC_reg_00 reg_00;
1999         int i;
2000
2001         data = container_of(dev, struct sysfs_ioapic_data, dev);
2002         entry = data->entry;
2003
2004         spin_lock_irqsave(&ioapic_lock, flags);
2005         reg_00.raw = io_apic_read(dev->id, 0);
2006         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2007                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2008                 io_apic_write(dev->id, 0, reg_00.raw);
2009         }
2010         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2011                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2012                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2013         }
2014         spin_unlock_irqrestore(&ioapic_lock, flags);
2015
2016         return 0;
2017 }
2018
2019 static struct sysdev_class ioapic_sysdev_class = {
2020         set_kset_name("ioapic"),
2021         .suspend = ioapic_suspend,
2022         .resume = ioapic_resume,
2023 };
2024
2025 static int __init ioapic_init_sysfs(void)
2026 {
2027         struct sys_device * dev;
2028         int i, size, error = 0;
2029
2030         error = sysdev_class_register(&ioapic_sysdev_class);
2031         if (error)
2032                 return error;
2033
2034         for (i = 0; i < nr_ioapics; i++ ) {
2035                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2036                         * sizeof(struct IO_APIC_route_entry);
2037                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2038                 if (!mp_ioapic_data[i]) {
2039                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2040                         continue;
2041                 }
2042                 memset(mp_ioapic_data[i], 0, size);
2043                 dev = &mp_ioapic_data[i]->dev;
2044                 dev->id = i;
2045                 dev->cls = &ioapic_sysdev_class;
2046                 error = sysdev_register(dev);
2047                 if (error) {
2048                         kfree(mp_ioapic_data[i]);
2049                         mp_ioapic_data[i] = NULL;
2050                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2051                         continue;
2052                 }
2053         }
2054
2055         return 0;
2056 }
2057
2058 device_initcall(ioapic_init_sysfs);
2059
2060 /* --------------------------------------------------------------------------
2061                           ACPI-based IOAPIC Configuration
2062    -------------------------------------------------------------------------- */
2063
2064 #ifdef CONFIG_ACPI
2065
2066 #define IO_APIC_MAX_ID          0xFE
2067
2068 int __init io_apic_get_version (int ioapic)
2069 {
2070         union IO_APIC_reg_01    reg_01;
2071         unsigned long flags;
2072
2073         spin_lock_irqsave(&ioapic_lock, flags);
2074         reg_01.raw = io_apic_read(ioapic, 1);
2075         spin_unlock_irqrestore(&ioapic_lock, flags);
2076
2077         return reg_01.bits.version;
2078 }
2079
2080
2081 int __init io_apic_get_redir_entries (int ioapic)
2082 {
2083         union IO_APIC_reg_01    reg_01;
2084         unsigned long flags;
2085
2086         spin_lock_irqsave(&ioapic_lock, flags);
2087         reg_01.raw = io_apic_read(ioapic, 1);
2088         spin_unlock_irqrestore(&ioapic_lock, flags);
2089
2090         return reg_01.bits.entries;
2091 }
2092
2093
2094 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2095 {
2096         struct IO_APIC_route_entry entry;
2097         unsigned long flags;
2098
2099         if (!IO_APIC_IRQ(irq)) {
2100                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2101                         ioapic);
2102                 return -EINVAL;
2103         }
2104
2105         /*
2106          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2107          * Note that we mask (disable) IRQs now -- these get enabled when the
2108          * corresponding device driver registers for this IRQ.
2109          */
2110
2111         memset(&entry,0,sizeof(entry));
2112
2113         entry.delivery_mode = INT_DELIVERY_MODE;
2114         entry.dest_mode = INT_DEST_MODE;
2115         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2116         entry.trigger = triggering;
2117         entry.polarity = polarity;
2118         entry.mask = 1;                                  /* Disabled (masked) */
2119
2120         irq = gsi_irq_sharing(irq);
2121         /*
2122          * IRQs < 16 are already in the irq_2_pin[] map
2123          */
2124         if (irq >= 16)
2125                 add_pin_to_irq(irq, ioapic, pin);
2126
2127         entry.vector = assign_irq_vector(irq);
2128
2129         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2130                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2131                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2132                triggering, polarity);
2133
2134         ioapic_register_intr(irq, entry.vector, triggering);
2135
2136         if (!ioapic && (irq < 16))
2137                 disable_8259A_irq(irq);
2138
2139         spin_lock_irqsave(&ioapic_lock, flags);
2140         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2141         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2142         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2143         spin_unlock_irqrestore(&ioapic_lock, flags);
2144
2145         return 0;
2146 }
2147
2148 #endif /* CONFIG_ACPI */
2149
2150
2151 /*
2152  * This function currently is only a helper for the i386 smp boot process where
2153  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2154  * so mask in all cases should simply be TARGET_CPUS
2155  */
2156 #ifdef CONFIG_SMP
2157 void __init setup_ioapic_dest(void)
2158 {
2159         int pin, ioapic, irq, irq_entry;
2160
2161         if (skip_ioapic_setup == 1)
2162                 return;
2163
2164         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2165                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2166                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2167                         if (irq_entry == -1)
2168                                 continue;
2169                         irq = pin_2_irq(irq_entry, ioapic, pin);
2170                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2171                 }
2172
2173         }
2174 }
2175 #endif