arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30 #include <linux/tboot.h>
  31 #include "kvm_cache_regs.h"
  32 #include "x86.h"
  33
  34 #include <asm/io.h>
  35 #include <asm/desc.h>
  36 #include <asm/vmx.h>
  37 #include <asm/virtext.h>
  38 #include <asm/mce.h>
  39
  40 #include "trace.h"
  41
  42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  43
  44 MODULE_AUTHOR("Qumranet");
  45 MODULE_LICENSE("GPL");
  46
  47 static int __read_mostly bypass_guest_pf = 1;
  48 module_param(bypass_guest_pf, bool, S_IRUGO);
  49
  50 static int __read_mostly enable_vpid = 1;
  51 module_param_named(vpid, enable_vpid, bool, 0444);
  52
  53 static int __read_mostly flexpriority_enabled = 1;
  54 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  55
  56 static int __read_mostly enable_ept = 1;
  57 module_param_named(ept, enable_ept, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_unrestricted_guest = 1;
  60 module_param_named(unrestricted_guest,
  61                         enable_unrestricted_guest, bool, S_IRUGO);
  62
  63 static int __read_mostly emulate_invalid_guest_state = 0;
  64 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  65
  66 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  67         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  68 #define KVM_GUEST_CR0_MASK                                              \
  69         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  70 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  71         (X86_CR0_WP | X86_CR0_NE)
  72 #define KVM_VM_CR0_ALWAYS_ON                                            \
  73         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  74 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  75         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  76          | X86_CR4_OSXMMEXCPT)
  77
  78 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  79 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  80
  81 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  82
  83 /*
  84  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  85  * ple_gap:    upper bound on the amount of time between two successive
  86  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  87  *             According to test, this time is usually small than 41 cycles.
  88  * ple_window: upper bound on the amount of time a guest is allowed to execute
  89  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  90  *             less than 2^12 cycles
  91  * Time is measured based on a counter that runs at the same rate as the TSC,
  92  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  93  */
  94 #define KVM_VMX_DEFAULT_PLE_GAP    41
  95 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  96 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  97 module_param(ple_gap, int, S_IRUGO);
  98
  99 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 100 module_param(ple_window, int, S_IRUGO);
 101
 102 #define NR_AUTOLOAD_MSRS 1
 103
 104 struct vmcs {
 105         u32 revision_id;
 106         u32 abort;
 107         char data[0];
 108 };
 109
 110 struct shared_msr_entry {
 111         unsigned index;
 112         u64 data;
 113         u64 mask;
 114 };
 115
 116 struct vcpu_vmx {
 117         struct kvm_vcpu       vcpu;
 118         struct list_head      local_vcpus_link;
 119         unsigned long         host_rsp;
 120         int                   launched;
 121         u8                    fail;
 122         u32                   idt_vectoring_info;
 123         struct shared_msr_entry *guest_msrs;
 124         int                   nmsrs;
 125         int                   save_nmsrs;
 126 #ifdef CONFIG_X86_64
 127         u64                   msr_host_kernel_gs_base;
 128         u64                   msr_guest_kernel_gs_base;
 129 #endif
 130         struct vmcs          *vmcs;
 131         struct msr_autoload {
 132                 unsigned nr;
 133                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 134                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 135         } msr_autoload;
 136         struct {
 137                 int           loaded;
 138                 u16           fs_sel, gs_sel, ldt_sel;
 139                 int           gs_ldt_reload_needed;
 140                 int           fs_reload_needed;
 141         } host_state;
 142         struct {
 143                 int vm86_active;
 144                 ulong save_rflags;
 145                 struct kvm_save_segment {
 146                         u16 selector;
 147                         unsigned long base;
 148                         u32 limit;
 149                         u32 ar;
 150                 } tr, es, ds, fs, gs;
 151                 struct {
 152                         bool pending;
 153                         u8 vector;
 154                         unsigned rip;
 155                 } irq;
 156         } rmode;
 157         int vpid;
 158         bool emulation_required;
 159
 160         /* Support for vnmi-less CPUs */
 161         int soft_vnmi_blocked;
 162         ktime_t entry_time;
 163         s64 vnmi_blocked_time;
 164         u32 exit_reason;
 165
 166         bool rdtscp_enabled;
 167 };
 168
 169 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 170 {
 171         return container_of(vcpu, struct vcpu_vmx, vcpu);
 172 }
 173
 174 static int init_rmode(struct kvm *kvm);
 175 static u64 construct_eptp(unsigned long root_hpa);
 176
 177 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 178 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 179 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 180
 181 static unsigned long *vmx_io_bitmap_a;
 182 static unsigned long *vmx_io_bitmap_b;
 183 static unsigned long *vmx_msr_bitmap_legacy;
 184 static unsigned long *vmx_msr_bitmap_longmode;
 185
 186 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 187 static DEFINE_SPINLOCK(vmx_vpid_lock);
 188
 189 static struct vmcs_config {
 190         int size;
 191         int order;
 192         u32 revision_id;
 193         u32 pin_based_exec_ctrl;
 194         u32 cpu_based_exec_ctrl;
 195         u32 cpu_based_2nd_exec_ctrl;
 196         u32 vmexit_ctrl;
 197         u32 vmentry_ctrl;
 198 } vmcs_config;
 199
 200 static struct vmx_capability {
 201         u32 ept;
 202         u32 vpid;
 203 } vmx_capability;
 204
 205 #define VMX_SEGMENT_FIELD(seg)                                  \
 206         [VCPU_SREG_##seg] = {                                   \
 207                 .selector = GUEST_##seg##_SELECTOR,             \
 208                 .base = GUEST_##seg##_BASE,                     \
 209                 .limit = GUEST_##seg##_LIMIT,                   \
 210                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 211         }
 212
 213 static struct kvm_vmx_segment_field {
 214         unsigned selector;
 215         unsigned base;
 216         unsigned limit;
 217         unsigned ar_bytes;
 218 } kvm_vmx_segment_fields[] = {
 219         VMX_SEGMENT_FIELD(CS),
 220         VMX_SEGMENT_FIELD(DS),
 221         VMX_SEGMENT_FIELD(ES),
 222         VMX_SEGMENT_FIELD(FS),
 223         VMX_SEGMENT_FIELD(GS),
 224         VMX_SEGMENT_FIELD(SS),
 225         VMX_SEGMENT_FIELD(TR),
 226         VMX_SEGMENT_FIELD(LDTR),
 227 };
 228
 229 static u64 host_efer;
 230
 231 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 232
 233 /*
 234  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 235  * away by decrementing the array size.
 236  */
 237 static const u32 vmx_msr_index[] = {
 238 #ifdef CONFIG_X86_64
 239         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 240 #endif
 241         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 242 };
 243 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 244
 245 static inline bool is_page_fault(u32 intr_info)
 246 {
 247         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 248                              INTR_INFO_VALID_MASK)) ==
 249                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 250 }
 251
 252 static inline bool is_no_device(u32 intr_info)
 253 {
 254         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 255                              INTR_INFO_VALID_MASK)) ==
 256                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 257 }
 258
 259 static inline bool is_invalid_opcode(u32 intr_info)
 260 {
 261         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 262                              INTR_INFO_VALID_MASK)) ==
 263                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 264 }
 265
 266 static inline bool is_external_interrupt(u32 intr_info)
 267 {
 268         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 269                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 270 }
 271
 272 static inline bool is_machine_check(u32 intr_info)
 273 {
 274         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 275                              INTR_INFO_VALID_MASK)) ==
 276                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 277 }
 278
 279 static inline bool cpu_has_vmx_msr_bitmap(void)
 280 {
 281         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 282 }
 283
 284 static inline bool cpu_has_vmx_tpr_shadow(void)
 285 {
 286         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 287 }
 288
 289 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 290 {
 291         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 292 }
 293
 294 static inline bool cpu_has_secondary_exec_ctrls(void)
 295 {
 296         return vmcs_config.cpu_based_exec_ctrl &
 297                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 298 }
 299
 300 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 301 {
 302         return vmcs_config.cpu_based_2nd_exec_ctrl &
 303                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 304 }
 305
 306 static inline bool cpu_has_vmx_flexpriority(void)
 307 {
 308         return cpu_has_vmx_tpr_shadow() &&
 309                 cpu_has_vmx_virtualize_apic_accesses();
 310 }
 311
 312 static inline bool cpu_has_vmx_ept_execute_only(void)
 313 {
 314         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 315 }
 316
 317 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 318 {
 319         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 320 }
 321
 322 static inline bool cpu_has_vmx_eptp_writeback(void)
 323 {
 324         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 325 }
 326
 327 static inline bool cpu_has_vmx_ept_2m_page(void)
 328 {
 329         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 330 }
 331
 332 static inline bool cpu_has_vmx_ept_1g_page(void)
 333 {
 334         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 335 }
 336
 337 static inline bool cpu_has_vmx_invept_individual_addr(void)
 338 {
 339         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 340 }
 341
 342 static inline bool cpu_has_vmx_invept_context(void)
 343 {
 344         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 345 }
 346
 347 static inline bool cpu_has_vmx_invept_global(void)
 348 {
 349         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 350 }
 351
 352 static inline bool cpu_has_vmx_ept(void)
 353 {
 354         return vmcs_config.cpu_based_2nd_exec_ctrl &
 355                 SECONDARY_EXEC_ENABLE_EPT;
 356 }
 357
 358 static inline bool cpu_has_vmx_unrestricted_guest(void)
 359 {
 360         return vmcs_config.cpu_based_2nd_exec_ctrl &
 361                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 362 }
 363
 364 static inline bool cpu_has_vmx_ple(void)
 365 {
 366         return vmcs_config.cpu_based_2nd_exec_ctrl &
 367                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 368 }
 369
 370 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 371 {
 372         return flexpriority_enabled && irqchip_in_kernel(kvm);
 373 }
 374
 375 static inline bool cpu_has_vmx_vpid(void)
 376 {
 377         return vmcs_config.cpu_based_2nd_exec_ctrl &
 378                 SECONDARY_EXEC_ENABLE_VPID;
 379 }
 380
 381 static inline bool cpu_has_vmx_rdtscp(void)
 382 {
 383         return vmcs_config.cpu_based_2nd_exec_ctrl &
 384                 SECONDARY_EXEC_RDTSCP;
 385 }
 386
 387 static inline bool cpu_has_virtual_nmis(void)
 388 {
 389         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 390 }
 391
 392 static inline bool report_flexpriority(void)
 393 {
 394         return flexpriority_enabled;
 395 }
 396
 397 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 398 {
 399         int i;
 400
 401         for (i = 0; i < vmx->nmsrs; ++i)
 402                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 403                         return i;
 404         return -1;
 405 }
 406
 407 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 408 {
 409     struct {
 410         u64 vpid : 16;
 411         u64 rsvd : 48;
 412         u64 gva;
 413     } operand = { vpid, 0, gva };
 414
 415     asm volatile (__ex(ASM_VMX_INVVPID)
 416                   /* CF==1 or ZF==1 --> rc = -1 */
 417                   "; ja 1f ; ud2 ; 1:"
 418                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 419 }
 420
 421 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 422 {
 423         struct {
 424                 u64 eptp, gpa;
 425         } operand = {eptp, gpa};
 426
 427         asm volatile (__ex(ASM_VMX_INVEPT)
 428                         /* CF==1 or ZF==1 --> rc = -1 */
 429                         "; ja 1f ; ud2 ; 1:\n"
 430                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 431 }
 432
 433 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 434 {
 435         int i;
 436
 437         i = __find_msr_index(vmx, msr);
 438         if (i >= 0)
 439                 return &vmx->guest_msrs[i];
 440         return NULL;
 441 }
 442
 443 static void vmcs_clear(struct vmcs *vmcs)
 444 {
 445         u64 phys_addr = __pa(vmcs);
 446         u8 error;
 447
 448         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 449                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 450                       : "cc", "memory");
 451         if (error)
 452                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 453                        vmcs, phys_addr);
 454 }
 455
 456 static void __vcpu_clear(void *arg)
 457 {
 458         struct vcpu_vmx *vmx = arg;
 459         int cpu = raw_smp_processor_id();
 460
 461         if (vmx->vcpu.cpu == cpu)
 462                 vmcs_clear(vmx->vmcs);
 463         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 464                 per_cpu(current_vmcs, cpu) = NULL;
 465         rdtscll(vmx->vcpu.arch.host_tsc);
 466         list_del(&vmx->local_vcpus_link);
 467         vmx->vcpu.cpu = -1;
 468         vmx->launched = 0;
 469 }
 470
 471 static void vcpu_clear(struct vcpu_vmx *vmx)
 472 {
 473         if (vmx->vcpu.cpu == -1)
 474                 return;
 475         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 476 }
 477
 478 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 479 {
 480         if (vmx->vpid == 0)
 481                 return;
 482
 483         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 484 }
 485
 486 static inline void ept_sync_global(void)
 487 {
 488         if (cpu_has_vmx_invept_global())
 489                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 490 }
 491
 492 static inline void ept_sync_context(u64 eptp)
 493 {
 494         if (enable_ept) {
 495                 if (cpu_has_vmx_invept_context())
 496                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 497                 else
 498                         ept_sync_global();
 499         }
 500 }
 501
 502 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 503 {
 504         if (enable_ept) {
 505                 if (cpu_has_vmx_invept_individual_addr())
 506                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 507                                         eptp, gpa);
 508                 else
 509                         ept_sync_context(eptp);
 510         }
 511 }
 512
 513 static unsigned long vmcs_readl(unsigned long field)
 514 {
 515         unsigned long value;
 516
 517         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 518                       : "=a"(value) : "d"(field) : "cc");
 519         return value;
 520 }
 521
 522 static u16 vmcs_read16(unsigned long field)
 523 {
 524         return vmcs_readl(field);
 525 }
 526
 527 static u32 vmcs_read32(unsigned long field)
 528 {
 529         return vmcs_readl(field);
 530 }
 531
 532 static u64 vmcs_read64(unsigned long field)
 533 {
 534 #ifdef CONFIG_X86_64
 535         return vmcs_readl(field);
 536 #else
 537         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 538 #endif
 539 }
 540
 541 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 542 {
 543         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 544                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 545         dump_stack();
 546 }
 547
 548 static void vmcs_writel(unsigned long field, unsigned long value)
 549 {
 550         u8 error;
 551
 552         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 553                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 554         if (unlikely(error))
 555                 vmwrite_error(field, value);
 556 }
 557
 558 static void vmcs_write16(unsigned long field, u16 value)
 559 {
 560         vmcs_writel(field, value);
 561 }
 562
 563 static void vmcs_write32(unsigned long field, u32 value)
 564 {
 565         vmcs_writel(field, value);
 566 }
 567
 568 static void vmcs_write64(unsigned long field, u64 value)
 569 {
 570         vmcs_writel(field, value);
 571 #ifndef CONFIG_X86_64
 572         asm volatile ("");
 573         vmcs_writel(field+1, value >> 32);
 574 #endif
 575 }
 576
 577 static void vmcs_clear_bits(unsigned long field, u32 mask)
 578 {
 579         vmcs_writel(field, vmcs_readl(field) & ~mask);
 580 }
 581
 582 static void vmcs_set_bits(unsigned long field, u32 mask)
 583 {
 584         vmcs_writel(field, vmcs_readl(field) | mask);
 585 }
 586
 587 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 588 {
 589         u32 eb;
 590
 591         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 592              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 593         if ((vcpu->guest_debug &
 594              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 595             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 596                 eb |= 1u << BP_VECTOR;
 597         if (to_vmx(vcpu)->rmode.vm86_active)
 598                 eb = ~0;
 599         if (enable_ept)
 600                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 601         if (vcpu->fpu_active)
 602                 eb &= ~(1u << NM_VECTOR);
 603         vmcs_write32(EXCEPTION_BITMAP, eb);
 604 }
 605
 606 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 607 {
 608         unsigned i;
 609         struct msr_autoload *m = &vmx->msr_autoload;
 610
 611         for (i = 0; i < m->nr; ++i)
 612                 if (m->guest[i].index == msr)
 613                         break;
 614
 615         if (i == m->nr)
 616                 return;
 617         --m->nr;
 618         m->guest[i] = m->guest[m->nr];
 619         m->host[i] = m->host[m->nr];
 620         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 621         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 622 }
 623
 624 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 625                                   u64 guest_val, u64 host_val)
 626 {
 627         unsigned i;
 628         struct msr_autoload *m = &vmx->msr_autoload;
 629
 630         for (i = 0; i < m->nr; ++i)
 631                 if (m->guest[i].index == msr)
 632                         break;
 633
 634         if (i == m->nr) {
 635                 ++m->nr;
 636                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 637                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 638         }
 639
 640         m->guest[i].index = msr;
 641         m->guest[i].value = guest_val;
 642         m->host[i].index = msr;
 643         m->host[i].value = host_val;
 644 }
 645
 646 static void reload_tss(void)
 647 {
 648         /*
 649          * VT restores TR but not its size.  Useless.
 650          */
 651         struct desc_ptr gdt;
 652         struct desc_struct *descs;
 653
 654         native_store_gdt(&gdt);
 655         descs = (void *)gdt.address;
 656         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 657         load_TR_desc();
 658 }
 659
 660 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 661 {
 662         u64 guest_efer;
 663         u64 ignore_bits;
 664
 665         guest_efer = vmx->vcpu.arch.efer;
 666
 667         /*
 668          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 669          * outside long mode
 670          */
 671         ignore_bits = EFER_NX | EFER_SCE;
 672 #ifdef CONFIG_X86_64
 673         ignore_bits |= EFER_LMA | EFER_LME;
 674         /* SCE is meaningful only in long mode on Intel */
 675         if (guest_efer & EFER_LMA)
 676                 ignore_bits &= ~(u64)EFER_SCE;
 677 #endif
 678         guest_efer &= ~ignore_bits;
 679         guest_efer |= host_efer & ignore_bits;
 680         vmx->guest_msrs[efer_offset].data = guest_efer;
 681         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 682
 683         clear_atomic_switch_msr(vmx, MSR_EFER);
 684         /* On ept, can't emulate nx, and must switch nx atomically */
 685         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 686                 guest_efer = vmx->vcpu.arch.efer;
 687                 if (!(guest_efer & EFER_LMA))
 688                         guest_efer &= ~EFER_LME;
 689                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 690                 return false;
 691         }
 692
 693         return true;
 694 }
 695
 696 static unsigned long segment_base(u16 selector)
 697 {
 698         struct desc_ptr gdt;
 699         struct desc_struct *d;
 700         unsigned long table_base;
 701         unsigned long v;
 702
 703         if (!(selector & ~3))
 704                 return 0;
 705
 706         native_store_gdt(&gdt);
 707         table_base = gdt.address;
 708
 709         if (selector & 4) {           /* from ldt */
 710                 u16 ldt_selector = kvm_read_ldt();
 711
 712                 if (!(ldt_selector & ~3))
 713                         return 0;
 714
 715                 table_base = segment_base(ldt_selector);
 716         }
 717         d = (struct desc_struct *)(table_base + (selector & ~7));
 718         v = get_desc_base(d);
 719 #ifdef CONFIG_X86_64
 720        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 721                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 722 #endif
 723         return v;
 724 }
 725
 726 static inline unsigned long kvm_read_tr_base(void)
 727 {
 728         u16 tr;
 729         asm("str %0" : "=g"(tr));
 730         return segment_base(tr);
 731 }
 732
 733 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 734 {
 735         struct vcpu_vmx *vmx = to_vmx(vcpu);
 736         int i;
 737
 738         if (vmx->host_state.loaded)
 739                 return;
 740
 741         vmx->host_state.loaded = 1;
 742         /*
 743          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 744          * allow segment selectors with cpl > 0 or ti == 1.
 745          */
 746         vmx->host_state.ldt_sel = kvm_read_ldt();
 747         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 748         vmx->host_state.fs_sel = kvm_read_fs();
 749         if (!(vmx->host_state.fs_sel & 7)) {
 750                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 751                 vmx->host_state.fs_reload_needed = 0;
 752         } else {
 753                 vmcs_write16(HOST_FS_SELECTOR, 0);
 754                 vmx->host_state.fs_reload_needed = 1;
 755         }
 756         vmx->host_state.gs_sel = kvm_read_gs();
 757         if (!(vmx->host_state.gs_sel & 7))
 758                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 759         else {
 760                 vmcs_write16(HOST_GS_SELECTOR, 0);
 761                 vmx->host_state.gs_ldt_reload_needed = 1;
 762         }
 763
 764 #ifdef CONFIG_X86_64
 765         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 766         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 767 #else
 768         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 769         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 770 #endif
 771
 772 #ifdef CONFIG_X86_64
 773         if (is_long_mode(&vmx->vcpu)) {
 774                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 775                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 776         }
 777 #endif
 778         for (i = 0; i < vmx->save_nmsrs; ++i)
 779                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 780                                    vmx->guest_msrs[i].data,
 781                                    vmx->guest_msrs[i].mask);
 782 }
 783
 784 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 785 {
 786         unsigned long flags;
 787
 788         if (!vmx->host_state.loaded)
 789                 return;
 790
 791         ++vmx->vcpu.stat.host_state_reload;
 792         vmx->host_state.loaded = 0;
 793         if (vmx->host_state.fs_reload_needed)
 794                 kvm_load_fs(vmx->host_state.fs_sel);
 795         if (vmx->host_state.gs_ldt_reload_needed) {
 796                 kvm_load_ldt(vmx->host_state.ldt_sel);
 797                 /*
 798                  * If we have to reload gs, we must take care to
 799                  * preserve our gs base.
 800                  */
 801                 local_irq_save(flags);
 802                 kvm_load_gs(vmx->host_state.gs_sel);
 803 #ifdef CONFIG_X86_64
 804                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 805 #endif
 806                 local_irq_restore(flags);
 807         }
 808         reload_tss();
 809 #ifdef CONFIG_X86_64
 810         if (is_long_mode(&vmx->vcpu)) {
 811                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 812                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 813         }
 814 #endif
 815 }
 816
 817 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 818 {
 819         preempt_disable();
 820         __vmx_load_host_state(vmx);
 821         preempt_enable();
 822 }
 823
 824 /*
 825  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 826  * vcpu mutex is already taken.
 827  */
 828 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 829 {
 830         struct vcpu_vmx *vmx = to_vmx(vcpu);
 831         u64 phys_addr = __pa(vmx->vmcs);
 832         u64 tsc_this, delta, new_offset;
 833
 834         if (vcpu->cpu != cpu) {
 835                 vcpu_clear(vmx);
 836                 kvm_migrate_timers(vcpu);
 837                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 838                 local_irq_disable();
 839                 list_add(&vmx->local_vcpus_link,
 840                          &per_cpu(vcpus_on_cpu, cpu));
 841                 local_irq_enable();
 842         }
 843
 844         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 845                 u8 error;
 846
 847                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 848                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 849                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 850                               : "cc");
 851                 if (error)
 852                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 853                                vmx->vmcs, phys_addr);
 854         }
 855
 856         if (vcpu->cpu != cpu) {
 857                 struct desc_ptr dt;
 858                 unsigned long sysenter_esp;
 859
 860                 vcpu->cpu = cpu;
 861                 /*
 862                  * Linux uses per-cpu TSS and GDT, so set these when switching
 863                  * processors.
 864                  */
 865                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 866                 native_store_gdt(&dt);
 867                 vmcs_writel(HOST_GDTR_BASE, dt.address);   /* 22.2.4 */
 868
 869                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 870                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 871
 872                 /*
 873                  * Make sure the time stamp counter is monotonous.
 874                  */
 875                 rdtscll(tsc_this);
 876                 if (tsc_this < vcpu->arch.host_tsc) {
 877                         delta = vcpu->arch.host_tsc - tsc_this;
 878                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 879                         vmcs_write64(TSC_OFFSET, new_offset);
 880                 }
 881         }
 882 }
 883
 884 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 885 {
 886         __vmx_load_host_state(to_vmx(vcpu));
 887 }
 888
 889 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 890 {
 891         ulong cr0;
 892
 893         if (vcpu->fpu_active)
 894                 return;
 895         vcpu->fpu_active = 1;
 896         cr0 = vmcs_readl(GUEST_CR0);
 897         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 898         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 899         vmcs_writel(GUEST_CR0, cr0);
 900         update_exception_bitmap(vcpu);
 901         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 902         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 903 }
 904
 905 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 906
 907 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 908 {
 909         vmx_decache_cr0_guest_bits(vcpu);
 910         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 911         update_exception_bitmap(vcpu);
 912         vcpu->arch.cr0_guest_owned_bits = 0;
 913         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 914         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 915 }
 916
 917 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 918 {
 919         unsigned long rflags, save_rflags;
 920
 921         rflags = vmcs_readl(GUEST_RFLAGS);
 922         if (to_vmx(vcpu)->rmode.vm86_active) {
 923                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 924                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 925                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 926         }
 927         return rflags;
 928 }
 929
 930 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 931 {
 932         if (to_vmx(vcpu)->rmode.vm86_active) {
 933                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 934                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 935         }
 936         vmcs_writel(GUEST_RFLAGS, rflags);
 937 }
 938
 939 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 940 {
 941         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 942         int ret = 0;
 943
 944         if (interruptibility & GUEST_INTR_STATE_STI)
 945                 ret |= KVM_X86_SHADOW_INT_STI;
 946         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 947                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 948
 949         return ret & mask;
 950 }
 951
 952 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 953 {
 954         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 955         u32 interruptibility = interruptibility_old;
 956
 957         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 958
 959         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
 960                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 961         else if (mask & KVM_X86_SHADOW_INT_STI)
 962                 interruptibility |= GUEST_INTR_STATE_STI;
 963
 964         if ((interruptibility != interruptibility_old))
 965                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 966 }
 967
 968 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 969 {
 970         unsigned long rip;
 971
 972         rip = kvm_rip_read(vcpu);
 973         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 974         kvm_rip_write(vcpu, rip);
 975
 976         /* skipping an emulated instruction also counts */
 977         vmx_set_interrupt_shadow(vcpu, 0);
 978 }
 979
 980 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 981                                 bool has_error_code, u32 error_code,
 982                                 bool reinject)
 983 {
 984         struct vcpu_vmx *vmx = to_vmx(vcpu);
 985         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 986
 987         if (has_error_code) {
 988                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 989                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 990         }
 991
 992         if (vmx->rmode.vm86_active) {
 993                 vmx->rmode.irq.pending = true;
 994                 vmx->rmode.irq.vector = nr;
 995                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 996                 if (kvm_exception_is_soft(nr))
 997                         vmx->rmode.irq.rip +=
 998                                 vmx->vcpu.arch.event_exit_inst_len;
 999                 intr_info |= INTR_TYPE_SOFT_INTR;
1000                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1001                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1002                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1003                 return;
1004         }
1005
1006         if (kvm_exception_is_soft(nr)) {
1007                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1008                              vmx->vcpu.arch.event_exit_inst_len);
1009                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1010         } else
1011                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1012
1013         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1014 }
1015
1016 static bool vmx_rdtscp_supported(void)
1017 {
1018         return cpu_has_vmx_rdtscp();
1019 }
1020
1021 /*
1022  * Swap MSR entry in host/guest MSR entry array.
1023  */
1024 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1025 {
1026         struct shared_msr_entry tmp;
1027
1028         tmp = vmx->guest_msrs[to];
1029         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1030         vmx->guest_msrs[from] = tmp;
1031 }
1032
1033 /*
1034  * Set up the vmcs to automatically save and restore system
1035  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1036  * mode, as fiddling with msrs is very expensive.
1037  */
1038 static void setup_msrs(struct vcpu_vmx *vmx)
1039 {
1040         int save_nmsrs, index;
1041         unsigned long *msr_bitmap;
1042
1043         vmx_load_host_state(vmx);
1044         save_nmsrs = 0;
1045 #ifdef CONFIG_X86_64
1046         if (is_long_mode(&vmx->vcpu)) {
1047                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1048                 if (index >= 0)
1049                         move_msr_up(vmx, index, save_nmsrs++);
1050                 index = __find_msr_index(vmx, MSR_LSTAR);
1051                 if (index >= 0)
1052                         move_msr_up(vmx, index, save_nmsrs++);
1053                 index = __find_msr_index(vmx, MSR_CSTAR);
1054                 if (index >= 0)
1055                         move_msr_up(vmx, index, save_nmsrs++);
1056                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1057                 if (index >= 0 && vmx->rdtscp_enabled)
1058                         move_msr_up(vmx, index, save_nmsrs++);
1059                 /*
1060                  * MSR_K6_STAR is only needed on long mode guests, and only
1061                  * if efer.sce is enabled.
1062                  */
1063                 index = __find_msr_index(vmx, MSR_K6_STAR);
1064                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1065                         move_msr_up(vmx, index, save_nmsrs++);
1066         }
1067 #endif
1068         index = __find_msr_index(vmx, MSR_EFER);
1069         if (index >= 0 && update_transition_efer(vmx, index))
1070                 move_msr_up(vmx, index, save_nmsrs++);
1071
1072         vmx->save_nmsrs = save_nmsrs;
1073
1074         if (cpu_has_vmx_msr_bitmap()) {
1075                 if (is_long_mode(&vmx->vcpu))
1076                         msr_bitmap = vmx_msr_bitmap_longmode;
1077                 else
1078                         msr_bitmap = vmx_msr_bitmap_legacy;
1079
1080                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1081         }
1082 }
1083
1084 /*
1085  * reads and returns guest's timestamp counter "register"
1086  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1087  */
1088 static u64 guest_read_tsc(void)
1089 {
1090         u64 host_tsc, tsc_offset;
1091
1092         rdtscll(host_tsc);
1093         tsc_offset = vmcs_read64(TSC_OFFSET);
1094         return host_tsc + tsc_offset;
1095 }
1096
1097 /*
1098  * writes 'guest_tsc' into guest's timestamp counter "register"
1099  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1100  */
1101 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1102 {
1103         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1104 }
1105
1106 /*
1107  * Reads an msr value (of 'msr_index') into 'pdata'.
1108  * Returns 0 on success, non-0 otherwise.
1109  * Assumes vcpu_load() was already called.
1110  */
1111 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1112 {
1113         u64 data;
1114         struct shared_msr_entry *msr;
1115
1116         if (!pdata) {
1117                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1118                 return -EINVAL;
1119         }
1120
1121         switch (msr_index) {
1122 #ifdef CONFIG_X86_64
1123         case MSR_FS_BASE:
1124                 data = vmcs_readl(GUEST_FS_BASE);
1125                 break;
1126         case MSR_GS_BASE:
1127                 data = vmcs_readl(GUEST_GS_BASE);
1128                 break;
1129         case MSR_KERNEL_GS_BASE:
1130                 vmx_load_host_state(to_vmx(vcpu));
1131                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1132                 break;
1133 #endif
1134         case MSR_EFER:
1135                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1136         case MSR_IA32_TSC:
1137                 data = guest_read_tsc();
1138                 break;
1139         case MSR_IA32_SYSENTER_CS:
1140                 data = vmcs_read32(GUEST_SYSENTER_CS);
1141                 break;
1142         case MSR_IA32_SYSENTER_EIP:
1143                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1144                 break;
1145         case MSR_IA32_SYSENTER_ESP:
1146                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1147                 break;
1148         case MSR_TSC_AUX:
1149                 if (!to_vmx(vcpu)->rdtscp_enabled)
1150                         return 1;
1151                 /* Otherwise falls through */
1152         default:
1153                 vmx_load_host_state(to_vmx(vcpu));
1154                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1155                 if (msr) {
1156                         vmx_load_host_state(to_vmx(vcpu));
1157                         data = msr->data;
1158                         break;
1159                 }
1160                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1161         }
1162
1163         *pdata = data;
1164         return 0;
1165 }
1166
1167 /*
1168  * Writes msr value into into the appropriate "register".
1169  * Returns 0 on success, non-0 otherwise.
1170  * Assumes vcpu_load() was already called.
1171  */
1172 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1173 {
1174         struct vcpu_vmx *vmx = to_vmx(vcpu);
1175         struct shared_msr_entry *msr;
1176         u64 host_tsc;
1177         int ret = 0;
1178
1179         switch (msr_index) {
1180         case MSR_EFER:
1181                 vmx_load_host_state(vmx);
1182                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1183                 break;
1184 #ifdef CONFIG_X86_64
1185         case MSR_FS_BASE:
1186                 vmcs_writel(GUEST_FS_BASE, data);
1187                 break;
1188         case MSR_GS_BASE:
1189                 vmcs_writel(GUEST_GS_BASE, data);
1190                 break;
1191         case MSR_KERNEL_GS_BASE:
1192                 vmx_load_host_state(vmx);
1193                 vmx->msr_guest_kernel_gs_base = data;
1194                 break;
1195 #endif
1196         case MSR_IA32_SYSENTER_CS:
1197                 vmcs_write32(GUEST_SYSENTER_CS, data);
1198                 break;
1199         case MSR_IA32_SYSENTER_EIP:
1200                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1201                 break;
1202         case MSR_IA32_SYSENTER_ESP:
1203                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1204                 break;
1205         case MSR_IA32_TSC:
1206                 rdtscll(host_tsc);
1207                 guest_write_tsc(data, host_tsc);
1208                 break;
1209         case MSR_IA32_CR_PAT:
1210                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1211                         vmcs_write64(GUEST_IA32_PAT, data);
1212                         vcpu->arch.pat = data;
1213                         break;
1214                 }
1215                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1216                 break;
1217         case MSR_TSC_AUX:
1218                 if (!vmx->rdtscp_enabled)
1219                         return 1;
1220                 /* Check reserved bit, higher 32 bits should be zero */
1221                 if ((data >> 32) != 0)
1222                         return 1;
1223                 /* Otherwise falls through */
1224         default:
1225                 msr = find_msr_entry(vmx, msr_index);
1226                 if (msr) {
1227                         vmx_load_host_state(vmx);
1228                         msr->data = data;
1229                         break;
1230                 }
1231                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1232         }
1233
1234         return ret;
1235 }
1236
1237 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1238 {
1239         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1240         switch (reg) {
1241         case VCPU_REGS_RSP:
1242                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1243                 break;
1244         case VCPU_REGS_RIP:
1245                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1246                 break;
1247         case VCPU_EXREG_PDPTR:
1248                 if (enable_ept)
1249                         ept_save_pdptrs(vcpu);
1250                 break;
1251         default:
1252                 break;
1253         }
1254 }
1255
1256 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1257 {
1258         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1259                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1260         else
1261                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1262
1263         update_exception_bitmap(vcpu);
1264 }
1265
1266 static __init int cpu_has_kvm_support(void)
1267 {
1268         return cpu_has_vmx();
1269 }
1270
1271 static __init int vmx_disabled_by_bios(void)
1272 {
1273         u64 msr;
1274
1275         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1276         if (msr & FEATURE_CONTROL_LOCKED) {
1277                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1278                         && tboot_enabled())
1279                         return 1;
1280                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1281                         && !tboot_enabled())
1282                         return 1;
1283         }
1284
1285         return 0;
1286         /* locked but not enabled */
1287 }
1288
1289 static int hardware_enable(void *garbage)
1290 {
1291         int cpu = raw_smp_processor_id();
1292         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1293         u64 old, test_bits;
1294
1295         if (read_cr4() & X86_CR4_VMXE)
1296                 return -EBUSY;
1297
1298         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1299         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1300
1301         test_bits = FEATURE_CONTROL_LOCKED;
1302         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1303         if (tboot_enabled())
1304                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1305
1306         if ((old & test_bits) != test_bits) {
1307                 /* enable and lock */
1308                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1309         }
1310         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1311         asm volatile (ASM_VMX_VMXON_RAX
1312                       : : "a"(&phys_addr), "m"(phys_addr)
1313                       : "memory", "cc");
1314
1315         ept_sync_global();
1316
1317         return 0;
1318 }
1319
1320 static void vmclear_local_vcpus(void)
1321 {
1322         int cpu = raw_smp_processor_id();
1323         struct vcpu_vmx *vmx, *n;
1324
1325         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1326                                  local_vcpus_link)
1327                 __vcpu_clear(vmx);
1328 }
1329
1330
1331 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1332  * tricks.
1333  */
1334 static void kvm_cpu_vmxoff(void)
1335 {
1336         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1337         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1338 }
1339
1340 static void hardware_disable(void *garbage)
1341 {
1342         vmclear_local_vcpus();
1343         kvm_cpu_vmxoff();
1344 }
1345
1346 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1347                                       u32 msr, u32 *result)
1348 {
1349         u32 vmx_msr_low, vmx_msr_high;
1350         u32 ctl = ctl_min | ctl_opt;
1351
1352         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1353
1354         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1355         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1356
1357         /* Ensure minimum (required) set of control bits are supported. */
1358         if (ctl_min & ~ctl)
1359                 return -EIO;
1360
1361         *result = ctl;
1362         return 0;
1363 }
1364
1365 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1366 {
1367         u32 vmx_msr_low, vmx_msr_high;
1368         u32 min, opt, min2, opt2;
1369         u32 _pin_based_exec_control = 0;
1370         u32 _cpu_based_exec_control = 0;
1371         u32 _cpu_based_2nd_exec_control = 0;
1372         u32 _vmexit_control = 0;
1373         u32 _vmentry_control = 0;
1374
1375         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1376         opt = PIN_BASED_VIRTUAL_NMIS;
1377         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1378                                 &_pin_based_exec_control) < 0)
1379                 return -EIO;
1380
1381         min = CPU_BASED_HLT_EXITING |
1382 #ifdef CONFIG_X86_64
1383               CPU_BASED_CR8_LOAD_EXITING |
1384               CPU_BASED_CR8_STORE_EXITING |
1385 #endif
1386               CPU_BASED_CR3_LOAD_EXITING |
1387               CPU_BASED_CR3_STORE_EXITING |
1388               CPU_BASED_USE_IO_BITMAPS |
1389               CPU_BASED_MOV_DR_EXITING |
1390               CPU_BASED_USE_TSC_OFFSETING |
1391               CPU_BASED_MWAIT_EXITING |
1392               CPU_BASED_MONITOR_EXITING |
1393               CPU_BASED_INVLPG_EXITING;
1394         opt = CPU_BASED_TPR_SHADOW |
1395               CPU_BASED_USE_MSR_BITMAPS |
1396               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1397         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1398                                 &_cpu_based_exec_control) < 0)
1399                 return -EIO;
1400 #ifdef CONFIG_X86_64
1401         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1402                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1403                                            ~CPU_BASED_CR8_STORE_EXITING;
1404 #endif
1405         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1406                 min2 = 0;
1407                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1408                         SECONDARY_EXEC_WBINVD_EXITING |
1409                         SECONDARY_EXEC_ENABLE_VPID |
1410                         SECONDARY_EXEC_ENABLE_EPT |
1411                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1412                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1413                         SECONDARY_EXEC_RDTSCP;
1414                 if (adjust_vmx_controls(min2, opt2,
1415                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1416                                         &_cpu_based_2nd_exec_control) < 0)
1417                         return -EIO;
1418         }
1419 #ifndef CONFIG_X86_64
1420         if (!(_cpu_based_2nd_exec_control &
1421                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1422                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1423 #endif
1424         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1425                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1426                    enabled */
1427                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1428                                              CPU_BASED_CR3_STORE_EXITING |
1429                                              CPU_BASED_INVLPG_EXITING);
1430                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1431                       vmx_capability.ept, vmx_capability.vpid);
1432         }
1433
1434         min = 0;
1435 #ifdef CONFIG_X86_64
1436         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1437 #endif
1438         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1439         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1440                                 &_vmexit_control) < 0)
1441                 return -EIO;
1442
1443         min = 0;
1444         opt = VM_ENTRY_LOAD_IA32_PAT;
1445         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1446                                 &_vmentry_control) < 0)
1447                 return -EIO;
1448
1449         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1450
1451         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1452         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1453                 return -EIO;
1454
1455 #ifdef CONFIG_X86_64
1456         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1457         if (vmx_msr_high & (1u<<16))
1458                 return -EIO;
1459 #endif
1460
1461         /* Require Write-Back (WB) memory type for VMCS accesses. */
1462         if (((vmx_msr_high >> 18) & 15) != 6)
1463                 return -EIO;
1464
1465         vmcs_conf->size = vmx_msr_high & 0x1fff;
1466         vmcs_conf->order = get_order(vmcs_config.size);
1467         vmcs_conf->revision_id = vmx_msr_low;
1468
1469         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1470         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1471         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1472         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1473         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1474
1475         return 0;
1476 }
1477
1478 static struct vmcs *alloc_vmcs_cpu(int cpu)
1479 {
1480         int node = cpu_to_node(cpu);
1481         struct page *pages;
1482         struct vmcs *vmcs;
1483
1484         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1485         if (!pages)
1486                 return NULL;
1487         vmcs = page_address(pages);
1488         memset(vmcs, 0, vmcs_config.size);
1489         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1490         return vmcs;
1491 }
1492
1493 static struct vmcs *alloc_vmcs(void)
1494 {
1495         return alloc_vmcs_cpu(raw_smp_processor_id());
1496 }
1497
1498 static void free_vmcs(struct vmcs *vmcs)
1499 {
1500         free_pages((unsigned long)vmcs, vmcs_config.order);
1501 }
1502
1503 static void free_kvm_area(void)
1504 {
1505         int cpu;
1506
1507         for_each_possible_cpu(cpu) {
1508                 free_vmcs(per_cpu(vmxarea, cpu));
1509                 per_cpu(vmxarea, cpu) = NULL;
1510         }
1511 }
1512
1513 static __init int alloc_kvm_area(void)
1514 {
1515         int cpu;
1516
1517         for_each_possible_cpu(cpu) {
1518                 struct vmcs *vmcs;
1519
1520                 vmcs = alloc_vmcs_cpu(cpu);
1521                 if (!vmcs) {
1522                         free_kvm_area();
1523                         return -ENOMEM;
1524                 }
1525
1526                 per_cpu(vmxarea, cpu) = vmcs;
1527         }
1528         return 0;
1529 }
1530
1531 static __init int hardware_setup(void)
1532 {
1533         if (setup_vmcs_config(&vmcs_config) < 0)
1534                 return -EIO;
1535
1536         if (boot_cpu_has(X86_FEATURE_NX))
1537                 kvm_enable_efer_bits(EFER_NX);
1538
1539         if (!cpu_has_vmx_vpid())
1540                 enable_vpid = 0;
1541
1542         if (!cpu_has_vmx_ept()) {
1543                 enable_ept = 0;
1544                 enable_unrestricted_guest = 0;
1545         }
1546
1547         if (!cpu_has_vmx_unrestricted_guest())
1548                 enable_unrestricted_guest = 0;
1549
1550         if (!cpu_has_vmx_flexpriority())
1551                 flexpriority_enabled = 0;
1552
1553         if (!cpu_has_vmx_tpr_shadow())
1554                 kvm_x86_ops->update_cr8_intercept = NULL;
1555
1556         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1557                 kvm_disable_largepages();
1558
1559         if (!cpu_has_vmx_ple())
1560                 ple_gap = 0;
1561
1562         return alloc_kvm_area();
1563 }
1564
1565 static __exit void hardware_unsetup(void)
1566 {
1567         free_kvm_area();
1568 }
1569
1570 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1571 {
1572         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1573
1574         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1575                 vmcs_write16(sf->selector, save->selector);
1576                 vmcs_writel(sf->base, save->base);
1577                 vmcs_write32(sf->limit, save->limit);
1578                 vmcs_write32(sf->ar_bytes, save->ar);
1579         } else {
1580                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1581                         << AR_DPL_SHIFT;
1582                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1583         }
1584 }
1585
1586 static void enter_pmode(struct kvm_vcpu *vcpu)
1587 {
1588         unsigned long flags;
1589         struct vcpu_vmx *vmx = to_vmx(vcpu);
1590
1591         vmx->emulation_required = 1;
1592         vmx->rmode.vm86_active = 0;
1593
1594         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1595         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1596         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1597
1598         flags = vmcs_readl(GUEST_RFLAGS);
1599         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1600         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1601         vmcs_writel(GUEST_RFLAGS, flags);
1602
1603         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1604                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1605
1606         update_exception_bitmap(vcpu);
1607
1608         if (emulate_invalid_guest_state)
1609                 return;
1610
1611         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1612         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1613         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1614         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1615
1616         vmcs_write16(GUEST_SS_SELECTOR, 0);
1617         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1618
1619         vmcs_write16(GUEST_CS_SELECTOR,
1620                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1621         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1622 }
1623
1624 static gva_t rmode_tss_base(struct kvm *kvm)
1625 {
1626         if (!kvm->arch.tss_addr) {
1627                 struct kvm_memslots *slots;
1628                 gfn_t base_gfn;
1629
1630                 slots = kvm_memslots(kvm);
1631                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1632                                  kvm->memslots->memslots[0].npages - 3;
1633                 return base_gfn << PAGE_SHIFT;
1634         }
1635         return kvm->arch.tss_addr;
1636 }
1637
1638 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1639 {
1640         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1641
1642         save->selector = vmcs_read16(sf->selector);
1643         save->base = vmcs_readl(sf->base);
1644         save->limit = vmcs_read32(sf->limit);
1645         save->ar = vmcs_read32(sf->ar_bytes);
1646         vmcs_write16(sf->selector, save->base >> 4);
1647         vmcs_write32(sf->base, save->base & 0xfffff);
1648         vmcs_write32(sf->limit, 0xffff);
1649         vmcs_write32(sf->ar_bytes, 0xf3);
1650 }
1651
1652 static void enter_rmode(struct kvm_vcpu *vcpu)
1653 {
1654         unsigned long flags;
1655         struct vcpu_vmx *vmx = to_vmx(vcpu);
1656
1657         if (enable_unrestricted_guest)
1658                 return;
1659
1660         vmx->emulation_required = 1;
1661         vmx->rmode.vm86_active = 1;
1662
1663         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1664         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1665
1666         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1667         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1668
1669         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1670         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1671
1672         flags = vmcs_readl(GUEST_RFLAGS);
1673         vmx->rmode.save_rflags = flags;
1674
1675         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1676
1677         vmcs_writel(GUEST_RFLAGS, flags);
1678         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1679         update_exception_bitmap(vcpu);
1680
1681         if (emulate_invalid_guest_state)
1682                 goto continue_rmode;
1683
1684         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1685         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1686         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1687
1688         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1689         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1690         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1691                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1692         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1693
1694         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1695         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1696         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1697         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1698
1699 continue_rmode:
1700         kvm_mmu_reset_context(vcpu);
1701         init_rmode(vcpu->kvm);
1702 }
1703
1704 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1705 {
1706         struct vcpu_vmx *vmx = to_vmx(vcpu);
1707         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1708
1709         if (!msr)
1710                 return;
1711
1712         /*
1713          * Force kernel_gs_base reloading before EFER changes, as control
1714          * of this msr depends on is_long_mode().
1715          */
1716         vmx_load_host_state(to_vmx(vcpu));
1717         vcpu->arch.efer = efer;
1718         if (efer & EFER_LMA) {
1719                 vmcs_write32(VM_ENTRY_CONTROLS,
1720                              vmcs_read32(VM_ENTRY_CONTROLS) |
1721                              VM_ENTRY_IA32E_MODE);
1722                 msr->data = efer;
1723         } else {
1724                 vmcs_write32(VM_ENTRY_CONTROLS,
1725                              vmcs_read32(VM_ENTRY_CONTROLS) &
1726                              ~VM_ENTRY_IA32E_MODE);
1727
1728                 msr->data = efer & ~EFER_LME;
1729         }
1730         setup_msrs(vmx);
1731 }
1732
1733 #ifdef CONFIG_X86_64
1734
1735 static void enter_lmode(struct kvm_vcpu *vcpu)
1736 {
1737         u32 guest_tr_ar;
1738
1739         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1740         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1741                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1742                        __func__);
1743                 vmcs_write32(GUEST_TR_AR_BYTES,
1744                              (guest_tr_ar & ~AR_TYPE_MASK)
1745                              | AR_TYPE_BUSY_64_TSS);
1746         }
1747         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1748 }
1749
1750 static void exit_lmode(struct kvm_vcpu *vcpu)
1751 {
1752         vmcs_write32(VM_ENTRY_CONTROLS,
1753                      vmcs_read32(VM_ENTRY_CONTROLS)
1754                      & ~VM_ENTRY_IA32E_MODE);
1755         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1756 }
1757
1758 #endif
1759
1760 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1761 {
1762         vpid_sync_vcpu_all(to_vmx(vcpu));
1763         if (enable_ept)
1764                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1765 }
1766
1767 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1768 {
1769         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1770
1771         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1772         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1773 }
1774
1775 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1776 {
1777         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1778
1779         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1780         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1781 }
1782
1783 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1784 {
1785         if (!test_bit(VCPU_EXREG_PDPTR,
1786                       (unsigned long *)&vcpu->arch.regs_dirty))
1787                 return;
1788
1789         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1790                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1791                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1792                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1793                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1794         }
1795 }
1796
1797 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1798 {
1799         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1800                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1801                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1802                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1803                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1804         }
1805
1806         __set_bit(VCPU_EXREG_PDPTR,
1807                   (unsigned long *)&vcpu->arch.regs_avail);
1808         __set_bit(VCPU_EXREG_PDPTR,
1809                   (unsigned long *)&vcpu->arch.regs_dirty);
1810 }
1811
1812 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1813
1814 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1815                                         unsigned long cr0,
1816                                         struct kvm_vcpu *vcpu)
1817 {
1818         if (!(cr0 & X86_CR0_PG)) {
1819                 /* From paging/starting to nonpaging */
1820                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1821                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1822                              (CPU_BASED_CR3_LOAD_EXITING |
1823                               CPU_BASED_CR3_STORE_EXITING));
1824                 vcpu->arch.cr0 = cr0;
1825                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1826         } else if (!is_paging(vcpu)) {
1827                 /* From nonpaging to paging */
1828                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1829                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1830                              ~(CPU_BASED_CR3_LOAD_EXITING |
1831                                CPU_BASED_CR3_STORE_EXITING));
1832                 vcpu->arch.cr0 = cr0;
1833                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1834         }
1835
1836         if (!(cr0 & X86_CR0_WP))
1837                 *hw_cr0 &= ~X86_CR0_WP;
1838 }
1839
1840 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1841 {
1842         struct vcpu_vmx *vmx = to_vmx(vcpu);
1843         unsigned long hw_cr0;
1844
1845         if (enable_unrestricted_guest)
1846                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1847                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1848         else
1849                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1850
1851         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1852                 enter_pmode(vcpu);
1853
1854         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1855                 enter_rmode(vcpu);
1856
1857 #ifdef CONFIG_X86_64
1858         if (vcpu->arch.efer & EFER_LME) {
1859                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1860                         enter_lmode(vcpu);
1861                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1862                         exit_lmode(vcpu);
1863         }
1864 #endif
1865
1866         if (enable_ept)
1867                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1868
1869         if (!vcpu->fpu_active)
1870                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1871
1872         vmcs_writel(CR0_READ_SHADOW, cr0);
1873         vmcs_writel(GUEST_CR0, hw_cr0);
1874         vcpu->arch.cr0 = cr0;
1875 }
1876
1877 static u64 construct_eptp(unsigned long root_hpa)
1878 {
1879         u64 eptp;
1880
1881         /* TODO write the value reading from MSR */
1882         eptp = VMX_EPT_DEFAULT_MT |
1883                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1884         eptp |= (root_hpa & PAGE_MASK);
1885
1886         return eptp;
1887 }
1888
1889 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1890 {
1891         unsigned long guest_cr3;
1892         u64 eptp;
1893
1894         guest_cr3 = cr3;
1895         if (enable_ept) {
1896                 eptp = construct_eptp(cr3);
1897                 vmcs_write64(EPT_POINTER, eptp);
1898                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1899                         vcpu->kvm->arch.ept_identity_map_addr;
1900                 ept_load_pdptrs(vcpu);
1901         }
1902
1903         vmx_flush_tlb(vcpu);
1904         vmcs_writel(GUEST_CR3, guest_cr3);
1905 }
1906
1907 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1908 {
1909         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1910                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1911
1912         vcpu->arch.cr4 = cr4;
1913         if (enable_ept) {
1914                 if (!is_paging(vcpu)) {
1915                         hw_cr4 &= ~X86_CR4_PAE;
1916                         hw_cr4 |= X86_CR4_PSE;
1917                 } else if (!(cr4 & X86_CR4_PAE)) {
1918                         hw_cr4 &= ~X86_CR4_PAE;
1919                 }
1920         }
1921
1922         vmcs_writel(CR4_READ_SHADOW, cr4);
1923         vmcs_writel(GUEST_CR4, hw_cr4);
1924 }
1925
1926 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1927 {
1928         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1929
1930         return vmcs_readl(sf->base);
1931 }
1932
1933 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1934                             struct kvm_segment *var, int seg)
1935 {
1936         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1937         u32 ar;
1938
1939         var->base = vmcs_readl(sf->base);
1940         var->limit = vmcs_read32(sf->limit);
1941         var->selector = vmcs_read16(sf->selector);
1942         ar = vmcs_read32(sf->ar_bytes);
1943         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1944                 ar = 0;
1945         var->type = ar & 15;
1946         var->s = (ar >> 4) & 1;
1947         var->dpl = (ar >> 5) & 3;
1948         var->present = (ar >> 7) & 1;
1949         var->avl = (ar >> 12) & 1;
1950         var->l = (ar >> 13) & 1;
1951         var->db = (ar >> 14) & 1;
1952         var->g = (ar >> 15) & 1;
1953         var->unusable = (ar >> 16) & 1;
1954 }
1955
1956 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1957 {
1958         if (!is_protmode(vcpu))
1959                 return 0;
1960
1961         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1962                 return 3;
1963
1964         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1965 }
1966
1967 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1968 {
1969         u32 ar;
1970
1971         if (var->unusable)
1972                 ar = 1 << 16;
1973         else {
1974                 ar = var->type & 15;
1975                 ar |= (var->s & 1) << 4;
1976                 ar |= (var->dpl & 3) << 5;
1977                 ar |= (var->present & 1) << 7;
1978                 ar |= (var->avl & 1) << 12;
1979                 ar |= (var->l & 1) << 13;
1980                 ar |= (var->db & 1) << 14;
1981                 ar |= (var->g & 1) << 15;
1982         }
1983         if (ar == 0) /* a 0 value means unusable */
1984                 ar = AR_UNUSABLE_MASK;
1985
1986         return ar;
1987 }
1988
1989 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1990                             struct kvm_segment *var, int seg)
1991 {
1992         struct vcpu_vmx *vmx = to_vmx(vcpu);
1993         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1994         u32 ar;
1995
1996         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1997                 vmx->rmode.tr.selector = var->selector;
1998                 vmx->rmode.tr.base = var->base;
1999                 vmx->rmode.tr.limit = var->limit;
2000                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2001                 return;
2002         }
2003         vmcs_writel(sf->base, var->base);
2004         vmcs_write32(sf->limit, var->limit);
2005         vmcs_write16(sf->selector, var->selector);
2006         if (vmx->rmode.vm86_active && var->s) {
2007                 /*
2008                  * Hack real-mode segments into vm86 compatibility.
2009                  */
2010                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2011                         vmcs_writel(sf->base, 0xf0000);
2012                 ar = 0xf3;
2013         } else
2014                 ar = vmx_segment_access_rights(var);
2015
2016         /*
2017          *   Fix the "Accessed" bit in AR field of segment registers for older
2018          * qemu binaries.
2019          *   IA32 arch specifies that at the time of processor reset the
2020          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2021          * is setting it to 0 in the usedland code. This causes invalid guest
2022          * state vmexit when "unrestricted guest" mode is turned on.
2023          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2024          * tree. Newer qemu binaries with that qemu fix would not need this
2025          * kvm hack.
2026          */
2027         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2028                 ar |= 0x1; /* Accessed */
2029
2030         vmcs_write32(sf->ar_bytes, ar);
2031 }
2032
2033 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2034 {
2035         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2036
2037         *db = (ar >> 14) & 1;
2038         *l = (ar >> 13) & 1;
2039 }
2040
2041 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2042 {
2043         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2044         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2045 }
2046
2047 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2048 {
2049         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2050         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2051 }
2052
2053 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2054 {
2055         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2056         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2057 }
2058
2059 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2060 {
2061         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2062         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2063 }
2064
2065 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2066 {
2067         struct kvm_segment var;
2068         u32 ar;
2069
2070         vmx_get_segment(vcpu, &var, seg);
2071         ar = vmx_segment_access_rights(&var);
2072
2073         if (var.base != (var.selector << 4))
2074                 return false;
2075         if (var.limit != 0xffff)
2076                 return false;
2077         if (ar != 0xf3)
2078                 return false;
2079
2080         return true;
2081 }
2082
2083 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2084 {
2085         struct kvm_segment cs;
2086         unsigned int cs_rpl;
2087
2088         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2089         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2090
2091         if (cs.unusable)
2092                 return false;
2093         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2094                 return false;
2095         if (!cs.s)
2096                 return false;
2097         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2098                 if (cs.dpl > cs_rpl)
2099                         return false;
2100         } else {
2101                 if (cs.dpl != cs_rpl)
2102                         return false;
2103         }
2104         if (!cs.present)
2105                 return false;
2106
2107         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2108         return true;
2109 }
2110
2111 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2112 {
2113         struct kvm_segment ss;
2114         unsigned int ss_rpl;
2115
2116         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2117         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2118
2119         if (ss.unusable)
2120                 return true;
2121         if (ss.type != 3 && ss.type != 7)
2122                 return false;
2123         if (!ss.s)
2124                 return false;
2125         if (ss.dpl != ss_rpl) /* DPL != RPL */
2126                 return false;
2127         if (!ss.present)
2128                 return false;
2129
2130         return true;
2131 }
2132
2133 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2134 {
2135         struct kvm_segment var;
2136         unsigned int rpl;
2137
2138         vmx_get_segment(vcpu, &var, seg);
2139         rpl = var.selector & SELECTOR_RPL_MASK;
2140
2141         if (var.unusable)
2142                 return true;
2143         if (!var.s)
2144                 return false;
2145         if (!var.present)
2146                 return false;
2147         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2148                 if (var.dpl < rpl) /* DPL < RPL */
2149                         return false;
2150         }
2151
2152         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2153          * rights flags
2154          */
2155         return true;
2156 }
2157
2158 static bool tr_valid(struct kvm_vcpu *vcpu)
2159 {
2160         struct kvm_segment tr;
2161
2162         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2163
2164         if (tr.unusable)
2165                 return false;
2166         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2167                 return false;
2168         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2169                 return false;
2170         if (!tr.present)
2171                 return false;
2172
2173         return true;
2174 }
2175
2176 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2177 {
2178         struct kvm_segment ldtr;
2179
2180         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2181
2182         if (ldtr.unusable)
2183                 return true;
2184         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2185                 return false;
2186         if (ldtr.type != 2)
2187                 return false;
2188         if (!ldtr.present)
2189                 return false;
2190
2191         return true;
2192 }
2193
2194 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2195 {
2196         struct kvm_segment cs, ss;
2197
2198         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2199         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2200
2201         return ((cs.selector & SELECTOR_RPL_MASK) ==
2202                  (ss.selector & SELECTOR_RPL_MASK));
2203 }
2204
2205 /*
2206  * Check if guest state is valid. Returns true if valid, false if
2207  * not.
2208  * We assume that registers are always usable
2209  */
2210 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2211 {
2212         /* real mode guest state checks */
2213         if (!is_protmode(vcpu)) {
2214                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2215                         return false;
2216                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2217                         return false;
2218                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2219                         return false;
2220                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2221                         return false;
2222                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2223                         return false;
2224                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2225                         return false;
2226         } else {
2227         /* protected mode guest state checks */
2228                 if (!cs_ss_rpl_check(vcpu))
2229                         return false;
2230                 if (!code_segment_valid(vcpu))
2231                         return false;
2232                 if (!stack_segment_valid(vcpu))
2233                         return false;
2234                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2235                         return false;
2236                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2237                         return false;
2238                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2239                         return false;
2240                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2241                         return false;
2242                 if (!tr_valid(vcpu))
2243                         return false;
2244                 if (!ldtr_valid(vcpu))
2245                         return false;
2246         }
2247         /* TODO:
2248          * - Add checks on RIP
2249          * - Add checks on RFLAGS
2250          */
2251
2252         return true;
2253 }
2254
2255 static int init_rmode_tss(struct kvm *kvm)
2256 {
2257         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2258         u16 data = 0;
2259         int ret = 0;
2260         int r;
2261
2262         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2263         if (r < 0)
2264                 goto out;
2265         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2266         r = kvm_write_guest_page(kvm, fn++, &data,
2267                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2268         if (r < 0)
2269                 goto out;
2270         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2271         if (r < 0)
2272                 goto out;
2273         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2274         if (r < 0)
2275                 goto out;
2276         data = ~0;
2277         r = kvm_write_guest_page(kvm, fn, &data,
2278                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2279                                  sizeof(u8));
2280         if (r < 0)
2281                 goto out;
2282
2283         ret = 1;
2284 out:
2285         return ret;
2286 }
2287
2288 static int init_rmode_identity_map(struct kvm *kvm)
2289 {
2290         int i, r, ret;
2291         pfn_t identity_map_pfn;
2292         u32 tmp;
2293
2294         if (!enable_ept)
2295                 return 1;
2296         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2297                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2298                         "haven't been allocated!\n");
2299                 return 0;
2300         }
2301         if (likely(kvm->arch.ept_identity_pagetable_done))
2302                 return 1;
2303         ret = 0;
2304         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2305         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2306         if (r < 0)
2307                 goto out;
2308         /* Set up identity-mapping pagetable for EPT in real mode */
2309         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2310                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2311                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2312                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2313                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2314                 if (r < 0)
2315                         goto out;
2316         }
2317         kvm->arch.ept_identity_pagetable_done = true;
2318         ret = 1;
2319 out:
2320         return ret;
2321 }
2322
2323 static void seg_setup(int seg)
2324 {
2325         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2326         unsigned int ar;
2327
2328         vmcs_write16(sf->selector, 0);
2329         vmcs_writel(sf->base, 0);
2330         vmcs_write32(sf->limit, 0xffff);
2331         if (enable_unrestricted_guest) {
2332                 ar = 0x93;
2333                 if (seg == VCPU_SREG_CS)
2334                         ar |= 0x08; /* code segment */
2335         } else
2336                 ar = 0xf3;
2337
2338         vmcs_write32(sf->ar_bytes, ar);
2339 }
2340
2341 static int alloc_apic_access_page(struct kvm *kvm)
2342 {
2343         struct kvm_userspace_memory_region kvm_userspace_mem;
2344         int r = 0;
2345
2346         mutex_lock(&kvm->slots_lock);
2347         if (kvm->arch.apic_access_page)
2348                 goto out;
2349         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2350         kvm_userspace_mem.flags = 0;
2351         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2352         kvm_userspace_mem.memory_size = PAGE_SIZE;
2353         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2354         if (r)
2355                 goto out;
2356
2357         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2358 out:
2359         mutex_unlock(&kvm->slots_lock);
2360         return r;
2361 }
2362
2363 static int alloc_identity_pagetable(struct kvm *kvm)
2364 {
2365         struct kvm_userspace_memory_region kvm_userspace_mem;
2366         int r = 0;
2367
2368         mutex_lock(&kvm->slots_lock);
2369         if (kvm->arch.ept_identity_pagetable)
2370                 goto out;
2371         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2372         kvm_userspace_mem.flags = 0;
2373         kvm_userspace_mem.guest_phys_addr =
2374                 kvm->arch.ept_identity_map_addr;
2375         kvm_userspace_mem.memory_size = PAGE_SIZE;
2376         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2377         if (r)
2378                 goto out;
2379
2380         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2381                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2382 out:
2383         mutex_unlock(&kvm->slots_lock);
2384         return r;
2385 }
2386
2387 static void allocate_vpid(struct vcpu_vmx *vmx)
2388 {
2389         int vpid;
2390
2391         vmx->vpid = 0;
2392         if (!enable_vpid)
2393                 return;
2394         spin_lock(&vmx_vpid_lock);
2395         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2396         if (vpid < VMX_NR_VPIDS) {
2397                 vmx->vpid = vpid;
2398                 __set_bit(vpid, vmx_vpid_bitmap);
2399         }
2400         spin_unlock(&vmx_vpid_lock);
2401 }
2402
2403 static void free_vpid(struct vcpu_vmx *vmx)
2404 {
2405         if (!enable_vpid)
2406                 return;
2407         spin_lock(&vmx_vpid_lock);
2408         if (vmx->vpid != 0)
2409                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2410         spin_unlock(&vmx_vpid_lock);
2411 }
2412
2413 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2414 {
2415         int f = sizeof(unsigned long);
2416
2417         if (!cpu_has_vmx_msr_bitmap())
2418                 return;
2419
2420         /*
2421          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2422          * have the write-low and read-high bitmap offsets the wrong way round.
2423          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2424          */
2425         if (msr <= 0x1fff) {
2426                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2427                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2428         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2429                 msr &= 0x1fff;
2430                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2431                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2432         }
2433 }
2434
2435 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2436 {
2437         if (!longmode_only)
2438                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2439         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2440 }
2441
2442 /*
2443  * Sets up the vmcs for emulated real mode.
2444  */
2445 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2446 {
2447         u32 host_sysenter_cs, msr_low, msr_high;
2448         u32 junk;
2449         u64 host_pat, tsc_this, tsc_base;
2450         unsigned long a;
2451         struct desc_ptr dt;
2452         int i;
2453         unsigned long kvm_vmx_return;
2454         u32 exec_control;
2455
2456         /* I/O */
2457         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2458         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2459
2460         if (cpu_has_vmx_msr_bitmap())
2461                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2462
2463         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2464
2465         /* Control */
2466         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2467                 vmcs_config.pin_based_exec_ctrl);
2468
2469         exec_control = vmcs_config.cpu_based_exec_ctrl;
2470         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2471                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2472 #ifdef CONFIG_X86_64
2473                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2474                                 CPU_BASED_CR8_LOAD_EXITING;
2475 #endif
2476         }
2477         if (!enable_ept)
2478                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2479                                 CPU_BASED_CR3_LOAD_EXITING  |
2480                                 CPU_BASED_INVLPG_EXITING;
2481         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2482
2483         if (cpu_has_secondary_exec_ctrls()) {
2484                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2485                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2486                         exec_control &=
2487                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2488                 if (vmx->vpid == 0)
2489                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2490                 if (!enable_ept) {
2491                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2492                         enable_unrestricted_guest = 0;
2493                 }
2494                 if (!enable_unrestricted_guest)
2495                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2496                 if (!ple_gap)
2497                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2498                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2499         }
2500
2501         if (ple_gap) {
2502                 vmcs_write32(PLE_GAP, ple_gap);
2503                 vmcs_write32(PLE_WINDOW, ple_window);
2504         }
2505
2506         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2507         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2508         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2509
2510         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2511         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2512         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2513
2514         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2515         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2516         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2517         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2518         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2519         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2520 #ifdef CONFIG_X86_64
2521         rdmsrl(MSR_FS_BASE, a);
2522         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2523         rdmsrl(MSR_GS_BASE, a);
2524         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2525 #else
2526         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2527         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2528 #endif
2529
2530         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2531
2532         native_store_idt(&dt);
2533         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2534
2535         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2536         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2537         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2538         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2539         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2540         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2541         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2542
2543         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2544         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2545         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2546         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2547         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2548         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2549
2550         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2551                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2552                 host_pat = msr_low | ((u64) msr_high << 32);
2553                 vmcs_write64(HOST_IA32_PAT, host_pat);
2554         }
2555         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2556                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2557                 host_pat = msr_low | ((u64) msr_high << 32);
2558                 /* Write the default value follow host pat */
2559                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2560                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2561                 vmx->vcpu.arch.pat = host_pat;
2562         }
2563
2564         for (i = 0; i < NR_VMX_MSR; ++i) {
2565                 u32 index = vmx_msr_index[i];
2566                 u32 data_low, data_high;
2567                 int j = vmx->nmsrs;
2568
2569                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2570                         continue;
2571                 if (wrmsr_safe(index, data_low, data_high) < 0)
2572                         continue;
2573                 vmx->guest_msrs[j].index = i;
2574                 vmx->guest_msrs[j].data = 0;
2575                 vmx->guest_msrs[j].mask = -1ull;
2576                 ++vmx->nmsrs;
2577         }
2578
2579         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2580
2581         /* 22.2.1, 20.8.1 */
2582         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2583
2584         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2585         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2586         if (enable_ept)
2587                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2588         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2589
2590         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2591         rdtscll(tsc_this);
2592         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2593                 tsc_base = tsc_this;
2594
2595         guest_write_tsc(0, tsc_base);
2596
2597         return 0;
2598 }
2599
2600 static int init_rmode(struct kvm *kvm)
2601 {
2602         if (!init_rmode_tss(kvm))
2603                 return 0;
2604         if (!init_rmode_identity_map(kvm))
2605                 return 0;
2606         return 1;
2607 }
2608
2609 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2610 {
2611         struct vcpu_vmx *vmx = to_vmx(vcpu);
2612         u64 msr;
2613         int ret, idx;
2614
2615         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2616         idx = srcu_read_lock(&vcpu->kvm->srcu);
2617         if (!init_rmode(vmx->vcpu.kvm)) {
2618                 ret = -ENOMEM;
2619                 goto out;
2620         }
2621
2622         vmx->rmode.vm86_active = 0;
2623
2624         vmx->soft_vnmi_blocked = 0;
2625
2626         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2627         kvm_set_cr8(&vmx->vcpu, 0);
2628         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2629         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2630                 msr |= MSR_IA32_APICBASE_BSP;
2631         kvm_set_apic_base(&vmx->vcpu, msr);
2632
2633         fx_init(&vmx->vcpu);
2634
2635         seg_setup(VCPU_SREG_CS);
2636         /*
2637          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2638          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2639          */
2640         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2641                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2642                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2643         } else {
2644                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2645                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2646         }
2647
2648         seg_setup(VCPU_SREG_DS);
2649         seg_setup(VCPU_SREG_ES);
2650         seg_setup(VCPU_SREG_FS);
2651         seg_setup(VCPU_SREG_GS);
2652         seg_setup(VCPU_SREG_SS);
2653
2654         vmcs_write16(GUEST_TR_SELECTOR, 0);
2655         vmcs_writel(GUEST_TR_BASE, 0);
2656         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2657         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2658
2659         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2660         vmcs_writel(GUEST_LDTR_BASE, 0);
2661         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2662         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2663
2664         vmcs_write32(GUEST_SYSENTER_CS, 0);
2665         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2666         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2667
2668         vmcs_writel(GUEST_RFLAGS, 0x02);
2669         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2670                 kvm_rip_write(vcpu, 0xfff0);
2671         else
2672                 kvm_rip_write(vcpu, 0);
2673         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2674
2675         vmcs_writel(GUEST_DR7, 0x400);
2676
2677         vmcs_writel(GUEST_GDTR_BASE, 0);
2678         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2679
2680         vmcs_writel(GUEST_IDTR_BASE, 0);
2681         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2682
2683         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2684         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2685         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2686
2687         /* Special registers */
2688         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2689
2690         setup_msrs(vmx);
2691
2692         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2693
2694         if (cpu_has_vmx_tpr_shadow()) {
2695                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2696                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2697                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2698                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2699                 vmcs_write32(TPR_THRESHOLD, 0);
2700         }
2701
2702         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2703                 vmcs_write64(APIC_ACCESS_ADDR,
2704                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2705
2706         if (vmx->vpid != 0)
2707                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2708
2709         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2710         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2711         vmx_set_cr4(&vmx->vcpu, 0);
2712         vmx_set_efer(&vmx->vcpu, 0);
2713         vmx_fpu_activate(&vmx->vcpu);
2714         update_exception_bitmap(&vmx->vcpu);
2715
2716         vpid_sync_vcpu_all(vmx);
2717
2718         ret = 0;
2719
2720         /* HACK: Don't enable emulation on guest boot/reset */
2721         vmx->emulation_required = 0;
2722
2723 out:
2724         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2725         return ret;
2726 }
2727
2728 static void enable_irq_window(struct kvm_vcpu *vcpu)
2729 {
2730         u32 cpu_based_vm_exec_control;
2731
2732         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2733         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2734         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2735 }
2736
2737 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2738 {
2739         u32 cpu_based_vm_exec_control;
2740
2741         if (!cpu_has_virtual_nmis()) {
2742                 enable_irq_window(vcpu);
2743                 return;
2744         }
2745
2746         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2747         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2748         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2749 }
2750
2751 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2752 {
2753         struct vcpu_vmx *vmx = to_vmx(vcpu);
2754         uint32_t intr;
2755         int irq = vcpu->arch.interrupt.nr;
2756
2757         trace_kvm_inj_virq(irq);
2758
2759         ++vcpu->stat.irq_injections;
2760         if (vmx->rmode.vm86_active) {
2761                 vmx->rmode.irq.pending = true;
2762                 vmx->rmode.irq.vector = irq;
2763                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2764                 if (vcpu->arch.interrupt.soft)
2765                         vmx->rmode.irq.rip +=
2766                                 vmx->vcpu.arch.event_exit_inst_len;
2767                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2768                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2769                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2770                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2771                 return;
2772         }
2773         intr = irq | INTR_INFO_VALID_MASK;
2774         if (vcpu->arch.interrupt.soft) {
2775                 intr |= INTR_TYPE_SOFT_INTR;
2776                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2777                              vmx->vcpu.arch.event_exit_inst_len);
2778         } else
2779                 intr |= INTR_TYPE_EXT_INTR;
2780         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2781 }
2782
2783 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2784 {
2785         struct vcpu_vmx *vmx = to_vmx(vcpu);
2786
2787         if (!cpu_has_virtual_nmis()) {
2788                 /*
2789                  * Tracking the NMI-blocked state in software is built upon
2790                  * finding the next open IRQ window. This, in turn, depends on
2791                  * well-behaving guests: They have to keep IRQs disabled at
2792                  * least as long as the NMI handler runs. Otherwise we may
2793                  * cause NMI nesting, maybe breaking the guest. But as this is
2794                  * highly unlikely, we can live with the residual risk.
2795                  */
2796                 vmx->soft_vnmi_blocked = 1;
2797                 vmx->vnmi_blocked_time = 0;
2798         }
2799
2800         ++vcpu->stat.nmi_injections;
2801         if (vmx->rmode.vm86_active) {
2802                 vmx->rmode.irq.pending = true;
2803                 vmx->rmode.irq.vector = NMI_VECTOR;
2804                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2805                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2806                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2807                              INTR_INFO_VALID_MASK);
2808                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2809                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2810                 return;
2811         }
2812         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2813                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2814 }
2815
2816 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2817 {
2818         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2819                 return 0;
2820
2821         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2822                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2823 }
2824
2825 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2826 {
2827         if (!cpu_has_virtual_nmis())
2828                 return to_vmx(vcpu)->soft_vnmi_blocked;
2829         else
2830                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2831                           GUEST_INTR_STATE_NMI);
2832 }
2833
2834 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2835 {
2836         struct vcpu_vmx *vmx = to_vmx(vcpu);
2837
2838         if (!cpu_has_virtual_nmis()) {
2839                 if (vmx->soft_vnmi_blocked != masked) {
2840                         vmx->soft_vnmi_blocked = masked;
2841                         vmx->vnmi_blocked_time = 0;
2842                 }
2843         } else {
2844                 if (masked)
2845                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2846                                       GUEST_INTR_STATE_NMI);
2847                 else
2848                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2849                                         GUEST_INTR_STATE_NMI);
2850         }
2851 }
2852
2853 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2854 {
2855         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2856                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2857                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2858 }
2859
2860 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2861 {
2862         int ret;
2863         struct kvm_userspace_memory_region tss_mem = {
2864                 .slot = TSS_PRIVATE_MEMSLOT,
2865                 .guest_phys_addr = addr,
2866                 .memory_size = PAGE_SIZE * 3,
2867                 .flags = 0,
2868         };
2869
2870         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2871         if (ret)
2872                 return ret;
2873         kvm->arch.tss_addr = addr;
2874         return 0;
2875 }
2876
2877 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2878                                   int vec, u32 err_code)
2879 {
2880         /*
2881          * Instruction with address size override prefix opcode 0x67
2882          * Cause the #SS fault with 0 error code in VM86 mode.
2883          */
2884         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2885                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2886                         return 1;
2887         /*
2888          * Forward all other exceptions that are valid in real mode.
2889          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2890          *        the required debugging infrastructure rework.
2891          */
2892         switch (vec) {
2893         case DB_VECTOR:
2894                 if (vcpu->guest_debug &
2895                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2896                         return 0;
2897                 kvm_queue_exception(vcpu, vec);
2898                 return 1;
2899         case BP_VECTOR:
2900                 /*
2901                  * Update instruction length as we may reinject the exception
2902                  * from user space while in guest debugging mode.
2903                  */
2904                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2905                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2906                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2907                         return 0;
2908                 /* fall through */
2909         case DE_VECTOR:
2910         case OF_VECTOR:
2911         case BR_VECTOR:
2912         case UD_VECTOR:
2913         case DF_VECTOR:
2914         case SS_VECTOR:
2915         case GP_VECTOR:
2916         case MF_VECTOR:
2917                 kvm_queue_exception(vcpu, vec);
2918                 return 1;
2919         }
2920         return 0;
2921 }
2922
2923 /*
2924  * Trigger machine check on the host. We assume all the MSRs are already set up
2925  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2926  * We pass a fake environment to the machine check handler because we want
2927  * the guest to be always treated like user space, no matter what context
2928  * it used internally.
2929  */
2930 static void kvm_machine_check(void)
2931 {
2932 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2933         struct pt_regs regs = {
2934                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2935                 .flags = X86_EFLAGS_IF,
2936         };
2937
2938         do_machine_check(&regs, 0);
2939 #endif
2940 }
2941
2942 static int handle_machine_check(struct kvm_vcpu *vcpu)
2943 {
2944         /* already handled by vcpu_run */
2945         return 1;
2946 }
2947
2948 static int handle_exception(struct kvm_vcpu *vcpu)
2949 {
2950         struct vcpu_vmx *vmx = to_vmx(vcpu);
2951         struct kvm_run *kvm_run = vcpu->run;
2952         u32 intr_info, ex_no, error_code;
2953         unsigned long cr2, rip, dr6;
2954         u32 vect_info;
2955         enum emulation_result er;
2956
2957         vect_info = vmx->idt_vectoring_info;
2958         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2959
2960         if (is_machine_check(intr_info))
2961                 return handle_machine_check(vcpu);
2962
2963         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2964             !is_page_fault(intr_info)) {
2965                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2966                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2967                 vcpu->run->internal.ndata = 2;
2968                 vcpu->run->internal.data[0] = vect_info;
2969                 vcpu->run->internal.data[1] = intr_info;
2970                 return 0;
2971         }
2972
2973         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2974                 return 1;  /* already handled by vmx_vcpu_run() */
2975
2976         if (is_no_device(intr_info)) {
2977                 vmx_fpu_activate(vcpu);
2978                 return 1;
2979         }
2980
2981         if (is_invalid_opcode(intr_info)) {
2982                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2983                 if (er != EMULATE_DONE)
2984                         kvm_queue_exception(vcpu, UD_VECTOR);
2985                 return 1;
2986         }
2987
2988         error_code = 0;
2989         rip = kvm_rip_read(vcpu);
2990         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2991                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2992         if (is_page_fault(intr_info)) {
2993                 /* EPT won't cause page fault directly */
2994                 if (enable_ept)
2995                         BUG();
2996                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2997                 trace_kvm_page_fault(cr2, error_code);
2998
2999                 if (kvm_event_needs_reinjection(vcpu))
3000                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3001                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3002         }
3003
3004         if (vmx->rmode.vm86_active &&
3005             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3006                                                                 error_code)) {
3007                 if (vcpu->arch.halt_request) {
3008                         vcpu->arch.halt_request = 0;
3009                         return kvm_emulate_halt(vcpu);
3010                 }
3011                 return 1;
3012         }
3013
3014         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3015         switch (ex_no) {
3016         case DB_VECTOR:
3017                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3018                 if (!(vcpu->guest_debug &
3019                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3020                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3021                         kvm_queue_exception(vcpu, DB_VECTOR);
3022                         return 1;
3023                 }
3024                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3025                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3026                 /* fall through */
3027         case BP_VECTOR:
3028                 /*
3029                  * Update instruction length as we may reinject #BP from
3030                  * user space while in guest debugging mode. Reading it for
3031                  * #DB as well causes no harm, it is not used in that case.
3032                  */
3033                 vmx->vcpu.arch.event_exit_inst_len =
3034                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3035                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3036                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3037                 kvm_run->debug.arch.exception = ex_no;
3038                 break;
3039         default:
3040                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3041                 kvm_run->ex.exception = ex_no;
3042                 kvm_run->ex.error_code = error_code;
3043                 break;
3044         }
3045         return 0;
3046 }
3047
3048 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3049 {
3050         ++vcpu->stat.irq_exits;
3051         return 1;
3052 }
3053
3054 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3055 {
3056         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3057         return 0;
3058 }
3059
3060 static int handle_io(struct kvm_vcpu *vcpu)
3061 {
3062         unsigned long exit_qualification;
3063         int size, in, string;
3064         unsigned port;
3065
3066         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3067         string = (exit_qualification & 16) != 0;
3068         in = (exit_qualification & 8) != 0;
3069
3070         ++vcpu->stat.io_exits;
3071
3072         if (string || in)
3073                 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
3074
3075         port = exit_qualification >> 16;
3076         size = (exit_qualification & 7) + 1;
3077         skip_emulated_instruction(vcpu);
3078
3079         return kvm_fast_pio_out(vcpu, size, port);
3080 }
3081
3082 static void
3083 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3084 {
3085         /*
3086          * Patch in the VMCALL instruction:
3087          */
3088         hypercall[0] = 0x0f;
3089         hypercall[1] = 0x01;
3090         hypercall[2] = 0xc1;
3091 }
3092
3093 static int handle_cr(struct kvm_vcpu *vcpu)
3094 {
3095         unsigned long exit_qualification, val;
3096         int cr;
3097         int reg;
3098
3099         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3100         cr = exit_qualification & 15;
3101         reg = (exit_qualification >> 8) & 15;
3102         switch ((exit_qualification >> 4) & 3) {
3103         case 0: /* mov to cr */
3104                 val = kvm_register_read(vcpu, reg);
3105                 trace_kvm_cr_write(cr, val);
3106                 switch (cr) {
3107                 case 0:
3108                         kvm_set_cr0(vcpu, val);
3109                         skip_emulated_instruction(vcpu);
3110                         return 1;
3111                 case 3:
3112                         kvm_set_cr3(vcpu, val);
3113                         skip_emulated_instruction(vcpu);
3114                         return 1;
3115                 case 4:
3116                         kvm_set_cr4(vcpu, val);
3117                         skip_emulated_instruction(vcpu);
3118                         return 1;
3119                 case 8: {
3120                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3121                                 u8 cr8 = kvm_register_read(vcpu, reg);
3122                                 kvm_set_cr8(vcpu, cr8);
3123                                 skip_emulated_instruction(vcpu);
3124                                 if (irqchip_in_kernel(vcpu->kvm))
3125                                         return 1;
3126                                 if (cr8_prev <= cr8)
3127                                         return 1;
3128                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3129                                 return 0;
3130                         }
3131                 };
3132                 break;
3133         case 2: /* clts */
3134                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3135                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3136                 skip_emulated_instruction(vcpu);
3137                 vmx_fpu_activate(vcpu);
3138                 return 1;
3139         case 1: /*mov from cr*/
3140                 switch (cr) {
3141                 case 3:
3142                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3143                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3144                         skip_emulated_instruction(vcpu);
3145                         return 1;
3146                 case 8:
3147                         val = kvm_get_cr8(vcpu);
3148                         kvm_register_write(vcpu, reg, val);
3149                         trace_kvm_cr_read(cr, val);
3150                         skip_emulated_instruction(vcpu);
3151                         return 1;
3152                 }
3153                 break;
3154         case 3: /* lmsw */
3155                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3156                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3157                 kvm_lmsw(vcpu, val);
3158
3159                 skip_emulated_instruction(vcpu);
3160                 return 1;
3161         default:
3162                 break;
3163         }
3164         vcpu->run->exit_reason = 0;
3165         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3166                (int)(exit_qualification >> 4) & 3, cr);
3167         return 0;
3168 }
3169
3170 static int handle_dr(struct kvm_vcpu *vcpu)
3171 {
3172         unsigned long exit_qualification;
3173         int dr, reg;
3174
3175         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3176         if (!kvm_require_cpl(vcpu, 0))
3177                 return 1;
3178         dr = vmcs_readl(GUEST_DR7);
3179         if (dr & DR7_GD) {
3180                 /*
3181                  * As the vm-exit takes precedence over the debug trap, we
3182                  * need to emulate the latter, either for the host or the
3183                  * guest debugging itself.
3184                  */
3185                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3186                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3187                         vcpu->run->debug.arch.dr7 = dr;
3188                         vcpu->run->debug.arch.pc =
3189                                 vmcs_readl(GUEST_CS_BASE) +
3190                                 vmcs_readl(GUEST_RIP);
3191                         vcpu->run->debug.arch.exception = DB_VECTOR;
3192                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3193                         return 0;
3194                 } else {
3195                         vcpu->arch.dr7 &= ~DR7_GD;
3196                         vcpu->arch.dr6 |= DR6_BD;
3197                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3198                         kvm_queue_exception(vcpu, DB_VECTOR);
3199                         return 1;
3200                 }
3201         }
3202
3203         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3204         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3205         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3206         if (exit_qualification & TYPE_MOV_FROM_DR) {
3207                 unsigned long val;
3208                 if (!kvm_get_dr(vcpu, dr, &val))
3209                         kvm_register_write(vcpu, reg, val);
3210         } else
3211                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3212         skip_emulated_instruction(vcpu);
3213         return 1;
3214 }
3215
3216 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3217 {
3218         vmcs_writel(GUEST_DR7, val);
3219 }
3220
3221 static int handle_cpuid(struct kvm_vcpu *vcpu)
3222 {
3223         kvm_emulate_cpuid(vcpu);
3224         return 1;
3225 }
3226
3227 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3228 {
3229         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3230         u64 data;
3231
3232         if (vmx_get_msr(vcpu, ecx, &data)) {
3233                 trace_kvm_msr_read_ex(ecx);
3234                 kvm_inject_gp(vcpu, 0);
3235                 return 1;
3236         }
3237
3238         trace_kvm_msr_read(ecx, data);
3239
3240         /* FIXME: handling of bits 32:63 of rax, rdx */
3241         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3242         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3243         skip_emulated_instruction(vcpu);
3244         return 1;
3245 }
3246
3247 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3248 {
3249         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3250         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3251                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3252
3253         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3254                 trace_kvm_msr_write_ex(ecx, data);
3255                 kvm_inject_gp(vcpu, 0);
3256                 return 1;
3257         }
3258
3259         trace_kvm_msr_write(ecx, data);
3260         skip_emulated_instruction(vcpu);
3261         return 1;
3262 }
3263
3264 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3265 {
3266         return 1;
3267 }
3268
3269 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3270 {
3271         u32 cpu_based_vm_exec_control;
3272
3273         /* clear pending irq */
3274         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3275         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3276         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3277
3278         ++vcpu->stat.irq_window_exits;
3279
3280         /*
3281          * If the user space waits to inject interrupts, exit as soon as
3282          * possible
3283          */
3284         if (!irqchip_in_kernel(vcpu->kvm) &&
3285             vcpu->run->request_interrupt_window &&
3286             !kvm_cpu_has_interrupt(vcpu)) {
3287                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3288                 return 0;
3289         }
3290         return 1;
3291 }
3292
3293 static int handle_halt(struct kvm_vcpu *vcpu)
3294 {
3295         skip_emulated_instruction(vcpu);
3296         return kvm_emulate_halt(vcpu);
3297 }
3298
3299 static int handle_vmcall(struct kvm_vcpu *vcpu)
3300 {
3301         skip_emulated_instruction(vcpu);
3302         kvm_emulate_hypercall(vcpu);
3303         return 1;
3304 }
3305
3306 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3307 {
3308         kvm_queue_exception(vcpu, UD_VECTOR);
3309         return 1;
3310 }
3311
3312 static int handle_invlpg(struct kvm_vcpu *vcpu)
3313 {
3314         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3315
3316         kvm_mmu_invlpg(vcpu, exit_qualification);
3317         skip_emulated_instruction(vcpu);
3318         return 1;
3319 }
3320
3321 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3322 {
3323         skip_emulated_instruction(vcpu);
3324         /* TODO: Add support for VT-d/pass-through device */
3325         return 1;
3326 }
3327
3328 static int handle_apic_access(struct kvm_vcpu *vcpu)
3329 {
3330         unsigned long exit_qualification;
3331         enum emulation_result er;
3332         unsigned long offset;
3333
3334         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3335         offset = exit_qualification & 0xffful;
3336
3337         er = emulate_instruction(vcpu, 0, 0, 0);
3338
3339         if (er !=  EMULATE_DONE) {
3340                 printk(KERN_ERR
3341                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3342                        offset);
3343                 return -ENOEXEC;
3344         }
3345         return 1;
3346 }
3347
3348 static int handle_task_switch(struct kvm_vcpu *vcpu)
3349 {
3350         struct vcpu_vmx *vmx = to_vmx(vcpu);
3351         unsigned long exit_qualification;
3352         bool has_error_code = false;
3353         u32 error_code = 0;
3354         u16 tss_selector;
3355         int reason, type, idt_v;
3356
3357         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3358         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3359
3360         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3361
3362         reason = (u32)exit_qualification >> 30;
3363         if (reason == TASK_SWITCH_GATE && idt_v) {
3364                 switch (type) {
3365                 case INTR_TYPE_NMI_INTR:
3366                         vcpu->arch.nmi_injected = false;
3367                         if (cpu_has_virtual_nmis())
3368                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3369                                               GUEST_INTR_STATE_NMI);
3370                         break;
3371                 case INTR_TYPE_EXT_INTR:
3372                 case INTR_TYPE_SOFT_INTR:
3373                         kvm_clear_interrupt_queue(vcpu);
3374                         break;
3375                 case INTR_TYPE_HARD_EXCEPTION:
3376                         if (vmx->idt_vectoring_info &
3377                             VECTORING_INFO_DELIVER_CODE_MASK) {
3378                                 has_error_code = true;
3379                                 error_code =
3380                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3381                         }
3382                         /* fall through */
3383                 case INTR_TYPE_SOFT_EXCEPTION:
3384                         kvm_clear_exception_queue(vcpu);
3385                         break;
3386                 default:
3387                         break;
3388                 }
3389         }
3390         tss_selector = exit_qualification;
3391
3392         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3393                        type != INTR_TYPE_EXT_INTR &&
3394                        type != INTR_TYPE_NMI_INTR))
3395                 skip_emulated_instruction(vcpu);
3396
3397         if (kvm_task_switch(vcpu, tss_selector, reason,
3398                                 has_error_code, error_code) == EMULATE_FAIL) {
3399                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3400                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3401                 vcpu->run->internal.ndata = 0;
3402                 return 0;
3403         }
3404
3405         /* clear all local breakpoint enable flags */
3406         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3407
3408         /*
3409          * TODO: What about debug traps on tss switch?
3410          *       Are we supposed to inject them and update dr6?
3411          */
3412
3413         return 1;
3414 }
3415
3416 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3417 {
3418         unsigned long exit_qualification;
3419         gpa_t gpa;
3420         int gla_validity;
3421
3422         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3423
3424         if (exit_qualification & (1 << 6)) {
3425                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3426                 return -EINVAL;
3427         }
3428
3429         gla_validity = (exit_qualification >> 7) & 0x3;
3430         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3431                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3432                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3433                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3434                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3435                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3436                         (long unsigned int)exit_qualification);
3437                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3438                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3439                 return 0;
3440         }
3441
3442         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3443         trace_kvm_page_fault(gpa, exit_qualification);
3444         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3445 }
3446
3447 static u64 ept_rsvd_mask(u64 spte, int level)
3448 {
3449         int i;
3450         u64 mask = 0;
3451
3452         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3453                 mask |= (1ULL << i);
3454
3455         if (level > 2)
3456                 /* bits 7:3 reserved */
3457                 mask |= 0xf8;
3458         else if (level == 2) {
3459                 if (spte & (1ULL << 7))
3460                         /* 2MB ref, bits 20:12 reserved */
3461                         mask |= 0x1ff000;
3462                 else
3463                         /* bits 6:3 reserved */
3464                         mask |= 0x78;
3465         }
3466
3467         return mask;
3468 }
3469
3470 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3471                                        int level)
3472 {
3473         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3474
3475         /* 010b (write-only) */
3476         WARN_ON((spte & 0x7) == 0x2);
3477
3478         /* 110b (write/execute) */
3479         WARN_ON((spte & 0x7) == 0x6);
3480
3481         /* 100b (execute-only) and value not supported by logical processor */
3482         if (!cpu_has_vmx_ept_execute_only())
3483                 WARN_ON((spte & 0x7) == 0x4);
3484
3485         /* not 000b */
3486         if ((spte & 0x7)) {
3487                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3488
3489                 if (rsvd_bits != 0) {
3490                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3491                                          __func__, rsvd_bits);
3492                         WARN_ON(1);
3493                 }
3494
3495                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3496                         u64 ept_mem_type = (spte & 0x38) >> 3;
3497
3498                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3499                             ept_mem_type == 7) {
3500                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3501                                                 __func__, ept_mem_type);
3502                                 WARN_ON(1);
3503                         }
3504                 }
3505         }
3506 }
3507
3508 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3509 {
3510         u64 sptes[4];
3511         int nr_sptes, i;
3512         gpa_t gpa;
3513
3514         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3515
3516         printk(KERN_ERR "EPT: Misconfiguration.\n");
3517         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3518
3519         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3520
3521         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3522                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3523
3524         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3525         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3526
3527         return 0;
3528 }
3529
3530 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3531 {
3532         u32 cpu_based_vm_exec_control;
3533
3534         /* clear pending NMI */
3535         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3536         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3537         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3538         ++vcpu->stat.nmi_window_exits;
3539
3540         return 1;
3541 }
3542
3543 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3544 {
3545         struct vcpu_vmx *vmx = to_vmx(vcpu);
3546         enum emulation_result err = EMULATE_DONE;
3547         int ret = 1;
3548
3549         while (!guest_state_valid(vcpu)) {
3550                 err = emulate_instruction(vcpu, 0, 0, 0);
3551
3552                 if (err == EMULATE_DO_MMIO) {
3553                         ret = 0;
3554                         goto out;
3555                 }
3556
3557                 if (err != EMULATE_DONE) {
3558                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3559                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3560                         vcpu->run->internal.ndata = 0;
3561                         ret = 0;
3562                         goto out;
3563                 }
3564
3565                 if (signal_pending(current))
3566                         goto out;
3567                 if (need_resched())
3568                         schedule();
3569         }
3570
3571         vmx->emulation_required = 0;
3572 out:
3573         return ret;
3574 }
3575
3576 /*
3577  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3578  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3579  */
3580 static int handle_pause(struct kvm_vcpu *vcpu)
3581 {
3582         skip_emulated_instruction(vcpu);
3583         kvm_vcpu_on_spin(vcpu);
3584
3585         return 1;
3586 }
3587
3588 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3589 {
3590         kvm_queue_exception(vcpu, UD_VECTOR);
3591         return 1;
3592 }
3593
3594 /*
3595  * The exit handlers return 1 if the exit was handled fully and guest execution
3596  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3597  * to be done to userspace and return 0.
3598  */
3599 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3600         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3601         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3602         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3603         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3604         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3605         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3606         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3607         [EXIT_REASON_CPUID]                   = handle_cpuid,
3608         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3609         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3610         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3611         [EXIT_REASON_HLT]                     = handle_halt,
3612         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3613         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3614         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3615         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3616         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3617         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3618         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3619         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3620         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3621         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3622         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3623         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3624         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3625         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3626         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3627         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3628         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3629         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3630         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3631         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3632         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3633 };
3634
3635 static const int kvm_vmx_max_exit_handlers =
3636         ARRAY_SIZE(kvm_vmx_exit_handlers);
3637
3638 /*
3639  * The guest has exited.  See if we can fix it or if we need userspace
3640  * assistance.
3641  */
3642 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3643 {
3644         struct vcpu_vmx *vmx = to_vmx(vcpu);
3645         u32 exit_reason = vmx->exit_reason;
3646         u32 vectoring_info = vmx->idt_vectoring_info;
3647
3648         trace_kvm_exit(exit_reason, vcpu);
3649
3650         /* If guest state is invalid, start emulating */
3651         if (vmx->emulation_required && emulate_invalid_guest_state)
3652                 return handle_invalid_guest_state(vcpu);
3653
3654         /* Access CR3 don't cause VMExit in paging mode, so we need
3655          * to sync with guest real CR3. */
3656         if (enable_ept && is_paging(vcpu))
3657                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3658
3659         if (unlikely(vmx->fail)) {
3660                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3661                 vcpu->run->fail_entry.hardware_entry_failure_reason
3662                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3663                 return 0;
3664         }
3665
3666         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3667                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3668                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3669                         exit_reason != EXIT_REASON_TASK_SWITCH))
3670                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3671                        "(0x%x) and exit reason is 0x%x\n",
3672                        __func__, vectoring_info, exit_reason);
3673
3674         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3675                 if (vmx_interrupt_allowed(vcpu)) {
3676                         vmx->soft_vnmi_blocked = 0;
3677                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3678                            vcpu->arch.nmi_pending) {
3679                         /*
3680                          * This CPU don't support us in finding the end of an
3681                          * NMI-blocked window if the guest runs with IRQs
3682                          * disabled. So we pull the trigger after 1 s of
3683                          * futile waiting, but inform the user about this.
3684                          */
3685                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3686                                "state on VCPU %d after 1 s timeout\n",
3687                                __func__, vcpu->vcpu_id);
3688                         vmx->soft_vnmi_blocked = 0;
3689                 }
3690         }
3691
3692         if (exit_reason < kvm_vmx_max_exit_handlers
3693             && kvm_vmx_exit_handlers[exit_reason])
3694                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3695         else {
3696                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3697                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3698         }
3699         return 0;
3700 }
3701
3702 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3703 {
3704         if (irr == -1 || tpr < irr) {
3705                 vmcs_write32(TPR_THRESHOLD, 0);
3706                 return;
3707         }
3708
3709         vmcs_write32(TPR_THRESHOLD, irr);
3710 }
3711
3712 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3713 {
3714         u32 exit_intr_info;
3715         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3716         bool unblock_nmi;
3717         u8 vector;
3718         int type;
3719         bool idtv_info_valid;
3720
3721         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3722
3723         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3724
3725         /* Handle machine checks before interrupts are enabled */
3726         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3727             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3728                 && is_machine_check(exit_intr_info)))
3729                 kvm_machine_check();
3730
3731         /* We need to handle NMIs before interrupts are enabled */
3732         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3733             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3734                 kvm_before_handle_nmi(&vmx->vcpu);
3735                 asm("int $2");
3736                 kvm_after_handle_nmi(&vmx->vcpu);
3737         }
3738
3739         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3740
3741         if (cpu_has_virtual_nmis()) {
3742                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3743                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3744                 /*
3745                  * SDM 3: 27.7.1.2 (September 2008)
3746                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3747                  * a guest IRET fault.
3748                  * SDM 3: 23.2.2 (September 2008)
3749                  * Bit 12 is undefined in any of the following cases:
3750                  *  If the VM exit sets the valid bit in the IDT-vectoring
3751                  *   information field.
3752                  *  If the VM exit is due to a double fault.
3753                  */
3754                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3755                     vector != DF_VECTOR && !idtv_info_valid)
3756                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3757                                       GUEST_INTR_STATE_NMI);
3758         } else if (unlikely(vmx->soft_vnmi_blocked))
3759                 vmx->vnmi_blocked_time +=
3760                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3761
3762         vmx->vcpu.arch.nmi_injected = false;
3763         kvm_clear_exception_queue(&vmx->vcpu);
3764         kvm_clear_interrupt_queue(&vmx->vcpu);
3765
3766         if (!idtv_info_valid)
3767                 return;
3768
3769         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3770         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3771
3772         switch (type) {
3773         case INTR_TYPE_NMI_INTR:
3774                 vmx->vcpu.arch.nmi_injected = true;
3775                 /*
3776                  * SDM 3: 27.7.1.2 (September 2008)
3777                  * Clear bit "block by NMI" before VM entry if a NMI
3778                  * delivery faulted.
3779                  */
3780                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3781                                 GUEST_INTR_STATE_NMI);
3782                 break;
3783         case INTR_TYPE_SOFT_EXCEPTION:
3784                 vmx->vcpu.arch.event_exit_inst_len =
3785                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3786                 /* fall through */
3787         case INTR_TYPE_HARD_EXCEPTION:
3788                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3789                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3790                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3791                 } else
3792                         kvm_queue_exception(&vmx->vcpu, vector);
3793                 break;
3794         case INTR_TYPE_SOFT_INTR:
3795                 vmx->vcpu.arch.event_exit_inst_len =
3796                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3797                 /* fall through */
3798         case INTR_TYPE_EXT_INTR:
3799                 kvm_queue_interrupt(&vmx->vcpu, vector,
3800                         type == INTR_TYPE_SOFT_INTR);
3801                 break;
3802         default:
3803                 break;
3804         }
3805 }
3806
3807 /*
3808  * Failure to inject an interrupt should give us the information
3809  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3810  * when fetching the interrupt redirection bitmap in the real-mode
3811  * tss, this doesn't happen.  So we do it ourselves.
3812  */
3813 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3814 {
3815         vmx->rmode.irq.pending = 0;
3816         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3817                 return;
3818         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3819         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3820                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3821                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3822                 return;
3823         }
3824         vmx->idt_vectoring_info =
3825                 VECTORING_INFO_VALID_MASK
3826                 | INTR_TYPE_EXT_INTR
3827                 | vmx->rmode.irq.vector;
3828 }
3829
3830 #ifdef CONFIG_X86_64
3831 #define R "r"
3832 #define Q "q"
3833 #else
3834 #define R "e"
3835 #define Q "l"
3836 #endif
3837
3838 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3839 {
3840         struct vcpu_vmx *vmx = to_vmx(vcpu);
3841
3842         /* Record the guest's net vcpu time for enforced NMI injections. */
3843         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3844                 vmx->entry_time = ktime_get();
3845
3846         /* Don't enter VMX if guest state is invalid, let the exit handler
3847            start emulation until we arrive back to a valid state */
3848         if (vmx->emulation_required && emulate_invalid_guest_state)
3849                 return;
3850
3851         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3852                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3853         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3854                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3855
3856         /* When single-stepping over STI and MOV SS, we must clear the
3857          * corresponding interruptibility bits in the guest state. Otherwise
3858          * vmentry fails as it then expects bit 14 (BS) in pending debug
3859          * exceptions being set, but that's not correct for the guest debugging
3860          * case. */
3861         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3862                 vmx_set_interrupt_shadow(vcpu, 0);
3863
3864         /*
3865          * Loading guest fpu may have cleared host cr0.ts
3866          */
3867         vmcs_writel(HOST_CR0, read_cr0());
3868
3869         asm(
3870                 /* Store host registers */
3871                 "push %%"R"dx; push %%"R"bp;"
3872                 "push %%"R"cx \n\t"
3873                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3874                 "je 1f \n\t"
3875                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3876                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3877                 "1: \n\t"
3878                 /* Reload cr2 if changed */
3879                 "mov %c[cr2](%0), %%"R"ax \n\t"
3880                 "mov %%cr2, %%"R"dx \n\t"
3881                 "cmp %%"R"ax, %%"R"dx \n\t"
3882                 "je 2f \n\t"
3883                 "mov %%"R"ax, %%cr2 \n\t"
3884                 "2: \n\t"
3885                 /* Check if vmlaunch of vmresume is needed */
3886                 "cmpl $0, %c[launched](%0) \n\t"
3887                 /* Load guest registers.  Don't clobber flags. */
3888                 "mov %c[rax](%0), %%"R"ax \n\t"
3889                 "mov %c[rbx](%0), %%"R"bx \n\t"
3890                 "mov %c[rdx](%0), %%"R"dx \n\t"
3891                 "mov %c[rsi](%0), %%"R"si \n\t"
3892                 "mov %c[rdi](%0), %%"R"di \n\t"
3893                 "mov %c[rbp](%0), %%"R"bp \n\t"
3894 #ifdef CONFIG_X86_64
3895                 "mov %c[r8](%0),  %%r8  \n\t"
3896                 "mov %c[r9](%0),  %%r9  \n\t"
3897                 "mov %c[r10](%0), %%r10 \n\t"
3898                 "mov %c[r11](%0), %%r11 \n\t"
3899                 "mov %c[r12](%0), %%r12 \n\t"
3900                 "mov %c[r13](%0), %%r13 \n\t"
3901                 "mov %c[r14](%0), %%r14 \n\t"
3902                 "mov %c[r15](%0), %%r15 \n\t"
3903 #endif
3904                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3905
3906                 /* Enter guest mode */
3907                 "jne .Llaunched \n\t"
3908                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3909                 "jmp .Lkvm_vmx_return \n\t"
3910                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3911                 ".Lkvm_vmx_return: "
3912                 /* Save guest registers, load host registers, keep flags */
3913                 "xchg %0,     (%%"R"sp) \n\t"
3914                 "mov %%"R"ax, %c[rax](%0) \n\t"
3915                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3916                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3917                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3918                 "mov %%"R"si, %c[rsi](%0) \n\t"
3919                 "mov %%"R"di, %c[rdi](%0) \n\t"
3920                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3921 #ifdef CONFIG_X86_64
3922                 "mov %%r8,  %c[r8](%0) \n\t"
3923                 "mov %%r9,  %c[r9](%0) \n\t"
3924                 "mov %%r10, %c[r10](%0) \n\t"
3925                 "mov %%r11, %c[r11](%0) \n\t"
3926                 "mov %%r12, %c[r12](%0) \n\t"
3927                 "mov %%r13, %c[r13](%0) \n\t"
3928                 "mov %%r14, %c[r14](%0) \n\t"
3929                 "mov %%r15, %c[r15](%0) \n\t"
3930 #endif
3931                 "mov %%cr2, %%"R"ax   \n\t"
3932                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3933
3934                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3935                 "setbe %c[fail](%0) \n\t"
3936               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3937                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3938                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3939                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3940                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3941                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3942                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3943                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3944                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3945                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3946                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3947 #ifdef CONFIG_X86_64
3948                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3949                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3950                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3951                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3952                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3953                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3954                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3955                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3956 #endif
3957                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3958               : "cc", "memory"
3959                 , R"bx", R"di", R"si"
3960 #ifdef CONFIG_X86_64
3961                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3962 #endif
3963               );
3964
3965         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3966                                   | (1 << VCPU_EXREG_PDPTR));
3967         vcpu->arch.regs_dirty = 0;
3968
3969         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3970         if (vmx->rmode.irq.pending)
3971                 fixup_rmode_irq(vmx);
3972
3973         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3974         vmx->launched = 1;
3975
3976         vmx_complete_interrupts(vmx);
3977 }
3978
3979 #undef R
3980 #undef Q
3981
3982 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3983 {
3984         struct vcpu_vmx *vmx = to_vmx(vcpu);
3985
3986         if (vmx->vmcs) {
3987                 vcpu_clear(vmx);
3988                 free_vmcs(vmx->vmcs);
3989                 vmx->vmcs = NULL;
3990         }
3991 }
3992
3993 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3994 {
3995         struct vcpu_vmx *vmx = to_vmx(vcpu);
3996
3997         free_vpid(vmx);
3998         vmx_free_vmcs(vcpu);
3999         kfree(vmx->guest_msrs);
4000         kvm_vcpu_uninit(vcpu);
4001         kmem_cache_free(kvm_vcpu_cache, vmx);
4002 }
4003
4004 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4005 {
4006         int err;
4007         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4008         int cpu;
4009
4010         if (!vmx)
4011                 return ERR_PTR(-ENOMEM);
4012
4013         allocate_vpid(vmx);
4014
4015         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4016         if (err)
4017                 goto free_vcpu;
4018
4019         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4020         if (!vmx->guest_msrs) {
4021                 err = -ENOMEM;
4022                 goto uninit_vcpu;
4023         }
4024
4025         vmx->vmcs = alloc_vmcs();
4026         if (!vmx->vmcs)
4027                 goto free_msrs;
4028
4029         vmcs_clear(vmx->vmcs);
4030
4031         cpu = get_cpu();
4032         vmx_vcpu_load(&vmx->vcpu, cpu);
4033         err = vmx_vcpu_setup(vmx);
4034         vmx_vcpu_put(&vmx->vcpu);
4035         put_cpu();
4036         if (err)
4037                 goto free_vmcs;
4038         if (vm_need_virtualize_apic_accesses(kvm))
4039                 if (alloc_apic_access_page(kvm) != 0)
4040                         goto free_vmcs;
4041
4042         if (enable_ept) {
4043                 if (!kvm->arch.ept_identity_map_addr)
4044                         kvm->arch.ept_identity_map_addr =
4045                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4046                 if (alloc_identity_pagetable(kvm) != 0)
4047                         goto free_vmcs;
4048         }
4049
4050         return &vmx->vcpu;
4051
4052 free_vmcs:
4053         free_vmcs(vmx->vmcs);
4054 free_msrs:
4055         kfree(vmx->guest_msrs);
4056 uninit_vcpu:
4057         kvm_vcpu_uninit(&vmx->vcpu);
4058 free_vcpu:
4059         free_vpid(vmx);
4060         kmem_cache_free(kvm_vcpu_cache, vmx);
4061         return ERR_PTR(err);
4062 }
4063
4064 static void __init vmx_check_processor_compat(void *rtn)
4065 {
4066         struct vmcs_config vmcs_conf;
4067
4068         *(int *)rtn = 0;
4069         if (setup_vmcs_config(&vmcs_conf) < 0)
4070                 *(int *)rtn = -EIO;
4071         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4072                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4073                                 smp_processor_id());
4074                 *(int *)rtn = -EIO;
4075         }
4076 }
4077
4078 static int get_ept_level(void)
4079 {
4080         return VMX_EPT_DEFAULT_GAW + 1;
4081 }
4082
4083 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4084 {
4085         u64 ret;
4086
4087         /* For VT-d and EPT combination
4088          * 1. MMIO: always map as UC
4089          * 2. EPT with VT-d:
4090          *   a. VT-d without snooping control feature: can't guarantee the
4091          *      result, try to trust guest.
4092          *   b. VT-d with snooping control feature: snooping control feature of
4093          *      VT-d engine can guarantee the cache correctness. Just set it
4094          *      to WB to keep consistent with host. So the same as item 3.
4095          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4096          *    consistent with host MTRR
4097          */
4098         if (is_mmio)
4099                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4100         else if (vcpu->kvm->arch.iommu_domain &&
4101                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4102                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4103                       VMX_EPT_MT_EPTE_SHIFT;
4104         else
4105                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4106                         | VMX_EPT_IPAT_BIT;
4107
4108         return ret;
4109 }
4110
4111 #define _ER(x) { EXIT_REASON_##x, #x }
4112
4113 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4114         _ER(EXCEPTION_NMI),
4115         _ER(EXTERNAL_INTERRUPT),
4116         _ER(TRIPLE_FAULT),
4117         _ER(PENDING_INTERRUPT),
4118         _ER(NMI_WINDOW),
4119         _ER(TASK_SWITCH),
4120         _ER(CPUID),
4121         _ER(HLT),
4122         _ER(INVLPG),
4123         _ER(RDPMC),
4124         _ER(RDTSC),
4125         _ER(VMCALL),
4126         _ER(VMCLEAR),
4127         _ER(VMLAUNCH),
4128         _ER(VMPTRLD),
4129         _ER(VMPTRST),
4130         _ER(VMREAD),
4131         _ER(VMRESUME),
4132         _ER(VMWRITE),
4133         _ER(VMOFF),
4134         _ER(VMON),
4135         _ER(CR_ACCESS),
4136         _ER(DR_ACCESS),
4137         _ER(IO_INSTRUCTION),
4138         _ER(MSR_READ),
4139         _ER(MSR_WRITE),
4140         _ER(MWAIT_INSTRUCTION),
4141         _ER(MONITOR_INSTRUCTION),
4142         _ER(PAUSE_INSTRUCTION),
4143         _ER(MCE_DURING_VMENTRY),
4144         _ER(TPR_BELOW_THRESHOLD),
4145         _ER(APIC_ACCESS),
4146         _ER(EPT_VIOLATION),
4147         _ER(EPT_MISCONFIG),
4148         _ER(WBINVD),
4149         { -1, NULL }
4150 };
4151
4152 #undef _ER
4153
4154 static int vmx_get_lpage_level(void)
4155 {
4156         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4157                 return PT_DIRECTORY_LEVEL;
4158         else
4159                 /* For shadow and EPT supported 1GB page */
4160                 return PT_PDPE_LEVEL;
4161 }
4162
4163 static inline u32 bit(int bitno)
4164 {
4165         return 1 << (bitno & 31);
4166 }
4167
4168 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4169 {
4170         struct kvm_cpuid_entry2 *best;
4171         struct vcpu_vmx *vmx = to_vmx(vcpu);
4172         u32 exec_control;
4173
4174         vmx->rdtscp_enabled = false;
4175         if (vmx_rdtscp_supported()) {
4176                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4177                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4178                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4179                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4180                                 vmx->rdtscp_enabled = true;
4181                         else {
4182                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4183                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4184                                                 exec_control);
4185                         }
4186                 }
4187         }
4188 }
4189
4190 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4191 {
4192 }
4193
4194 static struct kvm_x86_ops vmx_x86_ops = {
4195         .cpu_has_kvm_support = cpu_has_kvm_support,
4196         .disabled_by_bios = vmx_disabled_by_bios,
4197         .hardware_setup = hardware_setup,
4198         .hardware_unsetup = hardware_unsetup,
4199         .check_processor_compatibility = vmx_check_processor_compat,
4200         .hardware_enable = hardware_enable,
4201         .hardware_disable = hardware_disable,
4202         .cpu_has_accelerated_tpr = report_flexpriority,
4203
4204         .vcpu_create = vmx_create_vcpu,
4205         .vcpu_free = vmx_free_vcpu,
4206         .vcpu_reset = vmx_vcpu_reset,
4207
4208         .prepare_guest_switch = vmx_save_host_state,
4209         .vcpu_load = vmx_vcpu_load,
4210         .vcpu_put = vmx_vcpu_put,
4211
4212         .set_guest_debug = set_guest_debug,
4213         .get_msr = vmx_get_msr,
4214         .set_msr = vmx_set_msr,
4215         .get_segment_base = vmx_get_segment_base,
4216         .get_segment = vmx_get_segment,
4217         .set_segment = vmx_set_segment,
4218         .get_cpl = vmx_get_cpl,
4219         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4220         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4221         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4222         .set_cr0 = vmx_set_cr0,
4223         .set_cr3 = vmx_set_cr3,
4224         .set_cr4 = vmx_set_cr4,
4225         .set_efer = vmx_set_efer,
4226         .get_idt = vmx_get_idt,
4227         .set_idt = vmx_set_idt,
4228         .get_gdt = vmx_get_gdt,
4229         .set_gdt = vmx_set_gdt,
4230         .set_dr7 = vmx_set_dr7,
4231         .cache_reg = vmx_cache_reg,
4232         .get_rflags = vmx_get_rflags,
4233         .set_rflags = vmx_set_rflags,
4234         .fpu_activate = vmx_fpu_activate,
4235         .fpu_deactivate = vmx_fpu_deactivate,
4236
4237         .tlb_flush = vmx_flush_tlb,
4238
4239         .run = vmx_vcpu_run,
4240         .handle_exit = vmx_handle_exit,
4241         .skip_emulated_instruction = skip_emulated_instruction,
4242         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4243         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4244         .patch_hypercall = vmx_patch_hypercall,
4245         .set_irq = vmx_inject_irq,
4246         .set_nmi = vmx_inject_nmi,
4247         .queue_exception = vmx_queue_exception,
4248         .interrupt_allowed = vmx_interrupt_allowed,
4249         .nmi_allowed = vmx_nmi_allowed,
4250         .get_nmi_mask = vmx_get_nmi_mask,
4251         .set_nmi_mask = vmx_set_nmi_mask,
4252         .enable_nmi_window = enable_nmi_window,
4253         .enable_irq_window = enable_irq_window,
4254         .update_cr8_intercept = update_cr8_intercept,
4255
4256         .set_tss_addr = vmx_set_tss_addr,
4257         .get_tdp_level = get_ept_level,
4258         .get_mt_mask = vmx_get_mt_mask,
4259
4260         .exit_reasons_str = vmx_exit_reasons_str,
4261         .get_lpage_level = vmx_get_lpage_level,
4262
4263         .cpuid_update = vmx_cpuid_update,
4264
4265         .rdtscp_supported = vmx_rdtscp_supported,
4266
4267         .set_supported_cpuid = vmx_set_supported_cpuid,
4268 };
4269
4270 static int __init vmx_init(void)
4271 {
4272         int r, i;
4273
4274         rdmsrl_safe(MSR_EFER, &host_efer);
4275
4276         for (i = 0; i < NR_VMX_MSR; ++i)
4277                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4278
4279         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4280         if (!vmx_io_bitmap_a)
4281                 return -ENOMEM;
4282
4283         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4284         if (!vmx_io_bitmap_b) {
4285                 r = -ENOMEM;
4286                 goto out;
4287         }
4288
4289         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4290         if (!vmx_msr_bitmap_legacy) {
4291                 r = -ENOMEM;
4292                 goto out1;
4293         }
4294
4295         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4296         if (!vmx_msr_bitmap_longmode) {
4297                 r = -ENOMEM;
4298                 goto out2;
4299         }
4300
4301         /*
4302          * Allow direct access to the PC debug port (it is often used for I/O
4303          * delays, but the vmexits simply slow things down).
4304          */
4305         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4306         clear_bit(0x80, vmx_io_bitmap_a);
4307
4308         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4309
4310         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4311         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4312
4313         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4314
4315         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4316                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4317         if (r)
4318                 goto out3;
4319
4320         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4321         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4322         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4323         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4324         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4325         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4326
4327         if (enable_ept) {
4328                 bypass_guest_pf = 0;
4329                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4330                         VMX_EPT_WRITABLE_MASK);
4331                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4332                                 VMX_EPT_EXECUTABLE_MASK);
4333                 kvm_enable_tdp();
4334         } else
4335                 kvm_disable_tdp();
4336
4337         if (bypass_guest_pf)
4338                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4339
4340         return 0;
4341
4342 out3:
4343         free_page((unsigned long)vmx_msr_bitmap_longmode);
4344 out2:
4345         free_page((unsigned long)vmx_msr_bitmap_legacy);
4346 out1:
4347         free_page((unsigned long)vmx_io_bitmap_b);
4348 out:
4349         free_page((unsigned long)vmx_io_bitmap_a);
4350         return r;
4351 }
4352
4353 static void __exit vmx_exit(void)
4354 {
4355         free_page((unsigned long)vmx_msr_bitmap_legacy);
4356         free_page((unsigned long)vmx_msr_bitmap_longmode);
4357         free_page((unsigned long)vmx_io_bitmap_b);
4358         free_page((unsigned long)vmx_io_bitmap_a);
4359
4360         kvm_exit();
4361 }
4362
4363 module_init(vmx_init)
4364 module_exit(vmx_exit)