2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
30 #include "kvm_cache_regs.h"
36 #include <asm/virtext.h>
41 #define __ex(x) __kvm_handle_fault_on_reboot(x)
43 MODULE_AUTHOR("Qumranet");
44 MODULE_LICENSE("GPL");
46 static int __read_mostly bypass_guest_pf = 1;
47 module_param(bypass_guest_pf, bool, S_IRUGO);
49 static int __read_mostly enable_vpid = 1;
50 module_param_named(vpid, enable_vpid, bool, 0444);
52 static int __read_mostly flexpriority_enabled = 1;
53 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
55 static int __read_mostly enable_ept = 1;
56 module_param_named(ept, enable_ept, bool, S_IRUGO);
58 static int __read_mostly enable_unrestricted_guest = 1;
59 module_param_named(unrestricted_guest,
60 enable_unrestricted_guest, bool, S_IRUGO);
62 static int __read_mostly emulate_invalid_guest_state = 0;
63 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
65 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
66 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
67 #define KVM_GUEST_CR0_MASK \
68 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
69 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
70 (X86_CR0_WP | X86_CR0_NE)
71 #define KVM_VM_CR0_ALWAYS_ON \
72 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
73 #define KVM_CR4_GUEST_OWNED_BITS \
74 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
77 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
78 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
80 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
83 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
84 * ple_gap: upper bound on the amount of time between two successive
85 * executions of PAUSE in a loop. Also indicate if ple enabled.
86 * According to test, this time is usually small than 41 cycles.
87 * ple_window: upper bound on the amount of time a guest is allowed to execute
88 * in a PAUSE loop. Tests indicate that most spinlocks are held for
89 * less than 2^12 cycles
90 * Time is measured based on a counter that runs at the same rate as the TSC,
91 * refer SDM volume 3b section 21.6.13 & 22.1.3.
93 #define KVM_VMX_DEFAULT_PLE_GAP 41
94 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
95 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
96 module_param(ple_gap, int, S_IRUGO);
98 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
99 module_param(ple_window, int, S_IRUGO);
107 struct shared_msr_entry {
114 struct kvm_vcpu vcpu;
115 struct list_head local_vcpus_link;
116 unsigned long host_rsp;
119 u32 idt_vectoring_info;
120 struct shared_msr_entry *guest_msrs;
124 u64 msr_host_kernel_gs_base;
125 u64 msr_guest_kernel_gs_base;
130 u16 fs_sel, gs_sel, ldt_sel;
131 int gs_ldt_reload_needed;
132 int fs_reload_needed;
137 struct kvm_save_segment {
142 } tr, es, ds, fs, gs;
150 bool emulation_required;
152 /* Support for vnmi-less CPUs */
153 int soft_vnmi_blocked;
155 s64 vnmi_blocked_time;
161 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
163 return container_of(vcpu, struct vcpu_vmx, vcpu);
166 static int init_rmode(struct kvm *kvm);
167 static u64 construct_eptp(unsigned long root_hpa);
169 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
170 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
171 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
173 static unsigned long *vmx_io_bitmap_a;
174 static unsigned long *vmx_io_bitmap_b;
175 static unsigned long *vmx_msr_bitmap_legacy;
176 static unsigned long *vmx_msr_bitmap_longmode;
178 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
179 static DEFINE_SPINLOCK(vmx_vpid_lock);
181 static struct vmcs_config {
185 u32 pin_based_exec_ctrl;
186 u32 cpu_based_exec_ctrl;
187 u32 cpu_based_2nd_exec_ctrl;
192 static struct vmx_capability {
197 #define VMX_SEGMENT_FIELD(seg) \
198 [VCPU_SREG_##seg] = { \
199 .selector = GUEST_##seg##_SELECTOR, \
200 .base = GUEST_##seg##_BASE, \
201 .limit = GUEST_##seg##_LIMIT, \
202 .ar_bytes = GUEST_##seg##_AR_BYTES, \
205 static struct kvm_vmx_segment_field {
210 } kvm_vmx_segment_fields[] = {
211 VMX_SEGMENT_FIELD(CS),
212 VMX_SEGMENT_FIELD(DS),
213 VMX_SEGMENT_FIELD(ES),
214 VMX_SEGMENT_FIELD(FS),
215 VMX_SEGMENT_FIELD(GS),
216 VMX_SEGMENT_FIELD(SS),
217 VMX_SEGMENT_FIELD(TR),
218 VMX_SEGMENT_FIELD(LDTR),
221 static u64 host_efer;
223 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
226 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
227 * away by decrementing the array size.
229 static const u32 vmx_msr_index[] = {
231 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
233 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
235 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
237 static inline bool is_page_fault(u32 intr_info)
239 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
240 INTR_INFO_VALID_MASK)) ==
241 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
244 static inline bool is_no_device(u32 intr_info)
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
248 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
251 static inline bool is_invalid_opcode(u32 intr_info)
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
255 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
258 static inline bool is_external_interrupt(u32 intr_info)
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
261 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
264 static inline bool is_machine_check(u32 intr_info)
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
268 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
271 static inline bool cpu_has_vmx_msr_bitmap(void)
273 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
276 static inline bool cpu_has_vmx_tpr_shadow(void)
278 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
281 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
283 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
286 static inline bool cpu_has_secondary_exec_ctrls(void)
288 return vmcs_config.cpu_based_exec_ctrl &
289 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
292 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
294 return vmcs_config.cpu_based_2nd_exec_ctrl &
295 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
298 static inline bool cpu_has_vmx_flexpriority(void)
300 return cpu_has_vmx_tpr_shadow() &&
301 cpu_has_vmx_virtualize_apic_accesses();
304 static inline bool cpu_has_vmx_ept_execute_only(void)
306 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
309 static inline bool cpu_has_vmx_eptp_uncacheable(void)
311 return vmx_capability.ept & VMX_EPTP_UC_BIT;
314 static inline bool cpu_has_vmx_eptp_writeback(void)
316 return vmx_capability.ept & VMX_EPTP_WB_BIT;
319 static inline bool cpu_has_vmx_ept_2m_page(void)
321 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
324 static inline bool cpu_has_vmx_ept_1g_page(void)
326 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
329 static inline bool cpu_has_vmx_invept_individual_addr(void)
331 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
334 static inline bool cpu_has_vmx_invept_context(void)
336 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
339 static inline bool cpu_has_vmx_invept_global(void)
341 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
344 static inline bool cpu_has_vmx_ept(void)
346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_ENABLE_EPT;
350 static inline bool cpu_has_vmx_unrestricted_guest(void)
352 return vmcs_config.cpu_based_2nd_exec_ctrl &
353 SECONDARY_EXEC_UNRESTRICTED_GUEST;
356 static inline bool cpu_has_vmx_ple(void)
358 return vmcs_config.cpu_based_2nd_exec_ctrl &
359 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
362 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
364 return flexpriority_enabled && irqchip_in_kernel(kvm);
367 static inline bool cpu_has_vmx_vpid(void)
369 return vmcs_config.cpu_based_2nd_exec_ctrl &
370 SECONDARY_EXEC_ENABLE_VPID;
373 static inline bool cpu_has_vmx_rdtscp(void)
375 return vmcs_config.cpu_based_2nd_exec_ctrl &
376 SECONDARY_EXEC_RDTSCP;
379 static inline bool cpu_has_virtual_nmis(void)
381 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
384 static inline bool report_flexpriority(void)
386 return flexpriority_enabled;
389 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
393 for (i = 0; i < vmx->nmsrs; ++i)
394 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
399 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
405 } operand = { vpid, 0, gva };
407 asm volatile (__ex(ASM_VMX_INVVPID)
408 /* CF==1 or ZF==1 --> rc = -1 */
410 : : "a"(&operand), "c"(ext) : "cc", "memory");
413 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
417 } operand = {eptp, gpa};
419 asm volatile (__ex(ASM_VMX_INVEPT)
420 /* CF==1 or ZF==1 --> rc = -1 */
421 "; ja 1f ; ud2 ; 1:\n"
422 : : "a" (&operand), "c" (ext) : "cc", "memory");
425 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
429 i = __find_msr_index(vmx, msr);
431 return &vmx->guest_msrs[i];
435 static void vmcs_clear(struct vmcs *vmcs)
437 u64 phys_addr = __pa(vmcs);
440 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
441 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
444 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
448 static void __vcpu_clear(void *arg)
450 struct vcpu_vmx *vmx = arg;
451 int cpu = raw_smp_processor_id();
453 if (vmx->vcpu.cpu == cpu)
454 vmcs_clear(vmx->vmcs);
455 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
456 per_cpu(current_vmcs, cpu) = NULL;
457 rdtscll(vmx->vcpu.arch.host_tsc);
458 list_del(&vmx->local_vcpus_link);
463 static void vcpu_clear(struct vcpu_vmx *vmx)
465 if (vmx->vcpu.cpu == -1)
467 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
470 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
475 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
478 static inline void ept_sync_global(void)
480 if (cpu_has_vmx_invept_global())
481 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
484 static inline void ept_sync_context(u64 eptp)
487 if (cpu_has_vmx_invept_context())
488 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
494 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
497 if (cpu_has_vmx_invept_individual_addr())
498 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
501 ept_sync_context(eptp);
505 static unsigned long vmcs_readl(unsigned long field)
509 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
510 : "=a"(value) : "d"(field) : "cc");
514 static u16 vmcs_read16(unsigned long field)
516 return vmcs_readl(field);
519 static u32 vmcs_read32(unsigned long field)
521 return vmcs_readl(field);
524 static u64 vmcs_read64(unsigned long field)
527 return vmcs_readl(field);
529 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
533 static noinline void vmwrite_error(unsigned long field, unsigned long value)
535 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
536 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
540 static void vmcs_writel(unsigned long field, unsigned long value)
544 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
545 : "=q"(error) : "a"(value), "d"(field) : "cc");
547 vmwrite_error(field, value);
550 static void vmcs_write16(unsigned long field, u16 value)
552 vmcs_writel(field, value);
555 static void vmcs_write32(unsigned long field, u32 value)
557 vmcs_writel(field, value);
560 static void vmcs_write64(unsigned long field, u64 value)
562 vmcs_writel(field, value);
563 #ifndef CONFIG_X86_64
565 vmcs_writel(field+1, value >> 32);
569 static void vmcs_clear_bits(unsigned long field, u32 mask)
571 vmcs_writel(field, vmcs_readl(field) & ~mask);
574 static void vmcs_set_bits(unsigned long field, u32 mask)
576 vmcs_writel(field, vmcs_readl(field) | mask);
579 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
583 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
584 (1u << NM_VECTOR) | (1u << DB_VECTOR);
585 if ((vcpu->guest_debug &
586 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
587 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
588 eb |= 1u << BP_VECTOR;
589 if (to_vmx(vcpu)->rmode.vm86_active)
592 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
593 if (vcpu->fpu_active)
594 eb &= ~(1u << NM_VECTOR);
595 vmcs_write32(EXCEPTION_BITMAP, eb);
598 static void reload_tss(void)
601 * VT restores TR but not its size. Useless.
604 struct desc_struct *descs;
606 native_store_gdt(&gdt);
607 descs = (void *)gdt.address;
608 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
612 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
617 guest_efer = vmx->vcpu.arch.efer;
620 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
623 ignore_bits = EFER_NX | EFER_SCE;
625 ignore_bits |= EFER_LMA | EFER_LME;
626 /* SCE is meaningful only in long mode on Intel */
627 if (guest_efer & EFER_LMA)
628 ignore_bits &= ~(u64)EFER_SCE;
630 guest_efer &= ~ignore_bits;
631 guest_efer |= host_efer & ignore_bits;
632 vmx->guest_msrs[efer_offset].data = guest_efer;
633 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
637 static unsigned long segment_base(u16 selector)
640 struct desc_struct *d;
641 unsigned long table_base;
644 if (!(selector & ~3))
647 native_store_gdt(&gdt);
648 table_base = gdt.address;
650 if (selector & 4) { /* from ldt */
651 u16 ldt_selector = kvm_read_ldt();
653 if (!(ldt_selector & ~3))
656 table_base = segment_base(ldt_selector);
658 d = (struct desc_struct *)(table_base + (selector & ~7));
659 v = get_desc_base(d);
661 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
662 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
667 static inline unsigned long kvm_read_tr_base(void)
670 asm("str %0" : "=g"(tr));
671 return segment_base(tr);
674 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
676 struct vcpu_vmx *vmx = to_vmx(vcpu);
679 if (vmx->host_state.loaded)
682 vmx->host_state.loaded = 1;
684 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
685 * allow segment selectors with cpl > 0 or ti == 1.
687 vmx->host_state.ldt_sel = kvm_read_ldt();
688 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
689 vmx->host_state.fs_sel = kvm_read_fs();
690 if (!(vmx->host_state.fs_sel & 7)) {
691 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
692 vmx->host_state.fs_reload_needed = 0;
694 vmcs_write16(HOST_FS_SELECTOR, 0);
695 vmx->host_state.fs_reload_needed = 1;
697 vmx->host_state.gs_sel = kvm_read_gs();
698 if (!(vmx->host_state.gs_sel & 7))
699 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
701 vmcs_write16(HOST_GS_SELECTOR, 0);
702 vmx->host_state.gs_ldt_reload_needed = 1;
706 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
707 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
709 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
710 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
714 if (is_long_mode(&vmx->vcpu)) {
715 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
716 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
719 for (i = 0; i < vmx->save_nmsrs; ++i)
720 kvm_set_shared_msr(vmx->guest_msrs[i].index,
721 vmx->guest_msrs[i].data,
722 vmx->guest_msrs[i].mask);
725 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
729 if (!vmx->host_state.loaded)
732 ++vmx->vcpu.stat.host_state_reload;
733 vmx->host_state.loaded = 0;
734 if (vmx->host_state.fs_reload_needed)
735 kvm_load_fs(vmx->host_state.fs_sel);
736 if (vmx->host_state.gs_ldt_reload_needed) {
737 kvm_load_ldt(vmx->host_state.ldt_sel);
739 * If we have to reload gs, we must take care to
740 * preserve our gs base.
742 local_irq_save(flags);
743 kvm_load_gs(vmx->host_state.gs_sel);
745 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
747 local_irq_restore(flags);
751 if (is_long_mode(&vmx->vcpu)) {
752 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
753 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
758 static void vmx_load_host_state(struct vcpu_vmx *vmx)
761 __vmx_load_host_state(vmx);
766 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
767 * vcpu mutex is already taken.
769 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
771 struct vcpu_vmx *vmx = to_vmx(vcpu);
772 u64 phys_addr = __pa(vmx->vmcs);
773 u64 tsc_this, delta, new_offset;
775 if (vcpu->cpu != cpu) {
777 kvm_migrate_timers(vcpu);
778 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
780 list_add(&vmx->local_vcpus_link,
781 &per_cpu(vcpus_on_cpu, cpu));
785 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
788 per_cpu(current_vmcs, cpu) = vmx->vmcs;
789 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
790 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
793 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
794 vmx->vmcs, phys_addr);
797 if (vcpu->cpu != cpu) {
799 unsigned long sysenter_esp;
803 * Linux uses per-cpu TSS and GDT, so set these when switching
806 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
807 native_store_gdt(&dt);
808 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
810 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
811 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
814 * Make sure the time stamp counter is monotonous.
817 if (tsc_this < vcpu->arch.host_tsc) {
818 delta = vcpu->arch.host_tsc - tsc_this;
819 new_offset = vmcs_read64(TSC_OFFSET) + delta;
820 vmcs_write64(TSC_OFFSET, new_offset);
825 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
827 __vmx_load_host_state(to_vmx(vcpu));
830 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
834 if (vcpu->fpu_active)
836 vcpu->fpu_active = 1;
837 cr0 = vmcs_readl(GUEST_CR0);
838 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
839 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
840 vmcs_writel(GUEST_CR0, cr0);
841 update_exception_bitmap(vcpu);
842 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
843 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
846 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
848 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
850 vmx_decache_cr0_guest_bits(vcpu);
851 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
852 update_exception_bitmap(vcpu);
853 vcpu->arch.cr0_guest_owned_bits = 0;
854 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
855 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
858 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
860 unsigned long rflags, save_rflags;
862 rflags = vmcs_readl(GUEST_RFLAGS);
863 if (to_vmx(vcpu)->rmode.vm86_active) {
864 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
865 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
866 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
871 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
873 if (to_vmx(vcpu)->rmode.vm86_active) {
874 to_vmx(vcpu)->rmode.save_rflags = rflags;
875 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
877 vmcs_writel(GUEST_RFLAGS, rflags);
880 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
882 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
885 if (interruptibility & GUEST_INTR_STATE_STI)
886 ret |= KVM_X86_SHADOW_INT_STI;
887 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
888 ret |= KVM_X86_SHADOW_INT_MOV_SS;
893 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
895 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
896 u32 interruptibility = interruptibility_old;
898 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
900 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
901 interruptibility |= GUEST_INTR_STATE_MOV_SS;
902 else if (mask & KVM_X86_SHADOW_INT_STI)
903 interruptibility |= GUEST_INTR_STATE_STI;
905 if ((interruptibility != interruptibility_old))
906 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
909 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
913 rip = kvm_rip_read(vcpu);
914 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
915 kvm_rip_write(vcpu, rip);
917 /* skipping an emulated instruction also counts */
918 vmx_set_interrupt_shadow(vcpu, 0);
921 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
922 bool has_error_code, u32 error_code)
924 struct vcpu_vmx *vmx = to_vmx(vcpu);
925 u32 intr_info = nr | INTR_INFO_VALID_MASK;
927 if (has_error_code) {
928 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
929 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
932 if (vmx->rmode.vm86_active) {
933 vmx->rmode.irq.pending = true;
934 vmx->rmode.irq.vector = nr;
935 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
936 if (kvm_exception_is_soft(nr))
937 vmx->rmode.irq.rip +=
938 vmx->vcpu.arch.event_exit_inst_len;
939 intr_info |= INTR_TYPE_SOFT_INTR;
940 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
941 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
942 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
946 if (kvm_exception_is_soft(nr)) {
947 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
948 vmx->vcpu.arch.event_exit_inst_len);
949 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
951 intr_info |= INTR_TYPE_HARD_EXCEPTION;
953 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
956 static bool vmx_rdtscp_supported(void)
958 return cpu_has_vmx_rdtscp();
962 * Swap MSR entry in host/guest MSR entry array.
964 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
966 struct shared_msr_entry tmp;
968 tmp = vmx->guest_msrs[to];
969 vmx->guest_msrs[to] = vmx->guest_msrs[from];
970 vmx->guest_msrs[from] = tmp;
974 * Set up the vmcs to automatically save and restore system
975 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
976 * mode, as fiddling with msrs is very expensive.
978 static void setup_msrs(struct vcpu_vmx *vmx)
980 int save_nmsrs, index;
981 unsigned long *msr_bitmap;
983 vmx_load_host_state(vmx);
986 if (is_long_mode(&vmx->vcpu)) {
987 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
989 move_msr_up(vmx, index, save_nmsrs++);
990 index = __find_msr_index(vmx, MSR_LSTAR);
992 move_msr_up(vmx, index, save_nmsrs++);
993 index = __find_msr_index(vmx, MSR_CSTAR);
995 move_msr_up(vmx, index, save_nmsrs++);
996 index = __find_msr_index(vmx, MSR_TSC_AUX);
997 if (index >= 0 && vmx->rdtscp_enabled)
998 move_msr_up(vmx, index, save_nmsrs++);
1000 * MSR_K6_STAR is only needed on long mode guests, and only
1001 * if efer.sce is enabled.
1003 index = __find_msr_index(vmx, MSR_K6_STAR);
1004 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1005 move_msr_up(vmx, index, save_nmsrs++);
1008 index = __find_msr_index(vmx, MSR_EFER);
1009 if (index >= 0 && update_transition_efer(vmx, index))
1010 move_msr_up(vmx, index, save_nmsrs++);
1012 vmx->save_nmsrs = save_nmsrs;
1014 if (cpu_has_vmx_msr_bitmap()) {
1015 if (is_long_mode(&vmx->vcpu))
1016 msr_bitmap = vmx_msr_bitmap_longmode;
1018 msr_bitmap = vmx_msr_bitmap_legacy;
1020 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1025 * reads and returns guest's timestamp counter "register"
1026 * guest_tsc = host_tsc + tsc_offset -- 21.3
1028 static u64 guest_read_tsc(void)
1030 u64 host_tsc, tsc_offset;
1033 tsc_offset = vmcs_read64(TSC_OFFSET);
1034 return host_tsc + tsc_offset;
1038 * writes 'guest_tsc' into guest's timestamp counter "register"
1039 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1041 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1043 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1047 * Reads an msr value (of 'msr_index') into 'pdata'.
1048 * Returns 0 on success, non-0 otherwise.
1049 * Assumes vcpu_load() was already called.
1051 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1054 struct shared_msr_entry *msr;
1057 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1061 switch (msr_index) {
1062 #ifdef CONFIG_X86_64
1064 data = vmcs_readl(GUEST_FS_BASE);
1067 data = vmcs_readl(GUEST_GS_BASE);
1069 case MSR_KERNEL_GS_BASE:
1070 vmx_load_host_state(to_vmx(vcpu));
1071 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1075 return kvm_get_msr_common(vcpu, msr_index, pdata);
1077 data = guest_read_tsc();
1079 case MSR_IA32_SYSENTER_CS:
1080 data = vmcs_read32(GUEST_SYSENTER_CS);
1082 case MSR_IA32_SYSENTER_EIP:
1083 data = vmcs_readl(GUEST_SYSENTER_EIP);
1085 case MSR_IA32_SYSENTER_ESP:
1086 data = vmcs_readl(GUEST_SYSENTER_ESP);
1089 if (!to_vmx(vcpu)->rdtscp_enabled)
1091 /* Otherwise falls through */
1093 vmx_load_host_state(to_vmx(vcpu));
1094 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1096 vmx_load_host_state(to_vmx(vcpu));
1100 return kvm_get_msr_common(vcpu, msr_index, pdata);
1108 * Writes msr value into into the appropriate "register".
1109 * Returns 0 on success, non-0 otherwise.
1110 * Assumes vcpu_load() was already called.
1112 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1114 struct vcpu_vmx *vmx = to_vmx(vcpu);
1115 struct shared_msr_entry *msr;
1119 switch (msr_index) {
1121 vmx_load_host_state(vmx);
1122 ret = kvm_set_msr_common(vcpu, msr_index, data);
1124 #ifdef CONFIG_X86_64
1126 vmcs_writel(GUEST_FS_BASE, data);
1129 vmcs_writel(GUEST_GS_BASE, data);
1131 case MSR_KERNEL_GS_BASE:
1132 vmx_load_host_state(vmx);
1133 vmx->msr_guest_kernel_gs_base = data;
1136 case MSR_IA32_SYSENTER_CS:
1137 vmcs_write32(GUEST_SYSENTER_CS, data);
1139 case MSR_IA32_SYSENTER_EIP:
1140 vmcs_writel(GUEST_SYSENTER_EIP, data);
1142 case MSR_IA32_SYSENTER_ESP:
1143 vmcs_writel(GUEST_SYSENTER_ESP, data);
1147 guest_write_tsc(data, host_tsc);
1149 case MSR_IA32_CR_PAT:
1150 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1151 vmcs_write64(GUEST_IA32_PAT, data);
1152 vcpu->arch.pat = data;
1155 ret = kvm_set_msr_common(vcpu, msr_index, data);
1158 if (!vmx->rdtscp_enabled)
1160 /* Check reserved bit, higher 32 bits should be zero */
1161 if ((data >> 32) != 0)
1163 /* Otherwise falls through */
1165 msr = find_msr_entry(vmx, msr_index);
1167 vmx_load_host_state(vmx);
1171 ret = kvm_set_msr_common(vcpu, msr_index, data);
1177 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1179 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1182 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1185 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1187 case VCPU_EXREG_PDPTR:
1189 ept_save_pdptrs(vcpu);
1196 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1198 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1199 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1201 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1203 update_exception_bitmap(vcpu);
1206 static __init int cpu_has_kvm_support(void)
1208 return cpu_has_vmx();
1211 static __init int vmx_disabled_by_bios(void)
1215 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1216 return (msr & (FEATURE_CONTROL_LOCKED |
1217 FEATURE_CONTROL_VMXON_ENABLED))
1218 == FEATURE_CONTROL_LOCKED;
1219 /* locked but not enabled */
1222 static int hardware_enable(void *garbage)
1224 int cpu = raw_smp_processor_id();
1225 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1228 if (read_cr4() & X86_CR4_VMXE)
1231 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1232 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1233 if ((old & (FEATURE_CONTROL_LOCKED |
1234 FEATURE_CONTROL_VMXON_ENABLED))
1235 != (FEATURE_CONTROL_LOCKED |
1236 FEATURE_CONTROL_VMXON_ENABLED))
1237 /* enable and lock */
1238 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1239 FEATURE_CONTROL_LOCKED |
1240 FEATURE_CONTROL_VMXON_ENABLED);
1241 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1242 asm volatile (ASM_VMX_VMXON_RAX
1243 : : "a"(&phys_addr), "m"(phys_addr)
1251 static void vmclear_local_vcpus(void)
1253 int cpu = raw_smp_processor_id();
1254 struct vcpu_vmx *vmx, *n;
1256 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1262 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1265 static void kvm_cpu_vmxoff(void)
1267 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1268 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1271 static void hardware_disable(void *garbage)
1273 vmclear_local_vcpus();
1277 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1278 u32 msr, u32 *result)
1280 u32 vmx_msr_low, vmx_msr_high;
1281 u32 ctl = ctl_min | ctl_opt;
1283 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1285 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1286 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1288 /* Ensure minimum (required) set of control bits are supported. */
1296 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1298 u32 vmx_msr_low, vmx_msr_high;
1299 u32 min, opt, min2, opt2;
1300 u32 _pin_based_exec_control = 0;
1301 u32 _cpu_based_exec_control = 0;
1302 u32 _cpu_based_2nd_exec_control = 0;
1303 u32 _vmexit_control = 0;
1304 u32 _vmentry_control = 0;
1306 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1307 opt = PIN_BASED_VIRTUAL_NMIS;
1308 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1309 &_pin_based_exec_control) < 0)
1312 min = CPU_BASED_HLT_EXITING |
1313 #ifdef CONFIG_X86_64
1314 CPU_BASED_CR8_LOAD_EXITING |
1315 CPU_BASED_CR8_STORE_EXITING |
1317 CPU_BASED_CR3_LOAD_EXITING |
1318 CPU_BASED_CR3_STORE_EXITING |
1319 CPU_BASED_USE_IO_BITMAPS |
1320 CPU_BASED_MOV_DR_EXITING |
1321 CPU_BASED_USE_TSC_OFFSETING |
1322 CPU_BASED_MWAIT_EXITING |
1323 CPU_BASED_MONITOR_EXITING |
1324 CPU_BASED_INVLPG_EXITING;
1325 opt = CPU_BASED_TPR_SHADOW |
1326 CPU_BASED_USE_MSR_BITMAPS |
1327 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1328 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1329 &_cpu_based_exec_control) < 0)
1331 #ifdef CONFIG_X86_64
1332 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1333 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1334 ~CPU_BASED_CR8_STORE_EXITING;
1336 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1338 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1339 SECONDARY_EXEC_WBINVD_EXITING |
1340 SECONDARY_EXEC_ENABLE_VPID |
1341 SECONDARY_EXEC_ENABLE_EPT |
1342 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1343 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1344 SECONDARY_EXEC_RDTSCP;
1345 if (adjust_vmx_controls(min2, opt2,
1346 MSR_IA32_VMX_PROCBASED_CTLS2,
1347 &_cpu_based_2nd_exec_control) < 0)
1350 #ifndef CONFIG_X86_64
1351 if (!(_cpu_based_2nd_exec_control &
1352 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1353 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1355 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1356 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1358 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1359 CPU_BASED_CR3_STORE_EXITING |
1360 CPU_BASED_INVLPG_EXITING);
1361 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1362 vmx_capability.ept, vmx_capability.vpid);
1366 #ifdef CONFIG_X86_64
1367 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1369 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1370 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1371 &_vmexit_control) < 0)
1375 opt = VM_ENTRY_LOAD_IA32_PAT;
1376 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1377 &_vmentry_control) < 0)
1380 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1382 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1383 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1386 #ifdef CONFIG_X86_64
1387 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1388 if (vmx_msr_high & (1u<<16))
1392 /* Require Write-Back (WB) memory type for VMCS accesses. */
1393 if (((vmx_msr_high >> 18) & 15) != 6)
1396 vmcs_conf->size = vmx_msr_high & 0x1fff;
1397 vmcs_conf->order = get_order(vmcs_config.size);
1398 vmcs_conf->revision_id = vmx_msr_low;
1400 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1401 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1402 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1403 vmcs_conf->vmexit_ctrl = _vmexit_control;
1404 vmcs_conf->vmentry_ctrl = _vmentry_control;
1409 static struct vmcs *alloc_vmcs_cpu(int cpu)
1411 int node = cpu_to_node(cpu);
1415 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1418 vmcs = page_address(pages);
1419 memset(vmcs, 0, vmcs_config.size);
1420 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1424 static struct vmcs *alloc_vmcs(void)
1426 return alloc_vmcs_cpu(raw_smp_processor_id());
1429 static void free_vmcs(struct vmcs *vmcs)
1431 free_pages((unsigned long)vmcs, vmcs_config.order);
1434 static void free_kvm_area(void)
1438 for_each_possible_cpu(cpu) {
1439 free_vmcs(per_cpu(vmxarea, cpu));
1440 per_cpu(vmxarea, cpu) = NULL;
1444 static __init int alloc_kvm_area(void)
1448 for_each_possible_cpu(cpu) {
1451 vmcs = alloc_vmcs_cpu(cpu);
1457 per_cpu(vmxarea, cpu) = vmcs;
1462 static __init int hardware_setup(void)
1464 if (setup_vmcs_config(&vmcs_config) < 0)
1467 if (boot_cpu_has(X86_FEATURE_NX))
1468 kvm_enable_efer_bits(EFER_NX);
1470 if (!cpu_has_vmx_vpid())
1473 if (!cpu_has_vmx_ept()) {
1475 enable_unrestricted_guest = 0;
1478 if (!cpu_has_vmx_unrestricted_guest())
1479 enable_unrestricted_guest = 0;
1481 if (!cpu_has_vmx_flexpriority())
1482 flexpriority_enabled = 0;
1484 if (!cpu_has_vmx_tpr_shadow())
1485 kvm_x86_ops->update_cr8_intercept = NULL;
1487 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1488 kvm_disable_largepages();
1490 if (!cpu_has_vmx_ple())
1493 return alloc_kvm_area();
1496 static __exit void hardware_unsetup(void)
1501 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1503 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1505 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1506 vmcs_write16(sf->selector, save->selector);
1507 vmcs_writel(sf->base, save->base);
1508 vmcs_write32(sf->limit, save->limit);
1509 vmcs_write32(sf->ar_bytes, save->ar);
1511 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1513 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1517 static void enter_pmode(struct kvm_vcpu *vcpu)
1519 unsigned long flags;
1520 struct vcpu_vmx *vmx = to_vmx(vcpu);
1522 vmx->emulation_required = 1;
1523 vmx->rmode.vm86_active = 0;
1525 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1526 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1527 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1529 flags = vmcs_readl(GUEST_RFLAGS);
1530 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1531 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1532 vmcs_writel(GUEST_RFLAGS, flags);
1534 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1535 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1537 update_exception_bitmap(vcpu);
1539 if (emulate_invalid_guest_state)
1542 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1543 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1544 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1545 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1547 vmcs_write16(GUEST_SS_SELECTOR, 0);
1548 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1550 vmcs_write16(GUEST_CS_SELECTOR,
1551 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1552 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1555 static gva_t rmode_tss_base(struct kvm *kvm)
1557 if (!kvm->arch.tss_addr) {
1558 struct kvm_memslots *slots;
1561 slots = kvm_memslots(kvm);
1562 base_gfn = kvm->memslots->memslots[0].base_gfn +
1563 kvm->memslots->memslots[0].npages - 3;
1564 return base_gfn << PAGE_SHIFT;
1566 return kvm->arch.tss_addr;
1569 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1571 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1573 save->selector = vmcs_read16(sf->selector);
1574 save->base = vmcs_readl(sf->base);
1575 save->limit = vmcs_read32(sf->limit);
1576 save->ar = vmcs_read32(sf->ar_bytes);
1577 vmcs_write16(sf->selector, save->base >> 4);
1578 vmcs_write32(sf->base, save->base & 0xfffff);
1579 vmcs_write32(sf->limit, 0xffff);
1580 vmcs_write32(sf->ar_bytes, 0xf3);
1583 static void enter_rmode(struct kvm_vcpu *vcpu)
1585 unsigned long flags;
1586 struct vcpu_vmx *vmx = to_vmx(vcpu);
1588 if (enable_unrestricted_guest)
1591 vmx->emulation_required = 1;
1592 vmx->rmode.vm86_active = 1;
1594 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1595 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1597 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1598 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1600 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1601 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1603 flags = vmcs_readl(GUEST_RFLAGS);
1604 vmx->rmode.save_rflags = flags;
1606 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1608 vmcs_writel(GUEST_RFLAGS, flags);
1609 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1610 update_exception_bitmap(vcpu);
1612 if (emulate_invalid_guest_state)
1613 goto continue_rmode;
1615 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1616 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1617 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1619 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1620 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1621 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1622 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1623 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1625 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1626 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1627 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1628 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1631 kvm_mmu_reset_context(vcpu);
1632 init_rmode(vcpu->kvm);
1635 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1637 struct vcpu_vmx *vmx = to_vmx(vcpu);
1638 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1644 * Force kernel_gs_base reloading before EFER changes, as control
1645 * of this msr depends on is_long_mode().
1647 vmx_load_host_state(to_vmx(vcpu));
1648 vcpu->arch.efer = efer;
1649 if (efer & EFER_LMA) {
1650 vmcs_write32(VM_ENTRY_CONTROLS,
1651 vmcs_read32(VM_ENTRY_CONTROLS) |
1652 VM_ENTRY_IA32E_MODE);
1655 vmcs_write32(VM_ENTRY_CONTROLS,
1656 vmcs_read32(VM_ENTRY_CONTROLS) &
1657 ~VM_ENTRY_IA32E_MODE);
1659 msr->data = efer & ~EFER_LME;
1664 #ifdef CONFIG_X86_64
1666 static void enter_lmode(struct kvm_vcpu *vcpu)
1670 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1671 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1672 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1674 vmcs_write32(GUEST_TR_AR_BYTES,
1675 (guest_tr_ar & ~AR_TYPE_MASK)
1676 | AR_TYPE_BUSY_64_TSS);
1678 vcpu->arch.efer |= EFER_LMA;
1679 vmx_set_efer(vcpu, vcpu->arch.efer);
1682 static void exit_lmode(struct kvm_vcpu *vcpu)
1684 vcpu->arch.efer &= ~EFER_LMA;
1686 vmcs_write32(VM_ENTRY_CONTROLS,
1687 vmcs_read32(VM_ENTRY_CONTROLS)
1688 & ~VM_ENTRY_IA32E_MODE);
1693 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1695 vpid_sync_vcpu_all(to_vmx(vcpu));
1697 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1700 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1702 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1704 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1705 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1708 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1710 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1712 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1713 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1716 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1718 if (!test_bit(VCPU_EXREG_PDPTR,
1719 (unsigned long *)&vcpu->arch.regs_dirty))
1722 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1723 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1724 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1725 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1726 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1730 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1732 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1733 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1734 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1735 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1736 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1739 __set_bit(VCPU_EXREG_PDPTR,
1740 (unsigned long *)&vcpu->arch.regs_avail);
1741 __set_bit(VCPU_EXREG_PDPTR,
1742 (unsigned long *)&vcpu->arch.regs_dirty);
1745 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1747 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1749 struct kvm_vcpu *vcpu)
1751 if (!(cr0 & X86_CR0_PG)) {
1752 /* From paging/starting to nonpaging */
1753 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1754 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1755 (CPU_BASED_CR3_LOAD_EXITING |
1756 CPU_BASED_CR3_STORE_EXITING));
1757 vcpu->arch.cr0 = cr0;
1758 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1759 } else if (!is_paging(vcpu)) {
1760 /* From nonpaging to paging */
1761 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1762 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1763 ~(CPU_BASED_CR3_LOAD_EXITING |
1764 CPU_BASED_CR3_STORE_EXITING));
1765 vcpu->arch.cr0 = cr0;
1766 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1769 if (!(cr0 & X86_CR0_WP))
1770 *hw_cr0 &= ~X86_CR0_WP;
1773 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1775 struct vcpu_vmx *vmx = to_vmx(vcpu);
1776 unsigned long hw_cr0;
1778 if (enable_unrestricted_guest)
1779 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1780 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1782 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1784 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1787 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1790 #ifdef CONFIG_X86_64
1791 if (vcpu->arch.efer & EFER_LME) {
1792 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1794 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1800 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1802 if (!vcpu->fpu_active)
1803 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1805 vmcs_writel(CR0_READ_SHADOW, cr0);
1806 vmcs_writel(GUEST_CR0, hw_cr0);
1807 vcpu->arch.cr0 = cr0;
1810 static u64 construct_eptp(unsigned long root_hpa)
1814 /* TODO write the value reading from MSR */
1815 eptp = VMX_EPT_DEFAULT_MT |
1816 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1817 eptp |= (root_hpa & PAGE_MASK);
1822 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1824 unsigned long guest_cr3;
1829 eptp = construct_eptp(cr3);
1830 vmcs_write64(EPT_POINTER, eptp);
1831 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1832 vcpu->kvm->arch.ept_identity_map_addr;
1833 ept_load_pdptrs(vcpu);
1836 vmx_flush_tlb(vcpu);
1837 vmcs_writel(GUEST_CR3, guest_cr3);
1840 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1842 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1843 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1845 vcpu->arch.cr4 = cr4;
1847 if (!is_paging(vcpu)) {
1848 hw_cr4 &= ~X86_CR4_PAE;
1849 hw_cr4 |= X86_CR4_PSE;
1850 } else if (!(cr4 & X86_CR4_PAE)) {
1851 hw_cr4 &= ~X86_CR4_PAE;
1855 vmcs_writel(CR4_READ_SHADOW, cr4);
1856 vmcs_writel(GUEST_CR4, hw_cr4);
1859 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1861 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1863 return vmcs_readl(sf->base);
1866 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1867 struct kvm_segment *var, int seg)
1869 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1872 var->base = vmcs_readl(sf->base);
1873 var->limit = vmcs_read32(sf->limit);
1874 var->selector = vmcs_read16(sf->selector);
1875 ar = vmcs_read32(sf->ar_bytes);
1876 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1878 var->type = ar & 15;
1879 var->s = (ar >> 4) & 1;
1880 var->dpl = (ar >> 5) & 3;
1881 var->present = (ar >> 7) & 1;
1882 var->avl = (ar >> 12) & 1;
1883 var->l = (ar >> 13) & 1;
1884 var->db = (ar >> 14) & 1;
1885 var->g = (ar >> 15) & 1;
1886 var->unusable = (ar >> 16) & 1;
1889 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1891 if (!is_protmode(vcpu))
1894 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1897 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1900 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1907 ar = var->type & 15;
1908 ar |= (var->s & 1) << 4;
1909 ar |= (var->dpl & 3) << 5;
1910 ar |= (var->present & 1) << 7;
1911 ar |= (var->avl & 1) << 12;
1912 ar |= (var->l & 1) << 13;
1913 ar |= (var->db & 1) << 14;
1914 ar |= (var->g & 1) << 15;
1916 if (ar == 0) /* a 0 value means unusable */
1917 ar = AR_UNUSABLE_MASK;
1922 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1923 struct kvm_segment *var, int seg)
1925 struct vcpu_vmx *vmx = to_vmx(vcpu);
1926 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1929 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1930 vmx->rmode.tr.selector = var->selector;
1931 vmx->rmode.tr.base = var->base;
1932 vmx->rmode.tr.limit = var->limit;
1933 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1936 vmcs_writel(sf->base, var->base);
1937 vmcs_write32(sf->limit, var->limit);
1938 vmcs_write16(sf->selector, var->selector);
1939 if (vmx->rmode.vm86_active && var->s) {
1941 * Hack real-mode segments into vm86 compatibility.
1943 if (var->base == 0xffff0000 && var->selector == 0xf000)
1944 vmcs_writel(sf->base, 0xf0000);
1947 ar = vmx_segment_access_rights(var);
1950 * Fix the "Accessed" bit in AR field of segment registers for older
1952 * IA32 arch specifies that at the time of processor reset the
1953 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1954 * is setting it to 0 in the usedland code. This causes invalid guest
1955 * state vmexit when "unrestricted guest" mode is turned on.
1956 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1957 * tree. Newer qemu binaries with that qemu fix would not need this
1960 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1961 ar |= 0x1; /* Accessed */
1963 vmcs_write32(sf->ar_bytes, ar);
1966 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1968 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1970 *db = (ar >> 14) & 1;
1971 *l = (ar >> 13) & 1;
1974 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1976 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
1977 dt->address = vmcs_readl(GUEST_IDTR_BASE);
1980 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1982 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
1983 vmcs_writel(GUEST_IDTR_BASE, dt->address);
1986 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1988 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
1989 dt->address = vmcs_readl(GUEST_GDTR_BASE);
1992 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1994 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
1995 vmcs_writel(GUEST_GDTR_BASE, dt->address);
1998 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2000 struct kvm_segment var;
2003 vmx_get_segment(vcpu, &var, seg);
2004 ar = vmx_segment_access_rights(&var);
2006 if (var.base != (var.selector << 4))
2008 if (var.limit != 0xffff)
2016 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2018 struct kvm_segment cs;
2019 unsigned int cs_rpl;
2021 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2022 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2026 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2030 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2031 if (cs.dpl > cs_rpl)
2034 if (cs.dpl != cs_rpl)
2040 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2044 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2046 struct kvm_segment ss;
2047 unsigned int ss_rpl;
2049 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2050 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2054 if (ss.type != 3 && ss.type != 7)
2058 if (ss.dpl != ss_rpl) /* DPL != RPL */
2066 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2068 struct kvm_segment var;
2071 vmx_get_segment(vcpu, &var, seg);
2072 rpl = var.selector & SELECTOR_RPL_MASK;
2080 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2081 if (var.dpl < rpl) /* DPL < RPL */
2085 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2091 static bool tr_valid(struct kvm_vcpu *vcpu)
2093 struct kvm_segment tr;
2095 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2099 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2101 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2109 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2111 struct kvm_segment ldtr;
2113 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2117 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2127 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2129 struct kvm_segment cs, ss;
2131 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2132 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2134 return ((cs.selector & SELECTOR_RPL_MASK) ==
2135 (ss.selector & SELECTOR_RPL_MASK));
2139 * Check if guest state is valid. Returns true if valid, false if
2141 * We assume that registers are always usable
2143 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2145 /* real mode guest state checks */
2146 if (!is_protmode(vcpu)) {
2147 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2149 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2151 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2153 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2155 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2157 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2160 /* protected mode guest state checks */
2161 if (!cs_ss_rpl_check(vcpu))
2163 if (!code_segment_valid(vcpu))
2165 if (!stack_segment_valid(vcpu))
2167 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2169 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2171 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2173 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2175 if (!tr_valid(vcpu))
2177 if (!ldtr_valid(vcpu))
2181 * - Add checks on RIP
2182 * - Add checks on RFLAGS
2188 static int init_rmode_tss(struct kvm *kvm)
2190 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2195 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2198 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2199 r = kvm_write_guest_page(kvm, fn++, &data,
2200 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2203 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2206 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2210 r = kvm_write_guest_page(kvm, fn, &data,
2211 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2221 static int init_rmode_identity_map(struct kvm *kvm)
2224 pfn_t identity_map_pfn;
2229 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2230 printk(KERN_ERR "EPT: identity-mapping pagetable "
2231 "haven't been allocated!\n");
2234 if (likely(kvm->arch.ept_identity_pagetable_done))
2237 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2238 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2241 /* Set up identity-mapping pagetable for EPT in real mode */
2242 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2243 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2244 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2245 r = kvm_write_guest_page(kvm, identity_map_pfn,
2246 &tmp, i * sizeof(tmp), sizeof(tmp));
2250 kvm->arch.ept_identity_pagetable_done = true;
2256 static void seg_setup(int seg)
2258 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2261 vmcs_write16(sf->selector, 0);
2262 vmcs_writel(sf->base, 0);
2263 vmcs_write32(sf->limit, 0xffff);
2264 if (enable_unrestricted_guest) {
2266 if (seg == VCPU_SREG_CS)
2267 ar |= 0x08; /* code segment */
2271 vmcs_write32(sf->ar_bytes, ar);
2274 static int alloc_apic_access_page(struct kvm *kvm)
2276 struct kvm_userspace_memory_region kvm_userspace_mem;
2279 mutex_lock(&kvm->slots_lock);
2280 if (kvm->arch.apic_access_page)
2282 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2283 kvm_userspace_mem.flags = 0;
2284 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2285 kvm_userspace_mem.memory_size = PAGE_SIZE;
2286 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2290 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2292 mutex_unlock(&kvm->slots_lock);
2296 static int alloc_identity_pagetable(struct kvm *kvm)
2298 struct kvm_userspace_memory_region kvm_userspace_mem;
2301 mutex_lock(&kvm->slots_lock);
2302 if (kvm->arch.ept_identity_pagetable)
2304 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2305 kvm_userspace_mem.flags = 0;
2306 kvm_userspace_mem.guest_phys_addr =
2307 kvm->arch.ept_identity_map_addr;
2308 kvm_userspace_mem.memory_size = PAGE_SIZE;
2309 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2313 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2314 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2316 mutex_unlock(&kvm->slots_lock);
2320 static void allocate_vpid(struct vcpu_vmx *vmx)
2327 spin_lock(&vmx_vpid_lock);
2328 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2329 if (vpid < VMX_NR_VPIDS) {
2331 __set_bit(vpid, vmx_vpid_bitmap);
2333 spin_unlock(&vmx_vpid_lock);
2336 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2338 int f = sizeof(unsigned long);
2340 if (!cpu_has_vmx_msr_bitmap())
2344 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2345 * have the write-low and read-high bitmap offsets the wrong way round.
2346 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2348 if (msr <= 0x1fff) {
2349 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2350 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2351 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2353 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2354 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2358 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2361 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2362 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2366 * Sets up the vmcs for emulated real mode.
2368 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2370 u32 host_sysenter_cs, msr_low, msr_high;
2372 u64 host_pat, tsc_this, tsc_base;
2376 unsigned long kvm_vmx_return;
2380 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2381 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2383 if (cpu_has_vmx_msr_bitmap())
2384 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2386 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2389 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2390 vmcs_config.pin_based_exec_ctrl);
2392 exec_control = vmcs_config.cpu_based_exec_ctrl;
2393 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2394 exec_control &= ~CPU_BASED_TPR_SHADOW;
2395 #ifdef CONFIG_X86_64
2396 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2397 CPU_BASED_CR8_LOAD_EXITING;
2401 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2402 CPU_BASED_CR3_LOAD_EXITING |
2403 CPU_BASED_INVLPG_EXITING;
2404 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2406 if (cpu_has_secondary_exec_ctrls()) {
2407 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2408 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2410 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2412 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2414 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2415 enable_unrestricted_guest = 0;
2417 if (!enable_unrestricted_guest)
2418 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2420 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2421 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2425 vmcs_write32(PLE_GAP, ple_gap);
2426 vmcs_write32(PLE_WINDOW, ple_window);
2429 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2430 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2431 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2433 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2434 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2435 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2437 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2438 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2439 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2440 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2441 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2442 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2443 #ifdef CONFIG_X86_64
2444 rdmsrl(MSR_FS_BASE, a);
2445 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2446 rdmsrl(MSR_GS_BASE, a);
2447 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2449 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2450 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2453 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2455 native_store_idt(&dt);
2456 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2458 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2459 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2460 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2461 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2462 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2464 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2465 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2466 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2467 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2468 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2469 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2471 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2472 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2473 host_pat = msr_low | ((u64) msr_high << 32);
2474 vmcs_write64(HOST_IA32_PAT, host_pat);
2476 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2477 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2478 host_pat = msr_low | ((u64) msr_high << 32);
2479 /* Write the default value follow host pat */
2480 vmcs_write64(GUEST_IA32_PAT, host_pat);
2481 /* Keep arch.pat sync with GUEST_IA32_PAT */
2482 vmx->vcpu.arch.pat = host_pat;
2485 for (i = 0; i < NR_VMX_MSR; ++i) {
2486 u32 index = vmx_msr_index[i];
2487 u32 data_low, data_high;
2490 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2492 if (wrmsr_safe(index, data_low, data_high) < 0)
2494 vmx->guest_msrs[j].index = i;
2495 vmx->guest_msrs[j].data = 0;
2496 vmx->guest_msrs[j].mask = -1ull;
2500 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2502 /* 22.2.1, 20.8.1 */
2503 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2505 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2506 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2508 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2509 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2511 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2513 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2514 tsc_base = tsc_this;
2516 guest_write_tsc(0, tsc_base);
2521 static int init_rmode(struct kvm *kvm)
2523 if (!init_rmode_tss(kvm))
2525 if (!init_rmode_identity_map(kvm))
2530 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2532 struct vcpu_vmx *vmx = to_vmx(vcpu);
2536 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2537 idx = srcu_read_lock(&vcpu->kvm->srcu);
2538 if (!init_rmode(vmx->vcpu.kvm)) {
2543 vmx->rmode.vm86_active = 0;
2545 vmx->soft_vnmi_blocked = 0;
2547 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2548 kvm_set_cr8(&vmx->vcpu, 0);
2549 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2550 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2551 msr |= MSR_IA32_APICBASE_BSP;
2552 kvm_set_apic_base(&vmx->vcpu, msr);
2554 fx_init(&vmx->vcpu);
2556 seg_setup(VCPU_SREG_CS);
2558 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2559 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2561 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2562 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2563 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2565 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2566 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2569 seg_setup(VCPU_SREG_DS);
2570 seg_setup(VCPU_SREG_ES);
2571 seg_setup(VCPU_SREG_FS);
2572 seg_setup(VCPU_SREG_GS);
2573 seg_setup(VCPU_SREG_SS);
2575 vmcs_write16(GUEST_TR_SELECTOR, 0);
2576 vmcs_writel(GUEST_TR_BASE, 0);
2577 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2578 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2580 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2581 vmcs_writel(GUEST_LDTR_BASE, 0);
2582 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2583 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2585 vmcs_write32(GUEST_SYSENTER_CS, 0);
2586 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2587 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2589 vmcs_writel(GUEST_RFLAGS, 0x02);
2590 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2591 kvm_rip_write(vcpu, 0xfff0);
2593 kvm_rip_write(vcpu, 0);
2594 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2596 vmcs_writel(GUEST_DR7, 0x400);
2598 vmcs_writel(GUEST_GDTR_BASE, 0);
2599 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2601 vmcs_writel(GUEST_IDTR_BASE, 0);
2602 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2604 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2605 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2606 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2608 /* Special registers */
2609 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2613 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2615 if (cpu_has_vmx_tpr_shadow()) {
2616 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2617 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2618 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2619 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2620 vmcs_write32(TPR_THRESHOLD, 0);
2623 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2624 vmcs_write64(APIC_ACCESS_ADDR,
2625 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2628 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2630 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2631 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2632 vmx_set_cr4(&vmx->vcpu, 0);
2633 vmx_set_efer(&vmx->vcpu, 0);
2634 vmx_fpu_activate(&vmx->vcpu);
2635 update_exception_bitmap(&vmx->vcpu);
2637 vpid_sync_vcpu_all(vmx);
2641 /* HACK: Don't enable emulation on guest boot/reset */
2642 vmx->emulation_required = 0;
2645 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2649 static void enable_irq_window(struct kvm_vcpu *vcpu)
2651 u32 cpu_based_vm_exec_control;
2653 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2654 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2655 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2658 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2660 u32 cpu_based_vm_exec_control;
2662 if (!cpu_has_virtual_nmis()) {
2663 enable_irq_window(vcpu);
2667 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2668 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2669 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2672 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2674 struct vcpu_vmx *vmx = to_vmx(vcpu);
2676 int irq = vcpu->arch.interrupt.nr;
2678 trace_kvm_inj_virq(irq);
2680 ++vcpu->stat.irq_injections;
2681 if (vmx->rmode.vm86_active) {
2682 vmx->rmode.irq.pending = true;
2683 vmx->rmode.irq.vector = irq;
2684 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2685 if (vcpu->arch.interrupt.soft)
2686 vmx->rmode.irq.rip +=
2687 vmx->vcpu.arch.event_exit_inst_len;
2688 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2689 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2690 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2691 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2694 intr = irq | INTR_INFO_VALID_MASK;
2695 if (vcpu->arch.interrupt.soft) {
2696 intr |= INTR_TYPE_SOFT_INTR;
2697 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2698 vmx->vcpu.arch.event_exit_inst_len);
2700 intr |= INTR_TYPE_EXT_INTR;
2701 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2704 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2706 struct vcpu_vmx *vmx = to_vmx(vcpu);
2708 if (!cpu_has_virtual_nmis()) {
2710 * Tracking the NMI-blocked state in software is built upon
2711 * finding the next open IRQ window. This, in turn, depends on
2712 * well-behaving guests: They have to keep IRQs disabled at
2713 * least as long as the NMI handler runs. Otherwise we may
2714 * cause NMI nesting, maybe breaking the guest. But as this is
2715 * highly unlikely, we can live with the residual risk.
2717 vmx->soft_vnmi_blocked = 1;
2718 vmx->vnmi_blocked_time = 0;
2721 ++vcpu->stat.nmi_injections;
2722 if (vmx->rmode.vm86_active) {
2723 vmx->rmode.irq.pending = true;
2724 vmx->rmode.irq.vector = NMI_VECTOR;
2725 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2726 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2727 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2728 INTR_INFO_VALID_MASK);
2729 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2730 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2733 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2734 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2737 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2739 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2742 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2743 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2744 GUEST_INTR_STATE_NMI));
2747 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2749 if (!cpu_has_virtual_nmis())
2750 return to_vmx(vcpu)->soft_vnmi_blocked;
2752 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2753 GUEST_INTR_STATE_NMI);
2756 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2758 struct vcpu_vmx *vmx = to_vmx(vcpu);
2760 if (!cpu_has_virtual_nmis()) {
2761 if (vmx->soft_vnmi_blocked != masked) {
2762 vmx->soft_vnmi_blocked = masked;
2763 vmx->vnmi_blocked_time = 0;
2767 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2768 GUEST_INTR_STATE_NMI);
2770 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2771 GUEST_INTR_STATE_NMI);
2775 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2777 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2778 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2779 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2782 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2785 struct kvm_userspace_memory_region tss_mem = {
2786 .slot = TSS_PRIVATE_MEMSLOT,
2787 .guest_phys_addr = addr,
2788 .memory_size = PAGE_SIZE * 3,
2792 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2795 kvm->arch.tss_addr = addr;
2799 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2800 int vec, u32 err_code)
2803 * Instruction with address size override prefix opcode 0x67
2804 * Cause the #SS fault with 0 error code in VM86 mode.
2806 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2807 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2810 * Forward all other exceptions that are valid in real mode.
2811 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2812 * the required debugging infrastructure rework.
2816 if (vcpu->guest_debug &
2817 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2819 kvm_queue_exception(vcpu, vec);
2823 * Update instruction length as we may reinject the exception
2824 * from user space while in guest debugging mode.
2826 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2827 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2828 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2839 kvm_queue_exception(vcpu, vec);
2846 * Trigger machine check on the host. We assume all the MSRs are already set up
2847 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2848 * We pass a fake environment to the machine check handler because we want
2849 * the guest to be always treated like user space, no matter what context
2850 * it used internally.
2852 static void kvm_machine_check(void)
2854 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2855 struct pt_regs regs = {
2856 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2857 .flags = X86_EFLAGS_IF,
2860 do_machine_check(®s, 0);
2864 static int handle_machine_check(struct kvm_vcpu *vcpu)
2866 /* already handled by vcpu_run */
2870 static int handle_exception(struct kvm_vcpu *vcpu)
2872 struct vcpu_vmx *vmx = to_vmx(vcpu);
2873 struct kvm_run *kvm_run = vcpu->run;
2874 u32 intr_info, ex_no, error_code;
2875 unsigned long cr2, rip, dr6;
2877 enum emulation_result er;
2879 vect_info = vmx->idt_vectoring_info;
2880 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2882 if (is_machine_check(intr_info))
2883 return handle_machine_check(vcpu);
2885 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2886 !is_page_fault(intr_info)) {
2887 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2888 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2889 vcpu->run->internal.ndata = 2;
2890 vcpu->run->internal.data[0] = vect_info;
2891 vcpu->run->internal.data[1] = intr_info;
2895 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2896 return 1; /* already handled by vmx_vcpu_run() */
2898 if (is_no_device(intr_info)) {
2899 vmx_fpu_activate(vcpu);
2903 if (is_invalid_opcode(intr_info)) {
2904 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2905 if (er != EMULATE_DONE)
2906 kvm_queue_exception(vcpu, UD_VECTOR);
2911 rip = kvm_rip_read(vcpu);
2912 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2913 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2914 if (is_page_fault(intr_info)) {
2915 /* EPT won't cause page fault directly */
2918 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2919 trace_kvm_page_fault(cr2, error_code);
2921 if (kvm_event_needs_reinjection(vcpu))
2922 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2923 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2926 if (vmx->rmode.vm86_active &&
2927 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2929 if (vcpu->arch.halt_request) {
2930 vcpu->arch.halt_request = 0;
2931 return kvm_emulate_halt(vcpu);
2936 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2939 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2940 if (!(vcpu->guest_debug &
2941 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2942 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2943 kvm_queue_exception(vcpu, DB_VECTOR);
2946 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2947 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2951 * Update instruction length as we may reinject #BP from
2952 * user space while in guest debugging mode. Reading it for
2953 * #DB as well causes no harm, it is not used in that case.
2955 vmx->vcpu.arch.event_exit_inst_len =
2956 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2957 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2958 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2959 kvm_run->debug.arch.exception = ex_no;
2962 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2963 kvm_run->ex.exception = ex_no;
2964 kvm_run->ex.error_code = error_code;
2970 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2972 ++vcpu->stat.irq_exits;
2976 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2978 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2982 static int handle_io(struct kvm_vcpu *vcpu)
2984 unsigned long exit_qualification;
2985 int size, in, string;
2988 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2989 string = (exit_qualification & 16) != 0;
2990 in = (exit_qualification & 8) != 0;
2992 ++vcpu->stat.io_exits;
2995 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
2997 port = exit_qualification >> 16;
2998 size = (exit_qualification & 7) + 1;
2999 skip_emulated_instruction(vcpu);
3001 return kvm_fast_pio_out(vcpu, size, port);
3005 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3008 * Patch in the VMCALL instruction:
3010 hypercall[0] = 0x0f;
3011 hypercall[1] = 0x01;
3012 hypercall[2] = 0xc1;
3015 static int handle_cr(struct kvm_vcpu *vcpu)
3017 unsigned long exit_qualification, val;
3021 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3022 cr = exit_qualification & 15;
3023 reg = (exit_qualification >> 8) & 15;
3024 switch ((exit_qualification >> 4) & 3) {
3025 case 0: /* mov to cr */
3026 val = kvm_register_read(vcpu, reg);
3027 trace_kvm_cr_write(cr, val);
3030 kvm_set_cr0(vcpu, val);
3031 skip_emulated_instruction(vcpu);
3034 kvm_set_cr3(vcpu, val);
3035 skip_emulated_instruction(vcpu);
3038 kvm_set_cr4(vcpu, val);
3039 skip_emulated_instruction(vcpu);
3042 u8 cr8_prev = kvm_get_cr8(vcpu);
3043 u8 cr8 = kvm_register_read(vcpu, reg);
3044 kvm_set_cr8(vcpu, cr8);
3045 skip_emulated_instruction(vcpu);
3046 if (irqchip_in_kernel(vcpu->kvm))
3048 if (cr8_prev <= cr8)
3050 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3056 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3057 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3058 skip_emulated_instruction(vcpu);
3059 vmx_fpu_activate(vcpu);
3061 case 1: /*mov from cr*/
3064 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3065 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3066 skip_emulated_instruction(vcpu);
3069 val = kvm_get_cr8(vcpu);
3070 kvm_register_write(vcpu, reg, val);
3071 trace_kvm_cr_read(cr, val);
3072 skip_emulated_instruction(vcpu);
3077 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3078 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3079 kvm_lmsw(vcpu, val);
3081 skip_emulated_instruction(vcpu);
3086 vcpu->run->exit_reason = 0;
3087 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3088 (int)(exit_qualification >> 4) & 3, cr);
3092 static int handle_dr(struct kvm_vcpu *vcpu)
3094 unsigned long exit_qualification;
3097 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3098 if (!kvm_require_cpl(vcpu, 0))
3100 dr = vmcs_readl(GUEST_DR7);
3103 * As the vm-exit takes precedence over the debug trap, we
3104 * need to emulate the latter, either for the host or the
3105 * guest debugging itself.
3107 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3108 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3109 vcpu->run->debug.arch.dr7 = dr;
3110 vcpu->run->debug.arch.pc =
3111 vmcs_readl(GUEST_CS_BASE) +
3112 vmcs_readl(GUEST_RIP);
3113 vcpu->run->debug.arch.exception = DB_VECTOR;
3114 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3117 vcpu->arch.dr7 &= ~DR7_GD;
3118 vcpu->arch.dr6 |= DR6_BD;
3119 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3120 kvm_queue_exception(vcpu, DB_VECTOR);
3125 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3126 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3127 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3128 if (exit_qualification & TYPE_MOV_FROM_DR) {
3130 if (!kvm_get_dr(vcpu, dr, &val))
3131 kvm_register_write(vcpu, reg, val);
3133 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3134 skip_emulated_instruction(vcpu);
3138 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3140 vmcs_writel(GUEST_DR7, val);
3143 static int handle_cpuid(struct kvm_vcpu *vcpu)
3145 kvm_emulate_cpuid(vcpu);
3149 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3151 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3154 if (vmx_get_msr(vcpu, ecx, &data)) {
3155 trace_kvm_msr_read_ex(ecx);
3156 kvm_inject_gp(vcpu, 0);
3160 trace_kvm_msr_read(ecx, data);
3162 /* FIXME: handling of bits 32:63 of rax, rdx */
3163 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3164 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3165 skip_emulated_instruction(vcpu);
3169 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3171 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3172 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3173 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3175 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3176 trace_kvm_msr_write_ex(ecx, data);
3177 kvm_inject_gp(vcpu, 0);
3181 trace_kvm_msr_write(ecx, data);
3182 skip_emulated_instruction(vcpu);
3186 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3191 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3193 u32 cpu_based_vm_exec_control;
3195 /* clear pending irq */
3196 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3197 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3198 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3200 ++vcpu->stat.irq_window_exits;
3203 * If the user space waits to inject interrupts, exit as soon as
3206 if (!irqchip_in_kernel(vcpu->kvm) &&
3207 vcpu->run->request_interrupt_window &&
3208 !kvm_cpu_has_interrupt(vcpu)) {
3209 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3215 static int handle_halt(struct kvm_vcpu *vcpu)
3217 skip_emulated_instruction(vcpu);
3218 return kvm_emulate_halt(vcpu);
3221 static int handle_vmcall(struct kvm_vcpu *vcpu)
3223 skip_emulated_instruction(vcpu);
3224 kvm_emulate_hypercall(vcpu);
3228 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3230 kvm_queue_exception(vcpu, UD_VECTOR);
3234 static int handle_invlpg(struct kvm_vcpu *vcpu)
3236 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3238 kvm_mmu_invlpg(vcpu, exit_qualification);
3239 skip_emulated_instruction(vcpu);
3243 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3245 skip_emulated_instruction(vcpu);
3246 /* TODO: Add support for VT-d/pass-through device */
3250 static int handle_apic_access(struct kvm_vcpu *vcpu)
3252 unsigned long exit_qualification;
3253 enum emulation_result er;
3254 unsigned long offset;
3256 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3257 offset = exit_qualification & 0xffful;
3259 er = emulate_instruction(vcpu, 0, 0, 0);
3261 if (er != EMULATE_DONE) {
3263 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3270 static int handle_task_switch(struct kvm_vcpu *vcpu)
3272 struct vcpu_vmx *vmx = to_vmx(vcpu);
3273 unsigned long exit_qualification;
3274 bool has_error_code = false;
3277 int reason, type, idt_v;
3279 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3280 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3282 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3284 reason = (u32)exit_qualification >> 30;
3285 if (reason == TASK_SWITCH_GATE && idt_v) {
3287 case INTR_TYPE_NMI_INTR:
3288 vcpu->arch.nmi_injected = false;
3289 if (cpu_has_virtual_nmis())
3290 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3291 GUEST_INTR_STATE_NMI);
3293 case INTR_TYPE_EXT_INTR:
3294 case INTR_TYPE_SOFT_INTR:
3295 kvm_clear_interrupt_queue(vcpu);
3297 case INTR_TYPE_HARD_EXCEPTION:
3298 if (vmx->idt_vectoring_info &
3299 VECTORING_INFO_DELIVER_CODE_MASK) {
3300 has_error_code = true;
3302 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3305 case INTR_TYPE_SOFT_EXCEPTION:
3306 kvm_clear_exception_queue(vcpu);
3312 tss_selector = exit_qualification;
3314 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3315 type != INTR_TYPE_EXT_INTR &&
3316 type != INTR_TYPE_NMI_INTR))
3317 skip_emulated_instruction(vcpu);
3319 if (kvm_task_switch(vcpu, tss_selector, reason,
3320 has_error_code, error_code) == EMULATE_FAIL) {
3321 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3322 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3323 vcpu->run->internal.ndata = 0;
3327 /* clear all local breakpoint enable flags */
3328 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3331 * TODO: What about debug traps on tss switch?
3332 * Are we supposed to inject them and update dr6?
3338 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3340 unsigned long exit_qualification;
3344 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3346 if (exit_qualification & (1 << 6)) {
3347 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3351 gla_validity = (exit_qualification >> 7) & 0x3;
3352 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3353 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3354 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3355 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3356 vmcs_readl(GUEST_LINEAR_ADDRESS));
3357 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3358 (long unsigned int)exit_qualification);
3359 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3360 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3364 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3365 trace_kvm_page_fault(gpa, exit_qualification);
3366 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3369 static u64 ept_rsvd_mask(u64 spte, int level)
3374 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3375 mask |= (1ULL << i);
3378 /* bits 7:3 reserved */
3380 else if (level == 2) {
3381 if (spte & (1ULL << 7))
3382 /* 2MB ref, bits 20:12 reserved */
3385 /* bits 6:3 reserved */
3392 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3395 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3397 /* 010b (write-only) */
3398 WARN_ON((spte & 0x7) == 0x2);
3400 /* 110b (write/execute) */
3401 WARN_ON((spte & 0x7) == 0x6);
3403 /* 100b (execute-only) and value not supported by logical processor */
3404 if (!cpu_has_vmx_ept_execute_only())
3405 WARN_ON((spte & 0x7) == 0x4);
3409 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3411 if (rsvd_bits != 0) {
3412 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3413 __func__, rsvd_bits);
3417 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3418 u64 ept_mem_type = (spte & 0x38) >> 3;
3420 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3421 ept_mem_type == 7) {
3422 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3423 __func__, ept_mem_type);
3430 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3436 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3438 printk(KERN_ERR "EPT: Misconfiguration.\n");
3439 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3441 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3443 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3444 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3446 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3447 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3452 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3454 u32 cpu_based_vm_exec_control;
3456 /* clear pending NMI */
3457 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3458 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3459 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3460 ++vcpu->stat.nmi_window_exits;
3465 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3467 struct vcpu_vmx *vmx = to_vmx(vcpu);
3468 enum emulation_result err = EMULATE_DONE;
3471 while (!guest_state_valid(vcpu)) {
3472 err = emulate_instruction(vcpu, 0, 0, 0);
3474 if (err == EMULATE_DO_MMIO) {
3479 if (err != EMULATE_DONE) {
3480 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3481 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3482 vcpu->run->internal.ndata = 0;
3487 if (signal_pending(current))
3493 vmx->emulation_required = 0;
3499 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3500 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3502 static int handle_pause(struct kvm_vcpu *vcpu)
3504 skip_emulated_instruction(vcpu);
3505 kvm_vcpu_on_spin(vcpu);
3510 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3512 kvm_queue_exception(vcpu, UD_VECTOR);
3517 * The exit handlers return 1 if the exit was handled fully and guest execution
3518 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3519 * to be done to userspace and return 0.
3521 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3522 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3523 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3524 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3525 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3526 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3527 [EXIT_REASON_CR_ACCESS] = handle_cr,
3528 [EXIT_REASON_DR_ACCESS] = handle_dr,
3529 [EXIT_REASON_CPUID] = handle_cpuid,
3530 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3531 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3532 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3533 [EXIT_REASON_HLT] = handle_halt,
3534 [EXIT_REASON_INVLPG] = handle_invlpg,
3535 [EXIT_REASON_VMCALL] = handle_vmcall,
3536 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3537 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3538 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3539 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3540 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3541 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3542 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3543 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3544 [EXIT_REASON_VMON] = handle_vmx_insn,
3545 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3546 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3547 [EXIT_REASON_WBINVD] = handle_wbinvd,
3548 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3549 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3550 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3551 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3552 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3553 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3554 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3557 static const int kvm_vmx_max_exit_handlers =
3558 ARRAY_SIZE(kvm_vmx_exit_handlers);
3561 * The guest has exited. See if we can fix it or if we need userspace
3564 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3566 struct vcpu_vmx *vmx = to_vmx(vcpu);
3567 u32 exit_reason = vmx->exit_reason;
3568 u32 vectoring_info = vmx->idt_vectoring_info;
3570 trace_kvm_exit(exit_reason, vcpu);
3572 /* If guest state is invalid, start emulating */
3573 if (vmx->emulation_required && emulate_invalid_guest_state)
3574 return handle_invalid_guest_state(vcpu);
3576 /* Access CR3 don't cause VMExit in paging mode, so we need
3577 * to sync with guest real CR3. */
3578 if (enable_ept && is_paging(vcpu))
3579 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3581 if (unlikely(vmx->fail)) {
3582 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3583 vcpu->run->fail_entry.hardware_entry_failure_reason
3584 = vmcs_read32(VM_INSTRUCTION_ERROR);
3588 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3589 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3590 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3591 exit_reason != EXIT_REASON_TASK_SWITCH))
3592 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3593 "(0x%x) and exit reason is 0x%x\n",
3594 __func__, vectoring_info, exit_reason);
3596 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3597 if (vmx_interrupt_allowed(vcpu)) {
3598 vmx->soft_vnmi_blocked = 0;
3599 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3600 vcpu->arch.nmi_pending) {
3602 * This CPU don't support us in finding the end of an
3603 * NMI-blocked window if the guest runs with IRQs
3604 * disabled. So we pull the trigger after 1 s of
3605 * futile waiting, but inform the user about this.
3607 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3608 "state on VCPU %d after 1 s timeout\n",
3609 __func__, vcpu->vcpu_id);
3610 vmx->soft_vnmi_blocked = 0;
3614 if (exit_reason < kvm_vmx_max_exit_handlers
3615 && kvm_vmx_exit_handlers[exit_reason])
3616 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3618 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3619 vcpu->run->hw.hardware_exit_reason = exit_reason;
3624 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3626 if (irr == -1 || tpr < irr) {
3627 vmcs_write32(TPR_THRESHOLD, 0);
3631 vmcs_write32(TPR_THRESHOLD, irr);
3634 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3637 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3641 bool idtv_info_valid;
3643 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3645 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3647 /* Handle machine checks before interrupts are enabled */
3648 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3649 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3650 && is_machine_check(exit_intr_info)))
3651 kvm_machine_check();
3653 /* We need to handle NMIs before interrupts are enabled */
3654 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3655 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3656 kvm_before_handle_nmi(&vmx->vcpu);
3658 kvm_after_handle_nmi(&vmx->vcpu);
3661 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3663 if (cpu_has_virtual_nmis()) {
3664 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3665 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3667 * SDM 3: 27.7.1.2 (September 2008)
3668 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3669 * a guest IRET fault.
3670 * SDM 3: 23.2.2 (September 2008)
3671 * Bit 12 is undefined in any of the following cases:
3672 * If the VM exit sets the valid bit in the IDT-vectoring
3673 * information field.
3674 * If the VM exit is due to a double fault.
3676 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3677 vector != DF_VECTOR && !idtv_info_valid)
3678 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3679 GUEST_INTR_STATE_NMI);
3680 } else if (unlikely(vmx->soft_vnmi_blocked))
3681 vmx->vnmi_blocked_time +=
3682 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3684 vmx->vcpu.arch.nmi_injected = false;
3685 kvm_clear_exception_queue(&vmx->vcpu);
3686 kvm_clear_interrupt_queue(&vmx->vcpu);
3688 if (!idtv_info_valid)
3691 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3692 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3695 case INTR_TYPE_NMI_INTR:
3696 vmx->vcpu.arch.nmi_injected = true;
3698 * SDM 3: 27.7.1.2 (September 2008)
3699 * Clear bit "block by NMI" before VM entry if a NMI
3702 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3703 GUEST_INTR_STATE_NMI);
3705 case INTR_TYPE_SOFT_EXCEPTION:
3706 vmx->vcpu.arch.event_exit_inst_len =
3707 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3709 case INTR_TYPE_HARD_EXCEPTION:
3710 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3711 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3712 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3714 kvm_queue_exception(&vmx->vcpu, vector);
3716 case INTR_TYPE_SOFT_INTR:
3717 vmx->vcpu.arch.event_exit_inst_len =
3718 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3720 case INTR_TYPE_EXT_INTR:
3721 kvm_queue_interrupt(&vmx->vcpu, vector,
3722 type == INTR_TYPE_SOFT_INTR);
3730 * Failure to inject an interrupt should give us the information
3731 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3732 * when fetching the interrupt redirection bitmap in the real-mode
3733 * tss, this doesn't happen. So we do it ourselves.
3735 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3737 vmx->rmode.irq.pending = 0;
3738 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3740 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3741 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3742 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3743 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3746 vmx->idt_vectoring_info =
3747 VECTORING_INFO_VALID_MASK
3748 | INTR_TYPE_EXT_INTR
3749 | vmx->rmode.irq.vector;
3752 #ifdef CONFIG_X86_64
3760 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3762 struct vcpu_vmx *vmx = to_vmx(vcpu);
3764 /* Record the guest's net vcpu time for enforced NMI injections. */
3765 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3766 vmx->entry_time = ktime_get();
3768 /* Don't enter VMX if guest state is invalid, let the exit handler
3769 start emulation until we arrive back to a valid state */
3770 if (vmx->emulation_required && emulate_invalid_guest_state)
3773 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3774 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3775 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3776 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3778 /* When single-stepping over STI and MOV SS, we must clear the
3779 * corresponding interruptibility bits in the guest state. Otherwise
3780 * vmentry fails as it then expects bit 14 (BS) in pending debug
3781 * exceptions being set, but that's not correct for the guest debugging
3783 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3784 vmx_set_interrupt_shadow(vcpu, 0);
3787 * Loading guest fpu may have cleared host cr0.ts
3789 vmcs_writel(HOST_CR0, read_cr0());
3792 /* Store host registers */
3793 "push %%"R"dx; push %%"R"bp;"
3795 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3797 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3798 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3800 /* Reload cr2 if changed */
3801 "mov %c[cr2](%0), %%"R"ax \n\t"
3802 "mov %%cr2, %%"R"dx \n\t"
3803 "cmp %%"R"ax, %%"R"dx \n\t"
3805 "mov %%"R"ax, %%cr2 \n\t"
3807 /* Check if vmlaunch of vmresume is needed */
3808 "cmpl $0, %c[launched](%0) \n\t"
3809 /* Load guest registers. Don't clobber flags. */
3810 "mov %c[rax](%0), %%"R"ax \n\t"
3811 "mov %c[rbx](%0), %%"R"bx \n\t"
3812 "mov %c[rdx](%0), %%"R"dx \n\t"
3813 "mov %c[rsi](%0), %%"R"si \n\t"
3814 "mov %c[rdi](%0), %%"R"di \n\t"
3815 "mov %c[rbp](%0), %%"R"bp \n\t"
3816 #ifdef CONFIG_X86_64
3817 "mov %c[r8](%0), %%r8 \n\t"
3818 "mov %c[r9](%0), %%r9 \n\t"
3819 "mov %c[r10](%0), %%r10 \n\t"
3820 "mov %c[r11](%0), %%r11 \n\t"
3821 "mov %c[r12](%0), %%r12 \n\t"
3822 "mov %c[r13](%0), %%r13 \n\t"
3823 "mov %c[r14](%0), %%r14 \n\t"
3824 "mov %c[r15](%0), %%r15 \n\t"
3826 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3828 /* Enter guest mode */
3829 "jne .Llaunched \n\t"
3830 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3831 "jmp .Lkvm_vmx_return \n\t"
3832 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3833 ".Lkvm_vmx_return: "
3834 /* Save guest registers, load host registers, keep flags */
3835 "xchg %0, (%%"R"sp) \n\t"
3836 "mov %%"R"ax, %c[rax](%0) \n\t"
3837 "mov %%"R"bx, %c[rbx](%0) \n\t"
3838 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3839 "mov %%"R"dx, %c[rdx](%0) \n\t"
3840 "mov %%"R"si, %c[rsi](%0) \n\t"
3841 "mov %%"R"di, %c[rdi](%0) \n\t"
3842 "mov %%"R"bp, %c[rbp](%0) \n\t"
3843 #ifdef CONFIG_X86_64
3844 "mov %%r8, %c[r8](%0) \n\t"
3845 "mov %%r9, %c[r9](%0) \n\t"
3846 "mov %%r10, %c[r10](%0) \n\t"
3847 "mov %%r11, %c[r11](%0) \n\t"
3848 "mov %%r12, %c[r12](%0) \n\t"
3849 "mov %%r13, %c[r13](%0) \n\t"
3850 "mov %%r14, %c[r14](%0) \n\t"
3851 "mov %%r15, %c[r15](%0) \n\t"
3853 "mov %%cr2, %%"R"ax \n\t"
3854 "mov %%"R"ax, %c[cr2](%0) \n\t"
3856 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3857 "setbe %c[fail](%0) \n\t"
3858 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3859 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3860 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3861 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3862 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3863 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3864 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3865 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3866 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3867 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3868 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3869 #ifdef CONFIG_X86_64
3870 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3871 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3872 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3873 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3874 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3875 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3876 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3877 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3879 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3881 , R"bx", R"di", R"si"
3882 #ifdef CONFIG_X86_64
3883 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3887 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3888 | (1 << VCPU_EXREG_PDPTR));
3889 vcpu->arch.regs_dirty = 0;
3891 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3892 if (vmx->rmode.irq.pending)
3893 fixup_rmode_irq(vmx);
3895 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3898 vmx_complete_interrupts(vmx);
3904 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3906 struct vcpu_vmx *vmx = to_vmx(vcpu);
3910 free_vmcs(vmx->vmcs);
3915 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3917 struct vcpu_vmx *vmx = to_vmx(vcpu);
3919 spin_lock(&vmx_vpid_lock);
3921 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3922 spin_unlock(&vmx_vpid_lock);
3923 vmx_free_vmcs(vcpu);
3924 kfree(vmx->guest_msrs);
3925 kvm_vcpu_uninit(vcpu);
3926 kmem_cache_free(kvm_vcpu_cache, vmx);
3929 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3932 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3936 return ERR_PTR(-ENOMEM);
3940 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3944 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3945 if (!vmx->guest_msrs) {
3950 vmx->vmcs = alloc_vmcs();
3954 vmcs_clear(vmx->vmcs);
3957 vmx_vcpu_load(&vmx->vcpu, cpu);
3958 err = vmx_vcpu_setup(vmx);
3959 vmx_vcpu_put(&vmx->vcpu);
3963 if (vm_need_virtualize_apic_accesses(kvm))
3964 if (alloc_apic_access_page(kvm) != 0)
3968 if (!kvm->arch.ept_identity_map_addr)
3969 kvm->arch.ept_identity_map_addr =
3970 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3971 if (alloc_identity_pagetable(kvm) != 0)
3978 free_vmcs(vmx->vmcs);
3980 kfree(vmx->guest_msrs);
3982 kvm_vcpu_uninit(&vmx->vcpu);
3984 kmem_cache_free(kvm_vcpu_cache, vmx);
3985 return ERR_PTR(err);
3988 static void __init vmx_check_processor_compat(void *rtn)
3990 struct vmcs_config vmcs_conf;
3993 if (setup_vmcs_config(&vmcs_conf) < 0)
3995 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3996 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3997 smp_processor_id());
4002 static int get_ept_level(void)
4004 return VMX_EPT_DEFAULT_GAW + 1;
4007 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4011 /* For VT-d and EPT combination
4012 * 1. MMIO: always map as UC
4014 * a. VT-d without snooping control feature: can't guarantee the
4015 * result, try to trust guest.
4016 * b. VT-d with snooping control feature: snooping control feature of
4017 * VT-d engine can guarantee the cache correctness. Just set it
4018 * to WB to keep consistent with host. So the same as item 3.
4019 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4020 * consistent with host MTRR
4023 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4024 else if (vcpu->kvm->arch.iommu_domain &&
4025 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4026 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4027 VMX_EPT_MT_EPTE_SHIFT;
4029 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4035 #define _ER(x) { EXIT_REASON_##x, #x }
4037 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4039 _ER(EXTERNAL_INTERRUPT),
4041 _ER(PENDING_INTERRUPT),
4061 _ER(IO_INSTRUCTION),
4064 _ER(MWAIT_INSTRUCTION),
4065 _ER(MONITOR_INSTRUCTION),
4066 _ER(PAUSE_INSTRUCTION),
4067 _ER(MCE_DURING_VMENTRY),
4068 _ER(TPR_BELOW_THRESHOLD),
4078 static int vmx_get_lpage_level(void)
4080 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4081 return PT_DIRECTORY_LEVEL;
4083 /* For shadow and EPT supported 1GB page */
4084 return PT_PDPE_LEVEL;
4087 static inline u32 bit(int bitno)
4089 return 1 << (bitno & 31);
4092 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4094 struct kvm_cpuid_entry2 *best;
4095 struct vcpu_vmx *vmx = to_vmx(vcpu);
4098 vmx->rdtscp_enabled = false;
4099 if (vmx_rdtscp_supported()) {
4100 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4101 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4102 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4103 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4104 vmx->rdtscp_enabled = true;
4106 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4107 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4114 static struct kvm_x86_ops vmx_x86_ops = {
4115 .cpu_has_kvm_support = cpu_has_kvm_support,
4116 .disabled_by_bios = vmx_disabled_by_bios,
4117 .hardware_setup = hardware_setup,
4118 .hardware_unsetup = hardware_unsetup,
4119 .check_processor_compatibility = vmx_check_processor_compat,
4120 .hardware_enable = hardware_enable,
4121 .hardware_disable = hardware_disable,
4122 .cpu_has_accelerated_tpr = report_flexpriority,
4124 .vcpu_create = vmx_create_vcpu,
4125 .vcpu_free = vmx_free_vcpu,
4126 .vcpu_reset = vmx_vcpu_reset,
4128 .prepare_guest_switch = vmx_save_host_state,
4129 .vcpu_load = vmx_vcpu_load,
4130 .vcpu_put = vmx_vcpu_put,
4132 .set_guest_debug = set_guest_debug,
4133 .get_msr = vmx_get_msr,
4134 .set_msr = vmx_set_msr,
4135 .get_segment_base = vmx_get_segment_base,
4136 .get_segment = vmx_get_segment,
4137 .set_segment = vmx_set_segment,
4138 .get_cpl = vmx_get_cpl,
4139 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4140 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4141 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4142 .set_cr0 = vmx_set_cr0,
4143 .set_cr3 = vmx_set_cr3,
4144 .set_cr4 = vmx_set_cr4,
4145 .set_efer = vmx_set_efer,
4146 .get_idt = vmx_get_idt,
4147 .set_idt = vmx_set_idt,
4148 .get_gdt = vmx_get_gdt,
4149 .set_gdt = vmx_set_gdt,
4150 .set_dr7 = vmx_set_dr7,
4151 .cache_reg = vmx_cache_reg,
4152 .get_rflags = vmx_get_rflags,
4153 .set_rflags = vmx_set_rflags,
4154 .fpu_activate = vmx_fpu_activate,
4155 .fpu_deactivate = vmx_fpu_deactivate,
4157 .tlb_flush = vmx_flush_tlb,
4159 .run = vmx_vcpu_run,
4160 .handle_exit = vmx_handle_exit,
4161 .skip_emulated_instruction = skip_emulated_instruction,
4162 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4163 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4164 .patch_hypercall = vmx_patch_hypercall,
4165 .set_irq = vmx_inject_irq,
4166 .set_nmi = vmx_inject_nmi,
4167 .queue_exception = vmx_queue_exception,
4168 .interrupt_allowed = vmx_interrupt_allowed,
4169 .nmi_allowed = vmx_nmi_allowed,
4170 .get_nmi_mask = vmx_get_nmi_mask,
4171 .set_nmi_mask = vmx_set_nmi_mask,
4172 .enable_nmi_window = enable_nmi_window,
4173 .enable_irq_window = enable_irq_window,
4174 .update_cr8_intercept = update_cr8_intercept,
4176 .set_tss_addr = vmx_set_tss_addr,
4177 .get_tdp_level = get_ept_level,
4178 .get_mt_mask = vmx_get_mt_mask,
4180 .exit_reasons_str = vmx_exit_reasons_str,
4181 .get_lpage_level = vmx_get_lpage_level,
4183 .cpuid_update = vmx_cpuid_update,
4185 .rdtscp_supported = vmx_rdtscp_supported,
4188 static int __init vmx_init(void)
4192 rdmsrl_safe(MSR_EFER, &host_efer);
4194 for (i = 0; i < NR_VMX_MSR; ++i)
4195 kvm_define_shared_msr(i, vmx_msr_index[i]);
4197 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4198 if (!vmx_io_bitmap_a)
4201 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4202 if (!vmx_io_bitmap_b) {
4207 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4208 if (!vmx_msr_bitmap_legacy) {
4213 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4214 if (!vmx_msr_bitmap_longmode) {
4220 * Allow direct access to the PC debug port (it is often used for I/O
4221 * delays, but the vmexits simply slow things down).
4223 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4224 clear_bit(0x80, vmx_io_bitmap_a);
4226 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4228 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4229 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4231 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4233 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4237 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4238 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4239 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4240 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4241 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4242 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4245 bypass_guest_pf = 0;
4246 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4247 VMX_EPT_WRITABLE_MASK);
4248 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4249 VMX_EPT_EXECUTABLE_MASK);
4254 if (bypass_guest_pf)
4255 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4260 free_page((unsigned long)vmx_msr_bitmap_longmode);
4262 free_page((unsigned long)vmx_msr_bitmap_legacy);
4264 free_page((unsigned long)vmx_io_bitmap_b);
4266 free_page((unsigned long)vmx_io_bitmap_a);
4270 static void __exit vmx_exit(void)
4272 free_page((unsigned long)vmx_msr_bitmap_legacy);
4273 free_page((unsigned long)vmx_msr_bitmap_longmode);
4274 free_page((unsigned long)vmx_io_bitmap_b);
4275 free_page((unsigned long)vmx_io_bitmap_a);
4280 module_init(vmx_init)
4281 module_exit(vmx_exit)