arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  47
  48 MODULE_AUTHOR("Qumranet");
  49 MODULE_LICENSE("GPL");
  50
  51 #ifdef MODULE
  52 static const struct x86_cpu_id svm_cpu_id[] = {
  53         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  54         {}
  55 };
  56 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  57 #endif
  58
  59 #define IOPM_ALLOC_ORDER 2
  60 #define MSRPM_ALLOC_ORDER 1
  61
  62 #define SEG_TYPE_LDT 2
  63 #define SEG_TYPE_BUSY_TSS16 3
  64
  65 #define SVM_FEATURE_LBRV           (1 <<  1)
  66 #define SVM_FEATURE_SVML           (1 <<  2)
  67 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  68 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  69 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  70 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  71 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  72
  73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  74
  75 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  76 #define TSC_RATIO_MIN           0x0000000000000001ULL
  77 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  78
  79 static bool erratum_383_found __read_mostly;
  80
  81 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  82
  83 /*
  84  * Set osvw_len to higher value when updated Revision Guides
  85  * are published and we know what the new status bits are
  86  */
  87 static uint64_t osvw_len = 4, osvw_status;
  88
  89 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  90 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  91
  92 static const struct svm_direct_access_msrs {
  93         u32 index;   /* Index of the MSR */
  94         bool always; /* True if intercept is initially cleared */
  95 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  96         { .index = MSR_STAR,                            .always = true  },
  97         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  98 #ifdef CONFIG_X86_64
  99         { .index = MSR_GS_BASE,                         .always = true  },
 100         { .index = MSR_FS_BASE,                         .always = true  },
 101         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 102         { .index = MSR_LSTAR,                           .always = true  },
 103         { .index = MSR_CSTAR,                           .always = true  },
 104         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 105 #endif
 106         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 107         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 108         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 109         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 110         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 111         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 112         { .index = MSR_EFER,                            .always = false },
 113         { .index = MSR_IA32_CR_PAT,                     .always = false },
 114         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 115         { .index = MSR_INVALID,                         .always = false },
 116 };
 117
 118 /* enable NPT for AMD64 and X86 with PAE */
 119 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 120 bool npt_enabled = true;
 121 #else
 122 bool npt_enabled;
 123 #endif
 124
 125 /*
 126  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 127  * pause_filter_count: On processors that support Pause filtering(indicated
 128  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 129  *      count value. On VMRUN this value is loaded into an internal counter.
 130  *      Each time a pause instruction is executed, this counter is decremented
 131  *      until it reaches zero at which time a #VMEXIT is generated if pause
 132  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 133  *      Intercept Filtering for more details.
 134  *      This also indicate if ple logic enabled.
 135  *
 136  * pause_filter_thresh: In addition, some processor families support advanced
 137  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 138  *      the amount of time a guest is allowed to execute in a pause loop.
 139  *      In this mode, a 16-bit pause filter threshold field is added in the
 140  *      VMCB. The threshold value is a cycle count that is used to reset the
 141  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 142  *      count value from VMCB into an internal counter. Then, on each pause
 143  *      instruction the hardware checks the elapsed number of cycles since
 144  *      the most recent pause instruction against the pause filter threshold.
 145  *      If the elapsed cycle count is greater than the pause filter threshold,
 146  *      then the internal pause count is reloaded from the VMCB and execution
 147  *      continues. If the elapsed cycle count is less than the pause filter
 148  *      threshold, then the internal pause count is decremented. If the count
 149  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 150  *      triggered. If advanced pause filtering is supported and pause filter
 151  *      threshold field is set to zero, the filter will operate in the simpler,
 152  *      count only mode.
 153  */
 154
 155 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 156 module_param(pause_filter_thresh, ushort, 0444);
 157
 158 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 159 module_param(pause_filter_count, ushort, 0444);
 160
 161 /* Default doubles per-vcpu window every exit. */
 162 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 163 module_param(pause_filter_count_grow, ushort, 0444);
 164
 165 /* Default resets per-vcpu window every exit to pause_filter_count. */
 166 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 167 module_param(pause_filter_count_shrink, ushort, 0444);
 168
 169 /* Default is to compute the maximum so we can never overflow. */
 170 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 171 module_param(pause_filter_count_max, ushort, 0444);
 172
 173 /* allow nested paging (virtualized MMU) for all guests */
 174 static int npt = true;
 175 module_param(npt, int, S_IRUGO);
 176
 177 /* allow nested virtualization in KVM/SVM */
 178 static int nested = true;
 179 module_param(nested, int, S_IRUGO);
 180
 181 /* enable/disable Next RIP Save */
 182 static int nrips = true;
 183 module_param(nrips, int, 0444);
 184
 185 /* enable/disable Virtual VMLOAD VMSAVE */
 186 static int vls = true;
 187 module_param(vls, int, 0444);
 188
 189 /* enable/disable Virtual GIF */
 190 static int vgif = true;
 191 module_param(vgif, int, 0444);
 192
 193 /* enable/disable SEV support */
 194 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 195 module_param(sev, int, 0444);
 196
 197 /* enable/disable SEV-ES support */
 198 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 199 module_param(sev_es, int, 0444);
 200
 201 bool __read_mostly dump_invalid_vmcb;
 202 module_param(dump_invalid_vmcb, bool, 0644);
 203
 204 static bool svm_gp_erratum_intercept = true;
 205
 206 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 207
 208 static unsigned long iopm_base;
 209
 210 struct kvm_ldttss_desc {
 211         u16 limit0;
 212         u16 base0;
 213         unsigned base1:8, type:5, dpl:2, p:1;
 214         unsigned limit1:4, zero0:3, g:1, base2:8;
 215         u32 base3;
 216         u32 zero1;
 217 } __attribute__((packed));
 218
 219 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 220
 221 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 222
 223 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 224 #define MSRS_RANGE_SIZE 2048
 225 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 226
 227 u32 svm_msrpm_offset(u32 msr)
 228 {
 229         u32 offset;
 230         int i;
 231
 232         for (i = 0; i < NUM_MSR_MAPS; i++) {
 233                 if (msr < msrpm_ranges[i] ||
 234                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 235                         continue;
 236
 237                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 238                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 239
 240                 /* Now we have the u8 offset - but need the u32 offset */
 241                 return offset / 4;
 242         }
 243
 244         /* MSR not in any range */
 245         return MSR_INVALID;
 246 }
 247
 248 #define MAX_INST_SIZE 15
 249
 250 static int get_max_npt_level(void)
 251 {
 252 #ifdef CONFIG_X86_64
 253         return PT64_ROOT_4LEVEL;
 254 #else
 255         return PT32E_ROOT_LEVEL;
 256 #endif
 257 }
 258
 259 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 260 {
 261         struct vcpu_svm *svm = to_svm(vcpu);
 262         u64 old_efer = vcpu->arch.efer;
 263         vcpu->arch.efer = efer;
 264
 265         if (!npt_enabled) {
 266                 /* Shadow paging assumes NX to be available.  */
 267                 efer |= EFER_NX;
 268
 269                 if (!(efer & EFER_LMA))
 270                         efer &= ~EFER_LME;
 271         }
 272
 273         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 274                 if (!(efer & EFER_SVME)) {
 275                         svm_leave_nested(svm);
 276                         svm_set_gif(svm, true);
 277                         /* #GP intercept is still needed for vmware backdoor */
 278                         if (!enable_vmware_backdoor)
 279                                 clr_exception_intercept(svm, GP_VECTOR);
 280
 281                         /*
 282                          * Free the nested guest state, unless we are in SMM.
 283                          * In this case we will return to the nested guest
 284                          * as soon as we leave SMM.
 285                          */
 286                         if (!is_smm(&svm->vcpu))
 287                                 svm_free_nested(svm);
 288
 289                 } else {
 290                         int ret = svm_allocate_nested(svm);
 291
 292                         if (ret) {
 293                                 vcpu->arch.efer = old_efer;
 294                                 return ret;
 295                         }
 296
 297                         if (svm_gp_erratum_intercept)
 298                                 set_exception_intercept(svm, GP_VECTOR);
 299                 }
 300         }
 301
 302         svm->vmcb->save.efer = efer | EFER_SVME;
 303         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 304         return 0;
 305 }
 306
 307 static int is_external_interrupt(u32 info)
 308 {
 309         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 310         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 311 }
 312
 313 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 314 {
 315         struct vcpu_svm *svm = to_svm(vcpu);
 316         u32 ret = 0;
 317
 318         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 319                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 320         return ret;
 321 }
 322
 323 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 324 {
 325         struct vcpu_svm *svm = to_svm(vcpu);
 326
 327         if (mask == 0)
 328                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 329         else
 330                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 331
 332 }
 333
 334 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 335 {
 336         struct vcpu_svm *svm = to_svm(vcpu);
 337
 338         /*
 339          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 340          * the type of exit and the #VC handler in the guest.
 341          */
 342         if (sev_es_guest(vcpu->kvm))
 343                 goto done;
 344
 345         if (nrips && svm->vmcb->control.next_rip != 0) {
 346                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 347                 svm->next_rip = svm->vmcb->control.next_rip;
 348         }
 349
 350         if (!svm->next_rip) {
 351                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 352                         return 0;
 353         } else {
 354                 kvm_rip_write(vcpu, svm->next_rip);
 355         }
 356
 357 done:
 358         svm_set_interrupt_shadow(vcpu, 0);
 359
 360         return 1;
 361 }
 362
 363 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 364 {
 365         struct vcpu_svm *svm = to_svm(vcpu);
 366         unsigned nr = vcpu->arch.exception.nr;
 367         bool has_error_code = vcpu->arch.exception.has_error_code;
 368         u32 error_code = vcpu->arch.exception.error_code;
 369
 370         kvm_deliver_exception_payload(&svm->vcpu);
 371
 372         if (nr == BP_VECTOR && !nrips) {
 373                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 374
 375                 /*
 376                  * For guest debugging where we have to reinject #BP if some
 377                  * INT3 is guest-owned:
 378                  * Emulate nRIP by moving RIP forward. Will fail if injection
 379                  * raises a fault that is not intercepted. Still better than
 380                  * failing in all cases.
 381                  */
 382                 (void)skip_emulated_instruction(&svm->vcpu);
 383                 rip = kvm_rip_read(&svm->vcpu);
 384                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 385                 svm->int3_injected = rip - old_rip;
 386         }
 387
 388         svm->vmcb->control.event_inj = nr
 389                 | SVM_EVTINJ_VALID
 390                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 391                 | SVM_EVTINJ_TYPE_EXEPT;
 392         svm->vmcb->control.event_inj_err = error_code;
 393 }
 394
 395 static void svm_init_erratum_383(void)
 396 {
 397         u32 low, high;
 398         int err;
 399         u64 val;
 400
 401         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 402                 return;
 403
 404         /* Use _safe variants to not break nested virtualization */
 405         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 406         if (err)
 407                 return;
 408
 409         val |= (1ULL << 47);
 410
 411         low  = lower_32_bits(val);
 412         high = upper_32_bits(val);
 413
 414         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 415
 416         erratum_383_found = true;
 417 }
 418
 419 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 420 {
 421         /*
 422          * Guests should see errata 400 and 415 as fixed (assuming that
 423          * HLT and IO instructions are intercepted).
 424          */
 425         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 426         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 427
 428         /*
 429          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 430          * all osvw.status bits inside that length, including bit 0 (which is
 431          * reserved for erratum 298), are valid. However, if host processor's
 432          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 433          * be conservative here and therefore we tell the guest that erratum 298
 434          * is present (because we really don't know).
 435          */
 436         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 437                 vcpu->arch.osvw.status |= 1;
 438 }
 439
 440 static int has_svm(void)
 441 {
 442         const char *msg;
 443
 444         if (!cpu_has_svm(&msg)) {
 445                 printk(KERN_INFO "has_svm: %s\n", msg);
 446                 return 0;
 447         }
 448
 449         if (sev_active()) {
 450                 pr_info("KVM is unsupported when running as an SEV guest\n");
 451                 return 0;
 452         }
 453
 454         return 1;
 455 }
 456
 457 static void svm_hardware_disable(void)
 458 {
 459         /* Make sure we clean up behind us */
 460         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 461                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 462
 463         cpu_svm_disable();
 464
 465         amd_pmu_disable_virt();
 466 }
 467
 468 static int svm_hardware_enable(void)
 469 {
 470
 471         struct svm_cpu_data *sd;
 472         uint64_t efer;
 473         struct desc_struct *gdt;
 474         int me = raw_smp_processor_id();
 475
 476         rdmsrl(MSR_EFER, efer);
 477         if (efer & EFER_SVME)
 478                 return -EBUSY;
 479
 480         if (!has_svm()) {
 481                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 482                 return -EINVAL;
 483         }
 484         sd = per_cpu(svm_data, me);
 485         if (!sd) {
 486                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 487                 return -EINVAL;
 488         }
 489
 490         sd->asid_generation = 1;
 491         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 492         sd->next_asid = sd->max_asid + 1;
 493         sd->min_asid = max_sev_asid + 1;
 494
 495         gdt = get_current_gdt_rw();
 496         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 497
 498         wrmsrl(MSR_EFER, efer | EFER_SVME);
 499
 500         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 501
 502         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 503                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 504                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 505         }
 506
 507
 508         /*
 509          * Get OSVW bits.
 510          *
 511          * Note that it is possible to have a system with mixed processor
 512          * revisions and therefore different OSVW bits. If bits are not the same
 513          * on different processors then choose the worst case (i.e. if erratum
 514          * is present on one processor and not on another then assume that the
 515          * erratum is present everywhere).
 516          */
 517         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 518                 uint64_t len, status = 0;
 519                 int err;
 520
 521                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 522                 if (!err)
 523                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 524                                                       &err);
 525
 526                 if (err)
 527                         osvw_status = osvw_len = 0;
 528                 else {
 529                         if (len < osvw_len)
 530                                 osvw_len = len;
 531                         osvw_status |= status;
 532                         osvw_status &= (1ULL << osvw_len) - 1;
 533                 }
 534         } else
 535                 osvw_status = osvw_len = 0;
 536
 537         svm_init_erratum_383();
 538
 539         amd_pmu_enable_virt();
 540
 541         return 0;
 542 }
 543
 544 static void svm_cpu_uninit(int cpu)
 545 {
 546         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 547
 548         if (!sd)
 549                 return;
 550
 551         per_cpu(svm_data, cpu) = NULL;
 552         kfree(sd->sev_vmcbs);
 553         __free_page(sd->save_area);
 554         kfree(sd);
 555 }
 556
 557 static int svm_cpu_init(int cpu)
 558 {
 559         struct svm_cpu_data *sd;
 560
 561         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 562         if (!sd)
 563                 return -ENOMEM;
 564         sd->cpu = cpu;
 565         sd->save_area = alloc_page(GFP_KERNEL);
 566         if (!sd->save_area)
 567                 goto free_cpu_data;
 568         clear_page(page_address(sd->save_area));
 569
 570         if (svm_sev_enabled()) {
 571                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 572                                               sizeof(void *),
 573                                               GFP_KERNEL);
 574                 if (!sd->sev_vmcbs)
 575                         goto free_save_area;
 576         }
 577
 578         per_cpu(svm_data, cpu) = sd;
 579
 580         return 0;
 581
 582 free_save_area:
 583         __free_page(sd->save_area);
 584 free_cpu_data:
 585         kfree(sd);
 586         return -ENOMEM;
 587
 588 }
 589
 590 static int direct_access_msr_slot(u32 msr)
 591 {
 592         u32 i;
 593
 594         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 595                 if (direct_access_msrs[i].index == msr)
 596                         return i;
 597
 598         return -ENOENT;
 599 }
 600
 601 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 602                                      int write)
 603 {
 604         struct vcpu_svm *svm = to_svm(vcpu);
 605         int slot = direct_access_msr_slot(msr);
 606
 607         if (slot == -ENOENT)
 608                 return;
 609
 610         /* Set the shadow bitmaps to the desired intercept states */
 611         if (read)
 612                 set_bit(slot, svm->shadow_msr_intercept.read);
 613         else
 614                 clear_bit(slot, svm->shadow_msr_intercept.read);
 615
 616         if (write)
 617                 set_bit(slot, svm->shadow_msr_intercept.write);
 618         else
 619                 clear_bit(slot, svm->shadow_msr_intercept.write);
 620 }
 621
 622 static bool valid_msr_intercept(u32 index)
 623 {
 624         return direct_access_msr_slot(index) != -ENOENT;
 625 }
 626
 627 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 628 {
 629         u8 bit_write;
 630         unsigned long tmp;
 631         u32 offset;
 632         u32 *msrpm;
 633
 634         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 635                                       to_svm(vcpu)->msrpm;
 636
 637         offset    = svm_msrpm_offset(msr);
 638         bit_write = 2 * (msr & 0x0f) + 1;
 639         tmp       = msrpm[offset];
 640
 641         BUG_ON(offset == MSR_INVALID);
 642
 643         return !!test_bit(bit_write,  &tmp);
 644 }
 645
 646 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 647                                         u32 msr, int read, int write)
 648 {
 649         u8 bit_read, bit_write;
 650         unsigned long tmp;
 651         u32 offset;
 652
 653         /*
 654          * If this warning triggers extend the direct_access_msrs list at the
 655          * beginning of the file
 656          */
 657         WARN_ON(!valid_msr_intercept(msr));
 658
 659         /* Enforce non allowed MSRs to trap */
 660         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 661                 read = 0;
 662
 663         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 664                 write = 0;
 665
 666         offset    = svm_msrpm_offset(msr);
 667         bit_read  = 2 * (msr & 0x0f);
 668         bit_write = 2 * (msr & 0x0f) + 1;
 669         tmp       = msrpm[offset];
 670
 671         BUG_ON(offset == MSR_INVALID);
 672
 673         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 674         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 675
 676         msrpm[offset] = tmp;
 677 }
 678
 679 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 680                           int read, int write)
 681 {
 682         set_shadow_msr_intercept(vcpu, msr, read, write);
 683         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 684 }
 685
 686 u32 *svm_vcpu_alloc_msrpm(void)
 687 {
 688         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
 689         u32 *msrpm;
 690
 691         if (!pages)
 692                 return NULL;
 693
 694         msrpm = page_address(pages);
 695         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 696
 697         return msrpm;
 698 }
 699
 700 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 701 {
 702         int i;
 703
 704         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 705                 if (!direct_access_msrs[i].always)
 706                         continue;
 707                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 708         }
 709 }
 710
 711
 712 void svm_vcpu_free_msrpm(u32 *msrpm)
 713 {
 714         __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
 715 }
 716
 717 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 718 {
 719         struct vcpu_svm *svm = to_svm(vcpu);
 720         u32 i;
 721
 722         /*
 723          * Set intercept permissions for all direct access MSRs again. They
 724          * will automatically get filtered through the MSR filter, so we are
 725          * back in sync after this.
 726          */
 727         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 728                 u32 msr = direct_access_msrs[i].index;
 729                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 730                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 731
 732                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 733         }
 734 }
 735
 736 static void add_msr_offset(u32 offset)
 737 {
 738         int i;
 739
 740         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 741
 742                 /* Offset already in list? */
 743                 if (msrpm_offsets[i] == offset)
 744                         return;
 745
 746                 /* Slot used by another offset? */
 747                 if (msrpm_offsets[i] != MSR_INVALID)
 748                         continue;
 749
 750                 /* Add offset to list */
 751                 msrpm_offsets[i] = offset;
 752
 753                 return;
 754         }
 755
 756         /*
 757          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 758          * increase MSRPM_OFFSETS in this case.
 759          */
 760         BUG();
 761 }
 762
 763 static void init_msrpm_offsets(void)
 764 {
 765         int i;
 766
 767         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 768
 769         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 770                 u32 offset;
 771
 772                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 773                 BUG_ON(offset == MSR_INVALID);
 774
 775                 add_msr_offset(offset);
 776         }
 777 }
 778
 779 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 780 {
 781         struct vcpu_svm *svm = to_svm(vcpu);
 782
 783         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 784         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 785         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 786         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 787         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 788 }
 789
 790 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 791 {
 792         struct vcpu_svm *svm = to_svm(vcpu);
 793
 794         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 795         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 796         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 797         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 798         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 799 }
 800
 801 void disable_nmi_singlestep(struct vcpu_svm *svm)
 802 {
 803         svm->nmi_singlestep = false;
 804
 805         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 806                 /* Clear our flags if they were not set by the guest */
 807                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 808                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 809                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 810                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 811         }
 812 }
 813
 814 static void grow_ple_window(struct kvm_vcpu *vcpu)
 815 {
 816         struct vcpu_svm *svm = to_svm(vcpu);
 817         struct vmcb_control_area *control = &svm->vmcb->control;
 818         int old = control->pause_filter_count;
 819
 820         control->pause_filter_count = __grow_ple_window(old,
 821                                                         pause_filter_count,
 822                                                         pause_filter_count_grow,
 823                                                         pause_filter_count_max);
 824
 825         if (control->pause_filter_count != old) {
 826                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 827                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 828                                             control->pause_filter_count, old);
 829         }
 830 }
 831
 832 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 833 {
 834         struct vcpu_svm *svm = to_svm(vcpu);
 835         struct vmcb_control_area *control = &svm->vmcb->control;
 836         int old = control->pause_filter_count;
 837
 838         control->pause_filter_count =
 839                                 __shrink_ple_window(old,
 840                                                     pause_filter_count,
 841                                                     pause_filter_count_shrink,
 842                                                     pause_filter_count);
 843         if (control->pause_filter_count != old) {
 844                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 845                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 846                                             control->pause_filter_count, old);
 847         }
 848 }
 849
 850 /*
 851  * The default MMIO mask is a single bit (excluding the present bit),
 852  * which could conflict with the memory encryption bit. Check for
 853  * memory encryption support and override the default MMIO mask if
 854  * memory encryption is enabled.
 855  */
 856 static __init void svm_adjust_mmio_mask(void)
 857 {
 858         unsigned int enc_bit, mask_bit;
 859         u64 msr, mask;
 860
 861         /* If there is no memory encryption support, use existing mask */
 862         if (cpuid_eax(0x80000000) < 0x8000001f)
 863                 return;
 864
 865         /* If memory encryption is not enabled, use existing mask */
 866         rdmsrl(MSR_K8_SYSCFG, msr);
 867         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 868                 return;
 869
 870         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 871         mask_bit = boot_cpu_data.x86_phys_bits;
 872
 873         /* Increment the mask bit if it is the same as the encryption bit */
 874         if (enc_bit == mask_bit)
 875                 mask_bit++;
 876
 877         /*
 878          * If the mask bit location is below 52, then some bits above the
 879          * physical addressing limit will always be reserved, so use the
 880          * rsvd_bits() function to generate the mask. This mask, along with
 881          * the present bit, will be used to generate a page fault with
 882          * PFER.RSV = 1.
 883          *
 884          * If the mask bit location is 52 (or above), then clear the mask.
 885          */
 886         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 887
 888         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 889 }
 890
 891 static void svm_hardware_teardown(void)
 892 {
 893         int cpu;
 894
 895         if (svm_sev_enabled())
 896                 sev_hardware_teardown();
 897
 898         for_each_possible_cpu(cpu)
 899                 svm_cpu_uninit(cpu);
 900
 901         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 902         iopm_base = 0;
 903 }
 904
 905 static __init void svm_set_cpu_caps(void)
 906 {
 907         kvm_set_cpu_caps();
 908
 909         supported_xss = 0;
 910
 911         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 912         if (nested) {
 913                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 914
 915                 if (nrips)
 916                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 917
 918                 if (npt_enabled)
 919                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 920
 921                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 922                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 923         }
 924
 925         /* CPUID 0x80000008 */
 926         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 927             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 928                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 929 }
 930
 931 static __init int svm_hardware_setup(void)
 932 {
 933         int cpu;
 934         struct page *iopm_pages;
 935         void *iopm_va;
 936         int r;
 937
 938         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 939
 940         if (!iopm_pages)
 941                 return -ENOMEM;
 942
 943         iopm_va = page_address(iopm_pages);
 944         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 945         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 946
 947         init_msrpm_offsets();
 948
 949         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 950
 951         if (boot_cpu_has(X86_FEATURE_NX))
 952                 kvm_enable_efer_bits(EFER_NX);
 953
 954         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 955                 kvm_enable_efer_bits(EFER_FFXSR);
 956
 957         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 958                 kvm_has_tsc_control = true;
 959                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 960                 kvm_tsc_scaling_ratio_frac_bits = 32;
 961         }
 962
 963         /* Check for pause filtering support */
 964         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 965                 pause_filter_count = 0;
 966                 pause_filter_thresh = 0;
 967         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 968                 pause_filter_thresh = 0;
 969         }
 970
 971         if (nested) {
 972                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 973                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 974         }
 975
 976         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
 977                 sev_hardware_setup();
 978         } else {
 979                 sev = false;
 980                 sev_es = false;
 981         }
 982
 983         svm_adjust_mmio_mask();
 984
 985         for_each_possible_cpu(cpu) {
 986                 r = svm_cpu_init(cpu);
 987                 if (r)
 988                         goto err;
 989         }
 990
 991         if (!boot_cpu_has(X86_FEATURE_NPT))
 992                 npt_enabled = false;
 993
 994         if (npt_enabled && !npt)
 995                 npt_enabled = false;
 996
 997         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 998         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 999
1000         if (nrips) {
1001                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1002                         nrips = false;
1003         }
1004
1005         if (avic) {
1006                 if (!npt_enabled ||
1007                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1008                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1009                         avic = false;
1010                 } else {
1011                         pr_info("AVIC enabled\n");
1012
1013                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1014                 }
1015         }
1016
1017         if (vls) {
1018                 if (!npt_enabled ||
1019                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1020                     !IS_ENABLED(CONFIG_X86_64)) {
1021                         vls = false;
1022                 } else {
1023                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1024                 }
1025         }
1026
1027         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1028                 svm_gp_erratum_intercept = false;
1029
1030         if (vgif) {
1031                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1032                         vgif = false;
1033                 else
1034                         pr_info("Virtual GIF supported\n");
1035         }
1036
1037         svm_set_cpu_caps();
1038
1039         /*
1040          * It seems that on AMD processors PTE's accessed bit is
1041          * being set by the CPU hardware before the NPF vmexit.
1042          * This is not expected behaviour and our tests fail because
1043          * of it.
1044          * A workaround here is to disable support for
1045          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1046          * In this case userspace can know if there is support using
1047          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1048          * it
1049          * If future AMD CPU models change the behaviour described above,
1050          * this variable can be changed accordingly
1051          */
1052         allow_smaller_maxphyaddr = !npt_enabled;
1053
1054         return 0;
1055
1056 err:
1057         svm_hardware_teardown();
1058         return r;
1059 }
1060
1061 static void init_seg(struct vmcb_seg *seg)
1062 {
1063         seg->selector = 0;
1064         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1065                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1066         seg->limit = 0xffff;
1067         seg->base = 0;
1068 }
1069
1070 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1071 {
1072         seg->selector = 0;
1073         seg->attrib = SVM_SELECTOR_P_MASK | type;
1074         seg->limit = 0xffff;
1075         seg->base = 0;
1076 }
1077
1078 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1079 {
1080         struct vcpu_svm *svm = to_svm(vcpu);
1081         u64 g_tsc_offset = 0;
1082
1083         if (is_guest_mode(vcpu)) {
1084                 /* Write L1's TSC offset.  */
1085                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1086                                svm->nested.hsave->control.tsc_offset;
1087                 svm->nested.hsave->control.tsc_offset = offset;
1088         }
1089
1090         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1091                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1092                                    offset);
1093
1094         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1095
1096         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1097         return svm->vmcb->control.tsc_offset;
1098 }
1099
1100 static void svm_check_invpcid(struct vcpu_svm *svm)
1101 {
1102         /*
1103          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1104          * roots, or if INVPCID is disabled in the guest to inject #UD.
1105          */
1106         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1107                 if (!npt_enabled ||
1108                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1109                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1110                 else
1111                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1112         }
1113 }
1114
1115 static void init_vmcb(struct vcpu_svm *svm)
1116 {
1117         struct vmcb_control_area *control = &svm->vmcb->control;
1118         struct vmcb_save_area *save = &svm->vmcb->save;
1119
1120         svm->vcpu.arch.hflags = 0;
1121
1122         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1123         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1124         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1125         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1126         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1127         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1128         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1129                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1130
1131         set_dr_intercepts(svm);
1132
1133         set_exception_intercept(svm, PF_VECTOR);
1134         set_exception_intercept(svm, UD_VECTOR);
1135         set_exception_intercept(svm, MC_VECTOR);
1136         set_exception_intercept(svm, AC_VECTOR);
1137         set_exception_intercept(svm, DB_VECTOR);
1138         /*
1139          * Guest access to VMware backdoor ports could legitimately
1140          * trigger #GP because of TSS I/O permission bitmap.
1141          * We intercept those #GP and allow access to them anyway
1142          * as VMware does.
1143          */
1144         if (enable_vmware_backdoor)
1145                 set_exception_intercept(svm, GP_VECTOR);
1146
1147         svm_set_intercept(svm, INTERCEPT_INTR);
1148         svm_set_intercept(svm, INTERCEPT_NMI);
1149         svm_set_intercept(svm, INTERCEPT_SMI);
1150         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1151         svm_set_intercept(svm, INTERCEPT_RDPMC);
1152         svm_set_intercept(svm, INTERCEPT_CPUID);
1153         svm_set_intercept(svm, INTERCEPT_INVD);
1154         svm_set_intercept(svm, INTERCEPT_INVLPG);
1155         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1156         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1157         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1158         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1159         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1160         svm_set_intercept(svm, INTERCEPT_VMRUN);
1161         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1162         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1163         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1164         svm_set_intercept(svm, INTERCEPT_STGI);
1165         svm_set_intercept(svm, INTERCEPT_CLGI);
1166         svm_set_intercept(svm, INTERCEPT_SKINIT);
1167         svm_set_intercept(svm, INTERCEPT_WBINVD);
1168         svm_set_intercept(svm, INTERCEPT_XSETBV);
1169         svm_set_intercept(svm, INTERCEPT_RDPRU);
1170         svm_set_intercept(svm, INTERCEPT_RSM);
1171
1172         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1173                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1174                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1175         }
1176
1177         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1178                 svm_set_intercept(svm, INTERCEPT_HLT);
1179
1180         control->iopm_base_pa = __sme_set(iopm_base);
1181         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1182         control->int_ctl = V_INTR_MASKING_MASK;
1183
1184         init_seg(&save->es);
1185         init_seg(&save->ss);
1186         init_seg(&save->ds);
1187         init_seg(&save->fs);
1188         init_seg(&save->gs);
1189
1190         save->cs.selector = 0xf000;
1191         save->cs.base = 0xffff0000;
1192         /* Executable/Readable Code Segment */
1193         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1194                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1195         save->cs.limit = 0xffff;
1196
1197         save->gdtr.limit = 0xffff;
1198         save->idtr.limit = 0xffff;
1199
1200         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1201         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1202
1203         svm_set_efer(&svm->vcpu, 0);
1204         save->dr6 = 0xffff0ff0;
1205         kvm_set_rflags(&svm->vcpu, X86_EFLAGS_FIXED);
1206         save->rip = 0x0000fff0;
1207         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1208
1209         /*
1210          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1211          * It also updates the guest-visible cr0 value.
1212          */
1213         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1214         kvm_mmu_reset_context(&svm->vcpu);
1215
1216         save->cr4 = X86_CR4_PAE;
1217         /* rdx = ?? */
1218
1219         if (npt_enabled) {
1220                 /* Setup VMCB for Nested Paging */
1221                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1222                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1223                 clr_exception_intercept(svm, PF_VECTOR);
1224                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1225                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1226                 save->g_pat = svm->vcpu.arch.pat;
1227                 save->cr3 = 0;
1228                 save->cr4 = 0;
1229         }
1230         svm->asid_generation = 0;
1231         svm->asid = 0;
1232
1233         svm->nested.vmcb12_gpa = 0;
1234         svm->vcpu.arch.hflags = 0;
1235
1236         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1237                 control->pause_filter_count = pause_filter_count;
1238                 if (pause_filter_thresh)
1239                         control->pause_filter_thresh = pause_filter_thresh;
1240                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1241         } else {
1242                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1243         }
1244
1245         svm_check_invpcid(svm);
1246
1247         if (kvm_vcpu_apicv_active(&svm->vcpu))
1248                 avic_init_vmcb(svm);
1249
1250         /*
1251          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1252          * in VMCB and clear intercepts to avoid #VMEXIT.
1253          */
1254         if (vls) {
1255                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1256                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1257                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1258         }
1259
1260         if (vgif) {
1261                 svm_clr_intercept(svm, INTERCEPT_STGI);
1262                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1263                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1264         }
1265
1266         if (sev_guest(svm->vcpu.kvm)) {
1267                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1268                 clr_exception_intercept(svm, UD_VECTOR);
1269
1270                 if (sev_es_guest(svm->vcpu.kvm)) {
1271                         /* Perform SEV-ES specific VMCB updates */
1272                         sev_es_init_vmcb(svm);
1273                 }
1274         }
1275
1276         vmcb_mark_all_dirty(svm->vmcb);
1277
1278         enable_gif(svm);
1279
1280 }
1281
1282 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1283 {
1284         struct vcpu_svm *svm = to_svm(vcpu);
1285         u32 dummy;
1286         u32 eax = 1;
1287
1288         svm->spec_ctrl = 0;
1289         svm->virt_spec_ctrl = 0;
1290
1291         if (!init_event) {
1292                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1293                                            MSR_IA32_APICBASE_ENABLE;
1294                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1295                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1296         }
1297         init_vmcb(svm);
1298
1299         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1300         kvm_rdx_write(vcpu, eax);
1301
1302         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1303                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1304 }
1305
1306 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1307 {
1308         struct vcpu_svm *svm;
1309         struct page *vmcb_page;
1310         struct page *vmsa_page = NULL;
1311         int err;
1312
1313         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1314         svm = to_svm(vcpu);
1315
1316         err = -ENOMEM;
1317         vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1318         if (!vmcb_page)
1319                 goto out;
1320
1321         if (sev_es_guest(svm->vcpu.kvm)) {
1322                 /*
1323                  * SEV-ES guests require a separate VMSA page used to contain
1324                  * the encrypted register state of the guest.
1325                  */
1326                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1327                 if (!vmsa_page)
1328                         goto error_free_vmcb_page;
1329
1330                 /*
1331                  * SEV-ES guests maintain an encrypted version of their FPU
1332                  * state which is restored and saved on VMRUN and VMEXIT.
1333                  * Free the fpu structure to prevent KVM from attempting to
1334                  * access the FPU state.
1335                  */
1336                 kvm_free_guest_fpu(vcpu);
1337         }
1338
1339         err = avic_init_vcpu(svm);
1340         if (err)
1341                 goto error_free_vmsa_page;
1342
1343         /* We initialize this flag to true to make sure that the is_running
1344          * bit would be set the first time the vcpu is loaded.
1345          */
1346         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1347                 svm->avic_is_running = true;
1348
1349         svm->msrpm = svm_vcpu_alloc_msrpm();
1350         if (!svm->msrpm) {
1351                 err = -ENOMEM;
1352                 goto error_free_vmsa_page;
1353         }
1354
1355         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1356
1357         svm->vmcb = page_address(vmcb_page);
1358         svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1359
1360         if (vmsa_page)
1361                 svm->vmsa = page_address(vmsa_page);
1362
1363         svm->asid_generation = 0;
1364         svm->guest_state_loaded = false;
1365         init_vmcb(svm);
1366
1367         svm_init_osvw(vcpu);
1368         vcpu->arch.microcode_version = 0x01000065;
1369
1370         if (sev_es_guest(svm->vcpu.kvm))
1371                 /* Perform SEV-ES specific VMCB creation updates */
1372                 sev_es_create_vcpu(svm);
1373
1374         return 0;
1375
1376 error_free_vmsa_page:
1377         if (vmsa_page)
1378                 __free_page(vmsa_page);
1379 error_free_vmcb_page:
1380         __free_page(vmcb_page);
1381 out:
1382         return err;
1383 }
1384
1385 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1386 {
1387         int i;
1388
1389         for_each_online_cpu(i)
1390                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1391 }
1392
1393 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1394 {
1395         struct vcpu_svm *svm = to_svm(vcpu);
1396
1397         /*
1398          * The vmcb page can be recycled, causing a false negative in
1399          * svm_vcpu_load(). So, ensure that no logical CPU has this
1400          * vmcb page recorded as its current vmcb.
1401          */
1402         svm_clear_current_vmcb(svm->vmcb);
1403
1404         svm_free_nested(svm);
1405
1406         sev_free_vcpu(vcpu);
1407
1408         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1409         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1410 }
1411
1412 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1413 {
1414         struct vcpu_svm *svm = to_svm(vcpu);
1415         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1416         unsigned int i;
1417
1418         if (svm->guest_state_loaded)
1419                 return;
1420
1421         /*
1422          * Certain MSRs are restored on VMEXIT (sev-es), or vmload of host save
1423          * area (non-sev-es). Save ones that aren't so we can restore them
1424          * individually later.
1425          */
1426         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1427                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1428
1429         /*
1430          * Save additional host state that will be restored on VMEXIT (sev-es)
1431          * or subsequent vmload of host save area.
1432          */
1433         if (sev_es_guest(svm->vcpu.kvm)) {
1434                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1435         } else {
1436                 vmsave(__sme_page_pa(sd->save_area));
1437         }
1438
1439         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1440                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1441                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1442                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1443                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1444                 }
1445         }
1446
1447         /* This assumes that the kernel never uses MSR_TSC_AUX */
1448         if (static_cpu_has(X86_FEATURE_RDTSCP))
1449                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1450
1451         svm->guest_state_loaded = true;
1452 }
1453
1454 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1455 {
1456         struct vcpu_svm *svm = to_svm(vcpu);
1457         unsigned int i;
1458
1459         if (!svm->guest_state_loaded)
1460                 return;
1461
1462         /*
1463          * Certain MSRs are restored on VMEXIT (sev-es), or vmload of host save
1464          * area (non-sev-es). Restore the ones that weren't.
1465          */
1466         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1467                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1468
1469         svm->guest_state_loaded = false;
1470 }
1471
1472 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1473 {
1474         struct vcpu_svm *svm = to_svm(vcpu);
1475         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1476
1477         if (unlikely(cpu != vcpu->cpu)) {
1478                 svm->asid_generation = 0;
1479                 vmcb_mark_all_dirty(svm->vmcb);
1480         }
1481
1482         if (sd->current_vmcb != svm->vmcb) {
1483                 sd->current_vmcb = svm->vmcb;
1484                 indirect_branch_prediction_barrier();
1485         }
1486         avic_vcpu_load(vcpu, cpu);
1487 }
1488
1489 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1490 {
1491         avic_vcpu_put(vcpu);
1492         svm_prepare_host_switch(vcpu);
1493
1494         ++vcpu->stat.host_state_reload;
1495 }
1496
1497 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1498 {
1499         struct vcpu_svm *svm = to_svm(vcpu);
1500         unsigned long rflags = svm->vmcb->save.rflags;
1501
1502         if (svm->nmi_singlestep) {
1503                 /* Hide our flags if they were not set by the guest */
1504                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1505                         rflags &= ~X86_EFLAGS_TF;
1506                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1507                         rflags &= ~X86_EFLAGS_RF;
1508         }
1509         return rflags;
1510 }
1511
1512 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1513 {
1514         if (to_svm(vcpu)->nmi_singlestep)
1515                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1516
1517        /*
1518         * Any change of EFLAGS.VM is accompanied by a reload of SS
1519         * (caused by either a task switch or an inter-privilege IRET),
1520         * so we do not need to update the CPL here.
1521         */
1522         to_svm(vcpu)->vmcb->save.rflags = rflags;
1523 }
1524
1525 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1526 {
1527         switch (reg) {
1528         case VCPU_EXREG_PDPTR:
1529                 BUG_ON(!npt_enabled);
1530                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1531                 break;
1532         default:
1533                 WARN_ON_ONCE(1);
1534         }
1535 }
1536
1537 static void svm_set_vintr(struct vcpu_svm *svm)
1538 {
1539         struct vmcb_control_area *control;
1540
1541         /* The following fields are ignored when AVIC is enabled */
1542         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1543         svm_set_intercept(svm, INTERCEPT_VINTR);
1544
1545         /*
1546          * This is just a dummy VINTR to actually cause a vmexit to happen.
1547          * Actual injection of virtual interrupts happens through EVENTINJ.
1548          */
1549         control = &svm->vmcb->control;
1550         control->int_vector = 0x0;
1551         control->int_ctl &= ~V_INTR_PRIO_MASK;
1552         control->int_ctl |= V_IRQ_MASK |
1553                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1554         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1555 }
1556
1557 static void svm_clear_vintr(struct vcpu_svm *svm)
1558 {
1559         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1560         svm_clr_intercept(svm, INTERCEPT_VINTR);
1561
1562         /* Drop int_ctl fields related to VINTR injection.  */
1563         svm->vmcb->control.int_ctl &= mask;
1564         if (is_guest_mode(&svm->vcpu)) {
1565                 svm->nested.hsave->control.int_ctl &= mask;
1566
1567                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1568                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1569                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1570         }
1571
1572         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1573 }
1574
1575 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1576 {
1577         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1578
1579         switch (seg) {
1580         case VCPU_SREG_CS: return &save->cs;
1581         case VCPU_SREG_DS: return &save->ds;
1582         case VCPU_SREG_ES: return &save->es;
1583         case VCPU_SREG_FS: return &save->fs;
1584         case VCPU_SREG_GS: return &save->gs;
1585         case VCPU_SREG_SS: return &save->ss;
1586         case VCPU_SREG_TR: return &save->tr;
1587         case VCPU_SREG_LDTR: return &save->ldtr;
1588         }
1589         BUG();
1590         return NULL;
1591 }
1592
1593 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1594 {
1595         struct vmcb_seg *s = svm_seg(vcpu, seg);
1596
1597         return s->base;
1598 }
1599
1600 static void svm_get_segment(struct kvm_vcpu *vcpu,
1601                             struct kvm_segment *var, int seg)
1602 {
1603         struct vmcb_seg *s = svm_seg(vcpu, seg);
1604
1605         var->base = s->base;
1606         var->limit = s->limit;
1607         var->selector = s->selector;
1608         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1609         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1610         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1611         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1612         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1613         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1614         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1615
1616         /*
1617          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1618          * However, the SVM spec states that the G bit is not observed by the
1619          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1620          * So let's synthesize a legal G bit for all segments, this helps
1621          * running KVM nested. It also helps cross-vendor migration, because
1622          * Intel's vmentry has a check on the 'G' bit.
1623          */
1624         var->g = s->limit > 0xfffff;
1625
1626         /*
1627          * AMD's VMCB does not have an explicit unusable field, so emulate it
1628          * for cross vendor migration purposes by "not present"
1629          */
1630         var->unusable = !var->present;
1631
1632         switch (seg) {
1633         case VCPU_SREG_TR:
1634                 /*
1635                  * Work around a bug where the busy flag in the tr selector
1636                  * isn't exposed
1637                  */
1638                 var->type |= 0x2;
1639                 break;
1640         case VCPU_SREG_DS:
1641         case VCPU_SREG_ES:
1642         case VCPU_SREG_FS:
1643         case VCPU_SREG_GS:
1644                 /*
1645                  * The accessed bit must always be set in the segment
1646                  * descriptor cache, although it can be cleared in the
1647                  * descriptor, the cached bit always remains at 1. Since
1648                  * Intel has a check on this, set it here to support
1649                  * cross-vendor migration.
1650                  */
1651                 if (!var->unusable)
1652                         var->type |= 0x1;
1653                 break;
1654         case VCPU_SREG_SS:
1655                 /*
1656                  * On AMD CPUs sometimes the DB bit in the segment
1657                  * descriptor is left as 1, although the whole segment has
1658                  * been made unusable. Clear it here to pass an Intel VMX
1659                  * entry check when cross vendor migrating.
1660                  */
1661                 if (var->unusable)
1662                         var->db = 0;
1663                 /* This is symmetric with svm_set_segment() */
1664                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1665                 break;
1666         }
1667 }
1668
1669 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1670 {
1671         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1672
1673         return save->cpl;
1674 }
1675
1676 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1677 {
1678         struct vcpu_svm *svm = to_svm(vcpu);
1679
1680         dt->size = svm->vmcb->save.idtr.limit;
1681         dt->address = svm->vmcb->save.idtr.base;
1682 }
1683
1684 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1685 {
1686         struct vcpu_svm *svm = to_svm(vcpu);
1687
1688         svm->vmcb->save.idtr.limit = dt->size;
1689         svm->vmcb->save.idtr.base = dt->address ;
1690         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1691 }
1692
1693 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1694 {
1695         struct vcpu_svm *svm = to_svm(vcpu);
1696
1697         dt->size = svm->vmcb->save.gdtr.limit;
1698         dt->address = svm->vmcb->save.gdtr.base;
1699 }
1700
1701 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1702 {
1703         struct vcpu_svm *svm = to_svm(vcpu);
1704
1705         svm->vmcb->save.gdtr.limit = dt->size;
1706         svm->vmcb->save.gdtr.base = dt->address ;
1707         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1708 }
1709
1710 static void update_cr0_intercept(struct vcpu_svm *svm)
1711 {
1712         ulong gcr0;
1713         u64 *hcr0;
1714
1715         /*
1716          * SEV-ES guests must always keep the CR intercepts cleared. CR
1717          * tracking is done using the CR write traps.
1718          */
1719         if (sev_es_guest(svm->vcpu.kvm))
1720                 return;
1721
1722         gcr0 = svm->vcpu.arch.cr0;
1723         hcr0 = &svm->vmcb->save.cr0;
1724         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1725                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1726
1727         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1728
1729         if (gcr0 == *hcr0) {
1730                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1731                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1732         } else {
1733                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1734                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1735         }
1736 }
1737
1738 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1739 {
1740         struct vcpu_svm *svm = to_svm(vcpu);
1741
1742 #ifdef CONFIG_X86_64
1743         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1744                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1745                         vcpu->arch.efer |= EFER_LMA;
1746                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1747                 }
1748
1749                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1750                         vcpu->arch.efer &= ~EFER_LMA;
1751                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1752                 }
1753         }
1754 #endif
1755         vcpu->arch.cr0 = cr0;
1756
1757         if (!npt_enabled)
1758                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1759
1760         /*
1761          * re-enable caching here because the QEMU bios
1762          * does not do it - this results in some delay at
1763          * reboot
1764          */
1765         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1766                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1767         svm->vmcb->save.cr0 = cr0;
1768         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1769         update_cr0_intercept(svm);
1770 }
1771
1772 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1773 {
1774         return true;
1775 }
1776
1777 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1778 {
1779         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1780         unsigned long old_cr4 = vcpu->arch.cr4;
1781
1782         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1783                 svm_flush_tlb(vcpu);
1784
1785         vcpu->arch.cr4 = cr4;
1786         if (!npt_enabled)
1787                 cr4 |= X86_CR4_PAE;
1788         cr4 |= host_cr4_mce;
1789         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1790         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1791
1792         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1793                 kvm_update_cpuid_runtime(vcpu);
1794 }
1795
1796 static void svm_set_segment(struct kvm_vcpu *vcpu,
1797                             struct kvm_segment *var, int seg)
1798 {
1799         struct vcpu_svm *svm = to_svm(vcpu);
1800         struct vmcb_seg *s = svm_seg(vcpu, seg);
1801
1802         s->base = var->base;
1803         s->limit = var->limit;
1804         s->selector = var->selector;
1805         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1806         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1807         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1808         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1809         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1810         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1811         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1812         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1813
1814         /*
1815          * This is always accurate, except if SYSRET returned to a segment
1816          * with SS.DPL != 3.  Intel does not have this quirk, and always
1817          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1818          * would entail passing the CPL to userspace and back.
1819          */
1820         if (seg == VCPU_SREG_SS)
1821                 /* This is symmetric with svm_get_segment() */
1822                 svm->vmcb->save.cpl = (var->dpl & 3);
1823
1824         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1825 }
1826
1827 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1828 {
1829         struct vcpu_svm *svm = to_svm(vcpu);
1830
1831         clr_exception_intercept(svm, BP_VECTOR);
1832
1833         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1834                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1835                         set_exception_intercept(svm, BP_VECTOR);
1836         }
1837 }
1838
1839 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1840 {
1841         if (sd->next_asid > sd->max_asid) {
1842                 ++sd->asid_generation;
1843                 sd->next_asid = sd->min_asid;
1844                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1845                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1846         }
1847
1848         svm->asid_generation = sd->asid_generation;
1849         svm->asid = sd->next_asid++;
1850 }
1851
1852 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1853 {
1854         struct vmcb *vmcb = svm->vmcb;
1855
1856         if (svm->vcpu.arch.guest_state_protected)
1857                 return;
1858
1859         if (unlikely(value != vmcb->save.dr6)) {
1860                 vmcb->save.dr6 = value;
1861                 vmcb_mark_dirty(vmcb, VMCB_DR);
1862         }
1863 }
1864
1865 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1866 {
1867         struct vcpu_svm *svm = to_svm(vcpu);
1868
1869         if (vcpu->arch.guest_state_protected)
1870                 return;
1871
1872         get_debugreg(vcpu->arch.db[0], 0);
1873         get_debugreg(vcpu->arch.db[1], 1);
1874         get_debugreg(vcpu->arch.db[2], 2);
1875         get_debugreg(vcpu->arch.db[3], 3);
1876         /*
1877          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1878          * because db_interception might need it.  We can do it before vmentry.
1879          */
1880         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1881         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1882         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1883         set_dr_intercepts(svm);
1884 }
1885
1886 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1887 {
1888         struct vcpu_svm *svm = to_svm(vcpu);
1889
1890         if (vcpu->arch.guest_state_protected)
1891                 return;
1892
1893         svm->vmcb->save.dr7 = value;
1894         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1895 }
1896
1897 static int pf_interception(struct vcpu_svm *svm)
1898 {
1899         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1900         u64 error_code = svm->vmcb->control.exit_info_1;
1901
1902         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1903                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1904                         svm->vmcb->control.insn_bytes : NULL,
1905                         svm->vmcb->control.insn_len);
1906 }
1907
1908 static int npf_interception(struct vcpu_svm *svm)
1909 {
1910         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1911         u64 error_code = svm->vmcb->control.exit_info_1;
1912
1913         trace_kvm_page_fault(fault_address, error_code);
1914         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1915                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1916                         svm->vmcb->control.insn_bytes : NULL,
1917                         svm->vmcb->control.insn_len);
1918 }
1919
1920 static int db_interception(struct vcpu_svm *svm)
1921 {
1922         struct kvm_run *kvm_run = svm->vcpu.run;
1923         struct kvm_vcpu *vcpu = &svm->vcpu;
1924
1925         if (!(svm->vcpu.guest_debug &
1926               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1927                 !svm->nmi_singlestep) {
1928                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1929                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1930                 return 1;
1931         }
1932
1933         if (svm->nmi_singlestep) {
1934                 disable_nmi_singlestep(svm);
1935                 /* Make sure we check for pending NMIs upon entry */
1936                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1937         }
1938
1939         if (svm->vcpu.guest_debug &
1940             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1941                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1942                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1943                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1944                 kvm_run->debug.arch.pc =
1945                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1946                 kvm_run->debug.arch.exception = DB_VECTOR;
1947                 return 0;
1948         }
1949
1950         return 1;
1951 }
1952
1953 static int bp_interception(struct vcpu_svm *svm)
1954 {
1955         struct kvm_run *kvm_run = svm->vcpu.run;
1956
1957         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1958         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1959         kvm_run->debug.arch.exception = BP_VECTOR;
1960         return 0;
1961 }
1962
1963 static int ud_interception(struct vcpu_svm *svm)
1964 {
1965         return handle_ud(&svm->vcpu);
1966 }
1967
1968 static int ac_interception(struct vcpu_svm *svm)
1969 {
1970         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1971         return 1;
1972 }
1973
1974 static bool is_erratum_383(void)
1975 {
1976         int err, i;
1977         u64 value;
1978
1979         if (!erratum_383_found)
1980                 return false;
1981
1982         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1983         if (err)
1984                 return false;
1985
1986         /* Bit 62 may or may not be set for this mce */
1987         value &= ~(1ULL << 62);
1988
1989         if (value != 0xb600000000010015ULL)
1990                 return false;
1991
1992         /* Clear MCi_STATUS registers */
1993         for (i = 0; i < 6; ++i)
1994                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1995
1996         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1997         if (!err) {
1998                 u32 low, high;
1999
2000                 value &= ~(1ULL << 2);
2001                 low    = lower_32_bits(value);
2002                 high   = upper_32_bits(value);
2003
2004                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2005         }
2006
2007         /* Flush tlb to evict multi-match entries */
2008         __flush_tlb_all();
2009
2010         return true;
2011 }
2012
2013 static void svm_handle_mce(struct vcpu_svm *svm)
2014 {
2015         if (is_erratum_383()) {
2016                 /*
2017                  * Erratum 383 triggered. Guest state is corrupt so kill the
2018                  * guest.
2019                  */
2020                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2021
2022                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2023
2024                 return;
2025         }
2026
2027         /*
2028          * On an #MC intercept the MCE handler is not called automatically in
2029          * the host. So do it by hand here.
2030          */
2031         kvm_machine_check();
2032 }
2033
2034 static int mc_interception(struct vcpu_svm *svm)
2035 {
2036         return 1;
2037 }
2038
2039 static int shutdown_interception(struct vcpu_svm *svm)
2040 {
2041         struct kvm_run *kvm_run = svm->vcpu.run;
2042
2043         /*
2044          * The VM save area has already been encrypted so it
2045          * cannot be reinitialized - just terminate.
2046          */
2047         if (sev_es_guest(svm->vcpu.kvm))
2048                 return -EINVAL;
2049
2050         /*
2051          * VMCB is undefined after a SHUTDOWN intercept
2052          * so reinitialize it.
2053          */
2054         clear_page(svm->vmcb);
2055         init_vmcb(svm);
2056
2057         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2058         return 0;
2059 }
2060
2061 static int io_interception(struct vcpu_svm *svm)
2062 {
2063         struct kvm_vcpu *vcpu = &svm->vcpu;
2064         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2065         int size, in, string;
2066         unsigned port;
2067
2068         ++svm->vcpu.stat.io_exits;
2069         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2070         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2071         port = io_info >> 16;
2072         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2073
2074         if (string) {
2075                 if (sev_es_guest(vcpu->kvm))
2076                         return sev_es_string_io(svm, size, port, in);
2077                 else
2078                         return kvm_emulate_instruction(vcpu, 0);
2079         }
2080
2081         svm->next_rip = svm->vmcb->control.exit_info_2;
2082
2083         return kvm_fast_pio(&svm->vcpu, size, port, in);
2084 }
2085
2086 static int nmi_interception(struct vcpu_svm *svm)
2087 {
2088         return 1;
2089 }
2090
2091 static int intr_interception(struct vcpu_svm *svm)
2092 {
2093         ++svm->vcpu.stat.irq_exits;
2094         return 1;
2095 }
2096
2097 static int nop_on_interception(struct vcpu_svm *svm)
2098 {
2099         return 1;
2100 }
2101
2102 static int halt_interception(struct vcpu_svm *svm)
2103 {
2104         return kvm_emulate_halt(&svm->vcpu);
2105 }
2106
2107 static int vmmcall_interception(struct vcpu_svm *svm)
2108 {
2109         return kvm_emulate_hypercall(&svm->vcpu);
2110 }
2111
2112 static int vmload_interception(struct vcpu_svm *svm)
2113 {
2114         struct vmcb *nested_vmcb;
2115         struct kvm_host_map map;
2116         int ret;
2117
2118         if (nested_svm_check_permissions(svm))
2119                 return 1;
2120
2121         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2122         if (ret) {
2123                 if (ret == -EINVAL)
2124                         kvm_inject_gp(&svm->vcpu, 0);
2125                 return 1;
2126         }
2127
2128         nested_vmcb = map.hva;
2129
2130         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2131
2132         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2133         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2134
2135         return ret;
2136 }
2137
2138 static int vmsave_interception(struct vcpu_svm *svm)
2139 {
2140         struct vmcb *nested_vmcb;
2141         struct kvm_host_map map;
2142         int ret;
2143
2144         if (nested_svm_check_permissions(svm))
2145                 return 1;
2146
2147         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2148         if (ret) {
2149                 if (ret == -EINVAL)
2150                         kvm_inject_gp(&svm->vcpu, 0);
2151                 return 1;
2152         }
2153
2154         nested_vmcb = map.hva;
2155
2156         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2157
2158         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2159         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2160
2161         return ret;
2162 }
2163
2164 static int vmrun_interception(struct vcpu_svm *svm)
2165 {
2166         if (nested_svm_check_permissions(svm))
2167                 return 1;
2168
2169         return nested_svm_vmrun(svm);
2170 }
2171
2172 enum {
2173         NONE_SVM_INSTR,
2174         SVM_INSTR_VMRUN,
2175         SVM_INSTR_VMLOAD,
2176         SVM_INSTR_VMSAVE,
2177 };
2178
2179 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2180 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2181 {
2182         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2183
2184         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2185                 return NONE_SVM_INSTR;
2186
2187         switch (ctxt->modrm) {
2188         case 0xd8: /* VMRUN */
2189                 return SVM_INSTR_VMRUN;
2190         case 0xda: /* VMLOAD */
2191                 return SVM_INSTR_VMLOAD;
2192         case 0xdb: /* VMSAVE */
2193                 return SVM_INSTR_VMSAVE;
2194         default:
2195                 break;
2196         }
2197
2198         return NONE_SVM_INSTR;
2199 }
2200
2201 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2202 {
2203         const int guest_mode_exit_codes[] = {
2204                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2205                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2206                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2207         };
2208         int (*const svm_instr_handlers[])(struct vcpu_svm *svm) = {
2209                 [SVM_INSTR_VMRUN] = vmrun_interception,
2210                 [SVM_INSTR_VMLOAD] = vmload_interception,
2211                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2212         };
2213         struct vcpu_svm *svm = to_svm(vcpu);
2214         int ret;
2215
2216         if (is_guest_mode(vcpu)) {
2217                 svm->vmcb->control.exit_code = guest_mode_exit_codes[opcode];
2218                 svm->vmcb->control.exit_info_1 = 0;
2219                 svm->vmcb->control.exit_info_2 = 0;
2220
2221                 /* Returns '1' or -errno on failure, '0' on success. */
2222                 ret = nested_svm_vmexit(svm);
2223                 if (ret)
2224                         return ret;
2225                 return 1;
2226         }
2227         return svm_instr_handlers[opcode](svm);
2228 }
2229
2230 /*
2231  * #GP handling code. Note that #GP can be triggered under the following two
2232  * cases:
2233  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2234  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2235  *      regions (e.g. SMM memory on host).
2236  *   2) VMware backdoor
2237  */
2238 static int gp_interception(struct vcpu_svm *svm)
2239 {
2240         struct kvm_vcpu *vcpu = &svm->vcpu;
2241         u32 error_code = svm->vmcb->control.exit_info_1;
2242         int opcode;
2243
2244         /* Both #GP cases have zero error_code */
2245         if (error_code)
2246                 goto reinject;
2247
2248         /* Decode the instruction for usage later */
2249         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2250                 goto reinject;
2251
2252         opcode = svm_instr_opcode(vcpu);
2253
2254         if (opcode == NONE_SVM_INSTR) {
2255                 if (!enable_vmware_backdoor)
2256                         goto reinject;
2257
2258                 /*
2259                  * VMware backdoor emulation on #GP interception only handles
2260                  * IN{S}, OUT{S}, and RDPMC.
2261                  */
2262                 if (!is_guest_mode(vcpu))
2263                         return kvm_emulate_instruction(vcpu,
2264                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2265         } else
2266                 return emulate_svm_instr(vcpu, opcode);
2267
2268 reinject:
2269         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2270         return 1;
2271 }
2272
2273 void svm_set_gif(struct vcpu_svm *svm, bool value)
2274 {
2275         if (value) {
2276                 /*
2277                  * If VGIF is enabled, the STGI intercept is only added to
2278                  * detect the opening of the SMI/NMI window; remove it now.
2279                  * Likewise, clear the VINTR intercept, we will set it
2280                  * again while processing KVM_REQ_EVENT if needed.
2281                  */
2282                 if (vgif_enabled(svm))
2283                         svm_clr_intercept(svm, INTERCEPT_STGI);
2284                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2285                         svm_clear_vintr(svm);
2286
2287                 enable_gif(svm);
2288                 if (svm->vcpu.arch.smi_pending ||
2289                     svm->vcpu.arch.nmi_pending ||
2290                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2291                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2292         } else {
2293                 disable_gif(svm);
2294
2295                 /*
2296                  * After a CLGI no interrupts should come.  But if vGIF is
2297                  * in use, we still rely on the VINTR intercept (rather than
2298                  * STGI) to detect an open interrupt window.
2299                 */
2300                 if (!vgif_enabled(svm))
2301                         svm_clear_vintr(svm);
2302         }
2303 }
2304
2305 static int stgi_interception(struct vcpu_svm *svm)
2306 {
2307         int ret;
2308
2309         if (nested_svm_check_permissions(svm))
2310                 return 1;
2311
2312         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2313         svm_set_gif(svm, true);
2314         return ret;
2315 }
2316
2317 static int clgi_interception(struct vcpu_svm *svm)
2318 {
2319         int ret;
2320
2321         if (nested_svm_check_permissions(svm))
2322                 return 1;
2323
2324         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2325         svm_set_gif(svm, false);
2326         return ret;
2327 }
2328
2329 static int invlpga_interception(struct vcpu_svm *svm)
2330 {
2331         struct kvm_vcpu *vcpu = &svm->vcpu;
2332
2333         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2334                           kvm_rax_read(&svm->vcpu));
2335
2336         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2337         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2338
2339         return kvm_skip_emulated_instruction(&svm->vcpu);
2340 }
2341
2342 static int skinit_interception(struct vcpu_svm *svm)
2343 {
2344         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2345
2346         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2347         return 1;
2348 }
2349
2350 static int wbinvd_interception(struct vcpu_svm *svm)
2351 {
2352         return kvm_emulate_wbinvd(&svm->vcpu);
2353 }
2354
2355 static int xsetbv_interception(struct vcpu_svm *svm)
2356 {
2357         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2358         u32 index = kvm_rcx_read(&svm->vcpu);
2359
2360         int err = kvm_set_xcr(&svm->vcpu, index, new_bv);
2361         return kvm_complete_insn_gp(&svm->vcpu, err);
2362 }
2363
2364 static int rdpru_interception(struct vcpu_svm *svm)
2365 {
2366         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2367         return 1;
2368 }
2369
2370 static int task_switch_interception(struct vcpu_svm *svm)
2371 {
2372         u16 tss_selector;
2373         int reason;
2374         int int_type = svm->vmcb->control.exit_int_info &
2375                 SVM_EXITINTINFO_TYPE_MASK;
2376         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2377         uint32_t type =
2378                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2379         uint32_t idt_v =
2380                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2381         bool has_error_code = false;
2382         u32 error_code = 0;
2383
2384         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2385
2386         if (svm->vmcb->control.exit_info_2 &
2387             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2388                 reason = TASK_SWITCH_IRET;
2389         else if (svm->vmcb->control.exit_info_2 &
2390                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2391                 reason = TASK_SWITCH_JMP;
2392         else if (idt_v)
2393                 reason = TASK_SWITCH_GATE;
2394         else
2395                 reason = TASK_SWITCH_CALL;
2396
2397         if (reason == TASK_SWITCH_GATE) {
2398                 switch (type) {
2399                 case SVM_EXITINTINFO_TYPE_NMI:
2400                         svm->vcpu.arch.nmi_injected = false;
2401                         break;
2402                 case SVM_EXITINTINFO_TYPE_EXEPT:
2403                         if (svm->vmcb->control.exit_info_2 &
2404                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2405                                 has_error_code = true;
2406                                 error_code =
2407                                         (u32)svm->vmcb->control.exit_info_2;
2408                         }
2409                         kvm_clear_exception_queue(&svm->vcpu);
2410                         break;
2411                 case SVM_EXITINTINFO_TYPE_INTR:
2412                         kvm_clear_interrupt_queue(&svm->vcpu);
2413                         break;
2414                 default:
2415                         break;
2416                 }
2417         }
2418
2419         if (reason != TASK_SWITCH_GATE ||
2420             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2421             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2422              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2423                 if (!skip_emulated_instruction(&svm->vcpu))
2424                         return 0;
2425         }
2426
2427         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2428                 int_vec = -1;
2429
2430         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2431                                has_error_code, error_code);
2432 }
2433
2434 static int cpuid_interception(struct vcpu_svm *svm)
2435 {
2436         return kvm_emulate_cpuid(&svm->vcpu);
2437 }
2438
2439 static int iret_interception(struct vcpu_svm *svm)
2440 {
2441         ++svm->vcpu.stat.nmi_window_exits;
2442         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2443         if (!sev_es_guest(svm->vcpu.kvm)) {
2444                 svm_clr_intercept(svm, INTERCEPT_IRET);
2445                 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2446         }
2447         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2448         return 1;
2449 }
2450
2451 static int invd_interception(struct vcpu_svm *svm)
2452 {
2453         /* Treat an INVD instruction as a NOP and just skip it. */
2454         return kvm_skip_emulated_instruction(&svm->vcpu);
2455 }
2456
2457 static int invlpg_interception(struct vcpu_svm *svm)
2458 {
2459         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2460                 return kvm_emulate_instruction(&svm->vcpu, 0);
2461
2462         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2463         return kvm_skip_emulated_instruction(&svm->vcpu);
2464 }
2465
2466 static int emulate_on_interception(struct vcpu_svm *svm)
2467 {
2468         return kvm_emulate_instruction(&svm->vcpu, 0);
2469 }
2470
2471 static int rsm_interception(struct vcpu_svm *svm)
2472 {
2473         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2474 }
2475
2476 static int rdpmc_interception(struct vcpu_svm *svm)
2477 {
2478         int err;
2479
2480         if (!nrips)
2481                 return emulate_on_interception(svm);
2482
2483         err = kvm_rdpmc(&svm->vcpu);
2484         return kvm_complete_insn_gp(&svm->vcpu, err);
2485 }
2486
2487 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2488                                             unsigned long val)
2489 {
2490         unsigned long cr0 = svm->vcpu.arch.cr0;
2491         bool ret = false;
2492
2493         if (!is_guest_mode(&svm->vcpu) ||
2494             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2495                 return false;
2496
2497         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2498         val &= ~SVM_CR0_SELECTIVE_MASK;
2499
2500         if (cr0 ^ val) {
2501                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2502                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2503         }
2504
2505         return ret;
2506 }
2507
2508 #define CR_VALID (1ULL << 63)
2509
2510 static int cr_interception(struct vcpu_svm *svm)
2511 {
2512         int reg, cr;
2513         unsigned long val;
2514         int err;
2515
2516         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2517                 return emulate_on_interception(svm);
2518
2519         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2520                 return emulate_on_interception(svm);
2521
2522         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2523         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2524                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2525         else
2526                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2527
2528         err = 0;
2529         if (cr >= 16) { /* mov to cr */
2530                 cr -= 16;
2531                 val = kvm_register_read(&svm->vcpu, reg);
2532                 trace_kvm_cr_write(cr, val);
2533                 switch (cr) {
2534                 case 0:
2535                         if (!check_selective_cr0_intercepted(svm, val))
2536                                 err = kvm_set_cr0(&svm->vcpu, val);
2537                         else
2538                                 return 1;
2539
2540                         break;
2541                 case 3:
2542                         err = kvm_set_cr3(&svm->vcpu, val);
2543                         break;
2544                 case 4:
2545                         err = kvm_set_cr4(&svm->vcpu, val);
2546                         break;
2547                 case 8:
2548                         err = kvm_set_cr8(&svm->vcpu, val);
2549                         break;
2550                 default:
2551                         WARN(1, "unhandled write to CR%d", cr);
2552                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2553                         return 1;
2554                 }
2555         } else { /* mov from cr */
2556                 switch (cr) {
2557                 case 0:
2558                         val = kvm_read_cr0(&svm->vcpu);
2559                         break;
2560                 case 2:
2561                         val = svm->vcpu.arch.cr2;
2562                         break;
2563                 case 3:
2564                         val = kvm_read_cr3(&svm->vcpu);
2565                         break;
2566                 case 4:
2567                         val = kvm_read_cr4(&svm->vcpu);
2568                         break;
2569                 case 8:
2570                         val = kvm_get_cr8(&svm->vcpu);
2571                         break;
2572                 default:
2573                         WARN(1, "unhandled read from CR%d", cr);
2574                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2575                         return 1;
2576                 }
2577                 kvm_register_write(&svm->vcpu, reg, val);
2578                 trace_kvm_cr_read(cr, val);
2579         }
2580         return kvm_complete_insn_gp(&svm->vcpu, err);
2581 }
2582
2583 static int cr_trap(struct vcpu_svm *svm)
2584 {
2585         struct kvm_vcpu *vcpu = &svm->vcpu;
2586         unsigned long old_value, new_value;
2587         unsigned int cr;
2588         int ret = 0;
2589
2590         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2591
2592         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2593         switch (cr) {
2594         case 0:
2595                 old_value = kvm_read_cr0(vcpu);
2596                 svm_set_cr0(vcpu, new_value);
2597
2598                 kvm_post_set_cr0(vcpu, old_value, new_value);
2599                 break;
2600         case 4:
2601                 old_value = kvm_read_cr4(vcpu);
2602                 svm_set_cr4(vcpu, new_value);
2603
2604                 kvm_post_set_cr4(vcpu, old_value, new_value);
2605                 break;
2606         case 8:
2607                 ret = kvm_set_cr8(&svm->vcpu, new_value);
2608                 break;
2609         default:
2610                 WARN(1, "unhandled CR%d write trap", cr);
2611                 kvm_queue_exception(vcpu, UD_VECTOR);
2612                 return 1;
2613         }
2614
2615         return kvm_complete_insn_gp(vcpu, ret);
2616 }
2617
2618 static int dr_interception(struct vcpu_svm *svm)
2619 {
2620         int reg, dr;
2621         unsigned long val;
2622         int err = 0;
2623
2624         if (svm->vcpu.guest_debug == 0) {
2625                 /*
2626                  * No more DR vmexits; force a reload of the debug registers
2627                  * and reenter on this instruction.  The next vmexit will
2628                  * retrieve the full state of the debug registers.
2629                  */
2630                 clr_dr_intercepts(svm);
2631                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2632                 return 1;
2633         }
2634
2635         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2636                 return emulate_on_interception(svm);
2637
2638         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2639         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2640         if (dr >= 16) { /* mov to DRn  */
2641                 dr -= 16;
2642                 val = kvm_register_read(&svm->vcpu, reg);
2643                 err = kvm_set_dr(&svm->vcpu, dr, val);
2644         } else {
2645                 kvm_get_dr(&svm->vcpu, dr, &val);
2646                 kvm_register_write(&svm->vcpu, reg, val);
2647         }
2648
2649         return kvm_complete_insn_gp(&svm->vcpu, err);
2650 }
2651
2652 static int cr8_write_interception(struct vcpu_svm *svm)
2653 {
2654         struct kvm_run *kvm_run = svm->vcpu.run;
2655         int r;
2656
2657         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2658         /* instruction emulation calls kvm_set_cr8() */
2659         r = cr_interception(svm);
2660         if (lapic_in_kernel(&svm->vcpu))
2661                 return r;
2662         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2663                 return r;
2664         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2665         return 0;
2666 }
2667
2668 static int efer_trap(struct vcpu_svm *svm)
2669 {
2670         struct msr_data msr_info;
2671         int ret;
2672
2673         /*
2674          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2675          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2676          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2677          * the guest doesn't have X86_FEATURE_SVM.
2678          */
2679         msr_info.host_initiated = false;
2680         msr_info.index = MSR_EFER;
2681         msr_info.data = svm->vmcb->control.exit_info_1 & ~EFER_SVME;
2682         ret = kvm_set_msr_common(&svm->vcpu, &msr_info);
2683
2684         return kvm_complete_insn_gp(&svm->vcpu, ret);
2685 }
2686
2687 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2688 {
2689         msr->data = 0;
2690
2691         switch (msr->index) {
2692         case MSR_F10H_DECFG:
2693                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2694                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2695                 break;
2696         case MSR_IA32_PERF_CAPABILITIES:
2697                 return 0;
2698         default:
2699                 return KVM_MSR_RET_INVALID;
2700         }
2701
2702         return 0;
2703 }
2704
2705 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2706 {
2707         struct vcpu_svm *svm = to_svm(vcpu);
2708
2709         switch (msr_info->index) {
2710         case MSR_STAR:
2711                 msr_info->data = svm->vmcb->save.star;
2712                 break;
2713 #ifdef CONFIG_X86_64
2714         case MSR_LSTAR:
2715                 msr_info->data = svm->vmcb->save.lstar;
2716                 break;
2717         case MSR_CSTAR:
2718                 msr_info->data = svm->vmcb->save.cstar;
2719                 break;
2720         case MSR_KERNEL_GS_BASE:
2721                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2722                 break;
2723         case MSR_SYSCALL_MASK:
2724                 msr_info->data = svm->vmcb->save.sfmask;
2725                 break;
2726 #endif
2727         case MSR_IA32_SYSENTER_CS:
2728                 msr_info->data = svm->vmcb->save.sysenter_cs;
2729                 break;
2730         case MSR_IA32_SYSENTER_EIP:
2731                 msr_info->data = svm->sysenter_eip;
2732                 break;
2733         case MSR_IA32_SYSENTER_ESP:
2734                 msr_info->data = svm->sysenter_esp;
2735                 break;
2736         case MSR_TSC_AUX:
2737                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2738                         return 1;
2739                 msr_info->data = svm->tsc_aux;
2740                 break;
2741         /*
2742          * Nobody will change the following 5 values in the VMCB so we can
2743          * safely return them on rdmsr. They will always be 0 until LBRV is
2744          * implemented.
2745          */
2746         case MSR_IA32_DEBUGCTLMSR:
2747                 msr_info->data = svm->vmcb->save.dbgctl;
2748                 break;
2749         case MSR_IA32_LASTBRANCHFROMIP:
2750                 msr_info->data = svm->vmcb->save.br_from;
2751                 break;
2752         case MSR_IA32_LASTBRANCHTOIP:
2753                 msr_info->data = svm->vmcb->save.br_to;
2754                 break;
2755         case MSR_IA32_LASTINTFROMIP:
2756                 msr_info->data = svm->vmcb->save.last_excp_from;
2757                 break;
2758         case MSR_IA32_LASTINTTOIP:
2759                 msr_info->data = svm->vmcb->save.last_excp_to;
2760                 break;
2761         case MSR_VM_HSAVE_PA:
2762                 msr_info->data = svm->nested.hsave_msr;
2763                 break;
2764         case MSR_VM_CR:
2765                 msr_info->data = svm->nested.vm_cr_msr;
2766                 break;
2767         case MSR_IA32_SPEC_CTRL:
2768                 if (!msr_info->host_initiated &&
2769                     !guest_has_spec_ctrl_msr(vcpu))
2770                         return 1;
2771
2772                 msr_info->data = svm->spec_ctrl;
2773                 break;
2774         case MSR_AMD64_VIRT_SPEC_CTRL:
2775                 if (!msr_info->host_initiated &&
2776                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2777                         return 1;
2778
2779                 msr_info->data = svm->virt_spec_ctrl;
2780                 break;
2781         case MSR_F15H_IC_CFG: {
2782
2783                 int family, model;
2784
2785                 family = guest_cpuid_family(vcpu);
2786                 model  = guest_cpuid_model(vcpu);
2787
2788                 if (family < 0 || model < 0)
2789                         return kvm_get_msr_common(vcpu, msr_info);
2790
2791                 msr_info->data = 0;
2792
2793                 if (family == 0x15 &&
2794                     (model >= 0x2 && model < 0x20))
2795                         msr_info->data = 0x1E;
2796                 }
2797                 break;
2798         case MSR_F10H_DECFG:
2799                 msr_info->data = svm->msr_decfg;
2800                 break;
2801         default:
2802                 return kvm_get_msr_common(vcpu, msr_info);
2803         }
2804         return 0;
2805 }
2806
2807 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2808 {
2809         struct vcpu_svm *svm = to_svm(vcpu);
2810         if (!sev_es_guest(svm->vcpu.kvm) || !err)
2811                 return kvm_complete_insn_gp(&svm->vcpu, err);
2812
2813         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2814         ghcb_set_sw_exit_info_2(svm->ghcb,
2815                                 X86_TRAP_GP |
2816                                 SVM_EVTINJ_TYPE_EXEPT |
2817                                 SVM_EVTINJ_VALID);
2818         return 1;
2819 }
2820
2821 static int rdmsr_interception(struct vcpu_svm *svm)
2822 {
2823         return kvm_emulate_rdmsr(&svm->vcpu);
2824 }
2825
2826 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2827 {
2828         struct vcpu_svm *svm = to_svm(vcpu);
2829         int svm_dis, chg_mask;
2830
2831         if (data & ~SVM_VM_CR_VALID_MASK)
2832                 return 1;
2833
2834         chg_mask = SVM_VM_CR_VALID_MASK;
2835
2836         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2837                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2838
2839         svm->nested.vm_cr_msr &= ~chg_mask;
2840         svm->nested.vm_cr_msr |= (data & chg_mask);
2841
2842         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2843
2844         /* check for svm_disable while efer.svme is set */
2845         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2846                 return 1;
2847
2848         return 0;
2849 }
2850
2851 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2852 {
2853         struct vcpu_svm *svm = to_svm(vcpu);
2854
2855         u32 ecx = msr->index;
2856         u64 data = msr->data;
2857         switch (ecx) {
2858         case MSR_IA32_CR_PAT:
2859                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2860                         return 1;
2861                 vcpu->arch.pat = data;
2862                 svm->vmcb->save.g_pat = data;
2863                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2864                 break;
2865         case MSR_IA32_SPEC_CTRL:
2866                 if (!msr->host_initiated &&
2867                     !guest_has_spec_ctrl_msr(vcpu))
2868                         return 1;
2869
2870                 if (kvm_spec_ctrl_test_value(data))
2871                         return 1;
2872
2873                 svm->spec_ctrl = data;
2874                 if (!data)
2875                         break;
2876
2877                 /*
2878                  * For non-nested:
2879                  * When it's written (to non-zero) for the first time, pass
2880                  * it through.
2881                  *
2882                  * For nested:
2883                  * The handling of the MSR bitmap for L2 guests is done in
2884                  * nested_svm_vmrun_msrpm.
2885                  * We update the L1 MSR bit as well since it will end up
2886                  * touching the MSR anyway now.
2887                  */
2888                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2889                 break;
2890         case MSR_IA32_PRED_CMD:
2891                 if (!msr->host_initiated &&
2892                     !guest_has_pred_cmd_msr(vcpu))
2893                         return 1;
2894
2895                 if (data & ~PRED_CMD_IBPB)
2896                         return 1;
2897                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2898                         return 1;
2899                 if (!data)
2900                         break;
2901
2902                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2903                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2904                 break;
2905         case MSR_AMD64_VIRT_SPEC_CTRL:
2906                 if (!msr->host_initiated &&
2907                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2908                         return 1;
2909
2910                 if (data & ~SPEC_CTRL_SSBD)
2911                         return 1;
2912
2913                 svm->virt_spec_ctrl = data;
2914                 break;
2915         case MSR_STAR:
2916                 svm->vmcb->save.star = data;
2917                 break;
2918 #ifdef CONFIG_X86_64
2919         case MSR_LSTAR:
2920                 svm->vmcb->save.lstar = data;
2921                 break;
2922         case MSR_CSTAR:
2923                 svm->vmcb->save.cstar = data;
2924                 break;
2925         case MSR_KERNEL_GS_BASE:
2926                 svm->vmcb->save.kernel_gs_base = data;
2927                 break;
2928         case MSR_SYSCALL_MASK:
2929                 svm->vmcb->save.sfmask = data;
2930                 break;
2931 #endif
2932         case MSR_IA32_SYSENTER_CS:
2933                 svm->vmcb->save.sysenter_cs = data;
2934                 break;
2935         case MSR_IA32_SYSENTER_EIP:
2936                 svm->sysenter_eip = data;
2937                 svm->vmcb->save.sysenter_eip = data;
2938                 break;
2939         case MSR_IA32_SYSENTER_ESP:
2940                 svm->sysenter_esp = data;
2941                 svm->vmcb->save.sysenter_esp = data;
2942                 break;
2943         case MSR_TSC_AUX:
2944                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2945                         return 1;
2946
2947                 /*
2948                  * This is rare, so we update the MSR here instead of using
2949                  * direct_access_msrs.  Doing that would require a rdmsr in
2950                  * svm_vcpu_put.
2951                  */
2952                 svm->tsc_aux = data;
2953                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2954                 break;
2955         case MSR_IA32_DEBUGCTLMSR:
2956                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2957                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2958                                     __func__, data);
2959                         break;
2960                 }
2961                 if (data & DEBUGCTL_RESERVED_BITS)
2962                         return 1;
2963
2964                 svm->vmcb->save.dbgctl = data;
2965                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2966                 if (data & (1ULL<<0))
2967                         svm_enable_lbrv(vcpu);
2968                 else
2969                         svm_disable_lbrv(vcpu);
2970                 break;
2971         case MSR_VM_HSAVE_PA:
2972                 svm->nested.hsave_msr = data;
2973                 break;
2974         case MSR_VM_CR:
2975                 return svm_set_vm_cr(vcpu, data);
2976         case MSR_VM_IGNNE:
2977                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2978                 break;
2979         case MSR_F10H_DECFG: {
2980                 struct kvm_msr_entry msr_entry;
2981
2982                 msr_entry.index = msr->index;
2983                 if (svm_get_msr_feature(&msr_entry))
2984                         return 1;
2985
2986                 /* Check the supported bits */
2987                 if (data & ~msr_entry.data)
2988                         return 1;
2989
2990                 /* Don't allow the guest to change a bit, #GP */
2991                 if (!msr->host_initiated && (data ^ msr_entry.data))
2992                         return 1;
2993
2994                 svm->msr_decfg = data;
2995                 break;
2996         }
2997         case MSR_IA32_APICBASE:
2998                 if (kvm_vcpu_apicv_active(vcpu))
2999                         avic_update_vapic_bar(to_svm(vcpu), data);
3000                 fallthrough;
3001         default:
3002                 return kvm_set_msr_common(vcpu, msr);
3003         }
3004         return 0;
3005 }
3006
3007 static int wrmsr_interception(struct vcpu_svm *svm)
3008 {
3009         return kvm_emulate_wrmsr(&svm->vcpu);
3010 }
3011
3012 static int msr_interception(struct vcpu_svm *svm)
3013 {
3014         if (svm->vmcb->control.exit_info_1)
3015                 return wrmsr_interception(svm);
3016         else
3017                 return rdmsr_interception(svm);
3018 }
3019
3020 static int interrupt_window_interception(struct vcpu_svm *svm)
3021 {
3022         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3023         svm_clear_vintr(svm);
3024
3025         /*
3026          * For AVIC, the only reason to end up here is ExtINTs.
3027          * In this case AVIC was temporarily disabled for
3028          * requesting the IRQ window and we have to re-enable it.
3029          */
3030         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
3031
3032         ++svm->vcpu.stat.irq_window_exits;
3033         return 1;
3034 }
3035
3036 static int pause_interception(struct vcpu_svm *svm)
3037 {
3038         struct kvm_vcpu *vcpu = &svm->vcpu;
3039         bool in_kernel;
3040
3041         /*
3042          * CPL is not made available for an SEV-ES guest, therefore
3043          * vcpu->arch.preempted_in_kernel can never be true.  Just
3044          * set in_kernel to false as well.
3045          */
3046         in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
3047
3048         if (!kvm_pause_in_guest(vcpu->kvm))
3049                 grow_ple_window(vcpu);
3050
3051         kvm_vcpu_on_spin(vcpu, in_kernel);
3052         return 1;
3053 }
3054
3055 static int nop_interception(struct vcpu_svm *svm)
3056 {
3057         return kvm_skip_emulated_instruction(&(svm->vcpu));
3058 }
3059
3060 static int monitor_interception(struct vcpu_svm *svm)
3061 {
3062         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3063         return nop_interception(svm);
3064 }
3065
3066 static int mwait_interception(struct vcpu_svm *svm)
3067 {
3068         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3069         return nop_interception(svm);
3070 }
3071
3072 static int invpcid_interception(struct vcpu_svm *svm)
3073 {
3074         struct kvm_vcpu *vcpu = &svm->vcpu;
3075         unsigned long type;
3076         gva_t gva;
3077
3078         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3079                 kvm_queue_exception(vcpu, UD_VECTOR);
3080                 return 1;
3081         }
3082
3083         /*
3084          * For an INVPCID intercept:
3085          * EXITINFO1 provides the linear address of the memory operand.
3086          * EXITINFO2 provides the contents of the register operand.
3087          */
3088         type = svm->vmcb->control.exit_info_2;
3089         gva = svm->vmcb->control.exit_info_1;
3090
3091         if (type > 3) {
3092                 kvm_inject_gp(vcpu, 0);
3093                 return 1;
3094         }
3095
3096         return kvm_handle_invpcid(vcpu, type, gva);
3097 }
3098
3099 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3100         [SVM_EXIT_READ_CR0]                     = cr_interception,
3101         [SVM_EXIT_READ_CR3]                     = cr_interception,
3102         [SVM_EXIT_READ_CR4]                     = cr_interception,
3103         [SVM_EXIT_READ_CR8]                     = cr_interception,
3104         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3105         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3106         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3107         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3108         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3109         [SVM_EXIT_READ_DR0]                     = dr_interception,
3110         [SVM_EXIT_READ_DR1]                     = dr_interception,
3111         [SVM_EXIT_READ_DR2]                     = dr_interception,
3112         [SVM_EXIT_READ_DR3]                     = dr_interception,
3113         [SVM_EXIT_READ_DR4]                     = dr_interception,
3114         [SVM_EXIT_READ_DR5]                     = dr_interception,
3115         [SVM_EXIT_READ_DR6]                     = dr_interception,
3116         [SVM_EXIT_READ_DR7]                     = dr_interception,
3117         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3118         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3119         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3120         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3121         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3122         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3123         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3124         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3125         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3126         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3127         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3128         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3129         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3130         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3131         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3132         [SVM_EXIT_INTR]                         = intr_interception,
3133         [SVM_EXIT_NMI]                          = nmi_interception,
3134         [SVM_EXIT_SMI]                          = nop_on_interception,
3135         [SVM_EXIT_INIT]                         = nop_on_interception,
3136         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3137         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3138         [SVM_EXIT_CPUID]                        = cpuid_interception,
3139         [SVM_EXIT_IRET]                         = iret_interception,
3140         [SVM_EXIT_INVD]                         = invd_interception,
3141         [SVM_EXIT_PAUSE]                        = pause_interception,
3142         [SVM_EXIT_HLT]                          = halt_interception,
3143         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3144         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3145         [SVM_EXIT_IOIO]                         = io_interception,
3146         [SVM_EXIT_MSR]                          = msr_interception,
3147         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3148         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3149         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3150         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3151         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3152         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3153         [SVM_EXIT_STGI]                         = stgi_interception,
3154         [SVM_EXIT_CLGI]                         = clgi_interception,
3155         [SVM_EXIT_SKINIT]                       = skinit_interception,
3156         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3157         [SVM_EXIT_MONITOR]                      = monitor_interception,
3158         [SVM_EXIT_MWAIT]                        = mwait_interception,
3159         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3160         [SVM_EXIT_RDPRU]                        = rdpru_interception,
3161         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3162         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3163         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3164         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3165         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3166         [SVM_EXIT_NPF]                          = npf_interception,
3167         [SVM_EXIT_RSM]                          = rsm_interception,
3168         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3169         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3170         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3171 };
3172
3173 static void dump_vmcb(struct kvm_vcpu *vcpu)
3174 {
3175         struct vcpu_svm *svm = to_svm(vcpu);
3176         struct vmcb_control_area *control = &svm->vmcb->control;
3177         struct vmcb_save_area *save = &svm->vmcb->save;
3178
3179         if (!dump_invalid_vmcb) {
3180                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3181                 return;
3182         }
3183
3184         pr_err("VMCB Control Area:\n");
3185         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3186         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3187         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3188         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3189         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3190         pr_err("%-20s%08x %08x\n", "intercepts:",
3191               control->intercepts[INTERCEPT_WORD3],
3192                control->intercepts[INTERCEPT_WORD4]);
3193         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3194         pr_err("%-20s%d\n", "pause filter threshold:",
3195                control->pause_filter_thresh);
3196         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3197         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3198         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3199         pr_err("%-20s%d\n", "asid:", control->asid);
3200         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3201         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3202         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3203         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3204         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3205         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3206         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3207         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3208         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3209         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3210         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3211         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3212         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3213         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3214         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3215         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3216         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3217         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3218         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3219         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3220         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3221         pr_err("VMCB State Save Area:\n");
3222         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3223                "es:",
3224                save->es.selector, save->es.attrib,
3225                save->es.limit, save->es.base);
3226         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3227                "cs:",
3228                save->cs.selector, save->cs.attrib,
3229                save->cs.limit, save->cs.base);
3230         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3231                "ss:",
3232                save->ss.selector, save->ss.attrib,
3233                save->ss.limit, save->ss.base);
3234         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3235                "ds:",
3236                save->ds.selector, save->ds.attrib,
3237                save->ds.limit, save->ds.base);
3238         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3239                "fs:",
3240                save->fs.selector, save->fs.attrib,
3241                save->fs.limit, save->fs.base);
3242         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3243                "gs:",
3244                save->gs.selector, save->gs.attrib,
3245                save->gs.limit, save->gs.base);
3246         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3247                "gdtr:",
3248                save->gdtr.selector, save->gdtr.attrib,
3249                save->gdtr.limit, save->gdtr.base);
3250         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3251                "ldtr:",
3252                save->ldtr.selector, save->ldtr.attrib,
3253                save->ldtr.limit, save->ldtr.base);
3254         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3255                "idtr:",
3256                save->idtr.selector, save->idtr.attrib,
3257                save->idtr.limit, save->idtr.base);
3258         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3259                "tr:",
3260                save->tr.selector, save->tr.attrib,
3261                save->tr.limit, save->tr.base);
3262         pr_err("cpl:            %d                efer:         %016llx\n",
3263                 save->cpl, save->efer);
3264         pr_err("%-15s %016llx %-13s %016llx\n",
3265                "cr0:", save->cr0, "cr2:", save->cr2);
3266         pr_err("%-15s %016llx %-13s %016llx\n",
3267                "cr3:", save->cr3, "cr4:", save->cr4);
3268         pr_err("%-15s %016llx %-13s %016llx\n",
3269                "dr6:", save->dr6, "dr7:", save->dr7);
3270         pr_err("%-15s %016llx %-13s %016llx\n",
3271                "rip:", save->rip, "rflags:", save->rflags);
3272         pr_err("%-15s %016llx %-13s %016llx\n",
3273                "rsp:", save->rsp, "rax:", save->rax);
3274         pr_err("%-15s %016llx %-13s %016llx\n",
3275                "star:", save->star, "lstar:", save->lstar);
3276         pr_err("%-15s %016llx %-13s %016llx\n",
3277                "cstar:", save->cstar, "sfmask:", save->sfmask);
3278         pr_err("%-15s %016llx %-13s %016llx\n",
3279                "kernel_gs_base:", save->kernel_gs_base,
3280                "sysenter_cs:", save->sysenter_cs);
3281         pr_err("%-15s %016llx %-13s %016llx\n",
3282                "sysenter_esp:", save->sysenter_esp,
3283                "sysenter_eip:", save->sysenter_eip);
3284         pr_err("%-15s %016llx %-13s %016llx\n",
3285                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3286         pr_err("%-15s %016llx %-13s %016llx\n",
3287                "br_from:", save->br_from, "br_to:", save->br_to);
3288         pr_err("%-15s %016llx %-13s %016llx\n",
3289                "excp_from:", save->last_excp_from,
3290                "excp_to:", save->last_excp_to);
3291 }
3292
3293 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3294 {
3295         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3296             svm_exit_handlers[exit_code])
3297                 return 0;
3298
3299         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3300         dump_vmcb(vcpu);
3301         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3302         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3303         vcpu->run->internal.ndata = 2;
3304         vcpu->run->internal.data[0] = exit_code;
3305         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3306
3307         return -EINVAL;
3308 }
3309
3310 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code)
3311 {
3312         if (svm_handle_invalid_exit(&svm->vcpu, exit_code))
3313                 return 0;
3314
3315 #ifdef CONFIG_RETPOLINE
3316         if (exit_code == SVM_EXIT_MSR)
3317                 return msr_interception(svm);
3318         else if (exit_code == SVM_EXIT_VINTR)
3319                 return interrupt_window_interception(svm);
3320         else if (exit_code == SVM_EXIT_INTR)
3321                 return intr_interception(svm);
3322         else if (exit_code == SVM_EXIT_HLT)
3323                 return halt_interception(svm);
3324         else if (exit_code == SVM_EXIT_NPF)
3325                 return npf_interception(svm);
3326 #endif
3327         return svm_exit_handlers[exit_code](svm);
3328 }
3329
3330 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3331                               u32 *intr_info, u32 *error_code)
3332 {
3333         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3334
3335         *info1 = control->exit_info_1;
3336         *info2 = control->exit_info_2;
3337         *intr_info = control->exit_int_info;
3338         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3339             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3340                 *error_code = control->exit_int_info_err;
3341         else
3342                 *error_code = 0;
3343 }
3344
3345 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3346 {
3347         struct vcpu_svm *svm = to_svm(vcpu);
3348         struct kvm_run *kvm_run = vcpu->run;
3349         u32 exit_code = svm->vmcb->control.exit_code;
3350
3351         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3352
3353         /* SEV-ES guests must use the CR write traps to track CR registers. */
3354         if (!sev_es_guest(vcpu->kvm)) {
3355                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3356                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3357                 if (npt_enabled)
3358                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3359         }
3360
3361         if (is_guest_mode(vcpu)) {
3362                 int vmexit;
3363
3364                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3365
3366                 vmexit = nested_svm_exit_special(svm);
3367
3368                 if (vmexit == NESTED_EXIT_CONTINUE)
3369                         vmexit = nested_svm_exit_handled(svm);
3370
3371                 if (vmexit == NESTED_EXIT_DONE)
3372                         return 1;
3373         }
3374
3375         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3376                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3377                 kvm_run->fail_entry.hardware_entry_failure_reason
3378                         = svm->vmcb->control.exit_code;
3379                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3380                 dump_vmcb(vcpu);
3381                 return 0;
3382         }
3383
3384         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3385             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3386             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3387             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3388                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3389                        "exit_code 0x%x\n",
3390                        __func__, svm->vmcb->control.exit_int_info,
3391                        exit_code);
3392
3393         if (exit_fastpath != EXIT_FASTPATH_NONE)
3394                 return 1;
3395
3396         return svm_invoke_exit_handler(svm, exit_code);
3397 }
3398
3399 static void reload_tss(struct kvm_vcpu *vcpu)
3400 {
3401         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3402
3403         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3404         load_TR_desc();
3405 }
3406
3407 static void pre_svm_run(struct vcpu_svm *svm)
3408 {
3409         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3410
3411         if (sev_guest(svm->vcpu.kvm))
3412                 return pre_sev_run(svm, svm->vcpu.cpu);
3413
3414         /* FIXME: handle wraparound of asid_generation */
3415         if (svm->asid_generation != sd->asid_generation)
3416                 new_asid(svm, sd);
3417 }
3418
3419 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3420 {
3421         struct vcpu_svm *svm = to_svm(vcpu);
3422
3423         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3424         vcpu->arch.hflags |= HF_NMI_MASK;
3425         if (!sev_es_guest(svm->vcpu.kvm))
3426                 svm_set_intercept(svm, INTERCEPT_IRET);
3427         ++vcpu->stat.nmi_injections;
3428 }
3429
3430 static void svm_set_irq(struct kvm_vcpu *vcpu)
3431 {
3432         struct vcpu_svm *svm = to_svm(vcpu);
3433
3434         BUG_ON(!(gif_set(svm)));
3435
3436         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3437         ++vcpu->stat.irq_injections;
3438
3439         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3440                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3441 }
3442
3443 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3444 {
3445         struct vcpu_svm *svm = to_svm(vcpu);
3446
3447         /*
3448          * SEV-ES guests must always keep the CR intercepts cleared. CR
3449          * tracking is done using the CR write traps.
3450          */
3451         if (sev_es_guest(vcpu->kvm))
3452                 return;
3453
3454         if (nested_svm_virtualize_tpr(vcpu))
3455                 return;
3456
3457         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3458
3459         if (irr == -1)
3460                 return;
3461
3462         if (tpr >= irr)
3463                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3464 }
3465
3466 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3467 {
3468         struct vcpu_svm *svm = to_svm(vcpu);
3469         struct vmcb *vmcb = svm->vmcb;
3470         bool ret;
3471
3472         if (!gif_set(svm))
3473                 return true;
3474
3475         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3476                 return false;
3477
3478         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3479               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3480
3481         return ret;
3482 }
3483
3484 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3485 {
3486         struct vcpu_svm *svm = to_svm(vcpu);
3487         if (svm->nested.nested_run_pending)
3488                 return -EBUSY;
3489
3490         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3491         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3492                 return -EBUSY;
3493
3494         return !svm_nmi_blocked(vcpu);
3495 }
3496
3497 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3498 {
3499         struct vcpu_svm *svm = to_svm(vcpu);
3500
3501         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3502 }
3503
3504 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3505 {
3506         struct vcpu_svm *svm = to_svm(vcpu);
3507
3508         if (masked) {
3509                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3510                 if (!sev_es_guest(svm->vcpu.kvm))
3511                         svm_set_intercept(svm, INTERCEPT_IRET);
3512         } else {
3513                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3514                 if (!sev_es_guest(svm->vcpu.kvm))
3515                         svm_clr_intercept(svm, INTERCEPT_IRET);
3516         }
3517 }
3518
3519 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3520 {
3521         struct vcpu_svm *svm = to_svm(vcpu);
3522         struct vmcb *vmcb = svm->vmcb;
3523
3524         if (!gif_set(svm))
3525                 return true;
3526
3527         if (sev_es_guest(svm->vcpu.kvm)) {
3528                 /*
3529                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3530                  * bit to determine the state of the IF flag.
3531                  */
3532                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3533                         return true;
3534         } else if (is_guest_mode(vcpu)) {
3535                 /* As long as interrupts are being delivered...  */
3536                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3537                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3538                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3539                         return true;
3540
3541                 /* ... vmexits aren't blocked by the interrupt shadow  */
3542                 if (nested_exit_on_intr(svm))
3543                         return false;
3544         } else {
3545                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3546                         return true;
3547         }
3548
3549         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3550 }
3551
3552 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3553 {
3554         struct vcpu_svm *svm = to_svm(vcpu);
3555         if (svm->nested.nested_run_pending)
3556                 return -EBUSY;
3557
3558         /*
3559          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3560          * e.g. if the IRQ arrived asynchronously after checking nested events.
3561          */
3562         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3563                 return -EBUSY;
3564
3565         return !svm_interrupt_blocked(vcpu);
3566 }
3567
3568 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3569 {
3570         struct vcpu_svm *svm = to_svm(vcpu);
3571
3572         /*
3573          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3574          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3575          * get that intercept, this function will be called again though and
3576          * we'll get the vintr intercept. However, if the vGIF feature is
3577          * enabled, the STGI interception will not occur. Enable the irq
3578          * window under the assumption that the hardware will set the GIF.
3579          */
3580         if (vgif_enabled(svm) || gif_set(svm)) {
3581                 /*
3582                  * IRQ window is not needed when AVIC is enabled,
3583                  * unless we have pending ExtINT since it cannot be injected
3584                  * via AVIC. In such case, we need to temporarily disable AVIC,
3585                  * and fallback to injecting IRQ via V_IRQ.
3586                  */
3587                 svm_toggle_avic_for_irq_window(vcpu, false);
3588                 svm_set_vintr(svm);
3589         }
3590 }
3591
3592 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3593 {
3594         struct vcpu_svm *svm = to_svm(vcpu);
3595
3596         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3597             == HF_NMI_MASK)
3598                 return; /* IRET will cause a vm exit */
3599
3600         if (!gif_set(svm)) {
3601                 if (vgif_enabled(svm))
3602                         svm_set_intercept(svm, INTERCEPT_STGI);
3603                 return; /* STGI will cause a vm exit */
3604         }
3605
3606         /*
3607          * Something prevents NMI from been injected. Single step over possible
3608          * problem (IRET or exception injection or interrupt shadow)
3609          */
3610         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3611         svm->nmi_singlestep = true;
3612         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3613 }
3614
3615 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3616 {
3617         return 0;
3618 }
3619
3620 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3621 {
3622         return 0;
3623 }
3624
3625 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3626 {
3627         struct vcpu_svm *svm = to_svm(vcpu);
3628
3629         /*
3630          * Flush only the current ASID even if the TLB flush was invoked via
3631          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3632          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3633          * unconditionally does a TLB flush on both nested VM-Enter and nested
3634          * VM-Exit (via kvm_mmu_reset_context()).
3635          */
3636         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3637                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3638         else
3639                 svm->asid_generation--;
3640 }
3641
3642 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3643 {
3644         struct vcpu_svm *svm = to_svm(vcpu);
3645
3646         invlpga(gva, svm->vmcb->control.asid);
3647 }
3648
3649 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3650 {
3651         struct vcpu_svm *svm = to_svm(vcpu);
3652
3653         if (nested_svm_virtualize_tpr(vcpu))
3654                 return;
3655
3656         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3657                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3658                 kvm_set_cr8(vcpu, cr8);
3659         }
3660 }
3661
3662 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3663 {
3664         struct vcpu_svm *svm = to_svm(vcpu);
3665         u64 cr8;
3666
3667         if (nested_svm_virtualize_tpr(vcpu) ||
3668             kvm_vcpu_apicv_active(vcpu))
3669                 return;
3670
3671         cr8 = kvm_get_cr8(vcpu);
3672         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3673         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3674 }
3675
3676 static void svm_complete_interrupts(struct vcpu_svm *svm)
3677 {
3678         u8 vector;
3679         int type;
3680         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3681         unsigned int3_injected = svm->int3_injected;
3682
3683         svm->int3_injected = 0;
3684
3685         /*
3686          * If we've made progress since setting HF_IRET_MASK, we've
3687          * executed an IRET and can allow NMI injection.
3688          */
3689         if ((svm->vcpu.arch.hflags & HF_IRET_MASK) &&
3690             (sev_es_guest(svm->vcpu.kvm) ||
3691              kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip)) {
3692                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3693                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3694         }
3695
3696         svm->vcpu.arch.nmi_injected = false;
3697         kvm_clear_exception_queue(&svm->vcpu);
3698         kvm_clear_interrupt_queue(&svm->vcpu);
3699
3700         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3701                 return;
3702
3703         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3704
3705         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3706         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3707
3708         switch (type) {
3709         case SVM_EXITINTINFO_TYPE_NMI:
3710                 svm->vcpu.arch.nmi_injected = true;
3711                 break;
3712         case SVM_EXITINTINFO_TYPE_EXEPT:
3713                 /*
3714                  * Never re-inject a #VC exception.
3715                  */
3716                 if (vector == X86_TRAP_VC)
3717                         break;
3718
3719                 /*
3720                  * In case of software exceptions, do not reinject the vector,
3721                  * but re-execute the instruction instead. Rewind RIP first
3722                  * if we emulated INT3 before.
3723                  */
3724                 if (kvm_exception_is_soft(vector)) {
3725                         if (vector == BP_VECTOR && int3_injected &&
3726                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3727                                 kvm_rip_write(&svm->vcpu,
3728                                               kvm_rip_read(&svm->vcpu) -
3729                                               int3_injected);
3730                         break;
3731                 }
3732                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3733                         u32 err = svm->vmcb->control.exit_int_info_err;
3734                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3735
3736                 } else
3737                         kvm_requeue_exception(&svm->vcpu, vector);
3738                 break;
3739         case SVM_EXITINTINFO_TYPE_INTR:
3740                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3741                 break;
3742         default:
3743                 break;
3744         }
3745 }
3746
3747 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3748 {
3749         struct vcpu_svm *svm = to_svm(vcpu);
3750         struct vmcb_control_area *control = &svm->vmcb->control;
3751
3752         control->exit_int_info = control->event_inj;
3753         control->exit_int_info_err = control->event_inj_err;
3754         control->event_inj = 0;
3755         svm_complete_interrupts(svm);
3756 }
3757
3758 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3759 {
3760         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3761             to_svm(vcpu)->vmcb->control.exit_info_1)
3762                 return handle_fastpath_set_msr_irqoff(vcpu);
3763
3764         return EXIT_FASTPATH_NONE;
3765 }
3766
3767 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3768                                         struct vcpu_svm *svm)
3769 {
3770         /*
3771          * VMENTER enables interrupts (host state), but the kernel state is
3772          * interrupts disabled when this is invoked. Also tell RCU about
3773          * it. This is the same logic as for exit_to_user_mode().
3774          *
3775          * This ensures that e.g. latency analysis on the host observes
3776          * guest mode as interrupt enabled.
3777          *
3778          * guest_enter_irqoff() informs context tracking about the
3779          * transition to guest mode and if enabled adjusts RCU state
3780          * accordingly.
3781          */
3782         instrumentation_begin();
3783         trace_hardirqs_on_prepare();
3784         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3785         instrumentation_end();
3786
3787         guest_enter_irqoff();
3788         lockdep_hardirqs_on(CALLER_ADDR0);
3789
3790         if (sev_es_guest(svm->vcpu.kvm)) {
3791                 __svm_sev_es_vcpu_run(svm->vmcb_pa);
3792         } else {
3793                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3794
3795                 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3796
3797                 vmload(__sme_page_pa(sd->save_area));
3798         }
3799
3800         /*
3801          * VMEXIT disables interrupts (host state), but tracing and lockdep
3802          * have them in state 'on' as recorded before entering guest mode.
3803          * Same as enter_from_user_mode().
3804          *
3805          * guest_exit_irqoff() restores host context and reinstates RCU if
3806          * enabled and required.
3807          *
3808          * This needs to be done before the below as native_read_msr()
3809          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3810          * into world and some more.
3811          */
3812         lockdep_hardirqs_off(CALLER_ADDR0);
3813         guest_exit_irqoff();
3814
3815         instrumentation_begin();
3816         trace_hardirqs_off_finish();
3817         instrumentation_end();
3818 }
3819
3820 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3821 {
3822         struct vcpu_svm *svm = to_svm(vcpu);
3823
3824         trace_kvm_entry(vcpu);
3825
3826         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3827         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3828         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3829
3830         /*
3831          * Disable singlestep if we're injecting an interrupt/exception.
3832          * We don't want our modified rflags to be pushed on the stack where
3833          * we might not be able to easily reset them if we disabled NMI
3834          * singlestep later.
3835          */
3836         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3837                 /*
3838                  * Event injection happens before external interrupts cause a
3839                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3840                  * is enough to force an immediate vmexit.
3841                  */
3842                 disable_nmi_singlestep(svm);
3843                 smp_send_reschedule(vcpu->cpu);
3844         }
3845
3846         pre_svm_run(svm);
3847
3848         sync_lapic_to_cr8(vcpu);
3849
3850         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3851                 svm->vmcb->control.asid = svm->asid;
3852                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3853         }
3854         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3855
3856         /*
3857          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3858          * of a #DB.
3859          */
3860         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3861                 svm_set_dr6(svm, vcpu->arch.dr6);
3862         else
3863                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3864
3865         clgi();
3866         kvm_load_guest_xsave_state(vcpu);
3867
3868         kvm_wait_lapic_expire(vcpu);
3869
3870         /*
3871          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3872          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3873          * is no need to worry about the conditional branch over the wrmsr
3874          * being speculatively taken.
3875          */
3876         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3877
3878         svm_vcpu_enter_exit(vcpu, svm);
3879
3880         /*
3881          * We do not use IBRS in the kernel. If this vCPU has used the
3882          * SPEC_CTRL MSR it may have left it on; save the value and
3883          * turn it off. This is much more efficient than blindly adding
3884          * it to the atomic save/restore list. Especially as the former
3885          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3886          *
3887          * For non-nested case:
3888          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3889          * save it.
3890          *
3891          * For nested case:
3892          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3893          * save it.
3894          */
3895         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3896                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3897
3898         if (!sev_es_guest(svm->vcpu.kvm))
3899                 reload_tss(vcpu);
3900
3901         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3902
3903         if (!sev_es_guest(svm->vcpu.kvm)) {
3904                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3905                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3906                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3907                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3908         }
3909
3910         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3911                 kvm_before_interrupt(&svm->vcpu);
3912
3913         kvm_load_host_xsave_state(vcpu);
3914         stgi();
3915
3916         /* Any pending NMI will happen here */
3917
3918         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3919                 kvm_after_interrupt(&svm->vcpu);
3920
3921         sync_cr8_to_lapic(vcpu);
3922
3923         svm->next_rip = 0;
3924         if (is_guest_mode(&svm->vcpu)) {
3925                 sync_nested_vmcb_control(svm);
3926                 svm->nested.nested_run_pending = 0;
3927         }
3928
3929         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3930         vmcb_mark_all_clean(svm->vmcb);
3931
3932         /* if exit due to PF check for async PF */
3933         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3934                 svm->vcpu.arch.apf.host_apf_flags =
3935                         kvm_read_and_reset_apf_flags();
3936
3937         if (npt_enabled) {
3938                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3939                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3940         }
3941
3942         /*
3943          * We need to handle MC intercepts here before the vcpu has a chance to
3944          * change the physical cpu
3945          */
3946         if (unlikely(svm->vmcb->control.exit_code ==
3947                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3948                 svm_handle_mce(svm);
3949
3950         svm_complete_interrupts(svm);
3951
3952         if (is_guest_mode(vcpu))
3953                 return EXIT_FASTPATH_NONE;
3954
3955         return svm_exit_handlers_fastpath(vcpu);
3956 }
3957
3958 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3959                              int root_level)
3960 {
3961         struct vcpu_svm *svm = to_svm(vcpu);
3962         unsigned long cr3;
3963
3964         cr3 = __sme_set(root);
3965         if (npt_enabled) {
3966                 svm->vmcb->control.nested_cr3 = cr3;
3967                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3968
3969                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3970                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3971                         return;
3972                 cr3 = vcpu->arch.cr3;
3973         }
3974
3975         svm->vmcb->save.cr3 = cr3;
3976         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3977 }
3978
3979 static int is_disabled(void)
3980 {
3981         u64 vm_cr;
3982
3983         rdmsrl(MSR_VM_CR, vm_cr);
3984         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3985                 return 1;
3986
3987         return 0;
3988 }
3989
3990 static void
3991 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3992 {
3993         /*
3994          * Patch in the VMMCALL instruction:
3995          */
3996         hypercall[0] = 0x0f;
3997         hypercall[1] = 0x01;
3998         hypercall[2] = 0xd9;
3999 }
4000
4001 static int __init svm_check_processor_compat(void)
4002 {
4003         return 0;
4004 }
4005
4006 static bool svm_cpu_has_accelerated_tpr(void)
4007 {
4008         return false;
4009 }
4010
4011 /*
4012  * The kvm parameter can be NULL (module initialization, or invocation before
4013  * VM creation). Be sure to check the kvm parameter before using it.
4014  */
4015 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4016 {
4017         switch (index) {
4018         case MSR_IA32_MCG_EXT_CTL:
4019         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4020                 return false;
4021         case MSR_IA32_SMBASE:
4022                 /* SEV-ES guests do not support SMM, so report false */
4023                 if (kvm && sev_es_guest(kvm))
4024                         return false;
4025                 break;
4026         default:
4027                 break;
4028         }
4029
4030         return true;
4031 }
4032
4033 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4034 {
4035         return 0;
4036 }
4037
4038 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4039 {
4040         struct vcpu_svm *svm = to_svm(vcpu);
4041         struct kvm_cpuid_entry2 *best;
4042
4043         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4044                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
4045                                     boot_cpu_has(X86_FEATURE_XSAVES);
4046
4047         /* Update nrips enabled cache */
4048         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4049                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
4050
4051         /* Check again if INVPCID interception if required */
4052         svm_check_invpcid(svm);
4053
4054         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
4055         if (sev_guest(vcpu->kvm)) {
4056                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4057                 if (best)
4058                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4059         }
4060
4061         if (!kvm_vcpu_apicv_active(vcpu))
4062                 return;
4063
4064         /*
4065          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4066          * is exposed to the guest, disable AVIC.
4067          */
4068         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4069                 kvm_request_apicv_update(vcpu->kvm, false,
4070                                          APICV_INHIBIT_REASON_X2APIC);
4071
4072         /*
4073          * Currently, AVIC does not work with nested virtualization.
4074          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4075          */
4076         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4077                 kvm_request_apicv_update(vcpu->kvm, false,
4078                                          APICV_INHIBIT_REASON_NESTED);
4079 }
4080
4081 static bool svm_has_wbinvd_exit(void)
4082 {
4083         return true;
4084 }
4085
4086 #define PRE_EX(exit)  { .exit_code = (exit), \
4087                         .stage = X86_ICPT_PRE_EXCEPT, }
4088 #define POST_EX(exit) { .exit_code = (exit), \
4089                         .stage = X86_ICPT_POST_EXCEPT, }
4090 #define POST_MEM(exit) { .exit_code = (exit), \
4091                         .stage = X86_ICPT_POST_MEMACCESS, }
4092
4093 static const struct __x86_intercept {
4094         u32 exit_code;
4095         enum x86_intercept_stage stage;
4096 } x86_intercept_map[] = {
4097         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4098         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4099         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4100         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4101         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4102         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4103         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4104         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4105         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4106         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4107         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4108         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4109         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4110         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4111         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4112         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4113         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4114         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4115         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4116         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4117         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4118         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4119         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4120         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4121         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4122         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4123         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4124         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4125         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4126         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4127         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4128         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4129         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4130         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4131         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4132         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4133         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4134         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4135         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4136         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4137         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4138         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4139         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4140         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4141         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4142         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4143         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4144 };
4145
4146 #undef PRE_EX
4147 #undef POST_EX
4148 #undef POST_MEM
4149
4150 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4151                                struct x86_instruction_info *info,
4152                                enum x86_intercept_stage stage,
4153                                struct x86_exception *exception)
4154 {
4155         struct vcpu_svm *svm = to_svm(vcpu);
4156         int vmexit, ret = X86EMUL_CONTINUE;
4157         struct __x86_intercept icpt_info;
4158         struct vmcb *vmcb = svm->vmcb;
4159
4160         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4161                 goto out;
4162
4163         icpt_info = x86_intercept_map[info->intercept];
4164
4165         if (stage != icpt_info.stage)
4166                 goto out;
4167
4168         switch (icpt_info.exit_code) {
4169         case SVM_EXIT_READ_CR0:
4170                 if (info->intercept == x86_intercept_cr_read)
4171                         icpt_info.exit_code += info->modrm_reg;
4172                 break;
4173         case SVM_EXIT_WRITE_CR0: {
4174                 unsigned long cr0, val;
4175
4176                 if (info->intercept == x86_intercept_cr_write)
4177                         icpt_info.exit_code += info->modrm_reg;
4178
4179                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4180                     info->intercept == x86_intercept_clts)
4181                         break;
4182
4183                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4184                                         INTERCEPT_SELECTIVE_CR0)))
4185                         break;
4186
4187                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4188                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4189
4190                 if (info->intercept == x86_intercept_lmsw) {
4191                         cr0 &= 0xfUL;
4192                         val &= 0xfUL;
4193                         /* lmsw can't clear PE - catch this here */
4194                         if (cr0 & X86_CR0_PE)
4195                                 val |= X86_CR0_PE;
4196                 }
4197
4198                 if (cr0 ^ val)
4199                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4200
4201                 break;
4202         }
4203         case SVM_EXIT_READ_DR0:
4204         case SVM_EXIT_WRITE_DR0:
4205                 icpt_info.exit_code += info->modrm_reg;
4206                 break;
4207         case SVM_EXIT_MSR:
4208                 if (info->intercept == x86_intercept_wrmsr)
4209                         vmcb->control.exit_info_1 = 1;
4210                 else
4211                         vmcb->control.exit_info_1 = 0;
4212                 break;
4213         case SVM_EXIT_PAUSE:
4214                 /*
4215                  * We get this for NOP only, but pause
4216                  * is rep not, check this here
4217                  */
4218                 if (info->rep_prefix != REPE_PREFIX)
4219                         goto out;
4220                 break;
4221         case SVM_EXIT_IOIO: {
4222                 u64 exit_info;
4223                 u32 bytes;
4224
4225                 if (info->intercept == x86_intercept_in ||
4226                     info->intercept == x86_intercept_ins) {
4227                         exit_info = ((info->src_val & 0xffff) << 16) |
4228                                 SVM_IOIO_TYPE_MASK;
4229                         bytes = info->dst_bytes;
4230                 } else {
4231                         exit_info = (info->dst_val & 0xffff) << 16;
4232                         bytes = info->src_bytes;
4233                 }
4234
4235                 if (info->intercept == x86_intercept_outs ||
4236                     info->intercept == x86_intercept_ins)
4237                         exit_info |= SVM_IOIO_STR_MASK;
4238
4239                 if (info->rep_prefix)
4240                         exit_info |= SVM_IOIO_REP_MASK;
4241
4242                 bytes = min(bytes, 4u);
4243
4244                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4245
4246                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4247
4248                 vmcb->control.exit_info_1 = exit_info;
4249                 vmcb->control.exit_info_2 = info->next_rip;
4250
4251                 break;
4252         }
4253         default:
4254                 break;
4255         }
4256
4257         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4258         if (static_cpu_has(X86_FEATURE_NRIPS))
4259                 vmcb->control.next_rip  = info->next_rip;
4260         vmcb->control.exit_code = icpt_info.exit_code;
4261         vmexit = nested_svm_exit_handled(svm);
4262
4263         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4264                                            : X86EMUL_CONTINUE;
4265
4266 out:
4267         return ret;
4268 }
4269
4270 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4271 {
4272 }
4273
4274 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4275 {
4276         if (!kvm_pause_in_guest(vcpu->kvm))
4277                 shrink_ple_window(vcpu);
4278 }
4279
4280 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4281 {
4282         /* [63:9] are reserved. */
4283         vcpu->arch.mcg_cap &= 0x1ff;
4284 }
4285
4286 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4287 {
4288         struct vcpu_svm *svm = to_svm(vcpu);
4289
4290         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4291         if (!gif_set(svm))
4292                 return true;
4293
4294         return is_smm(vcpu);
4295 }
4296
4297 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4298 {
4299         struct vcpu_svm *svm = to_svm(vcpu);
4300         if (svm->nested.nested_run_pending)
4301                 return -EBUSY;
4302
4303         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4304         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4305                 return -EBUSY;
4306
4307         return !svm_smi_blocked(vcpu);
4308 }
4309
4310 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4311 {
4312         struct vcpu_svm *svm = to_svm(vcpu);
4313         int ret;
4314
4315         if (is_guest_mode(vcpu)) {
4316                 /* FED8h - SVM Guest */
4317                 put_smstate(u64, smstate, 0x7ed8, 1);
4318                 /* FEE0h - SVM Guest VMCB Physical Address */
4319                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4320
4321                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4322                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4323                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4324
4325                 ret = nested_svm_vmexit(svm);
4326                 if (ret)
4327                         return ret;
4328         }
4329         return 0;
4330 }
4331
4332 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4333 {
4334         struct vcpu_svm *svm = to_svm(vcpu);
4335         struct kvm_host_map map;
4336         int ret = 0;
4337
4338         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4339                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4340                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4341                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4342
4343                 if (guest) {
4344                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4345                                 return 1;
4346
4347                         if (!(saved_efer & EFER_SVME))
4348                                 return 1;
4349
4350                         if (kvm_vcpu_map(&svm->vcpu,
4351                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4352                                 return 1;
4353
4354                         if (svm_allocate_nested(svm))
4355                                 return 1;
4356
4357                         ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4358                         kvm_vcpu_unmap(&svm->vcpu, &map, true);
4359                 }
4360         }
4361
4362         return ret;
4363 }
4364
4365 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4366 {
4367         struct vcpu_svm *svm = to_svm(vcpu);
4368
4369         if (!gif_set(svm)) {
4370                 if (vgif_enabled(svm))
4371                         svm_set_intercept(svm, INTERCEPT_STGI);
4372                 /* STGI will cause a vm exit */
4373         } else {
4374                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4375         }
4376 }
4377
4378 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4379 {
4380         bool smep, smap, is_user;
4381         unsigned long cr4;
4382
4383         /*
4384          * When the guest is an SEV-ES guest, emulation is not possible.
4385          */
4386         if (sev_es_guest(vcpu->kvm))
4387                 return false;
4388
4389         /*
4390          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4391          *
4392          * Errata:
4393          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4394          * possible that CPU microcode implementing DecodeAssist will fail
4395          * to read bytes of instruction which caused #NPF. In this case,
4396          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4397          * return 0 instead of the correct guest instruction bytes.
4398          *
4399          * This happens because CPU microcode reading instruction bytes
4400          * uses a special opcode which attempts to read data using CPL=0
4401          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4402          * fault, it gives up and returns no instruction bytes.
4403          *
4404          * Detection:
4405          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4406          * returned 0 in GuestIntrBytes field of the VMCB.
4407          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4408          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4409          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4410          * a SMEP fault instead of #NPF).
4411          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4412          * As most guests enable SMAP if they have also enabled SMEP, use above
4413          * logic in order to attempt minimize false-positive of detecting errata
4414          * while still preserving all cases semantic correctness.
4415          *
4416          * Workaround:
4417          * To determine what instruction the guest was executing, the hypervisor
4418          * will have to decode the instruction at the instruction pointer.
4419          *
4420          * In non SEV guest, hypervisor will be able to read the guest
4421          * memory to decode the instruction pointer when insn_len is zero
4422          * so we return true to indicate that decoding is possible.
4423          *
4424          * But in the SEV guest, the guest memory is encrypted with the
4425          * guest specific key and hypervisor will not be able to decode the
4426          * instruction pointer so we will not able to workaround it. Lets
4427          * print the error and request to kill the guest.
4428          */
4429         if (likely(!insn || insn_len))
4430                 return true;
4431
4432         /*
4433          * If RIP is invalid, go ahead with emulation which will cause an
4434          * internal error exit.
4435          */
4436         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4437                 return true;
4438
4439         cr4 = kvm_read_cr4(vcpu);
4440         smep = cr4 & X86_CR4_SMEP;
4441         smap = cr4 & X86_CR4_SMAP;
4442         is_user = svm_get_cpl(vcpu) == 3;
4443         if (smap && (!smep || is_user)) {
4444                 if (!sev_guest(vcpu->kvm))
4445                         return true;
4446
4447                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4448                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4449         }
4450
4451         return false;
4452 }
4453
4454 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4455 {
4456         struct vcpu_svm *svm = to_svm(vcpu);
4457
4458         /*
4459          * TODO: Last condition latch INIT signals on vCPU when
4460          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4461          * To properly emulate the INIT intercept,
4462          * svm_check_nested_events() should call nested_svm_vmexit()
4463          * if an INIT signal is pending.
4464          */
4465         return !gif_set(svm) ||
4466                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4467 }
4468
4469 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4470 {
4471         if (!sev_es_guest(vcpu->kvm))
4472                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4473
4474         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4475 }
4476
4477 static void svm_vm_destroy(struct kvm *kvm)
4478 {
4479         avic_vm_destroy(kvm);
4480         sev_vm_destroy(kvm);
4481 }
4482
4483 static int svm_vm_init(struct kvm *kvm)
4484 {
4485         if (!pause_filter_count || !pause_filter_thresh)
4486                 kvm->arch.pause_in_guest = true;
4487
4488         if (avic) {
4489                 int ret = avic_vm_init(kvm);
4490                 if (ret)
4491                         return ret;
4492         }
4493
4494         kvm_apicv_init(kvm, avic);
4495         return 0;
4496 }
4497
4498 static struct kvm_x86_ops svm_x86_ops __initdata = {
4499         .hardware_unsetup = svm_hardware_teardown,
4500         .hardware_enable = svm_hardware_enable,
4501         .hardware_disable = svm_hardware_disable,
4502         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4503         .has_emulated_msr = svm_has_emulated_msr,
4504
4505         .vcpu_create = svm_create_vcpu,
4506         .vcpu_free = svm_free_vcpu,
4507         .vcpu_reset = svm_vcpu_reset,
4508
4509         .vm_size = sizeof(struct kvm_svm),
4510         .vm_init = svm_vm_init,
4511         .vm_destroy = svm_vm_destroy,
4512
4513         .prepare_guest_switch = svm_prepare_guest_switch,
4514         .vcpu_load = svm_vcpu_load,
4515         .vcpu_put = svm_vcpu_put,
4516         .vcpu_blocking = svm_vcpu_blocking,
4517         .vcpu_unblocking = svm_vcpu_unblocking,
4518
4519         .update_exception_bitmap = svm_update_exception_bitmap,
4520         .get_msr_feature = svm_get_msr_feature,
4521         .get_msr = svm_get_msr,
4522         .set_msr = svm_set_msr,
4523         .get_segment_base = svm_get_segment_base,
4524         .get_segment = svm_get_segment,
4525         .set_segment = svm_set_segment,
4526         .get_cpl = svm_get_cpl,
4527         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4528         .set_cr0 = svm_set_cr0,
4529         .is_valid_cr4 = svm_is_valid_cr4,
4530         .set_cr4 = svm_set_cr4,
4531         .set_efer = svm_set_efer,
4532         .get_idt = svm_get_idt,
4533         .set_idt = svm_set_idt,
4534         .get_gdt = svm_get_gdt,
4535         .set_gdt = svm_set_gdt,
4536         .set_dr7 = svm_set_dr7,
4537         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4538         .cache_reg = svm_cache_reg,
4539         .get_rflags = svm_get_rflags,
4540         .set_rflags = svm_set_rflags,
4541
4542         .tlb_flush_all = svm_flush_tlb,
4543         .tlb_flush_current = svm_flush_tlb,
4544         .tlb_flush_gva = svm_flush_tlb_gva,
4545         .tlb_flush_guest = svm_flush_tlb,
4546
4547         .run = svm_vcpu_run,
4548         .handle_exit = handle_exit,
4549         .skip_emulated_instruction = skip_emulated_instruction,
4550         .update_emulated_instruction = NULL,
4551         .set_interrupt_shadow = svm_set_interrupt_shadow,
4552         .get_interrupt_shadow = svm_get_interrupt_shadow,
4553         .patch_hypercall = svm_patch_hypercall,
4554         .set_irq = svm_set_irq,
4555         .set_nmi = svm_inject_nmi,
4556         .queue_exception = svm_queue_exception,
4557         .cancel_injection = svm_cancel_injection,
4558         .interrupt_allowed = svm_interrupt_allowed,
4559         .nmi_allowed = svm_nmi_allowed,
4560         .get_nmi_mask = svm_get_nmi_mask,
4561         .set_nmi_mask = svm_set_nmi_mask,
4562         .enable_nmi_window = svm_enable_nmi_window,
4563         .enable_irq_window = svm_enable_irq_window,
4564         .update_cr8_intercept = svm_update_cr8_intercept,
4565         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4566         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4567         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4568         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4569         .load_eoi_exitmap = svm_load_eoi_exitmap,
4570         .hwapic_irr_update = svm_hwapic_irr_update,
4571         .hwapic_isr_update = svm_hwapic_isr_update,
4572         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4573         .apicv_post_state_restore = avic_post_state_restore,
4574
4575         .set_tss_addr = svm_set_tss_addr,
4576         .set_identity_map_addr = svm_set_identity_map_addr,
4577         .get_mt_mask = svm_get_mt_mask,
4578
4579         .get_exit_info = svm_get_exit_info,
4580
4581         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4582
4583         .has_wbinvd_exit = svm_has_wbinvd_exit,
4584
4585         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4586
4587         .load_mmu_pgd = svm_load_mmu_pgd,
4588
4589         .check_intercept = svm_check_intercept,
4590         .handle_exit_irqoff = svm_handle_exit_irqoff,
4591
4592         .request_immediate_exit = __kvm_request_immediate_exit,
4593
4594         .sched_in = svm_sched_in,
4595
4596         .pmu_ops = &amd_pmu_ops,
4597         .nested_ops = &svm_nested_ops,
4598
4599         .deliver_posted_interrupt = svm_deliver_avic_intr,
4600         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4601         .update_pi_irte = svm_update_pi_irte,
4602         .setup_mce = svm_setup_mce,
4603
4604         .smi_allowed = svm_smi_allowed,
4605         .pre_enter_smm = svm_pre_enter_smm,
4606         .pre_leave_smm = svm_pre_leave_smm,
4607         .enable_smi_window = svm_enable_smi_window,
4608
4609         .mem_enc_op = svm_mem_enc_op,
4610         .mem_enc_reg_region = svm_register_enc_region,
4611         .mem_enc_unreg_region = svm_unregister_enc_region,
4612
4613         .can_emulate_instruction = svm_can_emulate_instruction,
4614
4615         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4616
4617         .msr_filter_changed = svm_msr_filter_changed,
4618         .complete_emulated_msr = svm_complete_emulated_msr,
4619
4620         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4621 };
4622
4623 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4624         .cpu_has_kvm_support = has_svm,
4625         .disabled_by_bios = is_disabled,
4626         .hardware_setup = svm_hardware_setup,
4627         .check_processor_compatibility = svm_check_processor_compat,
4628
4629         .runtime_ops = &svm_x86_ops,
4630 };
4631
4632 static int __init svm_init(void)
4633 {
4634         __unused_size_checks();
4635
4636         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4637                         __alignof__(struct vcpu_svm), THIS_MODULE);
4638 }
4639
4640 static void __exit svm_exit(void)
4641 {
4642         kvm_exit();
4643 }
4644
4645 module_init(svm_init)
4646 module_exit(svm_exit)