1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/numa.h>
57 #include <linux/pgtable.h>
58 #include <linux/overflow.h>
64 #include <asm/realmode.h>
67 #include <asm/tlbflush.h>
69 #include <asm/mwait.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
83 #include <asm/stackprotector.h>
85 #ifdef CONFIG_ACPI_CPPC_LIB
86 #include <acpi/cppc_acpi.h>
89 /* representing HT siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
93 /* representing HT and core siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
95 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
97 /* representing HT, core, and die siblings of each logical CPU */
98 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
99 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
103 /* Per CPU bogomips and other parameters */
104 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
105 EXPORT_PER_CPU_SYMBOL(cpu_info);
107 /* Logical package management. We might want to allocate that dynamically */
108 unsigned int __max_logical_packages __read_mostly;
109 EXPORT_SYMBOL(__max_logical_packages);
110 static unsigned int logical_packages __read_mostly;
111 static unsigned int logical_die __read_mostly;
113 /* Maximum number of SMT threads on any online core */
114 int __read_mostly __max_smt_threads = 1;
116 /* Flag to indicate if a complete sched domain rebuild is required */
117 bool x86_topology_update;
119 int arch_update_cpu_topology(void)
121 int retval = x86_topology_update;
123 x86_topology_update = false;
127 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
131 spin_lock_irqsave(&rtc_lock, flags);
132 CMOS_WRITE(0xa, 0xf);
133 spin_unlock_irqrestore(&rtc_lock, flags);
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
136 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
140 static inline void smpboot_restore_warm_reset_vector(void)
145 * Paranoid: Set warm reset code and vector here back
148 spin_lock_irqsave(&rtc_lock, flags);
150 spin_unlock_irqrestore(&rtc_lock, flags);
152 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
155 static void init_freq_invariance(bool secondary, bool cppc_ready);
158 * Report back to the Boot Processor during boot time or to the caller processor
161 static void smp_callin(void)
166 * If waken up by an INIT in an 82489DX configuration
167 * cpu_callout_mask guarantees we don't get here before
168 * an INIT_deassert IPI reaches our local APIC, so it is
169 * now safe to touch our local APIC.
171 cpuid = smp_processor_id();
174 * the boot CPU has finished the init stage and is spinning
175 * on callin_map until we finish. We are free to set up this
176 * CPU, first the APIC. (this is probably redundant on most
182 * Save our processor parameters. Note: this information
183 * is needed for clock calibration.
185 smp_store_cpu_info(cpuid);
188 * The topology information must be up to date before
189 * calibrate_delay() and notify_cpu_starting().
191 set_cpu_sibling_map(raw_smp_processor_id());
193 init_freq_invariance(true, false);
197 * Update loops_per_jiffy in cpu_data. Previous call to
198 * smp_store_cpu_info() stored a value that is close but not as
199 * accurate as the value just calculated.
202 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
203 pr_debug("Stack at about %p\n", &cpuid);
207 notify_cpu_starting(cpuid);
210 * Allow the master to continue.
212 cpumask_set_cpu(cpuid, cpu_callin_mask);
215 static int cpu0_logical_apicid;
216 static int enable_start_cpu0;
218 * Activate a secondary processor.
220 static void notrace start_secondary(void *unused)
223 * Don't put *anything* except direct CPU state initialization
224 * before cpu_init(), SMP booting is too fragile that we want to
225 * limit the things done here to the most necessary things.
230 /* switch away from the initial page table */
231 load_cr3(swapper_pg_dir);
234 cpu_init_exception_handling();
236 rcu_cpu_starting(raw_smp_processor_id());
237 x86_cpuinit.early_percpu_clock_init();
241 enable_start_cpu0 = 0;
243 /* otherwise gcc will move up smp_processor_id before the cpu_init */
246 * Check TSC synchronization with the boot CPU:
248 check_tsc_sync_target();
250 speculative_store_bypass_ht_init();
253 * Lock vector_lock, set CPU online and bring the vector
254 * allocator online. Online must be set with vector_lock held
255 * to prevent a concurrent irq setup/teardown from seeing a
256 * half valid vector space.
259 set_cpu_online(smp_processor_id(), true);
261 unlock_vector_lock();
262 cpu_set_state_online(smp_processor_id());
263 x86_platform.nmi_init();
265 /* enable local interrupts */
268 x86_cpuinit.setup_percpu_clockev();
271 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
275 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
278 bool topology_is_primary_thread(unsigned int cpu)
280 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
284 * topology_smt_supported - Check whether SMT is supported by the CPUs
286 bool topology_smt_supported(void)
288 return smp_num_siblings > 1;
292 * topology_phys_to_logical_pkg - Map a physical package id to a logical
294 * Returns logical package id or -1 if not found
296 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
300 for_each_possible_cpu(cpu) {
301 struct cpuinfo_x86 *c = &cpu_data(cpu);
303 if (c->initialized && c->phys_proc_id == phys_pkg)
304 return c->logical_proc_id;
308 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
310 * topology_phys_to_logical_die - Map a physical die id to logical
312 * Returns logical die id or -1 if not found
314 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
317 int proc_id = cpu_data(cur_cpu).phys_proc_id;
319 for_each_possible_cpu(cpu) {
320 struct cpuinfo_x86 *c = &cpu_data(cpu);
322 if (c->initialized && c->cpu_die_id == die_id &&
323 c->phys_proc_id == proc_id)
324 return c->logical_die_id;
328 EXPORT_SYMBOL(topology_phys_to_logical_die);
331 * topology_update_package_map - Update the physical to logical package map
332 * @pkg: The physical package id as retrieved via CPUID
333 * @cpu: The cpu for which this is updated
335 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
339 /* Already available somewhere? */
340 new = topology_phys_to_logical_pkg(pkg);
344 new = logical_packages++;
346 pr_info("CPU %u Converting physical %u to logical package %u\n",
350 cpu_data(cpu).logical_proc_id = new;
354 * topology_update_die_map - Update the physical to logical die map
355 * @die: The die id as retrieved via CPUID
356 * @cpu: The cpu for which this is updated
358 int topology_update_die_map(unsigned int die, unsigned int cpu)
362 /* Already available somewhere? */
363 new = topology_phys_to_logical_die(die, cpu);
369 pr_info("CPU %u Converting physical %u to logical die %u\n",
373 cpu_data(cpu).logical_die_id = new;
377 void __init smp_store_boot_cpu_info(void)
379 int id = 0; /* CPU 0 */
380 struct cpuinfo_x86 *c = &cpu_data(id);
384 topology_update_package_map(c->phys_proc_id, id);
385 topology_update_die_map(c->cpu_die_id, id);
386 c->initialized = true;
390 * The bootstrap kernel entry code has set these up. Save them for
393 void smp_store_cpu_info(int id)
395 struct cpuinfo_x86 *c = &cpu_data(id);
397 /* Copy boot_cpu_data only on the first bringup */
402 * During boot time, CPU0 has this setup already. Save the info when
403 * bringing up AP or offlined CPU0.
405 identify_secondary_cpu(c);
406 c->initialized = true;
410 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
412 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
414 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
418 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
420 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
422 return !WARN_ONCE(!topology_same_node(c, o),
423 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
424 "[node: %d != %d]. Ignoring dependency.\n",
425 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
428 #define link_mask(mfunc, c1, c2) \
430 cpumask_set_cpu((c1), mfunc(c2)); \
431 cpumask_set_cpu((c2), mfunc(c1)); \
434 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
436 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
437 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
439 if (c->phys_proc_id == o->phys_proc_id &&
440 c->cpu_die_id == o->cpu_die_id &&
441 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
442 if (c->cpu_core_id == o->cpu_core_id)
443 return topology_sane(c, o, "smt");
445 if ((c->cu_id != 0xff) &&
446 (o->cu_id != 0xff) &&
447 (c->cu_id == o->cu_id))
448 return topology_sane(c, o, "smt");
451 } else if (c->phys_proc_id == o->phys_proc_id &&
452 c->cpu_die_id == o->cpu_die_id &&
453 c->cpu_core_id == o->cpu_core_id) {
454 return topology_sane(c, o, "smt");
461 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
463 * These are Intel CPUs that enumerate an LLC that is shared by
464 * multiple NUMA nodes. The LLC on these systems is shared for
465 * off-package data access but private to the NUMA node (half
466 * of the package) for on-package access.
468 * CPUID (the source of the information about the LLC) can only
469 * enumerate the cache as being shared *or* unshared, but not
470 * this particular configuration. The CPU in this case enumerates
471 * the cache to be shared across the entire package (spanning both
475 static const struct x86_cpu_id snc_cpu[] = {
476 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL),
480 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
482 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
484 /* Do not match if we do not have a valid APICID for cpu: */
485 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
488 /* Do not match if LLC id does not match: */
489 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
493 * Allow the SNC topology without warning. Return of false
494 * means 'c' does not share the LLC of 'o'. This will be
495 * reflected to userspace.
497 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
500 return topology_sane(c, o, "llc");
504 * Unlike the other levels, we do not enforce keeping a
505 * multicore group inside a NUMA node. If this happens, we will
506 * discard the MC level of the topology later.
508 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
510 if (c->phys_proc_id == o->phys_proc_id)
515 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
517 if ((c->phys_proc_id == o->phys_proc_id) &&
518 (c->cpu_die_id == o->cpu_die_id))
524 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
525 static inline int x86_sched_itmt_flags(void)
527 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
530 #ifdef CONFIG_SCHED_MC
531 static int x86_core_flags(void)
533 return cpu_core_flags() | x86_sched_itmt_flags();
536 #ifdef CONFIG_SCHED_SMT
537 static int x86_smt_flags(void)
539 return cpu_smt_flags() | x86_sched_itmt_flags();
544 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
545 #ifdef CONFIG_SCHED_SMT
546 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
548 #ifdef CONFIG_SCHED_MC
549 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
554 static struct sched_domain_topology_level x86_topology[] = {
555 #ifdef CONFIG_SCHED_SMT
556 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
558 #ifdef CONFIG_SCHED_MC
559 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
561 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
566 * Set if a package/die has multiple NUMA nodes inside.
567 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
568 * Sub-NUMA Clustering have this.
570 static bool x86_has_numa_in_package;
572 void set_cpu_sibling_map(int cpu)
574 bool has_smt = smp_num_siblings > 1;
575 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
576 struct cpuinfo_x86 *c = &cpu_data(cpu);
577 struct cpuinfo_x86 *o;
580 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
583 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
584 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
585 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
586 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
591 for_each_cpu(i, cpu_sibling_setup_mask) {
594 if ((i == cpu) || (has_smt && match_smt(c, o)))
595 link_mask(topology_sibling_cpumask, cpu, i);
597 if ((i == cpu) || (has_mp && match_llc(c, o)))
598 link_mask(cpu_llc_shared_mask, cpu, i);
603 * This needs a separate iteration over the cpus because we rely on all
604 * topology_sibling_cpumask links to be set-up.
606 for_each_cpu(i, cpu_sibling_setup_mask) {
609 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
610 link_mask(topology_core_cpumask, cpu, i);
613 * Does this new cpu bringup a new core?
616 topology_sibling_cpumask(cpu)) == 1) {
618 * for each core in package, increment
619 * the booted_cores for this new cpu
622 topology_sibling_cpumask(i)) == i)
625 * increment the core count for all
626 * the other cpus in this package
629 cpu_data(i).booted_cores++;
630 } else if (i != cpu && !c->booted_cores)
631 c->booted_cores = cpu_data(i).booted_cores;
633 if (match_pkg(c, o) && !topology_same_node(c, o))
634 x86_has_numa_in_package = true;
636 if ((i == cpu) || (has_mp && match_die(c, o)))
637 link_mask(topology_die_cpumask, cpu, i);
640 threads = cpumask_weight(topology_sibling_cpumask(cpu));
641 if (threads > __max_smt_threads)
642 __max_smt_threads = threads;
645 /* maps the cpu to the sched domain representing multi-core */
646 const struct cpumask *cpu_coregroup_mask(int cpu)
648 return cpu_llc_shared_mask(cpu);
651 static void impress_friends(void)
654 unsigned long bogosum = 0;
656 * Allow the user to impress friends.
658 pr_debug("Before bogomips\n");
659 for_each_possible_cpu(cpu)
660 if (cpumask_test_cpu(cpu, cpu_callout_mask))
661 bogosum += cpu_data(cpu).loops_per_jiffy;
662 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
665 (bogosum/(5000/HZ))%100);
667 pr_debug("Before bogocount - setting activated=1\n");
670 void __inquire_remote_apic(int apicid)
672 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
673 const char * const names[] = { "ID", "VERSION", "SPIV" };
677 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
679 for (i = 0; i < ARRAY_SIZE(regs); i++) {
680 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
685 status = safe_apic_wait_icr_idle();
687 pr_cont("a previous APIC delivery may have failed\n");
689 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
694 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
695 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
698 case APIC_ICR_RR_VALID:
699 status = apic_read(APIC_RRR);
700 pr_cont("%08x\n", status);
709 * The Multiprocessor Specification 1.4 (1997) example code suggests
710 * that there should be a 10ms delay between the BSP asserting INIT
711 * and de-asserting INIT, when starting a remote processor.
712 * But that slows boot and resume on modern processors, which include
713 * many cores and don't require that delay.
715 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
716 * Modern processor families are quirked to remove the delay entirely.
718 #define UDELAY_10MS_DEFAULT 10000
720 static unsigned int init_udelay = UINT_MAX;
722 static int __init cpu_init_udelay(char *str)
724 get_option(&str, &init_udelay);
728 early_param("cpu_init_udelay", cpu_init_udelay);
730 static void __init smp_quirk_init_udelay(void)
732 /* if cmdline changed it from default, leave it alone */
733 if (init_udelay != UINT_MAX)
736 /* if modern processor, use no delay */
737 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
738 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
739 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
743 /* else, use legacy delay */
744 init_udelay = UDELAY_10MS_DEFAULT;
748 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
749 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
750 * won't ... remember to clear down the APIC, etc later.
753 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
755 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
756 unsigned long send_status, accept_status = 0;
760 /* Boot on the stack */
761 /* Kick the second */
762 apic_icr_write(APIC_DM_NMI | dm, apicid);
764 pr_debug("Waiting for send to finish...\n");
765 send_status = safe_apic_wait_icr_idle();
768 * Give the other CPU some time to accept the IPI.
771 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
772 maxlvt = lapic_get_maxlvt();
773 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
774 apic_write(APIC_ESR, 0);
775 accept_status = (apic_read(APIC_ESR) & 0xEF);
777 pr_debug("NMI sent\n");
780 pr_err("APIC never delivered???\n");
782 pr_err("APIC delivery error (%lx)\n", accept_status);
784 return (send_status | accept_status);
788 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
790 unsigned long send_status = 0, accept_status = 0;
791 int maxlvt, num_starts, j;
793 maxlvt = lapic_get_maxlvt();
796 * Be paranoid about clearing APIC errors.
798 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
799 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
800 apic_write(APIC_ESR, 0);
804 pr_debug("Asserting INIT\n");
807 * Turn INIT on target chip
812 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
815 pr_debug("Waiting for send to finish...\n");
816 send_status = safe_apic_wait_icr_idle();
820 pr_debug("Deasserting INIT\n");
824 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
826 pr_debug("Waiting for send to finish...\n");
827 send_status = safe_apic_wait_icr_idle();
832 * Should we send STARTUP IPIs ?
834 * Determine this based on the APIC version.
835 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
837 if (APIC_INTEGRATED(boot_cpu_apic_version))
843 * Run STARTUP IPI loop.
845 pr_debug("#startup loops: %d\n", num_starts);
847 for (j = 1; j <= num_starts; j++) {
848 pr_debug("Sending STARTUP #%d\n", j);
849 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
850 apic_write(APIC_ESR, 0);
852 pr_debug("After apic_write\n");
859 /* Boot on the stack */
860 /* Kick the second */
861 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
865 * Give the other CPU some time to accept the IPI.
867 if (init_udelay == 0)
872 pr_debug("Startup point 1\n");
874 pr_debug("Waiting for send to finish...\n");
875 send_status = safe_apic_wait_icr_idle();
878 * Give the other CPU some time to accept the IPI.
880 if (init_udelay == 0)
885 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
886 apic_write(APIC_ESR, 0);
887 accept_status = (apic_read(APIC_ESR) & 0xEF);
888 if (send_status || accept_status)
891 pr_debug("After Startup\n");
894 pr_err("APIC never delivered???\n");
896 pr_err("APIC delivery error (%lx)\n", accept_status);
898 return (send_status | accept_status);
901 /* reduce the number of lines printed when booting a large cpu count system */
902 static void announce_cpu(int cpu, int apicid)
904 static int current_node = NUMA_NO_NODE;
905 int node = early_cpu_to_node(cpu);
906 static int width, node_width;
909 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
912 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
915 printk(KERN_INFO "x86: Booting SMP configuration:\n");
917 if (system_state < SYSTEM_RUNNING) {
918 if (node != current_node) {
919 if (current_node > (-1))
923 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
924 node_width - num_digits(node), " ", node);
927 /* Add padding for the BSP */
929 pr_cont("%*s", width + 1, " ");
931 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
934 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
938 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
942 cpu = smp_processor_id();
943 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
950 * Wake up AP by INIT, INIT, STARTUP sequence.
952 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
953 * boot-strap code which is not a desired behavior for waking up BSP. To
954 * void the boot-strap code, wake up CPU0 by NMI instead.
956 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
957 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
958 * We'll change this code in the future to wake up hard offlined CPU0 if
959 * real platform and request are available.
962 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
963 int *cpu0_nmi_registered)
971 * Wake up AP by INIT, INIT, STARTUP sequence.
974 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
979 * Wake up BSP by nmi.
981 * Register a NMI handler to help wake up CPU0.
983 boot_error = register_nmi_handler(NMI_LOCAL,
984 wakeup_cpu0_nmi, 0, "wake_cpu0");
987 enable_start_cpu0 = 1;
988 *cpu0_nmi_registered = 1;
989 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
990 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
999 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1003 /* Just in case we booted with a single CPU. */
1004 alternatives_enable_smp();
1006 per_cpu(current_task, cpu) = idle;
1007 cpu_init_stack_canary(cpu, idle);
1009 /* Initialize the interrupt stack(s) */
1010 ret = irq_init_percpu_irqstack(cpu);
1014 #ifdef CONFIG_X86_32
1015 /* Stack for startup_32 can be just as for start_secondary onwards */
1016 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1018 initial_gs = per_cpu_offset(cpu);
1024 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1025 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1026 * Returns zero if CPU booted OK, else error code from
1027 * ->wakeup_secondary_cpu.
1029 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1030 int *cpu0_nmi_registered)
1032 /* start_ip had better be page-aligned! */
1033 unsigned long start_ip = real_mode_header->trampoline_start;
1035 unsigned long boot_error = 0;
1036 unsigned long timeout;
1038 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1039 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1040 initial_code = (unsigned long)start_secondary;
1041 initial_stack = idle->thread.sp;
1043 /* Enable the espfix hack for this CPU */
1044 init_espfix_ap(cpu);
1046 /* So we see what's up */
1047 announce_cpu(cpu, apicid);
1050 * This grunge runs the startup process for
1051 * the targeted processor.
1054 if (x86_platform.legacy.warm_reset) {
1056 pr_debug("Setting warm reset code and vector.\n");
1058 smpboot_setup_warm_reset_vector(start_ip);
1060 * Be paranoid about clearing APIC errors.
1062 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1063 apic_write(APIC_ESR, 0);
1064 apic_read(APIC_ESR);
1069 * AP might wait on cpu_callout_mask in cpu_init() with
1070 * cpu_initialized_mask set if previous attempt to online
1071 * it timed-out. Clear cpu_initialized_mask so that after
1072 * INIT/SIPI it could start with a clean state.
1074 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1078 * Wake up a CPU in difference cases:
1079 * - Use the method in the APIC driver if it's defined
1081 * - Use an INIT boot APIC message for APs or NMI for BSP.
1083 if (apic->wakeup_secondary_cpu)
1084 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1086 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1087 cpu0_nmi_registered);
1091 * Wait 10s total for first sign of life from AP
1094 timeout = jiffies + 10*HZ;
1095 while (time_before(jiffies, timeout)) {
1096 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1098 * Tell AP to proceed with initialization
1100 cpumask_set_cpu(cpu, cpu_callout_mask);
1110 * Wait till AP completes initial initialization
1112 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1114 * Allow other tasks to run while we wait for the
1115 * AP to come online. This also gives a chance
1116 * for the MTRR work(triggered by the AP coming online)
1117 * to be completed in the stop machine context.
1123 if (x86_platform.legacy.warm_reset) {
1125 * Cleanup possible dangling ends...
1127 smpboot_restore_warm_reset_vector();
1133 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1135 int apicid = apic->cpu_present_to_apicid(cpu);
1136 int cpu0_nmi_registered = 0;
1137 unsigned long flags;
1140 lockdep_assert_irqs_enabled();
1142 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1144 if (apicid == BAD_APICID ||
1145 !physid_isset(apicid, phys_cpu_present_map) ||
1146 !apic->apic_id_valid(apicid)) {
1147 pr_err("%s: bad cpu %d\n", __func__, cpu);
1152 * Already booted CPU?
1154 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1155 pr_debug("do_boot_cpu %d Already started\n", cpu);
1160 * Save current MTRR state in case it was changed since early boot
1161 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1165 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1166 err = cpu_check_up_prepare(cpu);
1167 if (err && err != -EBUSY)
1170 /* the FPU context is blank, nobody can own it */
1171 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1173 err = common_cpu_up(cpu, tidle);
1177 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1179 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1185 * Check TSC synchronization with the AP (keep irqs disabled
1188 local_irq_save(flags);
1189 check_tsc_sync_source(cpu);
1190 local_irq_restore(flags);
1192 while (!cpu_online(cpu)) {
1194 touch_nmi_watchdog();
1199 * Clean up the nmi handler. Do this after the callin and callout sync
1200 * to avoid impact of possible long unregister time.
1202 if (cpu0_nmi_registered)
1203 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1209 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1211 void arch_disable_smp_support(void)
1213 disable_ioapic_support();
1217 * Fall back to non SMP mode after errors.
1219 * RED-PEN audit/test this more. I bet there is more state messed up here.
1221 static __init void disable_smp(void)
1223 pr_info("SMP disabled\n");
1225 disable_ioapic_support();
1227 init_cpu_present(cpumask_of(0));
1228 init_cpu_possible(cpumask_of(0));
1230 if (smp_found_config)
1231 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1233 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1234 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1235 cpumask_set_cpu(0, topology_core_cpumask(0));
1236 cpumask_set_cpu(0, topology_die_cpumask(0));
1240 * Various sanity checks.
1242 static void __init smp_sanity_check(void)
1246 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1247 if (def_to_bigsmp && nr_cpu_ids > 8) {
1251 pr_warn("More than 8 CPUs detected - skipping them\n"
1252 "Use CONFIG_X86_BIGSMP\n");
1255 for_each_present_cpu(cpu) {
1257 set_cpu_present(cpu, false);
1262 for_each_possible_cpu(cpu) {
1264 set_cpu_possible(cpu, false);
1272 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1273 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1274 hard_smp_processor_id());
1276 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1280 * Should not be necessary because the MP table should list the boot
1281 * CPU too, but we do it for the sake of robustness anyway.
1283 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1284 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1285 boot_cpu_physical_apicid);
1286 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1291 static void __init smp_cpu_index_default(void)
1294 struct cpuinfo_x86 *c;
1296 for_each_possible_cpu(i) {
1298 /* mark all to hotplug */
1299 c->cpu_index = nr_cpu_ids;
1303 static void __init smp_get_logical_apicid(void)
1306 cpu0_logical_apicid = apic_read(APIC_LDR);
1308 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1312 * Prepare for SMP bootup.
1313 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1314 * for common interface support.
1316 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1320 smp_cpu_index_default();
1323 * Setup boot CPU information
1325 smp_store_boot_cpu_info(); /* Final full version of the data */
1326 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1329 for_each_possible_cpu(i) {
1330 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1331 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1332 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1333 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1337 * Set 'default' x86 topology, this matches default_topology() in that
1338 * it has NUMA nodes as a topology level. See also
1339 * native_smp_cpus_done().
1341 * Must be done before set_cpus_sibling_map() is ran.
1343 set_sched_topology(x86_topology);
1345 set_cpu_sibling_map(0);
1346 init_freq_invariance(false, false);
1349 switch (apic_intr_mode) {
1351 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1354 case APIC_SYMMETRIC_IO_NO_ROUTING:
1356 /* Setup local timer */
1357 x86_init.timers.setup_percpu_clockev();
1359 case APIC_VIRTUAL_WIRE:
1360 case APIC_SYMMETRIC_IO:
1364 /* Setup local timer */
1365 x86_init.timers.setup_percpu_clockev();
1367 smp_get_logical_apicid();
1370 print_cpu_info(&cpu_data(0));
1374 set_mtrr_aps_delayed_init();
1376 smp_quirk_init_udelay();
1378 speculative_store_bypass_ht_init();
1381 void arch_thaw_secondary_cpus_begin(void)
1383 set_mtrr_aps_delayed_init();
1386 void arch_thaw_secondary_cpus_end(void)
1392 * Early setup to make printk work.
1394 void __init native_smp_prepare_boot_cpu(void)
1396 int me = smp_processor_id();
1397 switch_to_new_gdt(me);
1398 /* already set me in cpu_online_mask in boot_cpu_init() */
1399 cpumask_set_cpu(me, cpu_callout_mask);
1400 cpu_set_state_online(me);
1401 native_pv_lock_init();
1404 void __init calculate_max_logical_packages(void)
1409 * Today neither Intel nor AMD support heterogenous systems so
1410 * extrapolate the boot cpu's data to all packages.
1412 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1413 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1414 pr_info("Max logical packages: %u\n", __max_logical_packages);
1417 void __init native_smp_cpus_done(unsigned int max_cpus)
1419 pr_debug("Boot done\n");
1421 calculate_max_logical_packages();
1423 if (x86_has_numa_in_package)
1424 set_sched_topology(x86_numa_in_package_topology);
1431 static int __initdata setup_possible_cpus = -1;
1432 static int __init _setup_possible_cpus(char *str)
1434 get_option(&str, &setup_possible_cpus);
1437 early_param("possible_cpus", _setup_possible_cpus);
1441 * cpu_possible_mask should be static, it cannot change as cpu's
1442 * are onlined, or offlined. The reason is per-cpu data-structures
1443 * are allocated by some modules at init time, and don't expect to
1444 * do this dynamically on cpu arrival/departure.
1445 * cpu_present_mask on the other hand can change dynamically.
1446 * In case when cpu_hotplug is not compiled, then we resort to current
1447 * behaviour, which is cpu_possible == cpu_present.
1450 * Three ways to find out the number of additional hotplug CPUs:
1451 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1452 * - The user can overwrite it with possible_cpus=NUM
1453 * - Otherwise don't reserve additional CPUs.
1454 * We do this because additional CPUs waste a lot of memory.
1457 __init void prefill_possible_map(void)
1461 /* No boot processor was found in mptable or ACPI MADT */
1462 if (!num_processors) {
1463 if (boot_cpu_has(X86_FEATURE_APIC)) {
1464 int apicid = boot_cpu_physical_apicid;
1465 int cpu = hard_smp_processor_id();
1467 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1469 /* Make sure boot cpu is enumerated */
1470 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1471 apic->apic_id_valid(apicid))
1472 generic_processor_info(apicid, boot_cpu_apic_version);
1475 if (!num_processors)
1479 i = setup_max_cpus ?: 1;
1480 if (setup_possible_cpus == -1) {
1481 possible = num_processors;
1482 #ifdef CONFIG_HOTPLUG_CPU
1484 possible += disabled_cpus;
1490 possible = setup_possible_cpus;
1492 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1494 /* nr_cpu_ids could be reduced via nr_cpus= */
1495 if (possible > nr_cpu_ids) {
1496 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1497 possible, nr_cpu_ids);
1498 possible = nr_cpu_ids;
1501 #ifdef CONFIG_HOTPLUG_CPU
1502 if (!setup_max_cpus)
1505 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1506 possible, setup_max_cpus);
1510 nr_cpu_ids = possible;
1512 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1513 possible, max_t(int, possible - num_processors, 0));
1515 reset_cpu_possible_mask();
1517 for (i = 0; i < possible; i++)
1518 set_cpu_possible(i, true);
1521 #ifdef CONFIG_HOTPLUG_CPU
1523 /* Recompute SMT state for all CPUs on offline */
1524 static void recompute_smt_state(void)
1526 int max_threads, cpu;
1529 for_each_online_cpu (cpu) {
1530 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1532 if (threads > max_threads)
1533 max_threads = threads;
1535 __max_smt_threads = max_threads;
1538 static void remove_siblinginfo(int cpu)
1541 struct cpuinfo_x86 *c = &cpu_data(cpu);
1543 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1544 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1546 * last thread sibling in this cpu core going down
1548 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1549 cpu_data(sibling).booted_cores--;
1552 for_each_cpu(sibling, topology_die_cpumask(cpu))
1553 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1554 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1555 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1556 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1557 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1558 cpumask_clear(cpu_llc_shared_mask(cpu));
1559 cpumask_clear(topology_sibling_cpumask(cpu));
1560 cpumask_clear(topology_core_cpumask(cpu));
1561 cpumask_clear(topology_die_cpumask(cpu));
1563 c->booted_cores = 0;
1564 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1565 recompute_smt_state();
1568 static void remove_cpu_from_maps(int cpu)
1570 set_cpu_online(cpu, false);
1571 cpumask_clear_cpu(cpu, cpu_callout_mask);
1572 cpumask_clear_cpu(cpu, cpu_callin_mask);
1573 /* was set by cpu_init() */
1574 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1575 numa_remove_cpu(cpu);
1578 void cpu_disable_common(void)
1580 int cpu = smp_processor_id();
1582 remove_siblinginfo(cpu);
1584 /* It's now safe to remove this processor from the online map */
1586 remove_cpu_from_maps(cpu);
1587 unlock_vector_lock();
1592 int native_cpu_disable(void)
1596 ret = lapic_can_unplug_cpu();
1600 cpu_disable_common();
1603 * Disable the local APIC. Otherwise IPI broadcasts will reach
1604 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1607 * Disabling the APIC must happen after cpu_disable_common()
1608 * which invokes fixup_irqs().
1610 * Disabling the APIC preserves already set bits in IRR, but
1611 * an interrupt arriving after disabling the local APIC does not
1612 * set the corresponding IRR bit.
1614 * fixup_irqs() scans IRR for set bits so it can raise a not
1615 * yet handled interrupt on the new destination CPU via an IPI
1616 * but obviously it can't do so for IRR bits which are not set.
1617 * IOW, interrupts arriving after disabling the local APIC will
1620 apic_soft_disable();
1625 int common_cpu_die(unsigned int cpu)
1629 /* We don't do anything here: idle task is faking death itself. */
1631 /* They ack this in play_dead() by setting CPU_DEAD */
1632 if (cpu_wait_death(cpu, 5)) {
1633 if (system_state == SYSTEM_RUNNING)
1634 pr_info("CPU %u is now offline\n", cpu);
1636 pr_err("CPU %u didn't die...\n", cpu);
1643 void native_cpu_die(unsigned int cpu)
1645 common_cpu_die(cpu);
1648 void play_dead_common(void)
1653 (void)cpu_report_death();
1656 * With physical CPU hotplug, we should halt the cpu
1658 local_irq_disable();
1661 static bool wakeup_cpu0(void)
1663 if (smp_processor_id() == 0 && enable_start_cpu0)
1670 * We need to flush the caches before going to sleep, lest we have
1671 * dirty data in our caches when we come back up.
1673 static inline void mwait_play_dead(void)
1675 unsigned int eax, ebx, ecx, edx;
1676 unsigned int highest_cstate = 0;
1677 unsigned int highest_subcstate = 0;
1681 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1682 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1684 if (!this_cpu_has(X86_FEATURE_MWAIT))
1686 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1688 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1691 eax = CPUID_MWAIT_LEAF;
1693 native_cpuid(&eax, &ebx, &ecx, &edx);
1696 * eax will be 0 if EDX enumeration is not valid.
1697 * Initialized below to cstate, sub_cstate value when EDX is valid.
1699 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1702 edx >>= MWAIT_SUBSTATE_SIZE;
1703 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1704 if (edx & MWAIT_SUBSTATE_MASK) {
1706 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1709 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1710 (highest_subcstate - 1);
1714 * This should be a memory location in a cache line which is
1715 * unlikely to be touched by other processors. The actual
1716 * content is immaterial as it is not actually modified in any way.
1718 mwait_ptr = ¤t_thread_info()->flags;
1724 * The CLFLUSH is a workaround for erratum AAI65 for
1725 * the Xeon 7400 series. It's not clear it is actually
1726 * needed, but it should be harmless in either case.
1727 * The WBINVD is insufficient due to the spurious-wakeup
1728 * case where we return around the loop.
1733 __monitor(mwait_ptr, 0, 0);
1737 * If NMI wants to wake up CPU0, start CPU0.
1744 void hlt_play_dead(void)
1746 if (__this_cpu_read(cpu_info.x86) >= 4)
1752 * If NMI wants to wake up CPU0, start CPU0.
1759 void native_play_dead(void)
1762 tboot_shutdown(TB_SHUTDOWN_WFS);
1764 mwait_play_dead(); /* Only returns on failure */
1765 if (cpuidle_play_dead())
1769 #else /* ... !CONFIG_HOTPLUG_CPU */
1770 int native_cpu_disable(void)
1775 void native_cpu_die(unsigned int cpu)
1777 /* We said "no" in __cpu_disable */
1781 void native_play_dead(void)
1788 #ifdef CONFIG_X86_64
1790 * APERF/MPERF frequency ratio computation.
1792 * The scheduler wants to do frequency invariant accounting and needs a <1
1793 * ratio to account for the 'current' frequency, corresponding to
1794 * freq_curr / freq_max.
1796 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1797 * our P-state setting is little more than a request/hint, we need to observe
1798 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1799 * interval after discarding idle time. This is given by:
1801 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1803 * where freq_base is the max non-turbo P-state.
1805 * The freq_max term has to be set to a somewhat arbitrary value, because we
1806 * can't know which turbo states will be available at a given point in time:
1807 * it all depends on the thermal headroom of the entire package. We set it to
1808 * the turbo level with 4 cores active.
1810 * Benchmarks show that's a good compromise between the 1C turbo ratio
1811 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1812 * which would ignore the entire turbo range (a conspicuous part, making
1813 * freq_curr/freq_max always maxed out).
1815 * An exception to the heuristic above is the Atom uarch, where we choose the
1816 * highest turbo level for freq_max since Atom's are generally oriented towards
1819 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1820 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1823 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key);
1825 static DEFINE_PER_CPU(u64, arch_prev_aperf);
1826 static DEFINE_PER_CPU(u64, arch_prev_mperf);
1827 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE;
1828 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE;
1830 void arch_set_max_freq_ratio(bool turbo_disabled)
1832 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE :
1833 arch_turbo_freq_ratio;
1836 static bool turbo_disabled(void)
1841 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en);
1845 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
1848 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1852 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq);
1856 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
1860 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */
1861 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */
1866 #include <asm/cpu_device_id.h>
1867 #include <asm/intel-family.h>
1869 #define X86_MATCH(model) \
1870 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
1871 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL)
1873 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = {
1874 X86_MATCH(XEON_PHI_KNL),
1875 X86_MATCH(XEON_PHI_KNM),
1879 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = {
1880 X86_MATCH(SKYLAKE_X),
1884 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = {
1885 X86_MATCH(ATOM_GOLDMONT),
1886 X86_MATCH(ATOM_GOLDMONT_D),
1887 X86_MATCH(ATOM_GOLDMONT_PLUS),
1891 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq,
1892 int num_delta_fratio)
1894 int fratio, delta_fratio, found;
1898 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1902 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1904 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1908 fratio = (msr >> 8) & 0xFF;
1912 if (found >= num_delta_fratio) {
1913 *turbo_freq = fratio;
1917 delta_fratio = (msr >> (i + 5)) & 0x7;
1921 fratio -= delta_fratio;
1930 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
1936 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1940 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1942 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
1946 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
1950 for (i = 0; i < 64; i += 8) {
1951 group_size = (counts >> i) & 0xFF;
1952 if (group_size >= size) {
1953 *turbo_freq = (ratios >> i) & 0xFF;
1961 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1966 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1970 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1974 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1975 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */
1977 /* The CPU may have less than 4 cores */
1979 *turbo_freq = msr & 0xFF; /* 1C turbo */
1984 static bool intel_set_max_freq_ratio(void)
1986 u64 base_freq, turbo_freq;
1989 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq))
1992 if (x86_match_cpu(has_glm_turbo_ratio_limits) &&
1993 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1996 if (x86_match_cpu(has_knl_turbo_ratio_limits) &&
1997 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
2000 if (x86_match_cpu(has_skx_turbo_ratio_limits) &&
2001 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4))
2004 if (core_set_max_freq_ratio(&base_freq, &turbo_freq))
2011 * Some hypervisors advertise X86_FEATURE_APERFMPERF
2012 * but then fill all MSR's with zeroes.
2013 * Some CPUs have turbo boost but don't declare any turbo ratio
2014 * in MSR_TURBO_RATIO_LIMIT.
2016 if (!base_freq || !turbo_freq) {
2017 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n");
2021 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq);
2023 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n");
2027 arch_turbo_freq_ratio = turbo_ratio;
2028 arch_set_max_freq_ratio(turbo_disabled());
2033 #ifdef CONFIG_ACPI_CPPC_LIB
2034 static bool amd_set_max_freq_ratio(void)
2036 struct cppc_perf_caps perf_caps;
2037 u64 highest_perf, nominal_perf;
2041 rc = cppc_get_perf_caps(0, &perf_caps);
2043 pr_debug("Could not retrieve perf counters (%d)\n", rc);
2047 highest_perf = perf_caps.highest_perf;
2048 nominal_perf = perf_caps.nominal_perf;
2050 if (!highest_perf || !nominal_perf) {
2051 pr_debug("Could not retrieve highest or nominal performance\n");
2055 perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf);
2056 /* midpoint between max_boost and max_P */
2057 perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1;
2059 pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n");
2063 arch_turbo_freq_ratio = perf_ratio;
2064 arch_set_max_freq_ratio(false);
2069 static bool amd_set_max_freq_ratio(void)
2075 static void init_counter_refs(void)
2079 rdmsrl(MSR_IA32_APERF, aperf);
2080 rdmsrl(MSR_IA32_MPERF, mperf);
2082 this_cpu_write(arch_prev_aperf, aperf);
2083 this_cpu_write(arch_prev_mperf, mperf);
2086 static void init_freq_invariance(bool secondary, bool cppc_ready)
2090 if (!boot_cpu_has(X86_FEATURE_APERFMPERF))
2094 if (static_branch_likely(&arch_scale_freq_key)) {
2095 init_counter_refs();
2100 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2101 ret = intel_set_max_freq_ratio();
2102 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
2106 ret = amd_set_max_freq_ratio();
2110 init_counter_refs();
2111 static_branch_enable(&arch_scale_freq_key);
2112 pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio);
2114 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2118 #ifdef CONFIG_ACPI_CPPC_LIB
2119 static DEFINE_MUTEX(freq_invariance_lock);
2121 void init_freq_invariance_cppc(void)
2123 static bool secondary;
2125 mutex_lock(&freq_invariance_lock);
2127 init_freq_invariance(secondary, true);
2130 mutex_unlock(&freq_invariance_lock);
2134 static void disable_freq_invariance_workfn(struct work_struct *work)
2136 static_branch_disable(&arch_scale_freq_key);
2139 static DECLARE_WORK(disable_freq_invariance_work,
2140 disable_freq_invariance_workfn);
2142 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
2144 void arch_scale_freq_tick(void)
2146 u64 freq_scale = SCHED_CAPACITY_SCALE;
2150 if (!arch_scale_freq_invariant())
2153 rdmsrl(MSR_IA32_APERF, aperf);
2154 rdmsrl(MSR_IA32_MPERF, mperf);
2156 acnt = aperf - this_cpu_read(arch_prev_aperf);
2157 mcnt = mperf - this_cpu_read(arch_prev_mperf);
2159 this_cpu_write(arch_prev_aperf, aperf);
2160 this_cpu_write(arch_prev_mperf, mperf);
2162 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt))
2165 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt)
2168 freq_scale = div64_u64(acnt, mcnt);
2172 if (freq_scale > SCHED_CAPACITY_SCALE)
2173 freq_scale = SCHED_CAPACITY_SCALE;
2175 this_cpu_write(arch_freq_scale, freq_scale);
2179 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n");
2180 schedule_work(&disable_freq_invariance_work);
2183 static inline void init_freq_invariance(bool secondary, bool cppc_ready)
2186 #endif /* CONFIG_X86_64 */