2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/timer.h>
40 #include "perf_event.h"
42 struct x86_pmu x86_pmu __read_mostly;
44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
50 u64 __read_mostly hw_cache_event_ids
51 [PERF_COUNT_HW_CACHE_MAX]
52 [PERF_COUNT_HW_CACHE_OP_MAX]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX];
54 u64 __read_mostly hw_cache_extra_regs
55 [PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX];
60 * Propagate event elapsed time into the generic event.
61 * Can only be executed on the CPU where the event is active.
62 * Returns the delta events processed.
64 u64 x86_perf_event_update(struct perf_event *event)
66 struct hw_perf_event *hwc = &event->hw;
67 int shift = 64 - x86_pmu.cntval_bits;
68 u64 prev_raw_count, new_raw_count;
72 if (idx == INTEL_PMC_IDX_FIXED_BTS)
76 * Careful: an NMI might modify the previous event value.
78 * Our tactic to handle this is to first atomically read and
79 * exchange a new raw count - then add that new-prev delta
80 * count to the generic event atomically:
83 prev_raw_count = local64_read(&hwc->prev_count);
84 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
86 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
87 new_raw_count) != prev_raw_count)
91 * Now we have the new raw value and have updated the prev
92 * timestamp already. We can now calculate the elapsed delta
93 * (event-)time and add that to the generic event.
95 * Careful, not all hw sign-extends above the physical width
98 delta = (new_raw_count << shift) - (prev_raw_count << shift);
101 local64_add(delta, &event->count);
102 local64_sub(delta, &hwc->period_left);
104 return new_raw_count;
108 * Find and validate any extra registers to set up.
110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
112 struct hw_perf_event_extra *reg;
113 struct extra_reg *er;
115 reg = &event->hw.extra_reg;
117 if (!x86_pmu.extra_regs)
120 for (er = x86_pmu.extra_regs; er->msr; er++) {
121 if (er->event != (config & er->config_mask))
123 if (event->attr.config1 & ~er->valid_mask)
125 /* Check if the extra msrs can be safely accessed*/
126 if (!er->extra_msr_access)
130 reg->config = event->attr.config1;
137 static atomic_t active_events;
138 static DEFINE_MUTEX(pmc_reserve_mutex);
140 #ifdef CONFIG_X86_LOCAL_APIC
142 static bool reserve_pmc_hardware(void)
146 for (i = 0; i < x86_pmu.num_counters; i++) {
147 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
151 for (i = 0; i < x86_pmu.num_counters; i++) {
152 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
159 for (i--; i >= 0; i--)
160 release_evntsel_nmi(x86_pmu_config_addr(i));
162 i = x86_pmu.num_counters;
165 for (i--; i >= 0; i--)
166 release_perfctr_nmi(x86_pmu_event_addr(i));
171 static void release_pmc_hardware(void)
175 for (i = 0; i < x86_pmu.num_counters; i++) {
176 release_perfctr_nmi(x86_pmu_event_addr(i));
177 release_evntsel_nmi(x86_pmu_config_addr(i));
183 static bool reserve_pmc_hardware(void) { return true; }
184 static void release_pmc_hardware(void) {}
188 static bool check_hw_exists(void)
190 u64 val, val_fail, val_new= ~0;
191 int i, reg, reg_fail, ret = 0;
195 * Check to see if the BIOS enabled any of the counters, if so
198 for (i = 0; i < x86_pmu.num_counters; i++) {
199 reg = x86_pmu_config_addr(i);
200 ret = rdmsrl_safe(reg, &val);
203 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
210 if (x86_pmu.num_counters_fixed) {
211 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
212 ret = rdmsrl_safe(reg, &val);
215 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
216 if (val & (0x03 << i*4)) {
225 * Read the current value, change it and read it back to see if it
226 * matches, this is needed to detect certain hardware emulators
227 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
229 reg = x86_pmu_event_addr(0);
230 if (rdmsrl_safe(reg, &val))
233 ret = wrmsrl_safe(reg, val);
234 ret |= rdmsrl_safe(reg, &val_new);
235 if (ret || val != val_new)
239 * We still allow the PMU driver to operate:
242 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
243 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
249 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
250 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
251 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
257 static void hw_perf_event_destroy(struct perf_event *event)
259 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
260 release_pmc_hardware();
261 release_ds_buffers();
262 mutex_unlock(&pmc_reserve_mutex);
266 void hw_perf_lbr_event_destroy(struct perf_event *event)
268 hw_perf_event_destroy(event);
270 /* undo the lbr/bts event accounting */
271 x86_del_exclusive(x86_lbr_exclusive_lbr);
274 static inline int x86_pmu_initialized(void)
276 return x86_pmu.handle_irq != NULL;
280 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
282 struct perf_event_attr *attr = &event->attr;
283 unsigned int cache_type, cache_op, cache_result;
286 config = attr->config;
288 cache_type = (config >> 0) & 0xff;
289 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
292 cache_op = (config >> 8) & 0xff;
293 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
296 cache_result = (config >> 16) & 0xff;
297 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
300 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
309 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
310 return x86_pmu_extra_regs(val, event);
314 * Check if we can create event of a certain type (that no conflicting events
317 int x86_add_exclusive(unsigned int what)
321 if (atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what]))
324 mutex_lock(&pmc_reserve_mutex);
325 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++)
326 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
329 atomic_inc(&x86_pmu.lbr_exclusive[what]);
333 mutex_unlock(&pmc_reserve_mutex);
337 void x86_del_exclusive(unsigned int what)
339 atomic_dec(&x86_pmu.lbr_exclusive[what]);
342 int x86_setup_perfctr(struct perf_event *event)
344 struct perf_event_attr *attr = &event->attr;
345 struct hw_perf_event *hwc = &event->hw;
348 if (!is_sampling_event(event)) {
349 hwc->sample_period = x86_pmu.max_period;
350 hwc->last_period = hwc->sample_period;
351 local64_set(&hwc->period_left, hwc->sample_period);
354 if (attr->type == PERF_TYPE_RAW)
355 return x86_pmu_extra_regs(event->attr.config, event);
357 if (attr->type == PERF_TYPE_HW_CACHE)
358 return set_ext_hw_attr(hwc, event);
360 if (attr->config >= x86_pmu.max_events)
366 config = x86_pmu.event_map(attr->config);
377 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
378 !attr->freq && hwc->sample_period == 1) {
379 /* BTS is not supported by this architecture. */
380 if (!x86_pmu.bts_active)
383 /* BTS is currently only allowed for user-mode. */
384 if (!attr->exclude_kernel)
387 /* disallow bts if conflicting events are present */
388 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
391 event->destroy = hw_perf_lbr_event_destroy;
394 hwc->config |= config;
400 * check that branch_sample_type is compatible with
401 * settings needed for precise_ip > 1 which implies
402 * using the LBR to capture ALL taken branches at the
403 * priv levels of the measurement
405 static inline int precise_br_compat(struct perf_event *event)
407 u64 m = event->attr.branch_sample_type;
410 /* must capture all branches */
411 if (!(m & PERF_SAMPLE_BRANCH_ANY))
414 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
416 if (!event->attr.exclude_user)
417 b |= PERF_SAMPLE_BRANCH_USER;
419 if (!event->attr.exclude_kernel)
420 b |= PERF_SAMPLE_BRANCH_KERNEL;
423 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
429 int x86_pmu_hw_config(struct perf_event *event)
431 if (event->attr.precise_ip) {
434 /* Support for constant skid */
435 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
438 /* Support for IP fixup */
439 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
443 if (event->attr.precise_ip > precise)
447 * check that PEBS LBR correction does not conflict with
448 * whatever the user is asking with attr->branch_sample_type
450 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
451 u64 *br_type = &event->attr.branch_sample_type;
453 if (has_branch_stack(event)) {
454 if (!precise_br_compat(event))
457 /* branch_sample_type is compatible */
461 * user did not specify branch_sample_type
463 * For PEBS fixups, we capture all
464 * the branches at the priv level of the
467 *br_type = PERF_SAMPLE_BRANCH_ANY;
469 if (!event->attr.exclude_user)
470 *br_type |= PERF_SAMPLE_BRANCH_USER;
472 if (!event->attr.exclude_kernel)
473 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
477 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
478 event->attach_state |= PERF_ATTACH_TASK_DATA;
482 * (keep 'enabled' bit clear for now)
484 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
487 * Count user and OS events unless requested not to
489 if (!event->attr.exclude_user)
490 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
491 if (!event->attr.exclude_kernel)
492 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
494 if (event->attr.type == PERF_TYPE_RAW)
495 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
497 if (event->attr.sample_period && x86_pmu.limit_period) {
498 if (x86_pmu.limit_period(event, event->attr.sample_period) >
499 event->attr.sample_period)
503 return x86_setup_perfctr(event);
507 * Setup the hardware configuration for a given attr_type
509 static int __x86_pmu_event_init(struct perf_event *event)
513 if (!x86_pmu_initialized())
517 if (!atomic_inc_not_zero(&active_events)) {
518 mutex_lock(&pmc_reserve_mutex);
519 if (atomic_read(&active_events) == 0) {
520 if (!reserve_pmc_hardware())
523 reserve_ds_buffers();
526 atomic_inc(&active_events);
527 mutex_unlock(&pmc_reserve_mutex);
532 event->destroy = hw_perf_event_destroy;
535 event->hw.last_cpu = -1;
536 event->hw.last_tag = ~0ULL;
539 event->hw.extra_reg.idx = EXTRA_REG_NONE;
540 event->hw.branch_reg.idx = EXTRA_REG_NONE;
542 return x86_pmu.hw_config(event);
545 void x86_pmu_disable_all(void)
547 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
550 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
553 if (!test_bit(idx, cpuc->active_mask))
555 rdmsrl(x86_pmu_config_addr(idx), val);
556 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
558 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
559 wrmsrl(x86_pmu_config_addr(idx), val);
563 static void x86_pmu_disable(struct pmu *pmu)
565 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
567 if (!x86_pmu_initialized())
577 x86_pmu.disable_all();
580 void x86_pmu_enable_all(int added)
582 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
585 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
586 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
588 if (!test_bit(idx, cpuc->active_mask))
591 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
595 static struct pmu pmu;
597 static inline int is_x86_event(struct perf_event *event)
599 return event->pmu == &pmu;
603 * Event scheduler state:
605 * Assign events iterating over all events and counters, beginning
606 * with events with least weights first. Keep the current iterator
607 * state in struct sched_state.
611 int event; /* event index */
612 int counter; /* counter index */
613 int unassigned; /* number of events to be assigned left */
614 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
617 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
618 #define SCHED_STATES_MAX 2
623 struct perf_event **events;
624 struct sched_state state;
626 struct sched_state saved[SCHED_STATES_MAX];
630 * Initialize interator that runs through all events and counters.
632 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
633 int num, int wmin, int wmax)
637 memset(sched, 0, sizeof(*sched));
638 sched->max_events = num;
639 sched->max_weight = wmax;
640 sched->events = events;
642 for (idx = 0; idx < num; idx++) {
643 if (events[idx]->hw.constraint->weight == wmin)
647 sched->state.event = idx; /* start with min weight */
648 sched->state.weight = wmin;
649 sched->state.unassigned = num;
652 static void perf_sched_save_state(struct perf_sched *sched)
654 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
657 sched->saved[sched->saved_states] = sched->state;
658 sched->saved_states++;
661 static bool perf_sched_restore_state(struct perf_sched *sched)
663 if (!sched->saved_states)
666 sched->saved_states--;
667 sched->state = sched->saved[sched->saved_states];
669 /* continue with next counter: */
670 clear_bit(sched->state.counter++, sched->state.used);
676 * Select a counter for the current event to schedule. Return true on
679 static bool __perf_sched_find_counter(struct perf_sched *sched)
681 struct event_constraint *c;
684 if (!sched->state.unassigned)
687 if (sched->state.event >= sched->max_events)
690 c = sched->events[sched->state.event]->hw.constraint;
691 /* Prefer fixed purpose counters */
692 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
693 idx = INTEL_PMC_IDX_FIXED;
694 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
695 if (!__test_and_set_bit(idx, sched->state.used))
699 /* Grab the first unused counter starting with idx */
700 idx = sched->state.counter;
701 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
702 if (!__test_and_set_bit(idx, sched->state.used))
709 sched->state.counter = idx;
712 perf_sched_save_state(sched);
717 static bool perf_sched_find_counter(struct perf_sched *sched)
719 while (!__perf_sched_find_counter(sched)) {
720 if (!perf_sched_restore_state(sched))
728 * Go through all unassigned events and find the next one to schedule.
729 * Take events with the least weight first. Return true on success.
731 static bool perf_sched_next_event(struct perf_sched *sched)
733 struct event_constraint *c;
735 if (!sched->state.unassigned || !--sched->state.unassigned)
740 sched->state.event++;
741 if (sched->state.event >= sched->max_events) {
743 sched->state.event = 0;
744 sched->state.weight++;
745 if (sched->state.weight > sched->max_weight)
748 c = sched->events[sched->state.event]->hw.constraint;
749 } while (c->weight != sched->state.weight);
751 sched->state.counter = 0; /* start with first counter */
757 * Assign a counter for each event.
759 int perf_assign_events(struct perf_event **events, int n,
760 int wmin, int wmax, int *assign)
762 struct perf_sched sched;
764 perf_sched_init(&sched, events, n, wmin, wmax);
767 if (!perf_sched_find_counter(&sched))
770 assign[sched.state.event] = sched.state.counter;
771 } while (perf_sched_next_event(&sched));
773 return sched.state.unassigned;
775 EXPORT_SYMBOL_GPL(perf_assign_events);
777 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
779 struct event_constraint *c;
780 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
781 struct perf_event *e;
782 int i, wmin, wmax, unsched = 0;
783 struct hw_perf_event *hwc;
785 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
787 if (x86_pmu.start_scheduling)
788 x86_pmu.start_scheduling(cpuc);
790 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
791 hwc = &cpuc->event_list[i]->hw;
792 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
795 wmin = min(wmin, c->weight);
796 wmax = max(wmax, c->weight);
800 * fastpath, try to reuse previous register
802 for (i = 0; i < n; i++) {
803 hwc = &cpuc->event_list[i]->hw;
810 /* constraint still honored */
811 if (!test_bit(hwc->idx, c->idxmsk))
814 /* not already used */
815 if (test_bit(hwc->idx, used_mask))
818 __set_bit(hwc->idx, used_mask);
820 assign[i] = hwc->idx;
825 unsched = perf_assign_events(cpuc->event_list, n, wmin,
829 * In case of success (unsched = 0), mark events as committed,
830 * so we do not put_constraint() in case new events are added
831 * and fail to be scheduled
833 * We invoke the lower level commit callback to lock the resource
835 * We do not need to do all of this in case we are called to
836 * validate an event group (assign == NULL)
838 if (!unsched && assign) {
839 for (i = 0; i < n; i++) {
840 e = cpuc->event_list[i];
841 e->hw.flags |= PERF_X86_EVENT_COMMITTED;
842 if (x86_pmu.commit_scheduling)
843 x86_pmu.commit_scheduling(cpuc, e, assign[i]);
847 if (!assign || unsched) {
849 for (i = 0; i < n; i++) {
850 e = cpuc->event_list[i];
852 * do not put_constraint() on comitted events,
853 * because they are good to go
855 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
859 * release events that failed scheduling
861 if (x86_pmu.put_event_constraints)
862 x86_pmu.put_event_constraints(cpuc, e);
866 if (x86_pmu.stop_scheduling)
867 x86_pmu.stop_scheduling(cpuc);
869 return unsched ? -EINVAL : 0;
873 * dogrp: true if must collect siblings events (group)
874 * returns total number of events and error code
876 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
878 struct perf_event *event;
881 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
883 /* current number of events already accepted */
886 if (is_x86_event(leader)) {
889 cpuc->event_list[n] = leader;
895 list_for_each_entry(event, &leader->sibling_list, group_entry) {
896 if (!is_x86_event(event) ||
897 event->state <= PERF_EVENT_STATE_OFF)
903 cpuc->event_list[n] = event;
909 static inline void x86_assign_hw_event(struct perf_event *event,
910 struct cpu_hw_events *cpuc, int i)
912 struct hw_perf_event *hwc = &event->hw;
914 hwc->idx = cpuc->assign[i];
915 hwc->last_cpu = smp_processor_id();
916 hwc->last_tag = ++cpuc->tags[i];
918 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
919 hwc->config_base = 0;
921 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
922 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
923 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
924 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
926 hwc->config_base = x86_pmu_config_addr(hwc->idx);
927 hwc->event_base = x86_pmu_event_addr(hwc->idx);
928 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
932 static inline int match_prev_assignment(struct hw_perf_event *hwc,
933 struct cpu_hw_events *cpuc,
936 return hwc->idx == cpuc->assign[i] &&
937 hwc->last_cpu == smp_processor_id() &&
938 hwc->last_tag == cpuc->tags[i];
941 static void x86_pmu_start(struct perf_event *event, int flags);
943 static void x86_pmu_enable(struct pmu *pmu)
945 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
946 struct perf_event *event;
947 struct hw_perf_event *hwc;
948 int i, added = cpuc->n_added;
950 if (!x86_pmu_initialized())
957 int n_running = cpuc->n_events - cpuc->n_added;
959 * apply assignment obtained either from
960 * hw_perf_group_sched_in() or x86_pmu_enable()
962 * step1: save events moving to new counters
964 for (i = 0; i < n_running; i++) {
965 event = cpuc->event_list[i];
969 * we can avoid reprogramming counter if:
970 * - assigned same counter as last time
971 * - running on same CPU as last time
972 * - no other event has used the counter since
974 if (hwc->idx == -1 ||
975 match_prev_assignment(hwc, cpuc, i))
979 * Ensure we don't accidentally enable a stopped
980 * counter simply because we rescheduled.
982 if (hwc->state & PERF_HES_STOPPED)
983 hwc->state |= PERF_HES_ARCH;
985 x86_pmu_stop(event, PERF_EF_UPDATE);
989 * step2: reprogram moved events into new counters
991 for (i = 0; i < cpuc->n_events; i++) {
992 event = cpuc->event_list[i];
995 if (!match_prev_assignment(hwc, cpuc, i))
996 x86_assign_hw_event(event, cpuc, i);
997 else if (i < n_running)
1000 if (hwc->state & PERF_HES_ARCH)
1003 x86_pmu_start(event, PERF_EF_RELOAD);
1006 perf_events_lapic_init();
1012 x86_pmu.enable_all(added);
1015 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1018 * Set the next IRQ period, based on the hwc->period_left value.
1019 * To be called with the event disabled in hw:
1021 int x86_perf_event_set_period(struct perf_event *event)
1023 struct hw_perf_event *hwc = &event->hw;
1024 s64 left = local64_read(&hwc->period_left);
1025 s64 period = hwc->sample_period;
1026 int ret = 0, idx = hwc->idx;
1028 if (idx == INTEL_PMC_IDX_FIXED_BTS)
1032 * If we are way outside a reasonable range then just skip forward:
1034 if (unlikely(left <= -period)) {
1036 local64_set(&hwc->period_left, left);
1037 hwc->last_period = period;
1041 if (unlikely(left <= 0)) {
1043 local64_set(&hwc->period_left, left);
1044 hwc->last_period = period;
1048 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1050 if (unlikely(left < 2))
1053 if (left > x86_pmu.max_period)
1054 left = x86_pmu.max_period;
1056 if (x86_pmu.limit_period)
1057 left = x86_pmu.limit_period(event, left);
1059 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1062 * The hw event starts counting from this event offset,
1063 * mark it to be able to extra future deltas:
1065 local64_set(&hwc->prev_count, (u64)-left);
1067 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1070 * Due to erratum on certan cpu we need
1071 * a second write to be sure the register
1072 * is updated properly
1074 if (x86_pmu.perfctr_second_write) {
1075 wrmsrl(hwc->event_base,
1076 (u64)(-left) & x86_pmu.cntval_mask);
1079 perf_event_update_userpage(event);
1084 void x86_pmu_enable_event(struct perf_event *event)
1086 if (__this_cpu_read(cpu_hw_events.enabled))
1087 __x86_pmu_enable_event(&event->hw,
1088 ARCH_PERFMON_EVENTSEL_ENABLE);
1092 * Add a single event to the PMU.
1094 * The event is added to the group of enabled events
1095 * but only if it can be scehduled with existing events.
1097 static int x86_pmu_add(struct perf_event *event, int flags)
1099 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1100 struct hw_perf_event *hwc;
1101 int assign[X86_PMC_IDX_MAX];
1106 n0 = cpuc->n_events;
1107 ret = n = collect_events(cpuc, event, false);
1111 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1112 if (!(flags & PERF_EF_START))
1113 hwc->state |= PERF_HES_ARCH;
1116 * If group events scheduling transaction was started,
1117 * skip the schedulability test here, it will be performed
1118 * at commit time (->commit_txn) as a whole.
1120 if (cpuc->group_flag & PERF_EVENT_TXN)
1123 ret = x86_pmu.schedule_events(cpuc, n, assign);
1127 * copy new assignment, now we know it is possible
1128 * will be used by hw_perf_enable()
1130 memcpy(cpuc->assign, assign, n*sizeof(int));
1134 * Commit the collect_events() state. See x86_pmu_del() and
1138 cpuc->n_added += n - n0;
1139 cpuc->n_txn += n - n0;
1146 static void x86_pmu_start(struct perf_event *event, int flags)
1148 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1149 int idx = event->hw.idx;
1151 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1154 if (WARN_ON_ONCE(idx == -1))
1157 if (flags & PERF_EF_RELOAD) {
1158 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1159 x86_perf_event_set_period(event);
1162 event->hw.state = 0;
1164 cpuc->events[idx] = event;
1165 __set_bit(idx, cpuc->active_mask);
1166 __set_bit(idx, cpuc->running);
1167 x86_pmu.enable(event);
1168 perf_event_update_userpage(event);
1171 void perf_event_print_debug(void)
1173 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1175 struct cpu_hw_events *cpuc;
1176 unsigned long flags;
1179 if (!x86_pmu.num_counters)
1182 local_irq_save(flags);
1184 cpu = smp_processor_id();
1185 cpuc = &per_cpu(cpu_hw_events, cpu);
1187 if (x86_pmu.version >= 2) {
1188 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1189 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1190 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1191 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1194 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1195 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1196 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1197 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1198 if (x86_pmu.pebs_constraints) {
1199 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1200 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1202 if (x86_pmu.lbr_nr) {
1203 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1204 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1207 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1209 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1210 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1211 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1213 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1215 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1216 cpu, idx, pmc_ctrl);
1217 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1218 cpu, idx, pmc_count);
1219 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1220 cpu, idx, prev_left);
1222 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1223 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1225 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1226 cpu, idx, pmc_count);
1228 local_irq_restore(flags);
1231 void x86_pmu_stop(struct perf_event *event, int flags)
1233 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1234 struct hw_perf_event *hwc = &event->hw;
1236 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1237 x86_pmu.disable(event);
1238 cpuc->events[hwc->idx] = NULL;
1239 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1240 hwc->state |= PERF_HES_STOPPED;
1243 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1245 * Drain the remaining delta count out of a event
1246 * that we are disabling:
1248 x86_perf_event_update(event);
1249 hwc->state |= PERF_HES_UPTODATE;
1253 static void x86_pmu_del(struct perf_event *event, int flags)
1255 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1259 * event is descheduled
1261 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1264 * If we're called during a txn, we don't need to do anything.
1265 * The events never got scheduled and ->cancel_txn will truncate
1268 * XXX assumes any ->del() called during a TXN will only be on
1269 * an event added during that same TXN.
1271 if (cpuc->group_flag & PERF_EVENT_TXN)
1275 * Not a TXN, therefore cleanup properly.
1277 x86_pmu_stop(event, PERF_EF_UPDATE);
1279 for (i = 0; i < cpuc->n_events; i++) {
1280 if (event == cpuc->event_list[i])
1284 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1287 /* If we have a newly added event; make sure to decrease n_added. */
1288 if (i >= cpuc->n_events - cpuc->n_added)
1291 if (x86_pmu.put_event_constraints)
1292 x86_pmu.put_event_constraints(cpuc, event);
1294 /* Delete the array entry. */
1295 while (++i < cpuc->n_events)
1296 cpuc->event_list[i-1] = cpuc->event_list[i];
1299 perf_event_update_userpage(event);
1302 int x86_pmu_handle_irq(struct pt_regs *regs)
1304 struct perf_sample_data data;
1305 struct cpu_hw_events *cpuc;
1306 struct perf_event *event;
1307 int idx, handled = 0;
1310 cpuc = this_cpu_ptr(&cpu_hw_events);
1313 * Some chipsets need to unmask the LVTPC in a particular spot
1314 * inside the nmi handler. As a result, the unmasking was pushed
1315 * into all the nmi handlers.
1317 * This generic handler doesn't seem to have any issues where the
1318 * unmasking occurs so it was left at the top.
1320 apic_write(APIC_LVTPC, APIC_DM_NMI);
1322 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1323 if (!test_bit(idx, cpuc->active_mask)) {
1325 * Though we deactivated the counter some cpus
1326 * might still deliver spurious interrupts still
1327 * in flight. Catch them:
1329 if (__test_and_clear_bit(idx, cpuc->running))
1334 event = cpuc->events[idx];
1336 val = x86_perf_event_update(event);
1337 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1344 perf_sample_data_init(&data, 0, event->hw.last_period);
1346 if (!x86_perf_event_set_period(event))
1349 if (perf_event_overflow(event, &data, regs))
1350 x86_pmu_stop(event, 0);
1354 inc_irq_stat(apic_perf_irqs);
1359 void perf_events_lapic_init(void)
1361 if (!x86_pmu.apic || !x86_pmu_initialized())
1365 * Always use NMI for PMU
1367 apic_write(APIC_LVTPC, APIC_DM_NMI);
1371 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1377 if (!atomic_read(&active_events))
1380 start_clock = sched_clock();
1381 ret = x86_pmu.handle_irq(regs);
1382 finish_clock = sched_clock();
1384 perf_sample_event_took(finish_clock - start_clock);
1388 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1390 struct event_constraint emptyconstraint;
1391 struct event_constraint unconstrained;
1394 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1396 unsigned int cpu = (long)hcpu;
1397 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1398 int i, ret = NOTIFY_OK;
1400 switch (action & ~CPU_TASKS_FROZEN) {
1401 case CPU_UP_PREPARE:
1402 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1403 cpuc->kfree_on_online[i] = NULL;
1404 if (x86_pmu.cpu_prepare)
1405 ret = x86_pmu.cpu_prepare(cpu);
1409 if (x86_pmu.cpu_starting)
1410 x86_pmu.cpu_starting(cpu);
1414 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1415 kfree(cpuc->kfree_on_online[i]);
1416 cpuc->kfree_on_online[i] = NULL;
1421 if (x86_pmu.cpu_dying)
1422 x86_pmu.cpu_dying(cpu);
1425 case CPU_UP_CANCELED:
1427 if (x86_pmu.cpu_dead)
1428 x86_pmu.cpu_dead(cpu);
1438 static void __init pmu_check_apic(void)
1444 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1445 pr_info("no hardware sampling interrupt available.\n");
1448 * If we have a PMU initialized but no APIC
1449 * interrupts, we cannot sample hardware
1450 * events (user-space has to fall back and
1451 * sample via a hrtimer based software event):
1453 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1457 static struct attribute_group x86_pmu_format_group = {
1463 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1464 * out of events_attr attributes.
1466 static void __init filter_events(struct attribute **attrs)
1468 struct device_attribute *d;
1469 struct perf_pmu_events_attr *pmu_attr;
1472 for (i = 0; attrs[i]; i++) {
1473 d = (struct device_attribute *)attrs[i];
1474 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1476 if (pmu_attr->event_str)
1478 if (x86_pmu.event_map(i))
1481 for (j = i; attrs[j]; j++)
1482 attrs[j] = attrs[j + 1];
1484 /* Check the shifted attr. */
1489 /* Merge two pointer arrays */
1490 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1492 struct attribute **new;
1495 for (j = 0; a[j]; j++)
1497 for (i = 0; b[i]; i++)
1501 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1506 for (i = 0; a[i]; i++)
1508 for (i = 0; b[i]; i++)
1515 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1518 struct perf_pmu_events_attr *pmu_attr = \
1519 container_of(attr, struct perf_pmu_events_attr, attr);
1520 u64 config = x86_pmu.event_map(pmu_attr->id);
1522 /* string trumps id */
1523 if (pmu_attr->event_str)
1524 return sprintf(page, "%s", pmu_attr->event_str);
1526 return x86_pmu.events_sysfs_show(page, config);
1529 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1530 EVENT_ATTR(instructions, INSTRUCTIONS );
1531 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1532 EVENT_ATTR(cache-misses, CACHE_MISSES );
1533 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1534 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1535 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1536 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1537 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1538 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1540 static struct attribute *empty_attrs;
1542 static struct attribute *events_attr[] = {
1543 EVENT_PTR(CPU_CYCLES),
1544 EVENT_PTR(INSTRUCTIONS),
1545 EVENT_PTR(CACHE_REFERENCES),
1546 EVENT_PTR(CACHE_MISSES),
1547 EVENT_PTR(BRANCH_INSTRUCTIONS),
1548 EVENT_PTR(BRANCH_MISSES),
1549 EVENT_PTR(BUS_CYCLES),
1550 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1551 EVENT_PTR(STALLED_CYCLES_BACKEND),
1552 EVENT_PTR(REF_CPU_CYCLES),
1556 static struct attribute_group x86_pmu_events_group = {
1558 .attrs = events_attr,
1561 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1563 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1564 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1565 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1566 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1567 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1568 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1572 * We have whole page size to spend and just little data
1573 * to write, so we can safely use sprintf.
1575 ret = sprintf(page, "event=0x%02llx", event);
1578 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1581 ret += sprintf(page + ret, ",edge");
1584 ret += sprintf(page + ret, ",pc");
1587 ret += sprintf(page + ret, ",any");
1590 ret += sprintf(page + ret, ",inv");
1593 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1595 ret += sprintf(page + ret, "\n");
1600 static int __init init_hw_perf_events(void)
1602 struct x86_pmu_quirk *quirk;
1605 pr_info("Performance Events: ");
1607 switch (boot_cpu_data.x86_vendor) {
1608 case X86_VENDOR_INTEL:
1609 err = intel_pmu_init();
1611 case X86_VENDOR_AMD:
1612 err = amd_pmu_init();
1618 pr_cont("no PMU driver, software events only.\n");
1624 /* sanity check that the hardware exists or is emulated */
1625 if (!check_hw_exists())
1628 pr_cont("%s PMU driver.\n", x86_pmu.name);
1630 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1632 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1635 if (!x86_pmu.intel_ctrl)
1636 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1638 perf_events_lapic_init();
1639 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1641 unconstrained = (struct event_constraint)
1642 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1643 0, x86_pmu.num_counters, 0, 0);
1645 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1647 if (x86_pmu.event_attrs)
1648 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1650 if (!x86_pmu.events_sysfs_show)
1651 x86_pmu_events_group.attrs = &empty_attrs;
1653 filter_events(x86_pmu_events_group.attrs);
1655 if (x86_pmu.cpu_events) {
1656 struct attribute **tmp;
1658 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1660 x86_pmu_events_group.attrs = tmp;
1663 pr_info("... version: %d\n", x86_pmu.version);
1664 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1665 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1666 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1667 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1668 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1669 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1671 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1672 perf_cpu_notifier(x86_pmu_notifier);
1676 early_initcall(init_hw_perf_events);
1678 static inline void x86_pmu_read(struct perf_event *event)
1680 x86_perf_event_update(event);
1684 * Start group events scheduling transaction
1685 * Set the flag to make pmu::enable() not perform the
1686 * schedulability test, it will be performed at commit time
1688 static void x86_pmu_start_txn(struct pmu *pmu)
1690 perf_pmu_disable(pmu);
1691 __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1692 __this_cpu_write(cpu_hw_events.n_txn, 0);
1696 * Stop group events scheduling transaction
1697 * Clear the flag and pmu::enable() will perform the
1698 * schedulability test.
1700 static void x86_pmu_cancel_txn(struct pmu *pmu)
1702 __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1704 * Truncate collected array by the number of events added in this
1705 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1707 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1708 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1709 perf_pmu_enable(pmu);
1713 * Commit group events scheduling transaction
1714 * Perform the group schedulability test as a whole
1715 * Return 0 if success
1717 * Does not cancel the transaction on failure; expects the caller to do this.
1719 static int x86_pmu_commit_txn(struct pmu *pmu)
1721 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1722 int assign[X86_PMC_IDX_MAX];
1727 if (!x86_pmu_initialized())
1730 ret = x86_pmu.schedule_events(cpuc, n, assign);
1735 * copy new assignment, now we know it is possible
1736 * will be used by hw_perf_enable()
1738 memcpy(cpuc->assign, assign, n*sizeof(int));
1740 cpuc->group_flag &= ~PERF_EVENT_TXN;
1741 perf_pmu_enable(pmu);
1745 * a fake_cpuc is used to validate event groups. Due to
1746 * the extra reg logic, we need to also allocate a fake
1747 * per_core and per_cpu structure. Otherwise, group events
1748 * using extra reg may conflict without the kernel being
1749 * able to catch this when the last event gets added to
1752 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1754 kfree(cpuc->shared_regs);
1758 static struct cpu_hw_events *allocate_fake_cpuc(void)
1760 struct cpu_hw_events *cpuc;
1761 int cpu = raw_smp_processor_id();
1763 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1765 return ERR_PTR(-ENOMEM);
1767 /* only needed, if we have extra_regs */
1768 if (x86_pmu.extra_regs) {
1769 cpuc->shared_regs = allocate_shared_regs(cpu);
1770 if (!cpuc->shared_regs)
1776 free_fake_cpuc(cpuc);
1777 return ERR_PTR(-ENOMEM);
1781 * validate that we can schedule this event
1783 static int validate_event(struct perf_event *event)
1785 struct cpu_hw_events *fake_cpuc;
1786 struct event_constraint *c;
1789 fake_cpuc = allocate_fake_cpuc();
1790 if (IS_ERR(fake_cpuc))
1791 return PTR_ERR(fake_cpuc);
1793 c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1795 if (!c || !c->weight)
1798 if (x86_pmu.put_event_constraints)
1799 x86_pmu.put_event_constraints(fake_cpuc, event);
1801 free_fake_cpuc(fake_cpuc);
1807 * validate a single event group
1809 * validation include:
1810 * - check events are compatible which each other
1811 * - events do not compete for the same counter
1812 * - number of events <= number of counters
1814 * validation ensures the group can be loaded onto the
1815 * PMU if it was the only group available.
1817 static int validate_group(struct perf_event *event)
1819 struct perf_event *leader = event->group_leader;
1820 struct cpu_hw_events *fake_cpuc;
1821 int ret = -EINVAL, n;
1823 fake_cpuc = allocate_fake_cpuc();
1824 if (IS_ERR(fake_cpuc))
1825 return PTR_ERR(fake_cpuc);
1827 * the event is not yet connected with its
1828 * siblings therefore we must first collect
1829 * existing siblings, then add the new event
1830 * before we can simulate the scheduling
1832 n = collect_events(fake_cpuc, leader, true);
1836 fake_cpuc->n_events = n;
1837 n = collect_events(fake_cpuc, event, false);
1841 fake_cpuc->n_events = n;
1843 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1846 free_fake_cpuc(fake_cpuc);
1850 static int x86_pmu_event_init(struct perf_event *event)
1855 switch (event->attr.type) {
1857 case PERF_TYPE_HARDWARE:
1858 case PERF_TYPE_HW_CACHE:
1865 err = __x86_pmu_event_init(event);
1868 * we temporarily connect event to its pmu
1869 * such that validate_group() can classify
1870 * it as an x86 event using is_x86_event()
1875 if (event->group_leader != event)
1876 err = validate_group(event);
1878 err = validate_event(event);
1884 event->destroy(event);
1887 if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1888 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1893 static void refresh_pce(void *ignored)
1896 load_mm_cr4(current->mm);
1899 static void x86_pmu_event_mapped(struct perf_event *event)
1901 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1904 if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1)
1905 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1908 static void x86_pmu_event_unmapped(struct perf_event *event)
1913 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1916 if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed))
1917 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1920 static int x86_pmu_event_idx(struct perf_event *event)
1922 int idx = event->hw.idx;
1924 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1927 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1928 idx -= INTEL_PMC_IDX_FIXED;
1935 static ssize_t get_attr_rdpmc(struct device *cdev,
1936 struct device_attribute *attr,
1939 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1942 static ssize_t set_attr_rdpmc(struct device *cdev,
1943 struct device_attribute *attr,
1944 const char *buf, size_t count)
1949 ret = kstrtoul(buf, 0, &val);
1956 if (x86_pmu.attr_rdpmc_broken)
1959 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
1961 * Changing into or out of always available, aka
1962 * perf-event-bypassing mode. This path is extremely slow,
1963 * but only root can trigger it, so it's okay.
1966 static_key_slow_inc(&rdpmc_always_available);
1968 static_key_slow_dec(&rdpmc_always_available);
1969 on_each_cpu(refresh_pce, NULL, 1);
1972 x86_pmu.attr_rdpmc = val;
1977 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1979 static struct attribute *x86_pmu_attrs[] = {
1980 &dev_attr_rdpmc.attr,
1984 static struct attribute_group x86_pmu_attr_group = {
1985 .attrs = x86_pmu_attrs,
1988 static const struct attribute_group *x86_pmu_attr_groups[] = {
1989 &x86_pmu_attr_group,
1990 &x86_pmu_format_group,
1991 &x86_pmu_events_group,
1995 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
1997 if (x86_pmu.sched_task)
1998 x86_pmu.sched_task(ctx, sched_in);
2001 void perf_check_microcode(void)
2003 if (x86_pmu.check_microcode)
2004 x86_pmu.check_microcode();
2006 EXPORT_SYMBOL_GPL(perf_check_microcode);
2008 static struct pmu pmu = {
2009 .pmu_enable = x86_pmu_enable,
2010 .pmu_disable = x86_pmu_disable,
2012 .attr_groups = x86_pmu_attr_groups,
2014 .event_init = x86_pmu_event_init,
2016 .event_mapped = x86_pmu_event_mapped,
2017 .event_unmapped = x86_pmu_event_unmapped,
2021 .start = x86_pmu_start,
2022 .stop = x86_pmu_stop,
2023 .read = x86_pmu_read,
2025 .start_txn = x86_pmu_start_txn,
2026 .cancel_txn = x86_pmu_cancel_txn,
2027 .commit_txn = x86_pmu_commit_txn,
2029 .event_idx = x86_pmu_event_idx,
2030 .sched_task = x86_pmu_sched_task,
2031 .task_ctx_size = sizeof(struct x86_perf_task_context),
2034 void arch_perf_update_userpage(struct perf_event *event,
2035 struct perf_event_mmap_page *userpg, u64 now)
2037 struct cyc2ns_data *data;
2039 userpg->cap_user_time = 0;
2040 userpg->cap_user_time_zero = 0;
2041 userpg->cap_user_rdpmc =
2042 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2043 userpg->pmc_width = x86_pmu.cntval_bits;
2045 if (!sched_clock_stable())
2048 data = cyc2ns_read_begin();
2051 * Internal timekeeping for enabled/running/stopped times
2052 * is always in the local_clock domain.
2054 userpg->cap_user_time = 1;
2055 userpg->time_mult = data->cyc2ns_mul;
2056 userpg->time_shift = data->cyc2ns_shift;
2057 userpg->time_offset = data->cyc2ns_offset - now;
2060 * cap_user_time_zero doesn't make sense when we're using a different
2061 * time base for the records.
2063 if (event->clock == &local_clock) {
2064 userpg->cap_user_time_zero = 1;
2065 userpg->time_zero = data->cyc2ns_offset;
2068 cyc2ns_read_end(data);
2075 static int backtrace_stack(void *data, char *name)
2080 static void backtrace_address(void *data, unsigned long addr, int reliable)
2082 struct perf_callchain_entry *entry = data;
2084 perf_callchain_store(entry, addr);
2087 static const struct stacktrace_ops backtrace_ops = {
2088 .stack = backtrace_stack,
2089 .address = backtrace_address,
2090 .walk_stack = print_context_stack_bp,
2094 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2096 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2097 /* TODO: We don't support guest os callchain now */
2101 perf_callchain_store(entry, regs->ip);
2103 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2107 valid_user_frame(const void __user *fp, unsigned long size)
2109 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2112 static unsigned long get_segment_base(unsigned int segment)
2114 struct desc_struct *desc;
2115 int idx = segment >> 3;
2117 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2118 if (idx > LDT_ENTRIES)
2121 if (idx > current->active_mm->context.size)
2124 desc = current->active_mm->context.ldt;
2126 if (idx > GDT_ENTRIES)
2129 desc = raw_cpu_ptr(gdt_page.gdt);
2132 return get_desc_base(desc + idx);
2135 #ifdef CONFIG_COMPAT
2137 #include <asm/compat.h>
2140 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2142 /* 32-bit process in 64-bit kernel. */
2143 unsigned long ss_base, cs_base;
2144 struct stack_frame_ia32 frame;
2145 const void __user *fp;
2147 if (!test_thread_flag(TIF_IA32))
2150 cs_base = get_segment_base(regs->cs);
2151 ss_base = get_segment_base(regs->ss);
2153 fp = compat_ptr(ss_base + regs->bp);
2154 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2155 unsigned long bytes;
2156 frame.next_frame = 0;
2157 frame.return_address = 0;
2159 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2163 if (!valid_user_frame(fp, sizeof(frame)))
2166 perf_callchain_store(entry, cs_base + frame.return_address);
2167 fp = compat_ptr(ss_base + frame.next_frame);
2173 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2180 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2182 struct stack_frame frame;
2183 const void __user *fp;
2185 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2186 /* TODO: We don't support guest os callchain now */
2191 * We don't know what to do with VM86 stacks.. ignore them for now.
2193 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2196 fp = (void __user *)regs->bp;
2198 perf_callchain_store(entry, regs->ip);
2203 if (perf_callchain_user32(regs, entry))
2206 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2207 unsigned long bytes;
2208 frame.next_frame = NULL;
2209 frame.return_address = 0;
2211 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2215 if (!valid_user_frame(fp, sizeof(frame)))
2218 perf_callchain_store(entry, frame.return_address);
2219 fp = frame.next_frame;
2224 * Deal with code segment offsets for the various execution modes:
2226 * VM86 - the good olde 16 bit days, where the linear address is
2227 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2229 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2230 * to figure out what the 32bit base address is.
2232 * X32 - has TIF_X32 set, but is running in x86_64
2234 * X86_64 - CS,DS,SS,ES are all zero based.
2236 static unsigned long code_segment_base(struct pt_regs *regs)
2239 * For IA32 we look at the GDT/LDT segment base to convert the
2240 * effective IP to a linear address.
2243 #ifdef CONFIG_X86_32
2245 * If we are in VM86 mode, add the segment offset to convert to a
2248 if (regs->flags & X86_VM_MASK)
2249 return 0x10 * regs->cs;
2251 if (user_mode(regs) && regs->cs != __USER_CS)
2252 return get_segment_base(regs->cs);
2254 if (user_mode(regs) && !user_64bit_mode(regs) &&
2255 regs->cs != __USER32_CS)
2256 return get_segment_base(regs->cs);
2261 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2263 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2264 return perf_guest_cbs->get_guest_ip();
2266 return regs->ip + code_segment_base(regs);
2269 unsigned long perf_misc_flags(struct pt_regs *regs)
2273 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2274 if (perf_guest_cbs->is_user_mode())
2275 misc |= PERF_RECORD_MISC_GUEST_USER;
2277 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2279 if (user_mode(regs))
2280 misc |= PERF_RECORD_MISC_USER;
2282 misc |= PERF_RECORD_MISC_KERNEL;
2285 if (regs->flags & PERF_EFLAGS_EXACT)
2286 misc |= PERF_RECORD_MISC_EXACT_IP;
2291 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2293 cap->version = x86_pmu.version;
2294 cap->num_counters_gp = x86_pmu.num_counters;
2295 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2296 cap->bit_width_gp = x86_pmu.cntval_bits;
2297 cap->bit_width_fixed = x86_pmu.cntval_bits;
2298 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2299 cap->events_mask_len = x86_pmu.events_mask_len;
2301 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);