2 * Intel CPU Microcode Update Driver for Linux
4 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
5 * 2006 Shaohua Li <shaohua.li@intel.com>
7 * Intel CPU microcode early update for Linux
9 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
10 * H Peter Anvin" <hpa@zytor.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
19 * This needs to be before all headers so that pr_debug in printk.h doesn't turn
20 * printk calls into no_printk().
24 #define pr_fmt(fmt) "microcode: " fmt
26 #include <linux/earlycpio.h>
27 #include <linux/firmware.h>
28 #include <linux/uaccess.h>
29 #include <linux/vmalloc.h>
30 #include <linux/initrd.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/cpu.h>
36 #include <asm/microcode_intel.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/setup.h>
42 static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin";
44 /* Current microcode patch used in early patching on the APs. */
45 static struct microcode_intel *intel_ucode_patch;
47 static inline bool cpu_signatures_match(unsigned int s1, unsigned int p1,
48 unsigned int s2, unsigned int p2)
53 /* Processor flags are either both 0 ... */
57 /* ... or they intersect. */
62 * Returns 1 if update has been found, 0 otherwise.
64 static int find_matching_signature(void *mc, unsigned int csig, int cpf)
66 struct microcode_header_intel *mc_hdr = mc;
67 struct extended_sigtable *ext_hdr;
68 struct extended_signature *ext_sig;
71 if (cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf))
74 /* Look for ext. headers: */
75 if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE)
78 ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE;
79 ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE;
81 for (i = 0; i < ext_hdr->count; i++) {
82 if (cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf))
90 * Returns 1 if update has been found, 0 otherwise.
92 static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev)
94 struct microcode_header_intel *mc_hdr = mc;
96 if (mc_hdr->rev <= new_rev)
99 return find_matching_signature(mc, csig, cpf);
103 * Given CPU signature and a microcode patch, this function finds if the
104 * microcode patch has matching family and model with the CPU.
106 * %true - if there's a match
109 static bool microcode_matches(struct microcode_header_intel *mc_header,
112 unsigned long total_size = get_totalsize(mc_header);
113 unsigned long data_size = get_datasize(mc_header);
114 struct extended_sigtable *ext_header;
115 unsigned int fam_ucode, model_ucode;
116 struct extended_signature *ext_sig;
117 unsigned int fam, model;
120 fam = x86_family(sig);
121 model = x86_model(sig);
123 fam_ucode = x86_family(mc_header->sig);
124 model_ucode = x86_model(mc_header->sig);
126 if (fam == fam_ucode && model == model_ucode)
129 /* Look for ext. headers: */
130 if (total_size <= data_size + MC_HEADER_SIZE)
133 ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE;
134 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
135 ext_sigcount = ext_header->count;
137 for (i = 0; i < ext_sigcount; i++) {
138 fam_ucode = x86_family(ext_sig->sig);
139 model_ucode = x86_model(ext_sig->sig);
141 if (fam == fam_ucode && model == model_ucode)
149 static struct ucode_patch *__alloc_microcode_buf(void *data, unsigned int size)
151 struct ucode_patch *p;
153 p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL);
155 return ERR_PTR(-ENOMEM);
157 p->data = kmemdup(data, size, GFP_KERNEL);
160 return ERR_PTR(-ENOMEM);
166 static void save_microcode_patch(void *data, unsigned int size)
168 struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
169 struct ucode_patch *iter, *tmp, *p = NULL;
170 bool prev_found = false;
171 unsigned int sig, pf;
173 mc_hdr = (struct microcode_header_intel *)data;
175 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) {
176 mc_saved_hdr = (struct microcode_header_intel *)iter->data;
177 sig = mc_saved_hdr->sig;
178 pf = mc_saved_hdr->pf;
180 if (find_matching_signature(data, sig, pf)) {
183 if (mc_hdr->rev <= mc_saved_hdr->rev)
186 p = __alloc_microcode_buf(data, size);
188 pr_err("Error allocating buffer %p\n", data);
190 list_replace(&iter->plist, &p->plist);
195 * There weren't any previous patches found in the list cache; save the
199 p = __alloc_microcode_buf(data, size);
201 pr_err("Error allocating buffer for %p\n", data);
203 list_add_tail(&p->plist, µcode_cache);
207 * Save for early loading. On 32-bit, that needs to be a physical
208 * address as the APs are running from physical addresses, before
209 * paging has been enabled.
212 if (IS_ENABLED(CONFIG_X86_32))
213 intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data);
215 intel_ucode_patch = p->data;
219 static int microcode_sanity_check(void *mc, int print_err)
221 unsigned long total_size, data_size, ext_table_size;
222 struct microcode_header_intel *mc_header = mc;
223 struct extended_sigtable *ext_header = NULL;
224 u32 sum, orig_sum, ext_sigcount = 0, i;
225 struct extended_signature *ext_sig;
227 total_size = get_totalsize(mc_header);
228 data_size = get_datasize(mc_header);
230 if (data_size + MC_HEADER_SIZE > total_size) {
232 pr_err("Error: bad microcode data file size.\n");
236 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
238 pr_err("Error: invalid/unknown microcode update format.\n");
242 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
243 if (ext_table_size) {
244 u32 ext_table_sum = 0;
247 if ((ext_table_size < EXT_HEADER_SIZE)
248 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
250 pr_err("Error: truncated extended signature table.\n");
254 ext_header = mc + MC_HEADER_SIZE + data_size;
255 if (ext_table_size != exttable_size(ext_header)) {
257 pr_err("Error: extended signature table size mismatch.\n");
261 ext_sigcount = ext_header->count;
264 * Check extended table checksum: the sum of all dwords that
265 * comprise a valid table must be 0.
267 ext_tablep = (u32 *)ext_header;
269 i = ext_table_size / sizeof(u32);
271 ext_table_sum += ext_tablep[i];
275 pr_warn("Bad extended signature table checksum, aborting.\n");
281 * Calculate the checksum of update data and header. The checksum of
282 * valid update data and header including the extended signature table
286 i = (MC_HEADER_SIZE + data_size) / sizeof(u32);
288 orig_sum += ((u32 *)mc)[i];
292 pr_err("Bad microcode data checksum, aborting.\n");
300 * Check extended signature checksum: 0 => valid.
302 for (i = 0; i < ext_sigcount; i++) {
303 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
304 EXT_SIGNATURE_SIZE * i;
306 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) -
307 (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
310 pr_err("Bad extended signature checksum, aborting.\n");
318 * Get microcode matching with BSP's model. Only CPUs with the same model as
319 * BSP can stay in the platform.
321 static struct microcode_intel *
322 scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save)
324 struct microcode_header_intel *mc_header;
325 struct microcode_intel *patch = NULL;
326 unsigned int mc_size;
329 if (size < sizeof(struct microcode_header_intel))
332 mc_header = (struct microcode_header_intel *)data;
334 mc_size = get_totalsize(mc_header);
337 microcode_sanity_check(data, 0) < 0)
342 if (!microcode_matches(mc_header, uci->cpu_sig.sig)) {
348 save_microcode_patch(data, mc_size);
354 if (!has_newer_microcode(data,
361 struct microcode_header_intel *phdr = &patch->hdr;
363 if (!has_newer_microcode(data,
370 /* We have a newer patch, save it. */
383 static int collect_cpu_info_early(struct ucode_cpu_info *uci)
386 unsigned int family, model;
387 struct cpu_signature csig = { 0 };
388 unsigned int eax, ebx, ecx, edx;
390 memset(uci, 0, sizeof(*uci));
394 native_cpuid(&eax, &ebx, &ecx, &edx);
397 family = x86_family(eax);
398 model = x86_model(eax);
400 if ((model >= 5) || (family > 6)) {
401 /* get processor flags from MSR 0x17 */
402 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
403 csig.pf = 1 << ((val[1] >> 18) & 7);
406 csig.rev = intel_get_microcode_revision();
414 static void show_saved_mc(void)
418 unsigned int sig, pf, rev, total_size, data_size, date;
419 struct ucode_cpu_info uci;
420 struct ucode_patch *p;
422 if (list_empty(µcode_cache)) {
423 pr_debug("no microcode data saved.\n");
427 collect_cpu_info_early(&uci);
429 sig = uci.cpu_sig.sig;
431 rev = uci.cpu_sig.rev;
432 pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev);
434 list_for_each_entry(p, µcode_cache, plist) {
435 struct microcode_header_intel *mc_saved_header;
436 struct extended_sigtable *ext_header;
437 struct extended_signature *ext_sig;
440 mc_saved_header = (struct microcode_header_intel *)p->data;
442 sig = mc_saved_header->sig;
443 pf = mc_saved_header->pf;
444 rev = mc_saved_header->rev;
445 date = mc_saved_header->date;
447 total_size = get_totalsize(mc_saved_header);
448 data_size = get_datasize(mc_saved_header);
450 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n",
451 i++, sig, pf, rev, total_size,
454 (date >> 16) & 0xff);
456 /* Look for ext. headers: */
457 if (total_size <= data_size + MC_HEADER_SIZE)
460 ext_header = (void *)mc_saved_header + data_size + MC_HEADER_SIZE;
461 ext_sigcount = ext_header->count;
462 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
464 for (j = 0; j < ext_sigcount; j++) {
468 pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n",
478 * Save this microcode patch. It will be loaded early when a CPU is
479 * hot-added or resumes.
481 static void save_mc_for_early(u8 *mc, unsigned int size)
483 #ifdef CONFIG_HOTPLUG_CPU
484 /* Synchronization during CPU hotplug. */
485 static DEFINE_MUTEX(x86_cpu_microcode_mutex);
487 mutex_lock(&x86_cpu_microcode_mutex);
489 save_microcode_patch(mc, size);
492 mutex_unlock(&x86_cpu_microcode_mutex);
496 static bool load_builtin_intel_microcode(struct cpio_data *cp)
498 unsigned int eax = 1, ebx, ecx = 0, edx;
501 if (IS_ENABLED(CONFIG_X86_32))
504 native_cpuid(&eax, &ebx, &ecx, &edx);
506 sprintf(name, "intel-ucode/%02x-%02x-%02x",
507 x86_family(eax), x86_model(eax), x86_stepping(eax));
509 return get_builtin_firmware(cp, name);
513 * Print ucode update info.
516 print_ucode_info(struct ucode_cpu_info *uci, unsigned int date)
518 pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n",
522 (date >> 16) & 0xff);
527 static int delay_ucode_info;
528 static int current_mc_date;
531 * Print early updated ucode info after printk works. This is delayed info dump.
533 void show_ucode_info_early(void)
535 struct ucode_cpu_info uci;
537 if (delay_ucode_info) {
538 collect_cpu_info_early(&uci);
539 print_ucode_info(&uci, current_mc_date);
540 delay_ucode_info = 0;
545 * At this point, we can not call printk() yet. Delay printing microcode info in
546 * show_ucode_info_early() until printk() works.
548 static void print_ucode(struct ucode_cpu_info *uci)
550 struct microcode_intel *mc;
551 int *delay_ucode_info_p;
552 int *current_mc_date_p;
558 delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info);
559 current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date);
561 *delay_ucode_info_p = 1;
562 *current_mc_date_p = mc->hdr.date;
567 * Flush global tlb. We only do this in x86_64 where paging has been enabled
568 * already and PGE should be enabled as well.
570 static inline void flush_tlb_early(void)
572 __native_flush_tlb_global_irq_disabled();
575 static inline void print_ucode(struct ucode_cpu_info *uci)
577 struct microcode_intel *mc;
583 print_ucode_info(uci, mc->hdr.date);
587 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
589 struct microcode_intel *mc;
596 /* write microcode via MSR 0x79 */
597 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
599 rev = intel_get_microcode_revision();
600 if (rev != mc->hdr.rev)
604 /* Flush global tlb. This is precaution. */
607 uci->cpu_sig.rev = rev;
612 print_ucode_info(uci, mc->hdr.date);
617 int __init save_microcode_in_initrd_intel(void)
619 struct ucode_cpu_info uci;
623 * initrd is going away, clear patch ptr. We will scan the microcode one
624 * last time before jettisoning and save a patch, if found. Then we will
625 * update that pointer too, with a stable patch address to use when
626 * resuming the cores.
628 intel_ucode_patch = NULL;
630 if (!load_builtin_intel_microcode(&cp))
631 cp = find_microcode_in_initrd(ucode_path, false);
633 if (!(cp.data && cp.size))
636 collect_cpu_info_early(&uci);
638 scan_microcode(cp.data, cp.size, &uci, true);
646 * @res_patch, output: a pointer to the patch we found.
648 static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci)
650 static const char *path;
654 if (IS_ENABLED(CONFIG_X86_32)) {
655 path = (const char *)__pa_nodebug(ucode_path);
662 /* try built-in microcode first */
663 if (!load_builtin_intel_microcode(&cp))
664 cp = find_microcode_in_initrd(path, use_pa);
666 if (!(cp.data && cp.size))
669 collect_cpu_info_early(uci);
671 return scan_microcode(cp.data, cp.size, uci, false);
674 void __init load_ucode_intel_bsp(void)
676 struct microcode_intel *patch;
677 struct ucode_cpu_info uci;
679 patch = __load_ucode_intel(&uci);
685 apply_microcode_early(&uci, true);
688 void load_ucode_intel_ap(void)
690 struct microcode_intel *patch, **iup;
691 struct ucode_cpu_info uci;
693 if (IS_ENABLED(CONFIG_X86_32))
694 iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch);
696 iup = &intel_ucode_patch;
700 patch = __load_ucode_intel(&uci);
709 if (apply_microcode_early(&uci, true)) {
710 /* Mixed-silicon system? Try to refetch the proper patch: */
717 static struct microcode_intel *find_patch(struct ucode_cpu_info *uci)
719 struct microcode_header_intel *phdr;
720 struct ucode_patch *iter, *tmp;
722 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) {
724 phdr = (struct microcode_header_intel *)iter->data;
726 if (phdr->rev <= uci->cpu_sig.rev)
729 if (!find_matching_signature(phdr,
739 void reload_ucode_intel(void)
741 struct microcode_intel *p;
742 struct ucode_cpu_info uci;
744 collect_cpu_info_early(&uci);
746 p = find_patch(&uci);
752 apply_microcode_early(&uci, false);
755 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
757 static struct cpu_signature prev;
758 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
761 memset(csig, 0, sizeof(*csig));
763 csig->sig = cpuid_eax(0x00000001);
765 if ((c->x86_model >= 5) || (c->x86 > 6)) {
766 /* get processor flags from MSR 0x17 */
767 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
768 csig->pf = 1 << ((val[1] >> 18) & 7);
771 csig->rev = c->microcode;
773 /* No extra locking on prev, races are harmless. */
774 if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) {
775 pr_info("sig=0x%x, pf=0x%x, revision=0x%x\n",
776 csig->sig, csig->pf, csig->rev);
783 static int apply_microcode_intel(int cpu)
785 struct microcode_intel *mc;
786 struct ucode_cpu_info *uci;
787 struct cpuinfo_x86 *c;
791 /* We should bind the task to the CPU */
792 if (WARN_ON(raw_smp_processor_id() != cpu))
795 uci = ucode_cpu_info + cpu;
798 /* Look for a newer patch in our cache: */
799 mc = find_patch(uci);
804 /* write microcode via MSR 0x79 */
805 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
807 rev = intel_get_microcode_revision();
809 if (rev != mc->hdr.rev) {
810 pr_err("CPU%d update to revision 0x%x failed\n",
815 if (rev != prev_rev) {
816 pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n",
818 mc->hdr.date & 0xffff,
820 (mc->hdr.date >> 16) & 0xff);
826 uci->cpu_sig.rev = rev;
832 static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
833 int (*get_ucode_data)(void *, const void *, size_t))
835 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
836 u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
837 int new_rev = uci->cpu_sig.rev;
838 unsigned int leftover = size;
839 unsigned int curr_mc_size = 0, new_mc_size = 0;
840 unsigned int csig, cpf;
843 struct microcode_header_intel mc_header;
844 unsigned int mc_size;
846 if (leftover < sizeof(mc_header)) {
847 pr_err("error! Truncated header in microcode data file\n");
851 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
854 mc_size = get_totalsize(&mc_header);
855 if (!mc_size || mc_size > leftover) {
856 pr_err("error! Bad data in microcode data file\n");
860 /* For performance reasons, reuse mc area when possible */
861 if (!mc || mc_size > curr_mc_size) {
863 mc = vmalloc(mc_size);
866 curr_mc_size = mc_size;
869 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
870 microcode_sanity_check(mc, 1) < 0) {
874 csig = uci->cpu_sig.sig;
875 cpf = uci->cpu_sig.pf;
876 if (has_newer_microcode(mc, csig, cpf, new_rev)) {
878 new_rev = mc_header.rev;
880 new_mc_size = mc_size;
881 mc = NULL; /* trigger new vmalloc */
884 ucode_ptr += mc_size;
899 uci->mc = (struct microcode_intel *)new_mc;
902 * If early loading microcode is supported, save this mc into
903 * permanent memory. So it will be loaded early when a CPU is hot added
906 save_mc_for_early(new_mc, new_mc_size);
908 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
909 cpu, new_rev, uci->cpu_sig.rev);
914 static int get_ucode_fw(void *to, const void *from, size_t n)
920 static enum ucode_state request_microcode_fw(int cpu, struct device *device,
924 struct cpuinfo_x86 *c = &cpu_data(cpu);
925 const struct firmware *firmware;
926 enum ucode_state ret;
928 sprintf(name, "intel-ucode/%02x-%02x-%02x",
929 c->x86, c->x86_model, c->x86_mask);
931 if (request_firmware_direct(&firmware, name, device)) {
932 pr_debug("data file %s load failed\n", name);
936 ret = generic_load_microcode(cpu, (void *)firmware->data,
937 firmware->size, &get_ucode_fw);
939 release_firmware(firmware);
944 static int get_ucode_user(void *to, const void *from, size_t n)
946 return copy_from_user(to, from, n);
949 static enum ucode_state
950 request_microcode_user(int cpu, const void __user *buf, size_t size)
952 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
955 static struct microcode_ops microcode_intel_ops = {
956 .request_microcode_user = request_microcode_user,
957 .request_microcode_fw = request_microcode_fw,
958 .collect_cpu_info = collect_cpu_info,
959 .apply_microcode = apply_microcode_intel,
962 struct microcode_ops * __init init_intel_microcode(void)
964 struct cpuinfo_x86 *c = &boot_cpu_data;
966 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
967 cpu_has(c, X86_FEATURE_IA64)) {
968 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
972 return µcode_intel_ops;