1 #ifndef _ASM_X86_MSR_INDEX_H
2 #define _ASM_X86_MSR_INDEX_H
5 * CPU model specific register (MSR) numbers.
7 * Do not add new entries to this file unless the definitions are shared
8 * between multiple compilation units.
11 /* x86-64 specific MSRs */
12 #define MSR_EFER 0xc0000080 /* extended feature register */
13 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
14 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
15 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
16 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
17 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
18 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
19 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
20 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
23 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
24 #define _EFER_LME 8 /* Long mode enable */
25 #define _EFER_LMA 10 /* Long mode active (read-only) */
26 #define _EFER_NX 11 /* No execute enable */
27 #define _EFER_SVME 12 /* Enable virtualization */
28 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
29 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
31 #define EFER_SCE (1<<_EFER_SCE)
32 #define EFER_LME (1<<_EFER_LME)
33 #define EFER_LMA (1<<_EFER_LMA)
34 #define EFER_NX (1<<_EFER_NX)
35 #define EFER_SVME (1<<_EFER_SVME)
36 #define EFER_LMSLE (1<<_EFER_LMSLE)
37 #define EFER_FFXSR (1<<_EFER_FFXSR)
39 /* Intel MSRs. Some also available on other CPUs */
41 #define MSR_PPIN_CTL 0x0000004e
42 #define MSR_PPIN 0x0000004f
44 #define MSR_IA32_PERFCTR0 0x000000c1
45 #define MSR_IA32_PERFCTR1 0x000000c2
46 #define MSR_FSB_FREQ 0x000000cd
47 #define MSR_PLATFORM_INFO 0x000000ce
48 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
49 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
51 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
52 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
53 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
54 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
55 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
56 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
58 #define MSR_MTRRcap 0x000000fe
59 #define MSR_IA32_BBL_CR_CTL 0x00000119
60 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
62 #define MSR_IA32_SYSENTER_CS 0x00000174
63 #define MSR_IA32_SYSENTER_ESP 0x00000175
64 #define MSR_IA32_SYSENTER_EIP 0x00000176
66 #define MSR_IA32_MCG_CAP 0x00000179
67 #define MSR_IA32_MCG_STATUS 0x0000017a
68 #define MSR_IA32_MCG_CTL 0x0000017b
69 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
71 #define MSR_OFFCORE_RSP_0 0x000001a6
72 #define MSR_OFFCORE_RSP_1 0x000001a7
73 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
74 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
75 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
77 #define MSR_LBR_SELECT 0x000001c8
78 #define MSR_LBR_TOS 0x000001c9
79 #define MSR_LBR_NHM_FROM 0x00000680
80 #define MSR_LBR_NHM_TO 0x000006c0
81 #define MSR_LBR_CORE_FROM 0x00000040
82 #define MSR_LBR_CORE_TO 0x00000060
84 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
85 #define LBR_INFO_MISPRED BIT_ULL(63)
86 #define LBR_INFO_IN_TX BIT_ULL(62)
87 #define LBR_INFO_ABORT BIT_ULL(61)
88 #define LBR_INFO_CYCLES 0xffff
90 #define MSR_IA32_PEBS_ENABLE 0x000003f1
91 #define MSR_IA32_DS_AREA 0x00000600
92 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
93 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
95 #define MSR_IA32_RTIT_CTL 0x00000570
96 #define MSR_IA32_RTIT_STATUS 0x00000571
97 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
98 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
99 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
100 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
101 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
102 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
103 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
104 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
105 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
106 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
107 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
109 #define MSR_MTRRfix64K_00000 0x00000250
110 #define MSR_MTRRfix16K_80000 0x00000258
111 #define MSR_MTRRfix16K_A0000 0x00000259
112 #define MSR_MTRRfix4K_C0000 0x00000268
113 #define MSR_MTRRfix4K_C8000 0x00000269
114 #define MSR_MTRRfix4K_D0000 0x0000026a
115 #define MSR_MTRRfix4K_D8000 0x0000026b
116 #define MSR_MTRRfix4K_E0000 0x0000026c
117 #define MSR_MTRRfix4K_E8000 0x0000026d
118 #define MSR_MTRRfix4K_F0000 0x0000026e
119 #define MSR_MTRRfix4K_F8000 0x0000026f
120 #define MSR_MTRRdefType 0x000002ff
122 #define MSR_IA32_CR_PAT 0x00000277
124 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
125 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
126 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
127 #define MSR_IA32_LASTINTFROMIP 0x000001dd
128 #define MSR_IA32_LASTINTTOIP 0x000001de
130 /* DEBUGCTLMSR bits (others vary by model): */
131 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
132 #define DEBUGCTLMSR_BTF_SHIFT 1
133 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
134 #define DEBUGCTLMSR_TR (1UL << 6)
135 #define DEBUGCTLMSR_BTS (1UL << 7)
136 #define DEBUGCTLMSR_BTINT (1UL << 8)
137 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
138 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
139 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
141 #define MSR_PEBS_FRONTEND 0x000003f7
143 #define MSR_IA32_POWER_CTL 0x000001fc
145 #define MSR_IA32_MC0_CTL 0x00000400
146 #define MSR_IA32_MC0_STATUS 0x00000401
147 #define MSR_IA32_MC0_ADDR 0x00000402
148 #define MSR_IA32_MC0_MISC 0x00000403
150 /* C-state Residency Counters */
151 #define MSR_PKG_C3_RESIDENCY 0x000003f8
152 #define MSR_PKG_C6_RESIDENCY 0x000003f9
153 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
154 #define MSR_PKG_C7_RESIDENCY 0x000003fa
155 #define MSR_CORE_C3_RESIDENCY 0x000003fc
156 #define MSR_CORE_C6_RESIDENCY 0x000003fd
157 #define MSR_CORE_C7_RESIDENCY 0x000003fe
158 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
159 #define MSR_PKG_C2_RESIDENCY 0x0000060d
160 #define MSR_PKG_C8_RESIDENCY 0x00000630
161 #define MSR_PKG_C9_RESIDENCY 0x00000631
162 #define MSR_PKG_C10_RESIDENCY 0x00000632
164 /* Interrupt Response Limit */
165 #define MSR_PKGC3_IRTL 0x0000060a
166 #define MSR_PKGC6_IRTL 0x0000060b
167 #define MSR_PKGC7_IRTL 0x0000060c
168 #define MSR_PKGC8_IRTL 0x00000633
169 #define MSR_PKGC9_IRTL 0x00000634
170 #define MSR_PKGC10_IRTL 0x00000635
172 /* Run Time Average Power Limiting (RAPL) Interface */
174 #define MSR_RAPL_POWER_UNIT 0x00000606
176 #define MSR_PKG_POWER_LIMIT 0x00000610
177 #define MSR_PKG_ENERGY_STATUS 0x00000611
178 #define MSR_PKG_PERF_STATUS 0x00000613
179 #define MSR_PKG_POWER_INFO 0x00000614
181 #define MSR_DRAM_POWER_LIMIT 0x00000618
182 #define MSR_DRAM_ENERGY_STATUS 0x00000619
183 #define MSR_DRAM_PERF_STATUS 0x0000061b
184 #define MSR_DRAM_POWER_INFO 0x0000061c
186 #define MSR_PP0_POWER_LIMIT 0x00000638
187 #define MSR_PP0_ENERGY_STATUS 0x00000639
188 #define MSR_PP0_POLICY 0x0000063a
189 #define MSR_PP0_PERF_STATUS 0x0000063b
191 #define MSR_PP1_POWER_LIMIT 0x00000640
192 #define MSR_PP1_ENERGY_STATUS 0x00000641
193 #define MSR_PP1_POLICY 0x00000642
195 /* Config TDP MSRs */
196 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
197 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
198 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
199 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
200 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
202 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
204 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
205 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
206 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
207 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
209 #define MSR_CORE_C1_RES 0x00000660
210 #define MSR_MODULE_C6_RES_MS 0x00000664
212 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
213 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
215 #define MSR_ATOM_CORE_RATIOS 0x0000066a
216 #define MSR_ATOM_CORE_VIDS 0x0000066b
217 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
218 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
221 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
222 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
223 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
225 /* Hardware P state interface */
226 #define MSR_PPERF 0x0000064e
227 #define MSR_PERF_LIMIT_REASONS 0x0000064f
228 #define MSR_PM_ENABLE 0x00000770
229 #define MSR_HWP_CAPABILITIES 0x00000771
230 #define MSR_HWP_REQUEST_PKG 0x00000772
231 #define MSR_HWP_INTERRUPT 0x00000773
232 #define MSR_HWP_REQUEST 0x00000774
233 #define MSR_HWP_STATUS 0x00000777
236 #define HWP_BASE_BIT (1<<7)
237 #define HWP_NOTIFICATIONS_BIT (1<<8)
238 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
239 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
240 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
242 /* IA32_HWP_CAPABILITIES */
243 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
244 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
245 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
246 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
248 /* IA32_HWP_REQUEST */
249 #define HWP_MIN_PERF(x) (x & 0xff)
250 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
251 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
252 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
253 #define HWP_EPP_PERFORMANCE 0x00
254 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
255 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
256 #define HWP_EPP_POWERSAVE 0xFF
257 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
258 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
260 /* IA32_HWP_STATUS */
261 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
262 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
264 /* IA32_HWP_INTERRUPT */
265 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
266 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
268 #define MSR_AMD64_MC0_MASK 0xc0010044
270 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
271 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
272 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
273 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
275 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
277 /* These are consecutive and not in the normal 4er MCE bank block */
278 #define MSR_IA32_MC0_CTL2 0x00000280
279 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
281 #define MSR_P6_PERFCTR0 0x000000c1
282 #define MSR_P6_PERFCTR1 0x000000c2
283 #define MSR_P6_EVNTSEL0 0x00000186
284 #define MSR_P6_EVNTSEL1 0x00000187
286 #define MSR_KNC_PERFCTR0 0x00000020
287 #define MSR_KNC_PERFCTR1 0x00000021
288 #define MSR_KNC_EVNTSEL0 0x00000028
289 #define MSR_KNC_EVNTSEL1 0x00000029
291 /* Alternative perfctr range with full access. */
292 #define MSR_IA32_PMC0 0x000004c1
294 /* AMD64 MSRs. Not complete. See the architecture manual for a more
297 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
298 #define MSR_AMD64_TSC_RATIO 0xc0000104
299 #define MSR_AMD64_NB_CFG 0xc001001f
300 #define MSR_AMD64_PATCH_LOADER 0xc0010020
301 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
302 #define MSR_AMD64_OSVW_STATUS 0xc0010141
303 #define MSR_AMD64_LS_CFG 0xc0011020
304 #define MSR_AMD64_DC_CFG 0xc0011022
305 #define MSR_AMD64_BU_CFG2 0xc001102a
306 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
307 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
308 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
309 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
310 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
311 #define MSR_AMD64_IBSOPCTL 0xc0011033
312 #define MSR_AMD64_IBSOPRIP 0xc0011034
313 #define MSR_AMD64_IBSOPDATA 0xc0011035
314 #define MSR_AMD64_IBSOPDATA2 0xc0011036
315 #define MSR_AMD64_IBSOPDATA3 0xc0011037
316 #define MSR_AMD64_IBSDCLINAD 0xc0011038
317 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
318 #define MSR_AMD64_IBSOP_REG_COUNT 7
319 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
320 #define MSR_AMD64_IBSCTL 0xc001103a
321 #define MSR_AMD64_IBSBRTARGET 0xc001103b
322 #define MSR_AMD64_IBSOPDATA4 0xc001103d
323 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
326 #define MSR_F17H_IRPERF 0xc00000e9
329 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
330 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
331 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
332 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
333 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
334 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
337 #define MSR_F15H_PERF_CTL 0xc0010200
338 #define MSR_F15H_PERF_CTR 0xc0010201
339 #define MSR_F15H_NB_PERF_CTL 0xc0010240
340 #define MSR_F15H_NB_PERF_CTR 0xc0010241
341 #define MSR_F15H_PTSC 0xc0010280
342 #define MSR_F15H_IC_CFG 0xc0011021
345 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
346 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
347 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
348 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
349 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
350 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
351 #define MSR_FAM10H_NODE_ID 0xc001100c
354 #define MSR_K8_TOP_MEM1 0xc001001a
355 #define MSR_K8_TOP_MEM2 0xc001001d
356 #define MSR_K8_SYSCFG 0xc0010010
357 #define MSR_K8_INT_PENDING_MSG 0xc0010055
358 /* C1E active bits in int pending message */
359 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
360 #define MSR_K8_TSEG_ADDR 0xc0010112
361 #define MSR_K8_TSEG_MASK 0xc0010113
362 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
363 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
364 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
367 #define MSR_K7_EVNTSEL0 0xc0010000
368 #define MSR_K7_PERFCTR0 0xc0010004
369 #define MSR_K7_EVNTSEL1 0xc0010001
370 #define MSR_K7_PERFCTR1 0xc0010005
371 #define MSR_K7_EVNTSEL2 0xc0010002
372 #define MSR_K7_PERFCTR2 0xc0010006
373 #define MSR_K7_EVNTSEL3 0xc0010003
374 #define MSR_K7_PERFCTR3 0xc0010007
375 #define MSR_K7_CLK_CTL 0xc001001b
376 #define MSR_K7_HWCR 0xc0010015
377 #define MSR_K7_FID_VID_CTL 0xc0010041
378 #define MSR_K7_FID_VID_STATUS 0xc0010042
381 #define MSR_K6_WHCR 0xc0000082
382 #define MSR_K6_UWCCR 0xc0000085
383 #define MSR_K6_EPMR 0xc0000086
384 #define MSR_K6_PSOR 0xc0000087
385 #define MSR_K6_PFIR 0xc0000088
387 /* Centaur-Hauls/IDT defined MSRs. */
388 #define MSR_IDT_FCR1 0x00000107
389 #define MSR_IDT_FCR2 0x00000108
390 #define MSR_IDT_FCR3 0x00000109
391 #define MSR_IDT_FCR4 0x0000010a
393 #define MSR_IDT_MCR0 0x00000110
394 #define MSR_IDT_MCR1 0x00000111
395 #define MSR_IDT_MCR2 0x00000112
396 #define MSR_IDT_MCR3 0x00000113
397 #define MSR_IDT_MCR4 0x00000114
398 #define MSR_IDT_MCR5 0x00000115
399 #define MSR_IDT_MCR6 0x00000116
400 #define MSR_IDT_MCR7 0x00000117
401 #define MSR_IDT_MCR_CTRL 0x00000120
403 /* VIA Cyrix defined MSRs*/
404 #define MSR_VIA_FCR 0x00001107
405 #define MSR_VIA_LONGHAUL 0x0000110a
406 #define MSR_VIA_RNG 0x0000110b
407 #define MSR_VIA_BCR2 0x00001147
409 /* Transmeta defined MSRs */
410 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
411 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
412 #define MSR_TMTA_LRTI_READOUT 0x80868018
413 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
415 /* Intel defined MSRs. */
416 #define MSR_IA32_P5_MC_ADDR 0x00000000
417 #define MSR_IA32_P5_MC_TYPE 0x00000001
418 #define MSR_IA32_TSC 0x00000010
419 #define MSR_IA32_PLATFORM_ID 0x00000017
420 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
421 #define MSR_EBC_FREQUENCY_ID 0x0000002c
422 #define MSR_SMI_COUNT 0x00000034
423 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
424 #define MSR_IA32_TSC_ADJUST 0x0000003b
425 #define MSR_IA32_BNDCFGS 0x00000d90
427 #define MSR_IA32_XSS 0x00000da0
429 #define FEATURE_CONTROL_LOCKED (1<<0)
430 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
431 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
432 #define FEATURE_CONTROL_LMCE (1<<20)
434 #define MSR_IA32_APICBASE 0x0000001b
435 #define MSR_IA32_APICBASE_BSP (1<<8)
436 #define MSR_IA32_APICBASE_ENABLE (1<<11)
437 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
439 #define MSR_IA32_TSCDEADLINE 0x000006e0
441 #define MSR_IA32_UCODE_WRITE 0x00000079
442 #define MSR_IA32_UCODE_REV 0x0000008b
444 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
445 #define MSR_IA32_SMBASE 0x0000009e
447 #define MSR_IA32_PERF_STATUS 0x00000198
448 #define MSR_IA32_PERF_CTL 0x00000199
449 #define INTEL_PERF_CTL_MASK 0xffff
450 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
451 #define MSR_AMD_PERF_STATUS 0xc0010063
452 #define MSR_AMD_PERF_CTL 0xc0010062
454 #define MSR_IA32_MPERF 0x000000e7
455 #define MSR_IA32_APERF 0x000000e8
457 #define MSR_IA32_THERM_CONTROL 0x0000019a
458 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
460 #define THERM_INT_HIGH_ENABLE (1 << 0)
461 #define THERM_INT_LOW_ENABLE (1 << 1)
462 #define THERM_INT_PLN_ENABLE (1 << 24)
464 #define MSR_IA32_THERM_STATUS 0x0000019c
466 #define THERM_STATUS_PROCHOT (1 << 0)
467 #define THERM_STATUS_POWER_LIMIT (1 << 10)
469 #define MSR_THERM2_CTL 0x0000019d
471 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
473 #define MSR_IA32_MISC_ENABLE 0x000001a0
475 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
477 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
478 #define MSR_MISC_PWR_MGMT 0x000001aa
480 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
481 #define ENERGY_PERF_BIAS_PERFORMANCE 0
482 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
483 #define ENERGY_PERF_BIAS_NORMAL 6
484 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
485 #define ENERGY_PERF_BIAS_POWERSAVE 15
487 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
489 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
490 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
492 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
494 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
495 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
496 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
498 /* Thermal Thresholds Support */
499 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
500 #define THERM_SHIFT_THRESHOLD0 8
501 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
502 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
503 #define THERM_SHIFT_THRESHOLD1 16
504 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
505 #define THERM_STATUS_THRESHOLD0 (1 << 6)
506 #define THERM_LOG_THRESHOLD0 (1 << 7)
507 #define THERM_STATUS_THRESHOLD1 (1 << 8)
508 #define THERM_LOG_THRESHOLD1 (1 << 9)
510 /* MISC_ENABLE bits: architectural */
511 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
512 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
513 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
514 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
515 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
516 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
517 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
518 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
519 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
520 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
521 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
522 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
523 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
524 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
525 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
526 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
527 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
528 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
529 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
530 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
532 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
533 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
534 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
535 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
536 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
537 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
538 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
539 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
540 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
541 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
542 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
543 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
544 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
545 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
546 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
547 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
548 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
549 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
550 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
551 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
552 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
553 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
554 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
555 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
556 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
557 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
558 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
559 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
560 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
561 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
562 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
564 /* MISC_FEATURES_ENABLES non-architectural features */
565 #define MSR_MISC_FEATURES_ENABLES 0x00000140
567 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
568 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
569 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
571 #define MSR_IA32_TSC_DEADLINE 0x000006E0
573 /* P4/Xeon+ specific */
574 #define MSR_IA32_MCG_EAX 0x00000180
575 #define MSR_IA32_MCG_EBX 0x00000181
576 #define MSR_IA32_MCG_ECX 0x00000182
577 #define MSR_IA32_MCG_EDX 0x00000183
578 #define MSR_IA32_MCG_ESI 0x00000184
579 #define MSR_IA32_MCG_EDI 0x00000185
580 #define MSR_IA32_MCG_EBP 0x00000186
581 #define MSR_IA32_MCG_ESP 0x00000187
582 #define MSR_IA32_MCG_EFLAGS 0x00000188
583 #define MSR_IA32_MCG_EIP 0x00000189
584 #define MSR_IA32_MCG_RESERVED 0x0000018a
586 /* Pentium IV performance counter MSRs */
587 #define MSR_P4_BPU_PERFCTR0 0x00000300
588 #define MSR_P4_BPU_PERFCTR1 0x00000301
589 #define MSR_P4_BPU_PERFCTR2 0x00000302
590 #define MSR_P4_BPU_PERFCTR3 0x00000303
591 #define MSR_P4_MS_PERFCTR0 0x00000304
592 #define MSR_P4_MS_PERFCTR1 0x00000305
593 #define MSR_P4_MS_PERFCTR2 0x00000306
594 #define MSR_P4_MS_PERFCTR3 0x00000307
595 #define MSR_P4_FLAME_PERFCTR0 0x00000308
596 #define MSR_P4_FLAME_PERFCTR1 0x00000309
597 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
598 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
599 #define MSR_P4_IQ_PERFCTR0 0x0000030c
600 #define MSR_P4_IQ_PERFCTR1 0x0000030d
601 #define MSR_P4_IQ_PERFCTR2 0x0000030e
602 #define MSR_P4_IQ_PERFCTR3 0x0000030f
603 #define MSR_P4_IQ_PERFCTR4 0x00000310
604 #define MSR_P4_IQ_PERFCTR5 0x00000311
605 #define MSR_P4_BPU_CCCR0 0x00000360
606 #define MSR_P4_BPU_CCCR1 0x00000361
607 #define MSR_P4_BPU_CCCR2 0x00000362
608 #define MSR_P4_BPU_CCCR3 0x00000363
609 #define MSR_P4_MS_CCCR0 0x00000364
610 #define MSR_P4_MS_CCCR1 0x00000365
611 #define MSR_P4_MS_CCCR2 0x00000366
612 #define MSR_P4_MS_CCCR3 0x00000367
613 #define MSR_P4_FLAME_CCCR0 0x00000368
614 #define MSR_P4_FLAME_CCCR1 0x00000369
615 #define MSR_P4_FLAME_CCCR2 0x0000036a
616 #define MSR_P4_FLAME_CCCR3 0x0000036b
617 #define MSR_P4_IQ_CCCR0 0x0000036c
618 #define MSR_P4_IQ_CCCR1 0x0000036d
619 #define MSR_P4_IQ_CCCR2 0x0000036e
620 #define MSR_P4_IQ_CCCR3 0x0000036f
621 #define MSR_P4_IQ_CCCR4 0x00000370
622 #define MSR_P4_IQ_CCCR5 0x00000371
623 #define MSR_P4_ALF_ESCR0 0x000003ca
624 #define MSR_P4_ALF_ESCR1 0x000003cb
625 #define MSR_P4_BPU_ESCR0 0x000003b2
626 #define MSR_P4_BPU_ESCR1 0x000003b3
627 #define MSR_P4_BSU_ESCR0 0x000003a0
628 #define MSR_P4_BSU_ESCR1 0x000003a1
629 #define MSR_P4_CRU_ESCR0 0x000003b8
630 #define MSR_P4_CRU_ESCR1 0x000003b9
631 #define MSR_P4_CRU_ESCR2 0x000003cc
632 #define MSR_P4_CRU_ESCR3 0x000003cd
633 #define MSR_P4_CRU_ESCR4 0x000003e0
634 #define MSR_P4_CRU_ESCR5 0x000003e1
635 #define MSR_P4_DAC_ESCR0 0x000003a8
636 #define MSR_P4_DAC_ESCR1 0x000003a9
637 #define MSR_P4_FIRM_ESCR0 0x000003a4
638 #define MSR_P4_FIRM_ESCR1 0x000003a5
639 #define MSR_P4_FLAME_ESCR0 0x000003a6
640 #define MSR_P4_FLAME_ESCR1 0x000003a7
641 #define MSR_P4_FSB_ESCR0 0x000003a2
642 #define MSR_P4_FSB_ESCR1 0x000003a3
643 #define MSR_P4_IQ_ESCR0 0x000003ba
644 #define MSR_P4_IQ_ESCR1 0x000003bb
645 #define MSR_P4_IS_ESCR0 0x000003b4
646 #define MSR_P4_IS_ESCR1 0x000003b5
647 #define MSR_P4_ITLB_ESCR0 0x000003b6
648 #define MSR_P4_ITLB_ESCR1 0x000003b7
649 #define MSR_P4_IX_ESCR0 0x000003c8
650 #define MSR_P4_IX_ESCR1 0x000003c9
651 #define MSR_P4_MOB_ESCR0 0x000003aa
652 #define MSR_P4_MOB_ESCR1 0x000003ab
653 #define MSR_P4_MS_ESCR0 0x000003c0
654 #define MSR_P4_MS_ESCR1 0x000003c1
655 #define MSR_P4_PMH_ESCR0 0x000003ac
656 #define MSR_P4_PMH_ESCR1 0x000003ad
657 #define MSR_P4_RAT_ESCR0 0x000003bc
658 #define MSR_P4_RAT_ESCR1 0x000003bd
659 #define MSR_P4_SAAT_ESCR0 0x000003ae
660 #define MSR_P4_SAAT_ESCR1 0x000003af
661 #define MSR_P4_SSU_ESCR0 0x000003be
662 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
664 #define MSR_P4_TBPU_ESCR0 0x000003c2
665 #define MSR_P4_TBPU_ESCR1 0x000003c3
666 #define MSR_P4_TC_ESCR0 0x000003c4
667 #define MSR_P4_TC_ESCR1 0x000003c5
668 #define MSR_P4_U2L_ESCR0 0x000003b0
669 #define MSR_P4_U2L_ESCR1 0x000003b1
671 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
673 /* Intel Core-based CPU performance counters */
674 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
675 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
676 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
677 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
678 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
679 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
680 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
682 /* Geode defined MSRs */
683 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
686 #define MSR_IA32_VMX_BASIC 0x00000480
687 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
688 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
689 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
690 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
691 #define MSR_IA32_VMX_MISC 0x00000485
692 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
693 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
694 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
695 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
696 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
697 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
698 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
699 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
700 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
701 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
702 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
703 #define MSR_IA32_VMX_VMFUNC 0x00000491
705 /* VMX_BASIC bits and bitmasks */
706 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
707 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
708 #define VMX_BASIC_64 0x0001000000000000LLU
709 #define VMX_BASIC_MEM_TYPE_SHIFT 50
710 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
711 #define VMX_BASIC_MEM_TYPE_WB 6LLU
712 #define VMX_BASIC_INOUT 0x0040000000000000LLU
714 /* MSR_IA32_VMX_MISC bits */
715 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
716 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
719 #define MSR_VM_CR 0xc0010114
720 #define MSR_VM_IGNNE 0xc0010115
721 #define MSR_VM_HSAVE_PA 0xc0010117
723 #endif /* _ASM_X86_MSR_INDEX_H */