1 // SPDX-License-Identifier: GPL-2.0-only
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
18 #include <asm/cpufeature.h>
19 #include <asm/hardirq.h>
20 #include <asm/intel-family.h>
21 #include <asm/intel_pt.h>
23 #include <asm/cpu_device_id.h>
25 #include "../perf_event.h"
28 * Intel PerfMon, used on Core and later.
30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
123 * When HT is off these events can only run on the bottom 4 counters
124 * When HT is on, they are impacted by the HT bug and require EXCL access
126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
151 * When HT is off these events can only run on the bottom 4 counters
152 * When HT is on, they are impacted by the HT bug and require EXCL access
154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
189 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
190 FIXED_EVENT_CONSTRAINT(0x0500, 4),
191 FIXED_EVENT_CONSTRAINT(0x0600, 5),
192 FIXED_EVENT_CONSTRAINT(0x0700, 6),
193 FIXED_EVENT_CONSTRAINT(0x0800, 7),
194 FIXED_EVENT_CONSTRAINT(0x0900, 8),
195 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
196 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
197 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
198 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
199 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
200 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
201 FIXED_EVENT_CONSTRAINT(0x1000, 15),
205 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
207 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
208 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
209 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
213 static struct event_constraint intel_skl_event_constraints[] = {
214 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
215 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
216 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
217 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
220 * when HT is off, these can only run on the bottom 4 counters
222 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
223 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
224 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
225 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
226 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
231 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
232 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
233 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
237 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
238 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
239 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
240 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
241 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
245 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
246 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
247 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
248 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
249 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
253 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
254 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
255 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
256 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
258 * Note the low 8 bits eventsel code is not a continuous field, containing
259 * some #GPing bits. These are masked out.
261 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
265 static struct event_constraint intel_icl_event_constraints[] = {
266 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
267 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
268 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
269 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
270 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
271 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
272 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
273 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
274 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
275 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
276 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
277 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
278 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
279 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
280 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
281 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
282 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
283 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
284 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
285 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
286 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
287 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
288 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
289 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
293 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
294 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
295 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
296 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
297 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
301 static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
302 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
303 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
304 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
305 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
306 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
307 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
311 static struct event_constraint intel_spr_event_constraints[] = {
312 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
313 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
314 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
315 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
316 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
317 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
318 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
319 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
320 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
321 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
322 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
323 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
324 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
326 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
327 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
329 * Generally event codes < 0x90 are restricted to counters 0-3.
330 * The 0x2E and 0x3C are exception, which has no restriction.
332 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
334 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
335 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
336 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
337 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
338 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
339 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
340 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
341 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
343 * Generally event codes >= 0x90 are likely to have no restrictions.
344 * The exception are defined as above.
346 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
352 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
353 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
354 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
356 static struct attribute *nhm_mem_events_attrs[] = {
357 EVENT_PTR(mem_ld_nhm),
362 * topdown events for Intel Core CPUs.
364 * The events are all in slots, which is a free slot in a 4 wide
365 * pipeline. Some events are already reported in slots, for cycle
366 * events we multiply by the pipeline width (4).
368 * With Hyper Threading on, topdown metrics are either summed or averaged
369 * between the threads of a core: (count_t0 + count_t1).
371 * For the average case the metric is always scaled to pipeline width,
372 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
375 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
376 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
377 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
378 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
379 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
380 "event=0xe,umask=0x1"); /* uops_issued.any */
381 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
382 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
383 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
384 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
385 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
386 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
387 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
388 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
391 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
392 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
393 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
394 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
395 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
396 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
397 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
398 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
399 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
401 static struct attribute *snb_events_attrs[] = {
402 EVENT_PTR(td_slots_issued),
403 EVENT_PTR(td_slots_retired),
404 EVENT_PTR(td_fetch_bubbles),
405 EVENT_PTR(td_total_slots),
406 EVENT_PTR(td_total_slots_scale),
407 EVENT_PTR(td_recovery_bubbles),
408 EVENT_PTR(td_recovery_bubbles_scale),
412 static struct attribute *snb_mem_events_attrs[] = {
413 EVENT_PTR(mem_ld_snb),
414 EVENT_PTR(mem_st_snb),
418 static struct event_constraint intel_hsw_event_constraints[] = {
419 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
420 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
421 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
422 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
423 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
424 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
425 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
426 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
427 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
428 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
429 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
430 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
433 * When HT is off these events can only run on the bottom 4 counters
434 * When HT is on, they are impacted by the HT bug and require EXCL access
436 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
437 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
438 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
439 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
444 static struct event_constraint intel_bdw_event_constraints[] = {
445 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
446 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
447 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
448 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
449 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
451 * when HT is off, these can only run on the bottom 4 counters
453 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
454 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
455 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
456 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
460 static u64 intel_pmu_event_map(int hw_event)
462 return intel_perfmon_event_map[hw_event];
465 static __initconst const u64 spr_hw_cache_event_ids
466 [PERF_COUNT_HW_CACHE_MAX]
467 [PERF_COUNT_HW_CACHE_OP_MAX]
468 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
472 [ C(RESULT_ACCESS) ] = 0x81d0,
473 [ C(RESULT_MISS) ] = 0xe124,
476 [ C(RESULT_ACCESS) ] = 0x82d0,
481 [ C(RESULT_MISS) ] = 0xe424,
484 [ C(RESULT_ACCESS) ] = -1,
485 [ C(RESULT_MISS) ] = -1,
490 [ C(RESULT_ACCESS) ] = 0x12a,
491 [ C(RESULT_MISS) ] = 0x12a,
494 [ C(RESULT_ACCESS) ] = 0x12a,
495 [ C(RESULT_MISS) ] = 0x12a,
500 [ C(RESULT_ACCESS) ] = 0x81d0,
501 [ C(RESULT_MISS) ] = 0xe12,
504 [ C(RESULT_ACCESS) ] = 0x82d0,
505 [ C(RESULT_MISS) ] = 0xe13,
510 [ C(RESULT_ACCESS) ] = -1,
511 [ C(RESULT_MISS) ] = 0xe11,
514 [ C(RESULT_ACCESS) ] = -1,
515 [ C(RESULT_MISS) ] = -1,
517 [ C(OP_PREFETCH) ] = {
518 [ C(RESULT_ACCESS) ] = -1,
519 [ C(RESULT_MISS) ] = -1,
524 [ C(RESULT_ACCESS) ] = 0x4c4,
525 [ C(RESULT_MISS) ] = 0x4c5,
528 [ C(RESULT_ACCESS) ] = -1,
529 [ C(RESULT_MISS) ] = -1,
531 [ C(OP_PREFETCH) ] = {
532 [ C(RESULT_ACCESS) ] = -1,
533 [ C(RESULT_MISS) ] = -1,
538 [ C(RESULT_ACCESS) ] = 0x12a,
539 [ C(RESULT_MISS) ] = 0x12a,
544 static __initconst const u64 spr_hw_cache_extra_regs
545 [PERF_COUNT_HW_CACHE_MAX]
546 [PERF_COUNT_HW_CACHE_OP_MAX]
547 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
551 [ C(RESULT_ACCESS) ] = 0x10001,
552 [ C(RESULT_MISS) ] = 0x3fbfc00001,
555 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
556 [ C(RESULT_MISS) ] = 0x3f3fc00002,
561 [ C(RESULT_ACCESS) ] = 0x10c000001,
562 [ C(RESULT_MISS) ] = 0x3fb3000001,
568 * Notes on the events:
569 * - data reads do not include code reads (comparable to earlier tables)
570 * - data counts include speculative execution (except L1 write, dtlb, bpu)
571 * - remote node access includes remote memory, remote cache, remote mmio.
572 * - prefetches are not included in the counts.
573 * - icache miss does not include decoded icache
576 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
577 #define SKL_DEMAND_RFO BIT_ULL(1)
578 #define SKL_ANY_RESPONSE BIT_ULL(16)
579 #define SKL_SUPPLIER_NONE BIT_ULL(17)
580 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
581 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
582 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
583 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
584 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
585 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
586 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
587 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
588 #define SKL_SPL_HIT BIT_ULL(30)
589 #define SKL_SNOOP_NONE BIT_ULL(31)
590 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
591 #define SKL_SNOOP_MISS BIT_ULL(33)
592 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
593 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
594 #define SKL_SNOOP_HITM BIT_ULL(36)
595 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
596 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
597 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
598 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
599 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
600 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
601 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
602 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
603 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
604 SKL_SNOOP_HITM|SKL_SPL_HIT)
605 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
606 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
607 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
608 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
609 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
611 static __initconst const u64 skl_hw_cache_event_ids
612 [PERF_COUNT_HW_CACHE_MAX]
613 [PERF_COUNT_HW_CACHE_OP_MAX]
614 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
618 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
619 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
622 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
623 [ C(RESULT_MISS) ] = 0x0,
625 [ C(OP_PREFETCH) ] = {
626 [ C(RESULT_ACCESS) ] = 0x0,
627 [ C(RESULT_MISS) ] = 0x0,
632 [ C(RESULT_ACCESS) ] = 0x0,
633 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
636 [ C(RESULT_ACCESS) ] = -1,
637 [ C(RESULT_MISS) ] = -1,
639 [ C(OP_PREFETCH) ] = {
640 [ C(RESULT_ACCESS) ] = 0x0,
641 [ C(RESULT_MISS) ] = 0x0,
646 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
647 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
650 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
651 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
653 [ C(OP_PREFETCH) ] = {
654 [ C(RESULT_ACCESS) ] = 0x0,
655 [ C(RESULT_MISS) ] = 0x0,
660 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
661 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
664 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
665 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
667 [ C(OP_PREFETCH) ] = {
668 [ C(RESULT_ACCESS) ] = 0x0,
669 [ C(RESULT_MISS) ] = 0x0,
674 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
675 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
678 [ C(RESULT_ACCESS) ] = -1,
679 [ C(RESULT_MISS) ] = -1,
681 [ C(OP_PREFETCH) ] = {
682 [ C(RESULT_ACCESS) ] = -1,
683 [ C(RESULT_MISS) ] = -1,
688 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
689 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
692 [ C(RESULT_ACCESS) ] = -1,
693 [ C(RESULT_MISS) ] = -1,
695 [ C(OP_PREFETCH) ] = {
696 [ C(RESULT_ACCESS) ] = -1,
697 [ C(RESULT_MISS) ] = -1,
702 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
703 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
706 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
707 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
709 [ C(OP_PREFETCH) ] = {
710 [ C(RESULT_ACCESS) ] = 0x0,
711 [ C(RESULT_MISS) ] = 0x0,
716 static __initconst const u64 skl_hw_cache_extra_regs
717 [PERF_COUNT_HW_CACHE_MAX]
718 [PERF_COUNT_HW_CACHE_OP_MAX]
719 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
723 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
724 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
725 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
726 SKL_L3_MISS|SKL_ANY_SNOOP|
730 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
731 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
732 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
733 SKL_L3_MISS|SKL_ANY_SNOOP|
736 [ C(OP_PREFETCH) ] = {
737 [ C(RESULT_ACCESS) ] = 0x0,
738 [ C(RESULT_MISS) ] = 0x0,
743 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
744 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
745 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
746 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
749 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
750 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
751 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
752 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
754 [ C(OP_PREFETCH) ] = {
755 [ C(RESULT_ACCESS) ] = 0x0,
756 [ C(RESULT_MISS) ] = 0x0,
761 #define SNB_DMND_DATA_RD (1ULL << 0)
762 #define SNB_DMND_RFO (1ULL << 1)
763 #define SNB_DMND_IFETCH (1ULL << 2)
764 #define SNB_DMND_WB (1ULL << 3)
765 #define SNB_PF_DATA_RD (1ULL << 4)
766 #define SNB_PF_RFO (1ULL << 5)
767 #define SNB_PF_IFETCH (1ULL << 6)
768 #define SNB_LLC_DATA_RD (1ULL << 7)
769 #define SNB_LLC_RFO (1ULL << 8)
770 #define SNB_LLC_IFETCH (1ULL << 9)
771 #define SNB_BUS_LOCKS (1ULL << 10)
772 #define SNB_STRM_ST (1ULL << 11)
773 #define SNB_OTHER (1ULL << 15)
774 #define SNB_RESP_ANY (1ULL << 16)
775 #define SNB_NO_SUPP (1ULL << 17)
776 #define SNB_LLC_HITM (1ULL << 18)
777 #define SNB_LLC_HITE (1ULL << 19)
778 #define SNB_LLC_HITS (1ULL << 20)
779 #define SNB_LLC_HITF (1ULL << 21)
780 #define SNB_LOCAL (1ULL << 22)
781 #define SNB_REMOTE (0xffULL << 23)
782 #define SNB_SNP_NONE (1ULL << 31)
783 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
784 #define SNB_SNP_MISS (1ULL << 33)
785 #define SNB_NO_FWD (1ULL << 34)
786 #define SNB_SNP_FWD (1ULL << 35)
787 #define SNB_HITM (1ULL << 36)
788 #define SNB_NON_DRAM (1ULL << 37)
790 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
791 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
792 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
794 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
795 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
798 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
799 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
801 #define SNB_L3_ACCESS SNB_RESP_ANY
802 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
804 static __initconst const u64 snb_hw_cache_extra_regs
805 [PERF_COUNT_HW_CACHE_MAX]
806 [PERF_COUNT_HW_CACHE_OP_MAX]
807 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
811 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
812 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
815 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
816 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
818 [ C(OP_PREFETCH) ] = {
819 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
820 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
825 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
826 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
829 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
830 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
832 [ C(OP_PREFETCH) ] = {
833 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
834 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
839 static __initconst const u64 snb_hw_cache_event_ids
840 [PERF_COUNT_HW_CACHE_MAX]
841 [PERF_COUNT_HW_CACHE_OP_MAX]
842 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
846 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
847 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
850 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
851 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
853 [ C(OP_PREFETCH) ] = {
854 [ C(RESULT_ACCESS) ] = 0x0,
855 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
860 [ C(RESULT_ACCESS) ] = 0x0,
861 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
864 [ C(RESULT_ACCESS) ] = -1,
865 [ C(RESULT_MISS) ] = -1,
867 [ C(OP_PREFETCH) ] = {
868 [ C(RESULT_ACCESS) ] = 0x0,
869 [ C(RESULT_MISS) ] = 0x0,
874 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
875 [ C(RESULT_ACCESS) ] = 0x01b7,
876 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
877 [ C(RESULT_MISS) ] = 0x01b7,
880 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
881 [ C(RESULT_ACCESS) ] = 0x01b7,
882 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
883 [ C(RESULT_MISS) ] = 0x01b7,
885 [ C(OP_PREFETCH) ] = {
886 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
887 [ C(RESULT_ACCESS) ] = 0x01b7,
888 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
889 [ C(RESULT_MISS) ] = 0x01b7,
894 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
895 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
898 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
899 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
901 [ C(OP_PREFETCH) ] = {
902 [ C(RESULT_ACCESS) ] = 0x0,
903 [ C(RESULT_MISS) ] = 0x0,
908 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
909 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
912 [ C(RESULT_ACCESS) ] = -1,
913 [ C(RESULT_MISS) ] = -1,
915 [ C(OP_PREFETCH) ] = {
916 [ C(RESULT_ACCESS) ] = -1,
917 [ C(RESULT_MISS) ] = -1,
922 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
923 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
926 [ C(RESULT_ACCESS) ] = -1,
927 [ C(RESULT_MISS) ] = -1,
929 [ C(OP_PREFETCH) ] = {
930 [ C(RESULT_ACCESS) ] = -1,
931 [ C(RESULT_MISS) ] = -1,
936 [ C(RESULT_ACCESS) ] = 0x01b7,
937 [ C(RESULT_MISS) ] = 0x01b7,
940 [ C(RESULT_ACCESS) ] = 0x01b7,
941 [ C(RESULT_MISS) ] = 0x01b7,
943 [ C(OP_PREFETCH) ] = {
944 [ C(RESULT_ACCESS) ] = 0x01b7,
945 [ C(RESULT_MISS) ] = 0x01b7,
952 * Notes on the events:
953 * - data reads do not include code reads (comparable to earlier tables)
954 * - data counts include speculative execution (except L1 write, dtlb, bpu)
955 * - remote node access includes remote memory, remote cache, remote mmio.
956 * - prefetches are not included in the counts because they are not
960 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
961 #define HSW_DEMAND_RFO BIT_ULL(1)
962 #define HSW_ANY_RESPONSE BIT_ULL(16)
963 #define HSW_SUPPLIER_NONE BIT_ULL(17)
964 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
965 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
966 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
967 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
968 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
969 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
970 HSW_L3_MISS_REMOTE_HOP2P)
971 #define HSW_SNOOP_NONE BIT_ULL(31)
972 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
973 #define HSW_SNOOP_MISS BIT_ULL(33)
974 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
975 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
976 #define HSW_SNOOP_HITM BIT_ULL(36)
977 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
978 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
979 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
980 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
981 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
982 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
983 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
984 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
985 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
986 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
987 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
989 #define BDW_L3_MISS_LOCAL BIT(26)
990 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
991 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
992 HSW_L3_MISS_REMOTE_HOP2P)
995 static __initconst const u64 hsw_hw_cache_event_ids
996 [PERF_COUNT_HW_CACHE_MAX]
997 [PERF_COUNT_HW_CACHE_OP_MAX]
998 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1002 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1003 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1006 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1007 [ C(RESULT_MISS) ] = 0x0,
1009 [ C(OP_PREFETCH) ] = {
1010 [ C(RESULT_ACCESS) ] = 0x0,
1011 [ C(RESULT_MISS) ] = 0x0,
1016 [ C(RESULT_ACCESS) ] = 0x0,
1017 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1020 [ C(RESULT_ACCESS) ] = -1,
1021 [ C(RESULT_MISS) ] = -1,
1023 [ C(OP_PREFETCH) ] = {
1024 [ C(RESULT_ACCESS) ] = 0x0,
1025 [ C(RESULT_MISS) ] = 0x0,
1030 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1031 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1034 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1035 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1037 [ C(OP_PREFETCH) ] = {
1038 [ C(RESULT_ACCESS) ] = 0x0,
1039 [ C(RESULT_MISS) ] = 0x0,
1044 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1045 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1048 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1049 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1051 [ C(OP_PREFETCH) ] = {
1052 [ C(RESULT_ACCESS) ] = 0x0,
1053 [ C(RESULT_MISS) ] = 0x0,
1058 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1059 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1062 [ C(RESULT_ACCESS) ] = -1,
1063 [ C(RESULT_MISS) ] = -1,
1065 [ C(OP_PREFETCH) ] = {
1066 [ C(RESULT_ACCESS) ] = -1,
1067 [ C(RESULT_MISS) ] = -1,
1072 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1073 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1076 [ C(RESULT_ACCESS) ] = -1,
1077 [ C(RESULT_MISS) ] = -1,
1079 [ C(OP_PREFETCH) ] = {
1080 [ C(RESULT_ACCESS) ] = -1,
1081 [ C(RESULT_MISS) ] = -1,
1086 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1087 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1090 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1091 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1093 [ C(OP_PREFETCH) ] = {
1094 [ C(RESULT_ACCESS) ] = 0x0,
1095 [ C(RESULT_MISS) ] = 0x0,
1100 static __initconst const u64 hsw_hw_cache_extra_regs
1101 [PERF_COUNT_HW_CACHE_MAX]
1102 [PERF_COUNT_HW_CACHE_OP_MAX]
1103 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1107 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1109 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1110 HSW_L3_MISS|HSW_ANY_SNOOP,
1113 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1115 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1116 HSW_L3_MISS|HSW_ANY_SNOOP,
1118 [ C(OP_PREFETCH) ] = {
1119 [ C(RESULT_ACCESS) ] = 0x0,
1120 [ C(RESULT_MISS) ] = 0x0,
1125 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1126 HSW_L3_MISS_LOCAL_DRAM|
1128 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1133 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1134 HSW_L3_MISS_LOCAL_DRAM|
1136 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1140 [ C(OP_PREFETCH) ] = {
1141 [ C(RESULT_ACCESS) ] = 0x0,
1142 [ C(RESULT_MISS) ] = 0x0,
1147 static __initconst const u64 westmere_hw_cache_event_ids
1148 [PERF_COUNT_HW_CACHE_MAX]
1149 [PERF_COUNT_HW_CACHE_OP_MAX]
1150 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1154 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1155 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1158 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1159 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1161 [ C(OP_PREFETCH) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1163 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1168 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1169 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1172 [ C(RESULT_ACCESS) ] = -1,
1173 [ C(RESULT_MISS) ] = -1,
1175 [ C(OP_PREFETCH) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x0,
1177 [ C(RESULT_MISS) ] = 0x0,
1182 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1183 [ C(RESULT_ACCESS) ] = 0x01b7,
1184 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1185 [ C(RESULT_MISS) ] = 0x01b7,
1188 * Use RFO, not WRITEBACK, because a write miss would typically occur
1192 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1193 [ C(RESULT_ACCESS) ] = 0x01b7,
1194 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1195 [ C(RESULT_MISS) ] = 0x01b7,
1197 [ C(OP_PREFETCH) ] = {
1198 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1199 [ C(RESULT_ACCESS) ] = 0x01b7,
1200 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1201 [ C(RESULT_MISS) ] = 0x01b7,
1206 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1207 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1210 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1211 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1213 [ C(OP_PREFETCH) ] = {
1214 [ C(RESULT_ACCESS) ] = 0x0,
1215 [ C(RESULT_MISS) ] = 0x0,
1220 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1221 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1224 [ C(RESULT_ACCESS) ] = -1,
1225 [ C(RESULT_MISS) ] = -1,
1227 [ C(OP_PREFETCH) ] = {
1228 [ C(RESULT_ACCESS) ] = -1,
1229 [ C(RESULT_MISS) ] = -1,
1234 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1235 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1238 [ C(RESULT_ACCESS) ] = -1,
1239 [ C(RESULT_MISS) ] = -1,
1241 [ C(OP_PREFETCH) ] = {
1242 [ C(RESULT_ACCESS) ] = -1,
1243 [ C(RESULT_MISS) ] = -1,
1248 [ C(RESULT_ACCESS) ] = 0x01b7,
1249 [ C(RESULT_MISS) ] = 0x01b7,
1252 [ C(RESULT_ACCESS) ] = 0x01b7,
1253 [ C(RESULT_MISS) ] = 0x01b7,
1255 [ C(OP_PREFETCH) ] = {
1256 [ C(RESULT_ACCESS) ] = 0x01b7,
1257 [ C(RESULT_MISS) ] = 0x01b7,
1263 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1264 * See IA32 SDM Vol 3B 30.6.1.3
1267 #define NHM_DMND_DATA_RD (1 << 0)
1268 #define NHM_DMND_RFO (1 << 1)
1269 #define NHM_DMND_IFETCH (1 << 2)
1270 #define NHM_DMND_WB (1 << 3)
1271 #define NHM_PF_DATA_RD (1 << 4)
1272 #define NHM_PF_DATA_RFO (1 << 5)
1273 #define NHM_PF_IFETCH (1 << 6)
1274 #define NHM_OFFCORE_OTHER (1 << 7)
1275 #define NHM_UNCORE_HIT (1 << 8)
1276 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1277 #define NHM_OTHER_CORE_HITM (1 << 10)
1279 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1280 #define NHM_REMOTE_DRAM (1 << 13)
1281 #define NHM_LOCAL_DRAM (1 << 14)
1282 #define NHM_NON_DRAM (1 << 15)
1284 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1285 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1287 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1288 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1289 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1291 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1292 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1293 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1295 static __initconst const u64 nehalem_hw_cache_extra_regs
1296 [PERF_COUNT_HW_CACHE_MAX]
1297 [PERF_COUNT_HW_CACHE_OP_MAX]
1298 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1302 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1303 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1306 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1307 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1309 [ C(OP_PREFETCH) ] = {
1310 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1311 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1316 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1317 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1320 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1321 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1323 [ C(OP_PREFETCH) ] = {
1324 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1325 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1330 static __initconst const u64 nehalem_hw_cache_event_ids
1331 [PERF_COUNT_HW_CACHE_MAX]
1332 [PERF_COUNT_HW_CACHE_OP_MAX]
1333 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1337 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1338 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1341 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1342 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1344 [ C(OP_PREFETCH) ] = {
1345 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1346 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1351 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1352 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1355 [ C(RESULT_ACCESS) ] = -1,
1356 [ C(RESULT_MISS) ] = -1,
1358 [ C(OP_PREFETCH) ] = {
1359 [ C(RESULT_ACCESS) ] = 0x0,
1360 [ C(RESULT_MISS) ] = 0x0,
1365 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1366 [ C(RESULT_ACCESS) ] = 0x01b7,
1367 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1368 [ C(RESULT_MISS) ] = 0x01b7,
1371 * Use RFO, not WRITEBACK, because a write miss would typically occur
1375 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1376 [ C(RESULT_ACCESS) ] = 0x01b7,
1377 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1378 [ C(RESULT_MISS) ] = 0x01b7,
1380 [ C(OP_PREFETCH) ] = {
1381 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1382 [ C(RESULT_ACCESS) ] = 0x01b7,
1383 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1384 [ C(RESULT_MISS) ] = 0x01b7,
1389 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1390 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1393 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1394 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1396 [ C(OP_PREFETCH) ] = {
1397 [ C(RESULT_ACCESS) ] = 0x0,
1398 [ C(RESULT_MISS) ] = 0x0,
1403 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1404 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1407 [ C(RESULT_ACCESS) ] = -1,
1408 [ C(RESULT_MISS) ] = -1,
1410 [ C(OP_PREFETCH) ] = {
1411 [ C(RESULT_ACCESS) ] = -1,
1412 [ C(RESULT_MISS) ] = -1,
1417 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1418 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1421 [ C(RESULT_ACCESS) ] = -1,
1422 [ C(RESULT_MISS) ] = -1,
1424 [ C(OP_PREFETCH) ] = {
1425 [ C(RESULT_ACCESS) ] = -1,
1426 [ C(RESULT_MISS) ] = -1,
1431 [ C(RESULT_ACCESS) ] = 0x01b7,
1432 [ C(RESULT_MISS) ] = 0x01b7,
1435 [ C(RESULT_ACCESS) ] = 0x01b7,
1436 [ C(RESULT_MISS) ] = 0x01b7,
1438 [ C(OP_PREFETCH) ] = {
1439 [ C(RESULT_ACCESS) ] = 0x01b7,
1440 [ C(RESULT_MISS) ] = 0x01b7,
1445 static __initconst const u64 core2_hw_cache_event_ids
1446 [PERF_COUNT_HW_CACHE_MAX]
1447 [PERF_COUNT_HW_CACHE_OP_MAX]
1448 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1452 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1453 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1456 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1457 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1459 [ C(OP_PREFETCH) ] = {
1460 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1461 [ C(RESULT_MISS) ] = 0,
1466 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1467 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1470 [ C(RESULT_ACCESS) ] = -1,
1471 [ C(RESULT_MISS) ] = -1,
1473 [ C(OP_PREFETCH) ] = {
1474 [ C(RESULT_ACCESS) ] = 0,
1475 [ C(RESULT_MISS) ] = 0,
1480 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1481 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1484 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1485 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1487 [ C(OP_PREFETCH) ] = {
1488 [ C(RESULT_ACCESS) ] = 0,
1489 [ C(RESULT_MISS) ] = 0,
1494 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1495 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1498 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1499 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1501 [ C(OP_PREFETCH) ] = {
1502 [ C(RESULT_ACCESS) ] = 0,
1503 [ C(RESULT_MISS) ] = 0,
1508 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1509 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1512 [ C(RESULT_ACCESS) ] = -1,
1513 [ C(RESULT_MISS) ] = -1,
1515 [ C(OP_PREFETCH) ] = {
1516 [ C(RESULT_ACCESS) ] = -1,
1517 [ C(RESULT_MISS) ] = -1,
1522 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1523 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1526 [ C(RESULT_ACCESS) ] = -1,
1527 [ C(RESULT_MISS) ] = -1,
1529 [ C(OP_PREFETCH) ] = {
1530 [ C(RESULT_ACCESS) ] = -1,
1531 [ C(RESULT_MISS) ] = -1,
1536 static __initconst const u64 atom_hw_cache_event_ids
1537 [PERF_COUNT_HW_CACHE_MAX]
1538 [PERF_COUNT_HW_CACHE_OP_MAX]
1539 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1543 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1544 [ C(RESULT_MISS) ] = 0,
1547 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1548 [ C(RESULT_MISS) ] = 0,
1550 [ C(OP_PREFETCH) ] = {
1551 [ C(RESULT_ACCESS) ] = 0x0,
1552 [ C(RESULT_MISS) ] = 0,
1557 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1558 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1561 [ C(RESULT_ACCESS) ] = -1,
1562 [ C(RESULT_MISS) ] = -1,
1564 [ C(OP_PREFETCH) ] = {
1565 [ C(RESULT_ACCESS) ] = 0,
1566 [ C(RESULT_MISS) ] = 0,
1571 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1572 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1575 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1576 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1578 [ C(OP_PREFETCH) ] = {
1579 [ C(RESULT_ACCESS) ] = 0,
1580 [ C(RESULT_MISS) ] = 0,
1585 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1586 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1589 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1590 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1592 [ C(OP_PREFETCH) ] = {
1593 [ C(RESULT_ACCESS) ] = 0,
1594 [ C(RESULT_MISS) ] = 0,
1599 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1600 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1603 [ C(RESULT_ACCESS) ] = -1,
1604 [ C(RESULT_MISS) ] = -1,
1606 [ C(OP_PREFETCH) ] = {
1607 [ C(RESULT_ACCESS) ] = -1,
1608 [ C(RESULT_MISS) ] = -1,
1613 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1614 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1617 [ C(RESULT_ACCESS) ] = -1,
1618 [ C(RESULT_MISS) ] = -1,
1620 [ C(OP_PREFETCH) ] = {
1621 [ C(RESULT_ACCESS) ] = -1,
1622 [ C(RESULT_MISS) ] = -1,
1627 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1628 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1629 /* no_alloc_cycles.not_delivered */
1630 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1631 "event=0xca,umask=0x50");
1632 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1633 /* uops_retired.all */
1634 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1635 "event=0xc2,umask=0x10");
1636 /* uops_retired.all */
1637 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1638 "event=0xc2,umask=0x10");
1640 static struct attribute *slm_events_attrs[] = {
1641 EVENT_PTR(td_total_slots_slm),
1642 EVENT_PTR(td_total_slots_scale_slm),
1643 EVENT_PTR(td_fetch_bubbles_slm),
1644 EVENT_PTR(td_fetch_bubbles_scale_slm),
1645 EVENT_PTR(td_slots_issued_slm),
1646 EVENT_PTR(td_slots_retired_slm),
1650 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1652 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1653 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1654 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1658 #define SLM_DMND_READ SNB_DMND_DATA_RD
1659 #define SLM_DMND_WRITE SNB_DMND_RFO
1660 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1662 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1663 #define SLM_LLC_ACCESS SNB_RESP_ANY
1664 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1666 static __initconst const u64 slm_hw_cache_extra_regs
1667 [PERF_COUNT_HW_CACHE_MAX]
1668 [PERF_COUNT_HW_CACHE_OP_MAX]
1669 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1673 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1674 [ C(RESULT_MISS) ] = 0,
1677 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1678 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1680 [ C(OP_PREFETCH) ] = {
1681 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1682 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1687 static __initconst const u64 slm_hw_cache_event_ids
1688 [PERF_COUNT_HW_CACHE_MAX]
1689 [PERF_COUNT_HW_CACHE_OP_MAX]
1690 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1694 [ C(RESULT_ACCESS) ] = 0,
1695 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1698 [ C(RESULT_ACCESS) ] = 0,
1699 [ C(RESULT_MISS) ] = 0,
1701 [ C(OP_PREFETCH) ] = {
1702 [ C(RESULT_ACCESS) ] = 0,
1703 [ C(RESULT_MISS) ] = 0,
1708 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1709 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1712 [ C(RESULT_ACCESS) ] = -1,
1713 [ C(RESULT_MISS) ] = -1,
1715 [ C(OP_PREFETCH) ] = {
1716 [ C(RESULT_ACCESS) ] = 0,
1717 [ C(RESULT_MISS) ] = 0,
1722 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1723 [ C(RESULT_ACCESS) ] = 0x01b7,
1724 [ C(RESULT_MISS) ] = 0,
1727 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1728 [ C(RESULT_ACCESS) ] = 0x01b7,
1729 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1730 [ C(RESULT_MISS) ] = 0x01b7,
1732 [ C(OP_PREFETCH) ] = {
1733 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1734 [ C(RESULT_ACCESS) ] = 0x01b7,
1735 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1736 [ C(RESULT_MISS) ] = 0x01b7,
1741 [ C(RESULT_ACCESS) ] = 0,
1742 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1745 [ C(RESULT_ACCESS) ] = 0,
1746 [ C(RESULT_MISS) ] = 0,
1748 [ C(OP_PREFETCH) ] = {
1749 [ C(RESULT_ACCESS) ] = 0,
1750 [ C(RESULT_MISS) ] = 0,
1755 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1756 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1759 [ C(RESULT_ACCESS) ] = -1,
1760 [ C(RESULT_MISS) ] = -1,
1762 [ C(OP_PREFETCH) ] = {
1763 [ C(RESULT_ACCESS) ] = -1,
1764 [ C(RESULT_MISS) ] = -1,
1769 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1770 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1773 [ C(RESULT_ACCESS) ] = -1,
1774 [ C(RESULT_MISS) ] = -1,
1776 [ C(OP_PREFETCH) ] = {
1777 [ C(RESULT_ACCESS) ] = -1,
1778 [ C(RESULT_MISS) ] = -1,
1783 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1784 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1785 /* UOPS_NOT_DELIVERED.ANY */
1786 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1787 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1788 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1789 /* UOPS_RETIRED.ANY */
1790 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1791 /* UOPS_ISSUED.ANY */
1792 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1794 static struct attribute *glm_events_attrs[] = {
1795 EVENT_PTR(td_total_slots_glm),
1796 EVENT_PTR(td_total_slots_scale_glm),
1797 EVENT_PTR(td_fetch_bubbles_glm),
1798 EVENT_PTR(td_recovery_bubbles_glm),
1799 EVENT_PTR(td_slots_issued_glm),
1800 EVENT_PTR(td_slots_retired_glm),
1804 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1805 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1806 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1807 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1811 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1812 #define GLM_DEMAND_RFO BIT_ULL(1)
1813 #define GLM_ANY_RESPONSE BIT_ULL(16)
1814 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1815 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1816 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1817 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1818 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1819 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1820 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1822 static __initconst const u64 glm_hw_cache_event_ids
1823 [PERF_COUNT_HW_CACHE_MAX]
1824 [PERF_COUNT_HW_CACHE_OP_MAX]
1825 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1828 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1829 [C(RESULT_MISS)] = 0x0,
1832 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1833 [C(RESULT_MISS)] = 0x0,
1835 [C(OP_PREFETCH)] = {
1836 [C(RESULT_ACCESS)] = 0x0,
1837 [C(RESULT_MISS)] = 0x0,
1842 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1843 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1846 [C(RESULT_ACCESS)] = -1,
1847 [C(RESULT_MISS)] = -1,
1849 [C(OP_PREFETCH)] = {
1850 [C(RESULT_ACCESS)] = 0x0,
1851 [C(RESULT_MISS)] = 0x0,
1856 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1857 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1860 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1861 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1863 [C(OP_PREFETCH)] = {
1864 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1865 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1870 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1871 [C(RESULT_MISS)] = 0x0,
1874 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1875 [C(RESULT_MISS)] = 0x0,
1877 [C(OP_PREFETCH)] = {
1878 [C(RESULT_ACCESS)] = 0x0,
1879 [C(RESULT_MISS)] = 0x0,
1884 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1885 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1888 [C(RESULT_ACCESS)] = -1,
1889 [C(RESULT_MISS)] = -1,
1891 [C(OP_PREFETCH)] = {
1892 [C(RESULT_ACCESS)] = -1,
1893 [C(RESULT_MISS)] = -1,
1898 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1899 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1902 [C(RESULT_ACCESS)] = -1,
1903 [C(RESULT_MISS)] = -1,
1905 [C(OP_PREFETCH)] = {
1906 [C(RESULT_ACCESS)] = -1,
1907 [C(RESULT_MISS)] = -1,
1912 static __initconst const u64 glm_hw_cache_extra_regs
1913 [PERF_COUNT_HW_CACHE_MAX]
1914 [PERF_COUNT_HW_CACHE_OP_MAX]
1915 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1918 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1920 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1924 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1926 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1929 [C(OP_PREFETCH)] = {
1930 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1932 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1938 static __initconst const u64 glp_hw_cache_event_ids
1939 [PERF_COUNT_HW_CACHE_MAX]
1940 [PERF_COUNT_HW_CACHE_OP_MAX]
1941 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1944 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1945 [C(RESULT_MISS)] = 0x0,
1948 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1949 [C(RESULT_MISS)] = 0x0,
1951 [C(OP_PREFETCH)] = {
1952 [C(RESULT_ACCESS)] = 0x0,
1953 [C(RESULT_MISS)] = 0x0,
1958 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1959 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1962 [C(RESULT_ACCESS)] = -1,
1963 [C(RESULT_MISS)] = -1,
1965 [C(OP_PREFETCH)] = {
1966 [C(RESULT_ACCESS)] = 0x0,
1967 [C(RESULT_MISS)] = 0x0,
1972 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1973 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1976 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1977 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1979 [C(OP_PREFETCH)] = {
1980 [C(RESULT_ACCESS)] = 0x0,
1981 [C(RESULT_MISS)] = 0x0,
1986 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1987 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1990 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1991 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1993 [C(OP_PREFETCH)] = {
1994 [C(RESULT_ACCESS)] = 0x0,
1995 [C(RESULT_MISS)] = 0x0,
2000 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2001 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2004 [C(RESULT_ACCESS)] = -1,
2005 [C(RESULT_MISS)] = -1,
2007 [C(OP_PREFETCH)] = {
2008 [C(RESULT_ACCESS)] = -1,
2009 [C(RESULT_MISS)] = -1,
2014 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2015 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2018 [C(RESULT_ACCESS)] = -1,
2019 [C(RESULT_MISS)] = -1,
2021 [C(OP_PREFETCH)] = {
2022 [C(RESULT_ACCESS)] = -1,
2023 [C(RESULT_MISS)] = -1,
2028 static __initconst const u64 glp_hw_cache_extra_regs
2029 [PERF_COUNT_HW_CACHE_MAX]
2030 [PERF_COUNT_HW_CACHE_OP_MAX]
2031 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2034 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2036 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2040 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2042 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2045 [C(OP_PREFETCH)] = {
2046 [C(RESULT_ACCESS)] = 0x0,
2047 [C(RESULT_MISS)] = 0x0,
2052 #define TNT_LOCAL_DRAM BIT_ULL(26)
2053 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2054 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2055 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2056 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2057 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2058 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2060 static __initconst const u64 tnt_hw_cache_extra_regs
2061 [PERF_COUNT_HW_CACHE_MAX]
2062 [PERF_COUNT_HW_CACHE_OP_MAX]
2063 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2066 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2068 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2072 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2074 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2077 [C(OP_PREFETCH)] = {
2078 [C(RESULT_ACCESS)] = 0x0,
2079 [C(RESULT_MISS)] = 0x0,
2084 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2085 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2086 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2087 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2089 static struct attribute *tnt_events_attrs[] = {
2090 EVENT_PTR(td_fe_bound_tnt),
2091 EVENT_PTR(td_retiring_tnt),
2092 EVENT_PTR(td_bad_spec_tnt),
2093 EVENT_PTR(td_be_bound_tnt),
2097 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2098 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2099 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2100 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2104 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2105 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2106 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2107 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2108 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2112 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2113 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2114 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2115 #define KNL_MCDRAM_FAR BIT_ULL(22)
2116 #define KNL_DDR_LOCAL BIT_ULL(23)
2117 #define KNL_DDR_FAR BIT_ULL(24)
2118 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2119 KNL_DDR_LOCAL | KNL_DDR_FAR)
2120 #define KNL_L2_READ SLM_DMND_READ
2121 #define KNL_L2_WRITE SLM_DMND_WRITE
2122 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2123 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2124 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2125 KNL_DRAM_ANY | SNB_SNP_ANY | \
2128 static __initconst const u64 knl_hw_cache_extra_regs
2129 [PERF_COUNT_HW_CACHE_MAX]
2130 [PERF_COUNT_HW_CACHE_OP_MAX]
2131 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2134 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2135 [C(RESULT_MISS)] = 0,
2138 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2139 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2141 [C(OP_PREFETCH)] = {
2142 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2143 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2149 * Used from PMIs where the LBRs are already disabled.
2151 * This function could be called consecutively. It is required to remain in
2152 * disabled state if called consecutively.
2154 * During consecutive calls, the same disable value will be written to related
2155 * registers, so the PMU state remains unchanged.
2157 * intel_bts events don't coexist with intel PMU's BTS events because of
2158 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2159 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2161 * Avoid PEBS_ENABLE MSR access in PMIs.
2162 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2163 * It doesn't matter if the PEBS is enabled or not.
2164 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2165 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2166 * However, there are some cases which may change PEBS status, e.g. PMI
2167 * throttle. The PEBS_ENABLE should be updated where the status changes.
2169 static __always_inline void __intel_pmu_disable_all(bool bts)
2171 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2173 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2175 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2176 intel_pmu_disable_bts();
2179 static __always_inline void intel_pmu_disable_all(void)
2181 __intel_pmu_disable_all(true);
2182 intel_pmu_pebs_disable_all();
2183 intel_pmu_lbr_disable_all();
2186 static void __intel_pmu_enable_all(int added, bool pmi)
2188 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2189 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2191 intel_pmu_lbr_enable_all(pmi);
2192 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2193 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2195 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2196 struct perf_event *event =
2197 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2199 if (WARN_ON_ONCE(!event))
2202 intel_pmu_enable_bts(event->hw.config);
2206 static void intel_pmu_enable_all(int added)
2208 intel_pmu_pebs_enable_all();
2209 __intel_pmu_enable_all(added, false);
2213 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2214 unsigned int cnt, unsigned long flags)
2216 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2218 intel_pmu_lbr_read();
2219 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2221 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2222 intel_pmu_enable_all(0);
2223 local_irq_restore(flags);
2228 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2230 unsigned long flags;
2232 /* must not have branches... */
2233 local_irq_save(flags);
2234 __intel_pmu_disable_all(false); /* we don't care about BTS */
2235 __intel_pmu_lbr_disable();
2236 /* ... until here */
2237 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2241 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2243 unsigned long flags;
2245 /* must not have branches... */
2246 local_irq_save(flags);
2247 __intel_pmu_disable_all(false); /* we don't care about BTS */
2248 __intel_pmu_arch_lbr_disable();
2249 /* ... until here */
2250 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2255 * Intel Errata AAK100 (model 26)
2256 * Intel Errata AAP53 (model 30)
2257 * Intel Errata BD53 (model 44)
2259 * The official story:
2260 * These chips need to be 'reset' when adding counters by programming the
2261 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2262 * in sequence on the same PMC or on different PMCs.
2264 * In practice it appears some of these events do in fact count, and
2265 * we need to program all 4 events.
2267 static void intel_pmu_nhm_workaround(void)
2269 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2270 static const unsigned long nhm_magic[4] = {
2276 struct perf_event *event;
2280 * The Errata requires below steps:
2281 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2282 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2283 * the corresponding PMCx;
2284 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2285 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2286 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2290 * The real steps we choose are a little different from above.
2291 * A) To reduce MSR operations, we don't run step 1) as they
2292 * are already cleared before this function is called;
2293 * B) Call x86_perf_event_update to save PMCx before configuring
2294 * PERFEVTSELx with magic number;
2295 * C) With step 5), we do clear only when the PERFEVTSELx is
2296 * not used currently.
2297 * D) Call x86_perf_event_set_period to restore PMCx;
2300 /* We always operate 4 pairs of PERF Counters */
2301 for (i = 0; i < 4; i++) {
2302 event = cpuc->events[i];
2304 x86_perf_event_update(event);
2307 for (i = 0; i < 4; i++) {
2308 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2309 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2312 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2315 for (i = 0; i < 4; i++) {
2316 event = cpuc->events[i];
2319 x86_perf_event_set_period(event);
2320 __x86_pmu_enable_event(&event->hw,
2321 ARCH_PERFMON_EVENTSEL_ENABLE);
2323 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2327 static void intel_pmu_nhm_enable_all(int added)
2330 intel_pmu_nhm_workaround();
2331 intel_pmu_enable_all(added);
2334 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2336 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2338 if (cpuc->tfa_shadow != val) {
2339 cpuc->tfa_shadow = val;
2340 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2344 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2347 * We're going to use PMC3, make sure TFA is set before we touch it.
2350 intel_set_tfa(cpuc, true);
2353 static void intel_tfa_pmu_enable_all(int added)
2355 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2358 * If we find PMC3 is no longer used when we enable the PMU, we can
2361 if (!test_bit(3, cpuc->active_mask))
2362 intel_set_tfa(cpuc, false);
2364 intel_pmu_enable_all(added);
2367 static inline u64 intel_pmu_get_status(void)
2371 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2376 static inline void intel_pmu_ack_status(u64 ack)
2378 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2381 static inline bool event_is_checkpointed(struct perf_event *event)
2383 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2386 static inline void intel_set_masks(struct perf_event *event, int idx)
2388 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2390 if (event->attr.exclude_host)
2391 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2392 if (event->attr.exclude_guest)
2393 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2394 if (event_is_checkpointed(event))
2395 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2398 static inline void intel_clear_masks(struct perf_event *event, int idx)
2400 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2402 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2403 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2404 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2407 static void intel_pmu_disable_fixed(struct perf_event *event)
2409 struct hw_perf_event *hwc = &event->hw;
2413 if (is_topdown_idx(idx)) {
2414 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2417 * When there are other active TopDown events,
2418 * don't disable the fixed counter 3.
2420 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2422 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2425 intel_clear_masks(event, idx);
2427 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2428 rdmsrl(hwc->config_base, ctrl_val);
2430 wrmsrl(hwc->config_base, ctrl_val);
2433 static void intel_pmu_disable_event(struct perf_event *event)
2435 struct hw_perf_event *hwc = &event->hw;
2439 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2440 intel_clear_masks(event, idx);
2441 x86_pmu_disable_event(event);
2443 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2444 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2445 intel_pmu_disable_fixed(event);
2447 case INTEL_PMC_IDX_FIXED_BTS:
2448 intel_pmu_disable_bts();
2449 intel_pmu_drain_bts_buffer();
2451 case INTEL_PMC_IDX_FIXED_VLBR:
2452 intel_clear_masks(event, idx);
2455 intel_clear_masks(event, idx);
2456 pr_warn("Failed to disable the event with invalid index %d\n",
2462 * Needs to be called after x86_pmu_disable_event,
2463 * so we don't trigger the event without PEBS bit set.
2465 if (unlikely(event->attr.precise_ip))
2466 intel_pmu_pebs_disable(event);
2469 static void intel_pmu_assign_event(struct perf_event *event, int idx)
2471 if (is_pebs_pt(event))
2472 perf_report_aux_output_id(event, idx);
2475 static void intel_pmu_del_event(struct perf_event *event)
2477 if (needs_branch_stack(event))
2478 intel_pmu_lbr_del(event);
2479 if (event->attr.precise_ip)
2480 intel_pmu_pebs_del(event);
2483 static int icl_set_topdown_event_period(struct perf_event *event)
2485 struct hw_perf_event *hwc = &event->hw;
2486 s64 left = local64_read(&hwc->period_left);
2489 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2490 * Software should start both registers, PERF_METRICS and fixed
2491 * counter 3, from zero.
2492 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2493 * After that, both MSRs will be cleared for each read.
2494 * Don't need to clear them again.
2496 if (left == x86_pmu.max_period) {
2497 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2498 wrmsrl(MSR_PERF_METRICS, 0);
2499 hwc->saved_slots = 0;
2500 hwc->saved_metric = 0;
2503 if ((hwc->saved_slots) && is_slots_event(event)) {
2504 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2505 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2508 perf_event_update_userpage(event);
2513 static int adl_set_topdown_event_period(struct perf_event *event)
2515 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2517 if (pmu->cpu_type != hybrid_big)
2520 return icl_set_topdown_event_period(event);
2523 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2528 * The metric is reported as an 8bit integer fraction
2529 * summing up to 0xff.
2530 * slots-in-metric = (Metric / 0xff) * slots
2532 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2533 return mul_u64_u32_div(slots, val, 0xff);
2536 static u64 icl_get_topdown_value(struct perf_event *event,
2537 u64 slots, u64 metrics)
2539 int idx = event->hw.idx;
2542 if (is_metric_idx(idx))
2543 delta = icl_get_metrics_event_value(metrics, slots, idx);
2550 static void __icl_update_topdown_event(struct perf_event *event,
2551 u64 slots, u64 metrics,
2552 u64 last_slots, u64 last_metrics)
2554 u64 delta, last = 0;
2556 delta = icl_get_topdown_value(event, slots, metrics);
2558 last = icl_get_topdown_value(event, last_slots, last_metrics);
2561 * The 8bit integer fraction of metric may be not accurate,
2562 * especially when the changes is very small.
2563 * For example, if only a few bad_spec happens, the fraction
2564 * may be reduced from 1 to 0. If so, the bad_spec event value
2565 * will be 0 which is definitely less than the last value.
2566 * Avoid update event->count for this case.
2570 local64_add(delta, &event->count);
2574 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2575 u64 metrics, int metric_end)
2577 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2578 struct perf_event *other;
2581 event->hw.saved_slots = slots;
2582 event->hw.saved_metric = metrics;
2584 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2585 if (!is_topdown_idx(idx))
2587 other = cpuc->events[idx];
2588 other->hw.saved_slots = slots;
2589 other->hw.saved_metric = metrics;
2594 * Update all active Topdown events.
2596 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2597 * modify by a NMI. PMU has to be disabled before calling this function.
2600 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2602 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2603 struct perf_event *other;
2608 /* read Fixed counter 3 */
2609 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2613 /* read PERF_METRICS */
2614 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2616 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2617 if (!is_topdown_idx(idx))
2619 other = cpuc->events[idx];
2620 __icl_update_topdown_event(other, slots, metrics,
2621 event ? event->hw.saved_slots : 0,
2622 event ? event->hw.saved_metric : 0);
2626 * Check and update this event, which may have been cleared
2627 * in active_mask e.g. x86_pmu_stop()
2629 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2630 __icl_update_topdown_event(event, slots, metrics,
2631 event->hw.saved_slots,
2632 event->hw.saved_metric);
2635 * In x86_pmu_stop(), the event is cleared in active_mask first,
2636 * then drain the delta, which indicates context switch for
2638 * Save metric and slots for context switch.
2639 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2640 * Because the values will be restored in next schedule in.
2642 update_saved_topdown_regs(event, slots, metrics, metric_end);
2647 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2648 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2649 wrmsrl(MSR_PERF_METRICS, 0);
2651 update_saved_topdown_regs(event, 0, 0, metric_end);
2657 static u64 icl_update_topdown_event(struct perf_event *event)
2659 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2660 x86_pmu.num_topdown_events - 1);
2663 static u64 adl_update_topdown_event(struct perf_event *event)
2665 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2667 if (pmu->cpu_type != hybrid_big)
2670 return icl_update_topdown_event(event);
2674 static void intel_pmu_read_topdown_event(struct perf_event *event)
2676 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2678 /* Only need to call update_topdown_event() once for group read. */
2679 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2680 !is_slots_event(event))
2683 perf_pmu_disable(event->pmu);
2684 x86_pmu.update_topdown_event(event);
2685 perf_pmu_enable(event->pmu);
2688 static void intel_pmu_read_event(struct perf_event *event)
2690 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2691 intel_pmu_auto_reload_read(event);
2692 else if (is_topdown_count(event) && x86_pmu.update_topdown_event)
2693 intel_pmu_read_topdown_event(event);
2695 x86_perf_event_update(event);
2698 static void intel_pmu_enable_fixed(struct perf_event *event)
2700 struct hw_perf_event *hwc = &event->hw;
2701 u64 ctrl_val, mask, bits = 0;
2704 if (is_topdown_idx(idx)) {
2705 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2707 * When there are other active TopDown events,
2708 * don't enable the fixed counter 3 again.
2710 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2713 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2716 intel_set_masks(event, idx);
2719 * Enable IRQ generation (0x8), if not PEBS,
2720 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2723 if (!event->attr.precise_ip)
2725 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2727 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2731 * ANY bit is supported in v3 and up
2733 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2736 idx -= INTEL_PMC_IDX_FIXED;
2738 mask = 0xfULL << (idx * 4);
2740 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2741 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2742 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2745 rdmsrl(hwc->config_base, ctrl_val);
2748 wrmsrl(hwc->config_base, ctrl_val);
2751 static void intel_pmu_enable_event(struct perf_event *event)
2753 struct hw_perf_event *hwc = &event->hw;
2756 if (unlikely(event->attr.precise_ip))
2757 intel_pmu_pebs_enable(event);
2760 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2761 intel_set_masks(event, idx);
2762 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2764 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2765 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2766 intel_pmu_enable_fixed(event);
2768 case INTEL_PMC_IDX_FIXED_BTS:
2769 if (!__this_cpu_read(cpu_hw_events.enabled))
2771 intel_pmu_enable_bts(hwc->config);
2773 case INTEL_PMC_IDX_FIXED_VLBR:
2774 intel_set_masks(event, idx);
2777 pr_warn("Failed to enable the event with invalid index %d\n",
2782 static void intel_pmu_add_event(struct perf_event *event)
2784 if (event->attr.precise_ip)
2785 intel_pmu_pebs_add(event);
2786 if (needs_branch_stack(event))
2787 intel_pmu_lbr_add(event);
2791 * Save and restart an expired event. Called by NMI contexts,
2792 * so it has to be careful about preempting normal event ops:
2794 int intel_pmu_save_and_restart(struct perf_event *event)
2796 x86_perf_event_update(event);
2798 * For a checkpointed counter always reset back to 0. This
2799 * avoids a situation where the counter overflows, aborts the
2800 * transaction and is then set back to shortly before the
2801 * overflow, and overflows and aborts again.
2803 if (unlikely(event_is_checkpointed(event))) {
2804 /* No race with NMIs because the counter should not be armed */
2805 wrmsrl(event->hw.event_base, 0);
2806 local64_set(&event->hw.prev_count, 0);
2808 return x86_perf_event_set_period(event);
2811 static void intel_pmu_reset(void)
2813 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2814 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2815 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2816 int num_counters = hybrid(cpuc->pmu, num_counters);
2817 unsigned long flags;
2823 local_irq_save(flags);
2825 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2827 for (idx = 0; idx < num_counters; idx++) {
2828 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2829 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2831 for (idx = 0; idx < num_counters_fixed; idx++) {
2832 if (fixed_counter_disabled(idx, cpuc->pmu))
2834 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2838 ds->bts_index = ds->bts_buffer_base;
2840 /* Ack all overflows and disable fixed counters */
2841 if (x86_pmu.version >= 2) {
2842 intel_pmu_ack_status(intel_pmu_get_status());
2843 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2846 /* Reset LBRs and LBR freezing */
2847 if (x86_pmu.lbr_nr) {
2848 update_debugctlmsr(get_debugctlmsr() &
2849 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2852 local_irq_restore(flags);
2855 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2857 struct perf_sample_data data;
2858 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2861 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2863 inc_irq_stat(apic_perf_irqs);
2866 * Ignore a range of extra bits in status that do not indicate
2867 * overflow by themselves.
2869 status &= ~(GLOBAL_STATUS_COND_CHG |
2870 GLOBAL_STATUS_ASIF |
2871 GLOBAL_STATUS_LBRS_FROZEN);
2875 * In case multiple PEBS events are sampled at the same time,
2876 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2877 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2878 * having their bits set in the status register. This is a sign
2879 * that there was at least one PEBS record pending at the time
2880 * of the PMU interrupt. PEBS counters must only be processed
2881 * via the drain_pebs() calls and not via the regular sample
2882 * processing loop coming after that the function, otherwise
2883 * phony regular samples may be generated in the sampling buffer
2884 * not marked with the EXACT tag. Another possibility is to have
2885 * one PEBS event and at least one non-PEBS event which overflows
2886 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2887 * not be set, yet the overflow status bit for the PEBS counter will
2890 * To avoid this problem, we systematically ignore the PEBS-enabled
2891 * counters from the GLOBAL_STATUS mask and we always process PEBS
2892 * events via drain_pebs().
2894 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2895 status &= ~cpuc->pebs_enabled;
2897 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2900 * PEBS overflow sets bit 62 in the global status register
2902 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2903 u64 pebs_enabled = cpuc->pebs_enabled;
2906 x86_pmu.drain_pebs(regs, &data);
2907 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2910 * PMI throttle may be triggered, which stops the PEBS event.
2911 * Although cpuc->pebs_enabled is updated accordingly, the
2912 * MSR_IA32_PEBS_ENABLE is not updated. Because the
2913 * cpuc->enabled has been forced to 0 in PMI.
2914 * Update the MSR if pebs_enabled is changed.
2916 if (pebs_enabled != cpuc->pebs_enabled)
2917 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2923 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2925 if (!perf_guest_handle_intel_pt_intr())
2926 intel_pt_interrupt();
2930 * Intel Perf metrics
2932 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
2934 if (x86_pmu.update_topdown_event)
2935 x86_pmu.update_topdown_event(NULL);
2939 * Checkpointed counters can lead to 'spurious' PMIs because the
2940 * rollback caused by the PMI will have cleared the overflow status
2941 * bit. Therefore always force probe these counters.
2943 status |= cpuc->intel_cp_status;
2945 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2946 struct perf_event *event = cpuc->events[bit];
2950 if (!test_bit(bit, cpuc->active_mask))
2953 if (!intel_pmu_save_and_restart(event))
2956 perf_sample_data_init(&data, 0, event->hw.last_period);
2958 if (has_branch_stack(event))
2959 data.br_stack = &cpuc->lbr_stack;
2961 if (perf_event_overflow(event, &data, regs))
2962 x86_pmu_stop(event, 0);
2969 * This handler is triggered by the local APIC, so the APIC IRQ handling
2972 static int intel_pmu_handle_irq(struct pt_regs *regs)
2974 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2975 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
2976 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
2983 * Save the PMU state.
2984 * It needs to be restored when leaving the handler.
2986 pmu_enabled = cpuc->enabled;
2988 * In general, the early ACK is only applied for old platforms.
2989 * For the big core starts from Haswell, the late ACK should be
2991 * For the small core after Tremont, we have to do the ACK right
2992 * before re-enabling counters, which is in the middle of the
2995 if (!late_ack && !mid_ack)
2996 apic_write(APIC_LVTPC, APIC_DM_NMI);
2997 intel_bts_disable_local();
2999 __intel_pmu_disable_all(true);
3000 handled = intel_pmu_drain_bts_buffer();
3001 handled += intel_bts_interrupt();
3002 status = intel_pmu_get_status();
3008 intel_pmu_lbr_read();
3009 intel_pmu_ack_status(status);
3010 if (++loops > 100) {
3014 WARN(1, "perfevents: irq loop stuck!\n");
3015 perf_event_print_debug();
3022 handled += handle_pmi_common(regs, status);
3025 * Repeat if there is more work to be done:
3027 status = intel_pmu_get_status();
3033 apic_write(APIC_LVTPC, APIC_DM_NMI);
3034 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3035 cpuc->enabled = pmu_enabled;
3037 __intel_pmu_enable_all(0, true);
3038 intel_bts_enable_local();
3041 * Only unmask the NMI after the overflow counters
3042 * have been reset. This avoids spurious NMIs on
3046 apic_write(APIC_LVTPC, APIC_DM_NMI);
3050 static struct event_constraint *
3051 intel_bts_constraints(struct perf_event *event)
3053 if (unlikely(intel_pmu_has_bts(event)))
3054 return &bts_constraint;
3060 * Note: matches a fake event, like Fixed2.
3062 static struct event_constraint *
3063 intel_vlbr_constraints(struct perf_event *event)
3065 struct event_constraint *c = &vlbr_constraint;
3067 if (unlikely(constraint_match(c, event->hw.config))) {
3068 event->hw.flags |= c->flags;
3075 static int intel_alt_er(struct cpu_hw_events *cpuc,
3076 int idx, u64 config)
3078 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3081 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3084 if (idx == EXTRA_REG_RSP_0)
3085 alt_idx = EXTRA_REG_RSP_1;
3087 if (idx == EXTRA_REG_RSP_1)
3088 alt_idx = EXTRA_REG_RSP_0;
3090 if (config & ~extra_regs[alt_idx].valid_mask)
3096 static void intel_fixup_er(struct perf_event *event, int idx)
3098 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3099 event->hw.extra_reg.idx = idx;
3101 if (idx == EXTRA_REG_RSP_0) {
3102 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3103 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3104 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3105 } else if (idx == EXTRA_REG_RSP_1) {
3106 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3107 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3108 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3113 * manage allocation of shared extra msr for certain events
3116 * per-cpu: to be shared between the various events on a single PMU
3117 * per-core: per-cpu + shared by HT threads
3119 static struct event_constraint *
3120 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3121 struct perf_event *event,
3122 struct hw_perf_event_extra *reg)
3124 struct event_constraint *c = &emptyconstraint;
3125 struct er_account *era;
3126 unsigned long flags;
3130 * reg->alloc can be set due to existing state, so for fake cpuc we
3131 * need to ignore this, otherwise we might fail to allocate proper fake
3132 * state for this extra reg constraint. Also see the comment below.
3134 if (reg->alloc && !cpuc->is_fake)
3135 return NULL; /* call x86_get_event_constraint() */
3138 era = &cpuc->shared_regs->regs[idx];
3140 * we use spin_lock_irqsave() to avoid lockdep issues when
3141 * passing a fake cpuc
3143 raw_spin_lock_irqsave(&era->lock, flags);
3145 if (!atomic_read(&era->ref) || era->config == reg->config) {
3148 * If its a fake cpuc -- as per validate_{group,event}() we
3149 * shouldn't touch event state and we can avoid doing so
3150 * since both will only call get_event_constraints() once
3151 * on each event, this avoids the need for reg->alloc.
3153 * Not doing the ER fixup will only result in era->reg being
3154 * wrong, but since we won't actually try and program hardware
3155 * this isn't a problem either.
3157 if (!cpuc->is_fake) {
3158 if (idx != reg->idx)
3159 intel_fixup_er(event, idx);
3162 * x86_schedule_events() can call get_event_constraints()
3163 * multiple times on events in the case of incremental
3164 * scheduling(). reg->alloc ensures we only do the ER
3170 /* lock in msr value */
3171 era->config = reg->config;
3172 era->reg = reg->reg;
3175 atomic_inc(&era->ref);
3178 * need to call x86_get_event_constraint()
3179 * to check if associated event has constraints
3183 idx = intel_alt_er(cpuc, idx, reg->config);
3184 if (idx != reg->idx) {
3185 raw_spin_unlock_irqrestore(&era->lock, flags);
3189 raw_spin_unlock_irqrestore(&era->lock, flags);
3195 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3196 struct hw_perf_event_extra *reg)
3198 struct er_account *era;
3201 * Only put constraint if extra reg was actually allocated. Also takes
3202 * care of event which do not use an extra shared reg.
3204 * Also, if this is a fake cpuc we shouldn't touch any event state
3205 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3206 * either since it'll be thrown out.
3208 if (!reg->alloc || cpuc->is_fake)
3211 era = &cpuc->shared_regs->regs[reg->idx];
3213 /* one fewer user */
3214 atomic_dec(&era->ref);
3216 /* allocate again next time */
3220 static struct event_constraint *
3221 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3222 struct perf_event *event)
3224 struct event_constraint *c = NULL, *d;
3225 struct hw_perf_event_extra *xreg, *breg;
3227 xreg = &event->hw.extra_reg;
3228 if (xreg->idx != EXTRA_REG_NONE) {
3229 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3230 if (c == &emptyconstraint)
3233 breg = &event->hw.branch_reg;
3234 if (breg->idx != EXTRA_REG_NONE) {
3235 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3236 if (d == &emptyconstraint) {
3237 __intel_shared_reg_put_constraints(cpuc, xreg);
3244 struct event_constraint *
3245 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3246 struct perf_event *event)
3248 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3249 struct event_constraint *c;
3251 if (event_constraints) {
3252 for_each_event_constraint(c, event_constraints) {
3253 if (constraint_match(c, event->hw.config)) {
3254 event->hw.flags |= c->flags;
3260 return &hybrid_var(cpuc->pmu, unconstrained);
3263 static struct event_constraint *
3264 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3265 struct perf_event *event)
3267 struct event_constraint *c;
3269 c = intel_vlbr_constraints(event);
3273 c = intel_bts_constraints(event);
3277 c = intel_shared_regs_constraints(cpuc, event);
3281 c = intel_pebs_constraints(event);
3285 return x86_get_event_constraints(cpuc, idx, event);
3289 intel_start_scheduling(struct cpu_hw_events *cpuc)
3291 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3292 struct intel_excl_states *xl;
3293 int tid = cpuc->excl_thread_id;
3296 * nothing needed if in group validation mode
3298 if (cpuc->is_fake || !is_ht_workaround_enabled())
3302 * no exclusion needed
3304 if (WARN_ON_ONCE(!excl_cntrs))
3307 xl = &excl_cntrs->states[tid];
3309 xl->sched_started = true;
3311 * lock shared state until we are done scheduling
3312 * in stop_event_scheduling()
3313 * makes scheduling appear as a transaction
3315 raw_spin_lock(&excl_cntrs->lock);
3318 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3320 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3321 struct event_constraint *c = cpuc->event_constraint[idx];
3322 struct intel_excl_states *xl;
3323 int tid = cpuc->excl_thread_id;
3325 if (cpuc->is_fake || !is_ht_workaround_enabled())
3328 if (WARN_ON_ONCE(!excl_cntrs))
3331 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3334 xl = &excl_cntrs->states[tid];
3336 lockdep_assert_held(&excl_cntrs->lock);
3338 if (c->flags & PERF_X86_EVENT_EXCL)
3339 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3341 xl->state[cntr] = INTEL_EXCL_SHARED;
3345 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3347 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3348 struct intel_excl_states *xl;
3349 int tid = cpuc->excl_thread_id;
3352 * nothing needed if in group validation mode
3354 if (cpuc->is_fake || !is_ht_workaround_enabled())
3357 * no exclusion needed
3359 if (WARN_ON_ONCE(!excl_cntrs))
3362 xl = &excl_cntrs->states[tid];
3364 xl->sched_started = false;
3366 * release shared state lock (acquired in intel_start_scheduling())
3368 raw_spin_unlock(&excl_cntrs->lock);
3371 static struct event_constraint *
3372 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3374 WARN_ON_ONCE(!cpuc->constraint_list);
3376 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3377 struct event_constraint *cx;
3380 * grab pre-allocated constraint entry
3382 cx = &cpuc->constraint_list[idx];
3385 * initialize dynamic constraint
3386 * with static constraint
3391 * mark constraint as dynamic
3393 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3400 static struct event_constraint *
3401 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3402 int idx, struct event_constraint *c)
3404 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3405 struct intel_excl_states *xlo;
3406 int tid = cpuc->excl_thread_id;
3410 * validating a group does not require
3411 * enforcing cross-thread exclusion
3413 if (cpuc->is_fake || !is_ht_workaround_enabled())
3417 * no exclusion needed
3419 if (WARN_ON_ONCE(!excl_cntrs))
3423 * because we modify the constraint, we need
3424 * to make a copy. Static constraints come
3425 * from static const tables.
3427 * only needed when constraint has not yet
3428 * been cloned (marked dynamic)
3430 c = dyn_constraint(cpuc, c, idx);
3433 * From here on, the constraint is dynamic.
3434 * Either it was just allocated above, or it
3435 * was allocated during a earlier invocation
3440 * state of sibling HT
3442 xlo = &excl_cntrs->states[tid ^ 1];
3445 * event requires exclusive counter access
3448 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3449 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3450 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3451 if (!cpuc->n_excl++)
3452 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3456 * Modify static constraint with current dynamic
3459 * EXCLUSIVE: sibling counter measuring exclusive event
3460 * SHARED : sibling counter measuring non-exclusive event
3461 * UNUSED : sibling counter unused
3464 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3466 * exclusive event in sibling counter
3467 * our corresponding counter cannot be used
3468 * regardless of our event
3470 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3471 __clear_bit(i, c->idxmsk);
3476 * if measuring an exclusive event, sibling
3477 * measuring non-exclusive, then counter cannot
3480 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3481 __clear_bit(i, c->idxmsk);
3488 * if we return an empty mask, then switch
3489 * back to static empty constraint to avoid
3490 * the cost of freeing later on
3493 c = &emptyconstraint;
3500 static struct event_constraint *
3501 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3502 struct perf_event *event)
3504 struct event_constraint *c1, *c2;
3506 c1 = cpuc->event_constraint[idx];
3510 * - static constraint: no change across incremental scheduling calls
3511 * - dynamic constraint: handled by intel_get_excl_constraints()
3513 c2 = __intel_get_event_constraints(cpuc, idx, event);
3515 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3516 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3517 c1->weight = c2->weight;
3521 if (cpuc->excl_cntrs)
3522 return intel_get_excl_constraints(cpuc, event, idx, c2);
3527 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3528 struct perf_event *event)
3530 struct hw_perf_event *hwc = &event->hw;
3531 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3532 int tid = cpuc->excl_thread_id;
3533 struct intel_excl_states *xl;
3536 * nothing needed if in group validation mode
3541 if (WARN_ON_ONCE(!excl_cntrs))
3544 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3545 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3546 if (!--cpuc->n_excl)
3547 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3551 * If event was actually assigned, then mark the counter state as
3554 if (hwc->idx >= 0) {
3555 xl = &excl_cntrs->states[tid];
3558 * put_constraint may be called from x86_schedule_events()
3559 * which already has the lock held so here make locking
3562 if (!xl->sched_started)
3563 raw_spin_lock(&excl_cntrs->lock);
3565 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3567 if (!xl->sched_started)
3568 raw_spin_unlock(&excl_cntrs->lock);
3573 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3574 struct perf_event *event)
3576 struct hw_perf_event_extra *reg;
3578 reg = &event->hw.extra_reg;
3579 if (reg->idx != EXTRA_REG_NONE)
3580 __intel_shared_reg_put_constraints(cpuc, reg);
3582 reg = &event->hw.branch_reg;
3583 if (reg->idx != EXTRA_REG_NONE)
3584 __intel_shared_reg_put_constraints(cpuc, reg);
3587 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3588 struct perf_event *event)
3590 intel_put_shared_regs_event_constraints(cpuc, event);
3593 * is PMU has exclusive counter restrictions, then
3594 * all events are subject to and must call the
3595 * put_excl_constraints() routine
3597 if (cpuc->excl_cntrs)
3598 intel_put_excl_constraints(cpuc, event);
3601 static void intel_pebs_aliases_core2(struct perf_event *event)
3603 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3605 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3606 * (0x003c) so that we can use it with PEBS.
3608 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3609 * PEBS capable. However we can use INST_RETIRED.ANY_P
3610 * (0x00c0), which is a PEBS capable event, to get the same
3613 * INST_RETIRED.ANY_P counts the number of cycles that retires
3614 * CNTMASK instructions. By setting CNTMASK to a value (16)
3615 * larger than the maximum number of instructions that can be
3616 * retired per cycle (4) and then inverting the condition, we
3617 * count all cycles that retire 16 or less instructions, which
3620 * Thereby we gain a PEBS capable cycle counter.
3622 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3624 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3625 event->hw.config = alt_config;
3629 static void intel_pebs_aliases_snb(struct perf_event *event)
3631 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3633 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3634 * (0x003c) so that we can use it with PEBS.
3636 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3637 * PEBS capable. However we can use UOPS_RETIRED.ALL
3638 * (0x01c2), which is a PEBS capable event, to get the same
3641 * UOPS_RETIRED.ALL counts the number of cycles that retires
3642 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3643 * larger than the maximum number of micro-ops that can be
3644 * retired per cycle (4) and then inverting the condition, we
3645 * count all cycles that retire 16 or less micro-ops, which
3648 * Thereby we gain a PEBS capable cycle counter.
3650 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3652 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3653 event->hw.config = alt_config;
3657 static void intel_pebs_aliases_precdist(struct perf_event *event)
3659 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3661 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3662 * (0x003c) so that we can use it with PEBS.
3664 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3665 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3666 * (0x01c0), which is a PEBS capable event, to get the same
3669 * The PREC_DIST event has special support to minimize sample
3670 * shadowing effects. One drawback is that it can be
3671 * only programmed on counter 1, but that seems like an
3672 * acceptable trade off.
3674 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3676 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3677 event->hw.config = alt_config;
3681 static void intel_pebs_aliases_ivb(struct perf_event *event)
3683 if (event->attr.precise_ip < 3)
3684 return intel_pebs_aliases_snb(event);
3685 return intel_pebs_aliases_precdist(event);
3688 static void intel_pebs_aliases_skl(struct perf_event *event)
3690 if (event->attr.precise_ip < 3)
3691 return intel_pebs_aliases_core2(event);
3692 return intel_pebs_aliases_precdist(event);
3695 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3697 unsigned long flags = x86_pmu.large_pebs_flags;
3699 if (event->attr.use_clockid)
3700 flags &= ~PERF_SAMPLE_TIME;
3701 if (!event->attr.exclude_kernel)
3702 flags &= ~PERF_SAMPLE_REGS_USER;
3703 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3704 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3708 static int intel_pmu_bts_config(struct perf_event *event)
3710 struct perf_event_attr *attr = &event->attr;
3712 if (unlikely(intel_pmu_has_bts(event))) {
3713 /* BTS is not supported by this architecture. */
3714 if (!x86_pmu.bts_active)
3717 /* BTS is currently only allowed for user-mode. */
3718 if (!attr->exclude_kernel)
3721 /* BTS is not allowed for precise events. */
3722 if (attr->precise_ip)
3725 /* disallow bts if conflicting events are present */
3726 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3729 event->destroy = hw_perf_lbr_event_destroy;
3735 static int core_pmu_hw_config(struct perf_event *event)
3737 int ret = x86_pmu_hw_config(event);
3742 return intel_pmu_bts_config(event);
3745 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
3746 ((x86_pmu.num_topdown_events - 1) << 8))
3748 static bool is_available_metric_event(struct perf_event *event)
3750 return is_metric_event(event) &&
3751 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3754 static inline bool is_mem_loads_event(struct perf_event *event)
3756 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3759 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3761 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3764 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3766 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3770 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big;
3775 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3777 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3779 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3782 static int intel_pmu_hw_config(struct perf_event *event)
3784 int ret = x86_pmu_hw_config(event);
3789 ret = intel_pmu_bts_config(event);
3793 if (event->attr.precise_ip) {
3794 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3797 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3798 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3799 if (!(event->attr.sample_type &
3800 ~intel_pmu_large_pebs_flags(event))) {
3801 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3802 event->attach_state |= PERF_ATTACH_SCHED_CB;
3805 if (x86_pmu.pebs_aliases)
3806 x86_pmu.pebs_aliases(event);
3808 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3809 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3812 if (needs_branch_stack(event)) {
3813 ret = intel_pmu_setup_lbr_filter(event);
3816 event->attach_state |= PERF_ATTACH_SCHED_CB;
3819 * BTS is set up earlier in this path, so don't account twice
3821 if (!unlikely(intel_pmu_has_bts(event))) {
3822 /* disallow lbr if conflicting events are present */
3823 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3826 event->destroy = hw_perf_lbr_event_destroy;
3830 if (event->attr.aux_output) {
3831 if (!event->attr.precise_ip)
3834 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3837 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
3838 (event->attr.type == PERF_TYPE_HW_CACHE))
3842 * Config Topdown slots and metric events
3844 * The slots event on Fixed Counter 3 can support sampling,
3845 * which will be handled normally in x86_perf_event_update().
3847 * Metric events don't support sampling and require being paired
3848 * with a slots event as group leader. When the slots event
3849 * is used in a metrics group, it too cannot support sampling.
3851 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
3852 if (event->attr.config1 || event->attr.config2)
3856 * The TopDown metrics events and slots event don't
3857 * support any filters.
3859 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3862 if (is_available_metric_event(event)) {
3863 struct perf_event *leader = event->group_leader;
3865 /* The metric events don't support sampling. */
3866 if (is_sampling_event(event))
3869 /* The metric events require a slots group leader. */
3870 if (!is_slots_event(leader))
3874 * The leader/SLOTS must not be a sampling event for
3875 * metric use; hardware requires it starts at 0 when used
3876 * in conjunction with MSR_PERF_METRICS.
3878 if (is_sampling_event(leader))
3881 event->event_caps |= PERF_EV_CAP_SIBLING;
3883 * Only once we have a METRICs sibling do we
3884 * need TopDown magic.
3886 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3887 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3892 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
3893 * doesn't function quite right. As a work-around it needs to always be
3894 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
3895 * The actual count of this second event is irrelevant it just needs
3896 * to be active to make the first event function correctly.
3898 * In a group, the auxiliary event must be in front of the load latency
3899 * event. The rule is to simplify the implementation of the check.
3900 * That's because perf cannot have a complete group at the moment.
3902 if (require_mem_loads_aux_event(event) &&
3903 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
3904 is_mem_loads_event(event)) {
3905 struct perf_event *leader = event->group_leader;
3906 struct perf_event *sibling = NULL;
3908 if (!is_mem_loads_aux_event(leader)) {
3909 for_each_sibling_event(sibling, leader) {
3910 if (is_mem_loads_aux_event(sibling))
3913 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
3918 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3921 if (x86_pmu.version < 3)
3924 ret = perf_allow_cpu(&event->attr);
3928 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3933 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3935 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3936 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3937 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3939 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3940 arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3941 arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3942 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3943 arr[0].guest &= ~cpuc->pebs_enabled;
3945 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3948 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3950 * If PMU counter has PEBS enabled it is not enough to
3951 * disable counter on a guest entry since PEBS memory
3952 * write can overshoot guest entry and corrupt guest
3953 * memory. Disabling PEBS solves the problem.
3955 * Don't do this if the CPU already enforces it.
3957 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3958 arr[1].host = cpuc->pebs_enabled;
3966 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3968 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3969 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3972 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3973 struct perf_event *event = cpuc->events[idx];
3975 arr[idx].msr = x86_pmu_config_addr(idx);
3976 arr[idx].host = arr[idx].guest = 0;
3978 if (!test_bit(idx, cpuc->active_mask))
3981 arr[idx].host = arr[idx].guest =
3982 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3984 if (event->attr.exclude_host)
3985 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3986 else if (event->attr.exclude_guest)
3987 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3990 *nr = x86_pmu.num_counters;
3994 static void core_pmu_enable_event(struct perf_event *event)
3996 if (!event->attr.exclude_host)
3997 x86_pmu_enable_event(event);
4000 static void core_pmu_enable_all(int added)
4002 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4005 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
4006 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4008 if (!test_bit(idx, cpuc->active_mask) ||
4009 cpuc->events[idx]->attr.exclude_host)
4012 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4016 static int hsw_hw_config(struct perf_event *event)
4018 int ret = intel_pmu_hw_config(event);
4022 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4024 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4027 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4028 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4031 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4032 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4033 event->attr.precise_ip > 0))
4036 if (event_is_checkpointed(event)) {
4038 * Sampling of checkpointed events can cause situations where
4039 * the CPU constantly aborts because of a overflow, which is
4040 * then checkpointed back and ignored. Forbid checkpointing
4043 * But still allow a long sampling period, so that perf stat
4046 if (event->attr.sample_period > 0 &&
4047 event->attr.sample_period < 0x7fffffff)
4053 static struct event_constraint counter0_constraint =
4054 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4056 static struct event_constraint counter2_constraint =
4057 EVENT_CONSTRAINT(0, 0x4, 0);
4059 static struct event_constraint fixed0_constraint =
4060 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4062 static struct event_constraint fixed0_counter0_constraint =
4063 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4065 static struct event_constraint *
4066 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4067 struct perf_event *event)
4069 struct event_constraint *c;
4071 c = intel_get_event_constraints(cpuc, idx, event);
4073 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4074 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4075 if (c->idxmsk64 & (1U << 2))
4076 return &counter2_constraint;
4077 return &emptyconstraint;
4083 static struct event_constraint *
4084 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4085 struct perf_event *event)
4088 * Fixed counter 0 has less skid.
4089 * Force instruction:ppp in Fixed counter 0
4091 if ((event->attr.precise_ip == 3) &&
4092 constraint_match(&fixed0_constraint, event->hw.config))
4093 return &fixed0_constraint;
4095 return hsw_get_event_constraints(cpuc, idx, event);
4098 static struct event_constraint *
4099 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4100 struct perf_event *event)
4102 struct event_constraint *c;
4104 c = icl_get_event_constraints(cpuc, idx, event);
4107 * The :ppp indicates the Precise Distribution (PDist) facility, which
4108 * is only supported on the GP counter 0. If a :ppp event which is not
4109 * available on the GP counter 0, error out.
4110 * Exception: Instruction PDIR is only available on the fixed counter 0.
4112 if ((event->attr.precise_ip == 3) &&
4113 !constraint_match(&fixed0_constraint, event->hw.config)) {
4114 if (c->idxmsk64 & BIT_ULL(0))
4115 return &counter0_constraint;
4117 return &emptyconstraint;
4123 static struct event_constraint *
4124 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4125 struct perf_event *event)
4127 struct event_constraint *c;
4129 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4130 if (event->attr.precise_ip == 3)
4131 return &counter0_constraint;
4133 c = intel_get_event_constraints(cpuc, idx, event);
4138 static struct event_constraint *
4139 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4140 struct perf_event *event)
4142 struct event_constraint *c;
4144 c = intel_get_event_constraints(cpuc, idx, event);
4147 * :ppp means to do reduced skid PEBS,
4148 * which is available on PMC0 and fixed counter 0.
4150 if (event->attr.precise_ip == 3) {
4151 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4152 if (constraint_match(&fixed0_constraint, event->hw.config))
4153 return &fixed0_counter0_constraint;
4155 return &counter0_constraint;
4161 static bool allow_tsx_force_abort = true;
4163 static struct event_constraint *
4164 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4165 struct perf_event *event)
4167 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4170 * Without TFA we must not use PMC3.
4172 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4173 c = dyn_constraint(cpuc, c, idx);
4174 c->idxmsk64 &= ~(1ULL << 3);
4181 static struct event_constraint *
4182 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4183 struct perf_event *event)
4185 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4187 if (pmu->cpu_type == hybrid_big)
4188 return spr_get_event_constraints(cpuc, idx, event);
4189 else if (pmu->cpu_type == hybrid_small)
4190 return tnt_get_event_constraints(cpuc, idx, event);
4193 return &emptyconstraint;
4196 static int adl_hw_config(struct perf_event *event)
4198 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4200 if (pmu->cpu_type == hybrid_big)
4201 return hsw_hw_config(event);
4202 else if (pmu->cpu_type == hybrid_small)
4203 return intel_pmu_hw_config(event);
4209 static u8 adl_get_hybrid_cpu_type(void)
4217 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4218 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4219 * the two to enforce a minimum period of 128 (the smallest value that has bits
4220 * 0-5 cleared and >= 100).
4222 * Because of how the code in x86_perf_event_set_period() works, the truncation
4223 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4224 * to make up for the 'lost' events due to carrying the 'error' in period_left.
4226 * Therefore the effective (average) period matches the requested period,
4227 * despite coarser hardware granularity.
4229 static u64 bdw_limit_period(struct perf_event *event, u64 left)
4231 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4232 X86_CONFIG(.event=0xc0, .umask=0x01)) {
4240 static u64 nhm_limit_period(struct perf_event *event, u64 left)
4242 return max(left, 32ULL);
4245 static u64 spr_limit_period(struct perf_event *event, u64 left)
4247 if (event->attr.precise_ip == 3)
4248 return max(left, 128ULL);
4253 PMU_FORMAT_ATTR(event, "config:0-7" );
4254 PMU_FORMAT_ATTR(umask, "config:8-15" );
4255 PMU_FORMAT_ATTR(edge, "config:18" );
4256 PMU_FORMAT_ATTR(pc, "config:19" );
4257 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
4258 PMU_FORMAT_ATTR(inv, "config:23" );
4259 PMU_FORMAT_ATTR(cmask, "config:24-31" );
4260 PMU_FORMAT_ATTR(in_tx, "config:32");
4261 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
4263 static struct attribute *intel_arch_formats_attr[] = {
4264 &format_attr_event.attr,
4265 &format_attr_umask.attr,
4266 &format_attr_edge.attr,
4267 &format_attr_pc.attr,
4268 &format_attr_inv.attr,
4269 &format_attr_cmask.attr,
4273 ssize_t intel_event_sysfs_show(char *page, u64 config)
4275 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4277 return x86_event_sysfs_show(page, config, event);
4280 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4282 struct intel_shared_regs *regs;
4285 regs = kzalloc_node(sizeof(struct intel_shared_regs),
4286 GFP_KERNEL, cpu_to_node(cpu));
4289 * initialize the locks to keep lockdep happy
4291 for (i = 0; i < EXTRA_REG_MAX; i++)
4292 raw_spin_lock_init(®s->regs[i].lock);
4299 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4301 struct intel_excl_cntrs *c;
4303 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4304 GFP_KERNEL, cpu_to_node(cpu));
4306 raw_spin_lock_init(&c->lock);
4313 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4315 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4317 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4318 cpuc->shared_regs = allocate_shared_regs(cpu);
4319 if (!cpuc->shared_regs)
4323 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4324 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4326 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4327 if (!cpuc->constraint_list)
4328 goto err_shared_regs;
4331 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4332 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4333 if (!cpuc->excl_cntrs)
4334 goto err_constraint_list;
4336 cpuc->excl_thread_id = 0;
4341 err_constraint_list:
4342 kfree(cpuc->constraint_list);
4343 cpuc->constraint_list = NULL;
4346 kfree(cpuc->shared_regs);
4347 cpuc->shared_regs = NULL;
4353 static int intel_pmu_cpu_prepare(int cpu)
4355 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4358 static void flip_smm_bit(void *data)
4360 unsigned long set = *(unsigned long *)data;
4363 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4364 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4366 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4367 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4371 static bool init_hybrid_pmu(int cpu)
4373 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4374 u8 cpu_type = get_this_hybrid_cpu_type();
4375 struct x86_hybrid_pmu *pmu = NULL;
4378 if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
4379 cpu_type = x86_pmu.get_hybrid_cpu_type();
4381 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
4382 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) {
4383 pmu = &x86_pmu.hybrid_pmu[i];
4387 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
4392 /* Only check and dump the PMU information for the first CPU */
4393 if (!cpumask_empty(&pmu->supported_cpus))
4396 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed))
4399 pr_info("%s PMU driver: ", pmu->name);
4401 if (pmu->intel_cap.pebs_output_pt_available)
4402 pr_cont("PEBS-via-PT ");
4406 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed,
4410 cpumask_set_cpu(cpu, &pmu->supported_cpus);
4411 cpuc->pmu = &pmu->pmu;
4413 x86_pmu_update_cpu_context(&pmu->pmu, cpu);
4418 static void intel_pmu_cpu_starting(int cpu)
4420 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4421 int core_id = topology_core_id(cpu);
4424 if (is_hybrid() && !init_hybrid_pmu(cpu))
4427 init_debug_store_on_cpu(cpu);
4429 * Deal with CPUs that don't clear their LBRs on power-up.
4431 intel_pmu_lbr_reset();
4433 cpuc->lbr_sel = NULL;
4435 if (x86_pmu.flags & PMU_FL_TFA) {
4436 WARN_ON_ONCE(cpuc->tfa_shadow);
4437 cpuc->tfa_shadow = ~0ULL;
4438 intel_set_tfa(cpuc, false);
4441 if (x86_pmu.version > 1)
4442 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4445 * Disable perf metrics if any added CPU doesn't support it.
4447 * Turn off the check for a hybrid architecture, because the
4448 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
4449 * the architecture features. The perf metrics is a model-specific
4450 * feature for now. The corresponding bit should always be 0 on
4451 * a hybrid platform, e.g., Alder Lake.
4453 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
4454 union perf_capabilities perf_cap;
4456 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4457 if (!perf_cap.perf_metrics) {
4458 x86_pmu.intel_cap.perf_metrics = 0;
4459 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4463 if (!cpuc->shared_regs)
4466 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4467 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4468 struct intel_shared_regs *pc;
4470 pc = per_cpu(cpu_hw_events, i).shared_regs;
4471 if (pc && pc->core_id == core_id) {
4472 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4473 cpuc->shared_regs = pc;
4477 cpuc->shared_regs->core_id = core_id;
4478 cpuc->shared_regs->refcnt++;
4481 if (x86_pmu.lbr_sel_map)
4482 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4484 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4485 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4486 struct cpu_hw_events *sibling;
4487 struct intel_excl_cntrs *c;
4489 sibling = &per_cpu(cpu_hw_events, i);
4490 c = sibling->excl_cntrs;
4491 if (c && c->core_id == core_id) {
4492 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4493 cpuc->excl_cntrs = c;
4494 if (!sibling->excl_thread_id)
4495 cpuc->excl_thread_id = 1;
4499 cpuc->excl_cntrs->core_id = core_id;
4500 cpuc->excl_cntrs->refcnt++;
4504 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4506 struct intel_excl_cntrs *c;
4508 c = cpuc->excl_cntrs;
4510 if (c->core_id == -1 || --c->refcnt == 0)
4512 cpuc->excl_cntrs = NULL;
4515 kfree(cpuc->constraint_list);
4516 cpuc->constraint_list = NULL;
4519 static void intel_pmu_cpu_dying(int cpu)
4521 fini_debug_store_on_cpu(cpu);
4524 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4526 struct intel_shared_regs *pc;
4528 pc = cpuc->shared_regs;
4530 if (pc->core_id == -1 || --pc->refcnt == 0)
4532 cpuc->shared_regs = NULL;
4535 free_excl_cntrs(cpuc);
4538 static void intel_pmu_cpu_dead(int cpu)
4540 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4542 intel_cpuc_finish(cpuc);
4544 if (is_hybrid() && cpuc->pmu)
4545 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
4548 static void intel_pmu_sched_task(struct perf_event_context *ctx,
4551 intel_pmu_pebs_sched_task(ctx, sched_in);
4552 intel_pmu_lbr_sched_task(ctx, sched_in);
4555 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
4556 struct perf_event_context *next)
4558 intel_pmu_lbr_swap_task_ctx(prev, next);
4561 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4563 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4566 static void intel_aux_output_init(void)
4568 /* Refer also intel_pmu_aux_output_match() */
4569 if (x86_pmu.intel_cap.pebs_output_pt_available)
4570 x86_pmu.assign = intel_pmu_assign_event;
4573 static int intel_pmu_aux_output_match(struct perf_event *event)
4575 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
4576 if (!x86_pmu.intel_cap.pebs_output_pt_available)
4579 return is_intel_pt_event(event);
4582 static int intel_pmu_filter_match(struct perf_event *event)
4584 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4585 unsigned int cpu = smp_processor_id();
4587 return cpumask_test_cpu(cpu, &pmu->supported_cpus);
4590 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4592 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4594 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4596 static struct attribute *intel_arch3_formats_attr[] = {
4597 &format_attr_event.attr,
4598 &format_attr_umask.attr,
4599 &format_attr_edge.attr,
4600 &format_attr_pc.attr,
4601 &format_attr_any.attr,
4602 &format_attr_inv.attr,
4603 &format_attr_cmask.attr,
4607 static struct attribute *hsw_format_attr[] = {
4608 &format_attr_in_tx.attr,
4609 &format_attr_in_tx_cp.attr,
4610 &format_attr_offcore_rsp.attr,
4611 &format_attr_ldlat.attr,
4615 static struct attribute *nhm_format_attr[] = {
4616 &format_attr_offcore_rsp.attr,
4617 &format_attr_ldlat.attr,
4621 static struct attribute *slm_format_attr[] = {
4622 &format_attr_offcore_rsp.attr,
4626 static struct attribute *skl_format_attr[] = {
4627 &format_attr_frontend.attr,
4631 static __initconst const struct x86_pmu core_pmu = {
4633 .handle_irq = x86_pmu_handle_irq,
4634 .disable_all = x86_pmu_disable_all,
4635 .enable_all = core_pmu_enable_all,
4636 .enable = core_pmu_enable_event,
4637 .disable = x86_pmu_disable_event,
4638 .hw_config = core_pmu_hw_config,
4639 .schedule_events = x86_schedule_events,
4640 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4641 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4642 .event_map = intel_pmu_event_map,
4643 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4645 .large_pebs_flags = LARGE_PEBS_FLAGS,
4648 * Intel PMCs cannot be accessed sanely above 32-bit width,
4649 * so we install an artificial 1<<31 period regardless of
4650 * the generic event period:
4652 .max_period = (1ULL<<31) - 1,
4653 .get_event_constraints = intel_get_event_constraints,
4654 .put_event_constraints = intel_put_event_constraints,
4655 .event_constraints = intel_core_event_constraints,
4656 .guest_get_msrs = core_guest_get_msrs,
4657 .format_attrs = intel_arch_formats_attr,
4658 .events_sysfs_show = intel_event_sysfs_show,
4661 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4662 * together with PMU version 1 and thus be using core_pmu with
4663 * shared_regs. We need following callbacks here to allocate
4666 .cpu_prepare = intel_pmu_cpu_prepare,
4667 .cpu_starting = intel_pmu_cpu_starting,
4668 .cpu_dying = intel_pmu_cpu_dying,
4669 .cpu_dead = intel_pmu_cpu_dead,
4671 .check_period = intel_pmu_check_period,
4673 .lbr_reset = intel_pmu_lbr_reset_64,
4674 .lbr_read = intel_pmu_lbr_read_64,
4675 .lbr_save = intel_pmu_lbr_save,
4676 .lbr_restore = intel_pmu_lbr_restore,
4679 static __initconst const struct x86_pmu intel_pmu = {
4681 .handle_irq = intel_pmu_handle_irq,
4682 .disable_all = intel_pmu_disable_all,
4683 .enable_all = intel_pmu_enable_all,
4684 .enable = intel_pmu_enable_event,
4685 .disable = intel_pmu_disable_event,
4686 .add = intel_pmu_add_event,
4687 .del = intel_pmu_del_event,
4688 .read = intel_pmu_read_event,
4689 .hw_config = intel_pmu_hw_config,
4690 .schedule_events = x86_schedule_events,
4691 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4692 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4693 .event_map = intel_pmu_event_map,
4694 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4696 .large_pebs_flags = LARGE_PEBS_FLAGS,
4698 * Intel PMCs cannot be accessed sanely above 32 bit width,
4699 * so we install an artificial 1<<31 period regardless of
4700 * the generic event period:
4702 .max_period = (1ULL << 31) - 1,
4703 .get_event_constraints = intel_get_event_constraints,
4704 .put_event_constraints = intel_put_event_constraints,
4705 .pebs_aliases = intel_pebs_aliases_core2,
4707 .format_attrs = intel_arch3_formats_attr,
4708 .events_sysfs_show = intel_event_sysfs_show,
4710 .cpu_prepare = intel_pmu_cpu_prepare,
4711 .cpu_starting = intel_pmu_cpu_starting,
4712 .cpu_dying = intel_pmu_cpu_dying,
4713 .cpu_dead = intel_pmu_cpu_dead,
4715 .guest_get_msrs = intel_guest_get_msrs,
4716 .sched_task = intel_pmu_sched_task,
4717 .swap_task_ctx = intel_pmu_swap_task_ctx,
4719 .check_period = intel_pmu_check_period,
4721 .aux_output_match = intel_pmu_aux_output_match,
4723 .lbr_reset = intel_pmu_lbr_reset_64,
4724 .lbr_read = intel_pmu_lbr_read_64,
4725 .lbr_save = intel_pmu_lbr_save,
4726 .lbr_restore = intel_pmu_lbr_restore,
4729 * SMM has access to all 4 rings and while traditionally SMM code only
4730 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
4732 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
4733 * between SMM or not, this results in what should be pure userspace
4734 * counters including SMM data.
4736 * This is a clear privilege issue, therefore globally disable
4737 * counting SMM by default.
4739 .attr_freeze_on_smi = 1,
4742 static __init void intel_clovertown_quirk(void)
4745 * PEBS is unreliable due to:
4747 * AJ67 - PEBS may experience CPL leaks
4748 * AJ68 - PEBS PMI may be delayed by one event
4749 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4750 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4752 * AJ67 could be worked around by restricting the OS/USR flags.
4753 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4755 * AJ106 could possibly be worked around by not allowing LBR
4756 * usage from PEBS, including the fixup.
4757 * AJ68 could possibly be worked around by always programming
4758 * a pebs_event_reset[0] value and coping with the lost events.
4760 * But taken together it might just make sense to not enable PEBS on
4763 pr_warn("PEBS disabled due to CPU errata\n");
4765 x86_pmu.pebs_constraints = NULL;
4768 static const struct x86_cpu_desc isolation_ucodes[] = {
4769 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
4770 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4771 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4772 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
4773 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
4774 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
4775 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4776 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
4777 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
4778 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
4779 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
4780 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014),
4781 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
4782 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
4783 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000),
4784 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000),
4785 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000),
4786 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
4787 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
4788 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
4789 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
4790 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
4791 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
4792 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
4793 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
4794 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
4795 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
4796 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
4800 static void intel_check_pebs_isolation(void)
4802 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4805 static __init void intel_pebs_isolation_quirk(void)
4807 WARN_ON_ONCE(x86_pmu.check_microcode);
4808 x86_pmu.check_microcode = intel_check_pebs_isolation;
4809 intel_check_pebs_isolation();
4812 static const struct x86_cpu_desc pebs_ucodes[] = {
4813 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
4814 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
4815 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
4819 static bool intel_snb_pebs_broken(void)
4821 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4824 static void intel_snb_check_microcode(void)
4826 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4830 * Serialized by the microcode lock..
4832 if (x86_pmu.pebs_broken) {
4833 pr_info("PEBS enabled due to microcode update\n");
4834 x86_pmu.pebs_broken = 0;
4836 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4837 x86_pmu.pebs_broken = 1;
4841 static bool is_lbr_from(unsigned long msr)
4843 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4845 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4849 * Under certain circumstances, access certain MSR may cause #GP.
4850 * The function tests if the input MSR can be safely accessed.
4852 static bool check_msr(unsigned long msr, u64 mask)
4854 u64 val_old, val_new, val_tmp;
4857 * Disable the check for real HW, so we don't
4858 * mess with potentially enabled registers:
4860 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4864 * Read the current value, change it and read it back to see if it
4865 * matches, this is needed to detect certain hardware emulators
4866 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4868 if (rdmsrl_safe(msr, &val_old))
4872 * Only change the bits which can be updated by wrmsrl.
4874 val_tmp = val_old ^ mask;
4876 if (is_lbr_from(msr))
4877 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4879 if (wrmsrl_safe(msr, val_tmp) ||
4880 rdmsrl_safe(msr, &val_new))
4884 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4885 * should equal rdmsrl()'s even with the quirk.
4887 if (val_new != val_tmp)
4890 if (is_lbr_from(msr))
4891 val_old = lbr_from_signext_quirk_wr(val_old);
4893 /* Here it's sure that the MSR can be safely accessed.
4894 * Restore the old value and return.
4896 wrmsrl(msr, val_old);
4901 static __init void intel_sandybridge_quirk(void)
4903 x86_pmu.check_microcode = intel_snb_check_microcode;
4905 intel_snb_check_microcode();
4909 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4910 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4911 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4912 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4913 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4914 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4915 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4916 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4919 static __init void intel_arch_events_quirk(void)
4923 /* disable event that reported as not present by cpuid */
4924 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4925 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4926 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4927 intel_arch_events_map[bit].name);
4931 static __init void intel_nehalem_quirk(void)
4933 union cpuid10_ebx ebx;
4935 ebx.full = x86_pmu.events_maskl;
4936 if (ebx.split.no_branch_misses_retired) {
4938 * Erratum AAJ80 detected, we work it around by using
4939 * the BR_MISP_EXEC.ANY event. This will over-count
4940 * branch-misses, but it's still much better than the
4941 * architectural event which is often completely bogus:
4943 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4944 ebx.split.no_branch_misses_retired = 0;
4945 x86_pmu.events_maskl = ebx.full;
4946 pr_info("CPU erratum AAJ80 worked around\n");
4951 * enable software workaround for errata:
4956 * Only needed when HT is enabled. However detecting
4957 * if HT is enabled is difficult (model specific). So instead,
4958 * we enable the workaround in the early boot, and verify if
4959 * it is needed in a later initcall phase once we have valid
4960 * topology information to check if HT is actually enabled
4962 static __init void intel_ht_bug(void)
4964 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4966 x86_pmu.start_scheduling = intel_start_scheduling;
4967 x86_pmu.commit_scheduling = intel_commit_scheduling;
4968 x86_pmu.stop_scheduling = intel_stop_scheduling;
4971 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
4972 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
4974 /* Haswell special events */
4975 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
4976 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
4977 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
4978 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
4979 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
4980 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
4981 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
4982 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
4983 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
4984 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
4985 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4986 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4988 static struct attribute *hsw_events_attrs[] = {
4989 EVENT_PTR(td_slots_issued),
4990 EVENT_PTR(td_slots_retired),
4991 EVENT_PTR(td_fetch_bubbles),
4992 EVENT_PTR(td_total_slots),
4993 EVENT_PTR(td_total_slots_scale),
4994 EVENT_PTR(td_recovery_bubbles),
4995 EVENT_PTR(td_recovery_bubbles_scale),
4999 static struct attribute *hsw_mem_events_attrs[] = {
5000 EVENT_PTR(mem_ld_hsw),
5001 EVENT_PTR(mem_st_hsw),
5005 static struct attribute *hsw_tsx_events_attrs[] = {
5006 EVENT_PTR(tx_start),
5007 EVENT_PTR(tx_commit),
5008 EVENT_PTR(tx_abort),
5009 EVENT_PTR(tx_capacity),
5010 EVENT_PTR(tx_conflict),
5011 EVENT_PTR(el_start),
5012 EVENT_PTR(el_commit),
5013 EVENT_PTR(el_abort),
5014 EVENT_PTR(el_capacity),
5015 EVENT_PTR(el_conflict),
5016 EVENT_PTR(cycles_t),
5017 EVENT_PTR(cycles_ct),
5021 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
5022 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
5023 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
5024 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
5026 static struct attribute *icl_events_attrs[] = {
5027 EVENT_PTR(mem_ld_hsw),
5028 EVENT_PTR(mem_st_hsw),
5032 static struct attribute *icl_td_events_attrs[] = {
5034 EVENT_PTR(td_retiring),
5035 EVENT_PTR(td_bad_spec),
5036 EVENT_PTR(td_fe_bound),
5037 EVENT_PTR(td_be_bound),
5041 static struct attribute *icl_tsx_events_attrs[] = {
5042 EVENT_PTR(tx_start),
5043 EVENT_PTR(tx_abort),
5044 EVENT_PTR(tx_commit),
5045 EVENT_PTR(tx_capacity_read),
5046 EVENT_PTR(tx_capacity_write),
5047 EVENT_PTR(tx_conflict),
5048 EVENT_PTR(el_start),
5049 EVENT_PTR(el_abort),
5050 EVENT_PTR(el_commit),
5051 EVENT_PTR(el_capacity_read),
5052 EVENT_PTR(el_capacity_write),
5053 EVENT_PTR(el_conflict),
5054 EVENT_PTR(cycles_t),
5055 EVENT_PTR(cycles_ct),
5060 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
5061 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
5063 static struct attribute *spr_events_attrs[] = {
5064 EVENT_PTR(mem_ld_hsw),
5065 EVENT_PTR(mem_st_spr),
5066 EVENT_PTR(mem_ld_aux),
5070 static struct attribute *spr_td_events_attrs[] = {
5072 EVENT_PTR(td_retiring),
5073 EVENT_PTR(td_bad_spec),
5074 EVENT_PTR(td_fe_bound),
5075 EVENT_PTR(td_be_bound),
5076 EVENT_PTR(td_heavy_ops),
5077 EVENT_PTR(td_br_mispredict),
5078 EVENT_PTR(td_fetch_lat),
5079 EVENT_PTR(td_mem_bound),
5083 static struct attribute *spr_tsx_events_attrs[] = {
5084 EVENT_PTR(tx_start),
5085 EVENT_PTR(tx_abort),
5086 EVENT_PTR(tx_commit),
5087 EVENT_PTR(tx_capacity_read),
5088 EVENT_PTR(tx_capacity_write),
5089 EVENT_PTR(tx_conflict),
5090 EVENT_PTR(cycles_t),
5091 EVENT_PTR(cycles_ct),
5095 static ssize_t freeze_on_smi_show(struct device *cdev,
5096 struct device_attribute *attr,
5099 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5102 static DEFINE_MUTEX(freeze_on_smi_mutex);
5104 static ssize_t freeze_on_smi_store(struct device *cdev,
5105 struct device_attribute *attr,
5106 const char *buf, size_t count)
5111 ret = kstrtoul(buf, 0, &val);
5118 mutex_lock(&freeze_on_smi_mutex);
5120 if (x86_pmu.attr_freeze_on_smi == val)
5123 x86_pmu.attr_freeze_on_smi = val;
5126 on_each_cpu(flip_smm_bit, &val, 1);
5129 mutex_unlock(&freeze_on_smi_mutex);
5134 static void update_tfa_sched(void *ignored)
5136 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5139 * check if PMC3 is used
5140 * and if so force schedule out for all event types all contexts
5142 if (test_bit(3, cpuc->active_mask))
5143 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5146 static ssize_t show_sysctl_tfa(struct device *cdev,
5147 struct device_attribute *attr,
5150 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5153 static ssize_t set_sysctl_tfa(struct device *cdev,
5154 struct device_attribute *attr,
5155 const char *buf, size_t count)
5160 ret = kstrtobool(buf, &val);
5165 if (val == allow_tsx_force_abort)
5168 allow_tsx_force_abort = val;
5171 on_each_cpu(update_tfa_sched, NULL, 1);
5178 static DEVICE_ATTR_RW(freeze_on_smi);
5180 static ssize_t branches_show(struct device *cdev,
5181 struct device_attribute *attr,
5184 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5187 static DEVICE_ATTR_RO(branches);
5189 static struct attribute *lbr_attrs[] = {
5190 &dev_attr_branches.attr,
5194 static char pmu_name_str[30];
5196 static ssize_t pmu_name_show(struct device *cdev,
5197 struct device_attribute *attr,
5200 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
5203 static DEVICE_ATTR_RO(pmu_name);
5205 static struct attribute *intel_pmu_caps_attrs[] = {
5206 &dev_attr_pmu_name.attr,
5210 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5214 static struct attribute *intel_pmu_attrs[] = {
5215 &dev_attr_freeze_on_smi.attr,
5216 &dev_attr_allow_tsx_force_abort.attr,
5221 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5223 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5227 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5229 return x86_pmu.pebs ? attr->mode : 0;
5233 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5235 return x86_pmu.lbr_nr ? attr->mode : 0;
5239 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5241 return x86_pmu.version >= 2 ? attr->mode : 0;
5245 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5247 if (attr == &dev_attr_allow_tsx_force_abort.attr)
5248 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5253 static struct attribute_group group_events_td = {
5257 static struct attribute_group group_events_mem = {
5259 .is_visible = pebs_is_visible,
5262 static struct attribute_group group_events_tsx = {
5264 .is_visible = tsx_is_visible,
5267 static struct attribute_group group_caps_gen = {
5269 .attrs = intel_pmu_caps_attrs,
5272 static struct attribute_group group_caps_lbr = {
5275 .is_visible = lbr_is_visible,
5278 static struct attribute_group group_format_extra = {
5280 .is_visible = exra_is_visible,
5283 static struct attribute_group group_format_extra_skl = {
5285 .is_visible = exra_is_visible,
5288 static struct attribute_group group_default = {
5289 .attrs = intel_pmu_attrs,
5290 .is_visible = default_is_visible,
5293 static const struct attribute_group *attr_update[] = {
5299 &group_format_extra,
5300 &group_format_extra_skl,
5305 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
5306 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
5307 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
5308 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
5309 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
5310 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
5311 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
5312 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
5313 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
5315 static struct attribute *adl_hybrid_events_attrs[] = {
5316 EVENT_PTR(slots_adl),
5317 EVENT_PTR(td_retiring_adl),
5318 EVENT_PTR(td_bad_spec_adl),
5319 EVENT_PTR(td_fe_bound_adl),
5320 EVENT_PTR(td_be_bound_adl),
5321 EVENT_PTR(td_heavy_ops_adl),
5322 EVENT_PTR(td_br_mis_adl),
5323 EVENT_PTR(td_fetch_lat_adl),
5324 EVENT_PTR(td_mem_bound_adl),
5328 /* Must be in IDX order */
5329 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
5330 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
5331 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
5333 static struct attribute *adl_hybrid_mem_attrs[] = {
5334 EVENT_PTR(mem_ld_adl),
5335 EVENT_PTR(mem_st_adl),
5336 EVENT_PTR(mem_ld_aux_adl),
5340 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
5341 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
5342 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
5343 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
5344 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
5345 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
5346 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
5347 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
5349 static struct attribute *adl_hybrid_tsx_attrs[] = {
5350 EVENT_PTR(tx_start_adl),
5351 EVENT_PTR(tx_abort_adl),
5352 EVENT_PTR(tx_commit_adl),
5353 EVENT_PTR(tx_capacity_read_adl),
5354 EVENT_PTR(tx_capacity_write_adl),
5355 EVENT_PTR(tx_conflict_adl),
5356 EVENT_PTR(cycles_t_adl),
5357 EVENT_PTR(cycles_ct_adl),
5361 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
5362 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
5363 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small);
5364 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small);
5365 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
5367 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
5368 FORMAT_HYBRID_PTR(in_tx),
5369 FORMAT_HYBRID_PTR(in_tx_cp),
5370 FORMAT_HYBRID_PTR(offcore_rsp),
5371 FORMAT_HYBRID_PTR(ldlat),
5372 FORMAT_HYBRID_PTR(frontend),
5376 static struct attribute *adl_hybrid_extra_attr[] = {
5377 FORMAT_HYBRID_PTR(offcore_rsp),
5378 FORMAT_HYBRID_PTR(ldlat),
5379 FORMAT_HYBRID_PTR(frontend),
5383 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
5385 struct device *dev = kobj_to_dev(kobj);
5386 struct x86_hybrid_pmu *pmu =
5387 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5388 struct perf_pmu_events_hybrid_attr *pmu_attr =
5389 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
5391 return pmu->cpu_type & pmu_attr->pmu_type;
5394 static umode_t hybrid_events_is_visible(struct kobject *kobj,
5395 struct attribute *attr, int i)
5397 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
5400 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
5402 int cpu = cpumask_first(&pmu->supported_cpus);
5404 return (cpu >= nr_cpu_ids) ? -1 : cpu;
5407 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
5408 struct attribute *attr, int i)
5410 struct device *dev = kobj_to_dev(kobj);
5411 struct x86_hybrid_pmu *pmu =
5412 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5413 int cpu = hybrid_find_supported_cpu(pmu);
5415 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
5418 static umode_t hybrid_format_is_visible(struct kobject *kobj,
5419 struct attribute *attr, int i)
5421 struct device *dev = kobj_to_dev(kobj);
5422 struct x86_hybrid_pmu *pmu =
5423 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5424 struct perf_pmu_format_hybrid_attr *pmu_attr =
5425 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
5426 int cpu = hybrid_find_supported_cpu(pmu);
5428 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0;
5431 static struct attribute_group hybrid_group_events_td = {
5433 .is_visible = hybrid_events_is_visible,
5436 static struct attribute_group hybrid_group_events_mem = {
5438 .is_visible = hybrid_events_is_visible,
5441 static struct attribute_group hybrid_group_events_tsx = {
5443 .is_visible = hybrid_tsx_is_visible,
5446 static struct attribute_group hybrid_group_format_extra = {
5448 .is_visible = hybrid_format_is_visible,
5451 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
5452 struct device_attribute *attr,
5455 struct x86_hybrid_pmu *pmu =
5456 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5458 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
5461 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
5462 static struct attribute *intel_hybrid_cpus_attrs[] = {
5463 &dev_attr_cpus.attr,
5467 static struct attribute_group hybrid_group_cpus = {
5468 .attrs = intel_hybrid_cpus_attrs,
5471 static const struct attribute_group *hybrid_attr_update[] = {
5472 &hybrid_group_events_td,
5473 &hybrid_group_events_mem,
5474 &hybrid_group_events_tsx,
5477 &hybrid_group_format_extra,
5483 static struct attribute *empty_attrs;
5485 static void intel_pmu_check_num_counters(int *num_counters,
5486 int *num_counters_fixed,
5487 u64 *intel_ctrl, u64 fixed_mask)
5489 if (*num_counters > INTEL_PMC_MAX_GENERIC) {
5490 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5491 *num_counters, INTEL_PMC_MAX_GENERIC);
5492 *num_counters = INTEL_PMC_MAX_GENERIC;
5494 *intel_ctrl = (1ULL << *num_counters) - 1;
5496 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5497 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5498 *num_counters_fixed, INTEL_PMC_MAX_FIXED);
5499 *num_counters_fixed = INTEL_PMC_MAX_FIXED;
5502 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED;
5505 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5507 int num_counters_fixed,
5510 struct event_constraint *c;
5512 if (!event_constraints)
5516 * event on fixed counter2 (REF_CYCLES) only works on this
5517 * counter, so do not extend mask to generic counters
5519 for_each_event_constraint(c, event_constraints) {
5521 * Don't extend the topdown slots and metrics
5522 * events to the generic counters.
5524 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5526 * Disable topdown slots and metrics events,
5527 * if slots event is not in CPUID.
5529 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
5531 c->weight = hweight64(c->idxmsk64);
5535 if (c->cmask == FIXED_EVENT_FLAGS) {
5536 /* Disabled fixed counters which are not in CPUID */
5537 c->idxmsk64 &= intel_ctrl;
5540 * Don't extend the pseudo-encoding to the
5543 if (!use_fixed_pseudo_encoding(c->code))
5544 c->idxmsk64 |= (1ULL << num_counters) - 1;
5547 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed));
5548 c->weight = hweight64(c->idxmsk64);
5552 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
5554 struct extra_reg *er;
5557 * Access extra MSR may cause #GP under certain circumstances.
5558 * E.g. KVM doesn't support offcore event
5559 * Check all extra_regs here.
5564 for (er = extra_regs; er->msr; er++) {
5565 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5566 /* Disable LBR select mapping */
5567 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5568 x86_pmu.lbr_sel_map = NULL;
5572 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask)
5574 struct x86_hybrid_pmu *pmu;
5577 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5578 pmu = &x86_pmu.hybrid_pmu[i];
5580 intel_pmu_check_num_counters(&pmu->num_counters,
5581 &pmu->num_counters_fixed,
5585 if (pmu->intel_cap.perf_metrics) {
5586 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5587 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS;
5590 if (pmu->intel_cap.pebs_output_pt_available)
5591 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
5593 intel_pmu_check_event_constraints(pmu->event_constraints,
5595 pmu->num_counters_fixed,
5598 intel_pmu_check_extra_regs(pmu->extra_regs);
5602 __init int intel_pmu_init(void)
5604 struct attribute **extra_skl_attr = &empty_attrs;
5605 struct attribute **extra_attr = &empty_attrs;
5606 struct attribute **td_attr = &empty_attrs;
5607 struct attribute **mem_attr = &empty_attrs;
5608 struct attribute **tsx_attr = &empty_attrs;
5609 union cpuid10_edx edx;
5610 union cpuid10_eax eax;
5611 union cpuid10_ebx ebx;
5612 unsigned int fixed_mask;
5616 struct x86_hybrid_pmu *pmu;
5618 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
5619 switch (boot_cpu_data.x86) {
5621 return p6_pmu_init();
5623 return knc_pmu_init();
5625 return p4_pmu_init();
5631 * Check whether the Architectural PerfMon supports
5632 * Branch Misses Retired hw_event or not.
5634 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
5635 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
5638 version = eax.split.version_id;
5642 x86_pmu = intel_pmu;
5644 x86_pmu.version = version;
5645 x86_pmu.num_counters = eax.split.num_counters;
5646 x86_pmu.cntval_bits = eax.split.bit_width;
5647 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
5649 x86_pmu.events_maskl = ebx.full;
5650 x86_pmu.events_mask_len = eax.split.mask_length;
5652 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
5655 * Quirk: v2 perfmon does not report fixed-purpose events, so
5656 * assume at least 3 events, when not running in a hypervisor:
5658 if (version > 1 && version < 5) {
5659 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
5661 x86_pmu.num_counters_fixed =
5662 max((int)edx.split.num_counters_fixed, assume);
5664 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
5665 } else if (version >= 5)
5666 x86_pmu.num_counters_fixed = fls(fixed_mask);
5668 if (boot_cpu_has(X86_FEATURE_PDCM)) {
5671 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
5672 x86_pmu.intel_cap.capabilities = capabilities;
5675 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
5676 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
5677 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
5680 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
5681 intel_pmu_arch_lbr_init();
5685 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
5688 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
5689 if (x86_pmu.intel_cap.anythread_deprecated)
5690 pr_cont(" AnyThread deprecated, ");
5694 * Install the hw-cache-events table:
5696 switch (boot_cpu_data.x86_model) {
5697 case INTEL_FAM6_CORE_YONAH:
5698 pr_cont("Core events, ");
5702 case INTEL_FAM6_CORE2_MEROM:
5703 x86_add_quirk(intel_clovertown_quirk);
5706 case INTEL_FAM6_CORE2_MEROM_L:
5707 case INTEL_FAM6_CORE2_PENRYN:
5708 case INTEL_FAM6_CORE2_DUNNINGTON:
5709 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5710 sizeof(hw_cache_event_ids));
5712 intel_pmu_lbr_init_core();
5714 x86_pmu.event_constraints = intel_core2_event_constraints;
5715 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5716 pr_cont("Core2 events, ");
5720 case INTEL_FAM6_NEHALEM:
5721 case INTEL_FAM6_NEHALEM_EP:
5722 case INTEL_FAM6_NEHALEM_EX:
5723 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5724 sizeof(hw_cache_event_ids));
5725 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5726 sizeof(hw_cache_extra_regs));
5728 intel_pmu_lbr_init_nhm();
5730 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5731 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5732 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5733 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5734 x86_pmu.limit_period = nhm_limit_period;
5736 mem_attr = nhm_mem_events_attrs;
5738 /* UOPS_ISSUED.STALLED_CYCLES */
5739 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5740 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5741 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5742 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5743 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5745 intel_pmu_pebs_data_source_nhm();
5746 x86_add_quirk(intel_nehalem_quirk);
5747 x86_pmu.pebs_no_tlb = 1;
5748 extra_attr = nhm_format_attr;
5750 pr_cont("Nehalem events, ");
5754 case INTEL_FAM6_ATOM_BONNELL:
5755 case INTEL_FAM6_ATOM_BONNELL_MID:
5756 case INTEL_FAM6_ATOM_SALTWELL:
5757 case INTEL_FAM6_ATOM_SALTWELL_MID:
5758 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5759 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5760 sizeof(hw_cache_event_ids));
5762 intel_pmu_lbr_init_atom();
5764 x86_pmu.event_constraints = intel_gen_event_constraints;
5765 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5766 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5767 pr_cont("Atom events, ");
5771 case INTEL_FAM6_ATOM_SILVERMONT:
5772 case INTEL_FAM6_ATOM_SILVERMONT_D:
5773 case INTEL_FAM6_ATOM_SILVERMONT_MID:
5774 case INTEL_FAM6_ATOM_AIRMONT:
5775 case INTEL_FAM6_ATOM_AIRMONT_MID:
5776 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5777 sizeof(hw_cache_event_ids));
5778 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5779 sizeof(hw_cache_extra_regs));
5781 intel_pmu_lbr_init_slm();
5783 x86_pmu.event_constraints = intel_slm_event_constraints;
5784 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5785 x86_pmu.extra_regs = intel_slm_extra_regs;
5786 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5787 td_attr = slm_events_attrs;
5788 extra_attr = slm_format_attr;
5789 pr_cont("Silvermont events, ");
5790 name = "silvermont";
5793 case INTEL_FAM6_ATOM_GOLDMONT:
5794 case INTEL_FAM6_ATOM_GOLDMONT_D:
5795 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5796 sizeof(hw_cache_event_ids));
5797 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5798 sizeof(hw_cache_extra_regs));
5800 intel_pmu_lbr_init_skl();
5802 x86_pmu.event_constraints = intel_slm_event_constraints;
5803 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5804 x86_pmu.extra_regs = intel_glm_extra_regs;
5806 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5807 * for precise cycles.
5808 * :pp is identical to :ppp
5810 x86_pmu.pebs_aliases = NULL;
5811 x86_pmu.pebs_prec_dist = true;
5812 x86_pmu.lbr_pt_coexist = true;
5813 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5814 td_attr = glm_events_attrs;
5815 extra_attr = slm_format_attr;
5816 pr_cont("Goldmont events, ");
5820 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5821 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5822 sizeof(hw_cache_event_ids));
5823 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5824 sizeof(hw_cache_extra_regs));
5826 intel_pmu_lbr_init_skl();
5828 x86_pmu.event_constraints = intel_slm_event_constraints;
5829 x86_pmu.extra_regs = intel_glm_extra_regs;
5831 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5832 * for precise cycles.
5834 x86_pmu.pebs_aliases = NULL;
5835 x86_pmu.pebs_prec_dist = true;
5836 x86_pmu.lbr_pt_coexist = true;
5837 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5838 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5839 x86_pmu.get_event_constraints = glp_get_event_constraints;
5840 td_attr = glm_events_attrs;
5841 /* Goldmont Plus has 4-wide pipeline */
5842 event_attr_td_total_slots_scale_glm.event_str = "4";
5843 extra_attr = slm_format_attr;
5844 pr_cont("Goldmont plus events, ");
5845 name = "goldmont_plus";
5848 case INTEL_FAM6_ATOM_TREMONT_D:
5849 case INTEL_FAM6_ATOM_TREMONT:
5850 case INTEL_FAM6_ATOM_TREMONT_L:
5851 x86_pmu.late_ack = true;
5852 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5853 sizeof(hw_cache_event_ids));
5854 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5855 sizeof(hw_cache_extra_regs));
5856 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5858 intel_pmu_lbr_init_skl();
5860 x86_pmu.event_constraints = intel_slm_event_constraints;
5861 x86_pmu.extra_regs = intel_tnt_extra_regs;
5863 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5864 * for precise cycles.
5866 x86_pmu.pebs_aliases = NULL;
5867 x86_pmu.pebs_prec_dist = true;
5868 x86_pmu.lbr_pt_coexist = true;
5869 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5870 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5871 td_attr = tnt_events_attrs;
5872 extra_attr = slm_format_attr;
5873 pr_cont("Tremont events, ");
5877 case INTEL_FAM6_WESTMERE:
5878 case INTEL_FAM6_WESTMERE_EP:
5879 case INTEL_FAM6_WESTMERE_EX:
5880 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
5881 sizeof(hw_cache_event_ids));
5882 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5883 sizeof(hw_cache_extra_regs));
5885 intel_pmu_lbr_init_nhm();
5887 x86_pmu.event_constraints = intel_westmere_event_constraints;
5888 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5889 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
5890 x86_pmu.extra_regs = intel_westmere_extra_regs;
5891 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5893 mem_attr = nhm_mem_events_attrs;
5895 /* UOPS_ISSUED.STALLED_CYCLES */
5896 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5897 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5898 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5899 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5900 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5902 intel_pmu_pebs_data_source_nhm();
5903 extra_attr = nhm_format_attr;
5904 pr_cont("Westmere events, ");
5908 case INTEL_FAM6_SANDYBRIDGE:
5909 case INTEL_FAM6_SANDYBRIDGE_X:
5910 x86_add_quirk(intel_sandybridge_quirk);
5911 x86_add_quirk(intel_ht_bug);
5912 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5913 sizeof(hw_cache_event_ids));
5914 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5915 sizeof(hw_cache_extra_regs));
5917 intel_pmu_lbr_init_snb();
5919 x86_pmu.event_constraints = intel_snb_event_constraints;
5920 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
5921 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
5922 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
5923 x86_pmu.extra_regs = intel_snbep_extra_regs;
5925 x86_pmu.extra_regs = intel_snb_extra_regs;
5928 /* all extra regs are per-cpu when HT is on */
5929 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5930 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5932 td_attr = snb_events_attrs;
5933 mem_attr = snb_mem_events_attrs;
5935 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5936 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5937 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5938 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
5939 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5940 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
5942 extra_attr = nhm_format_attr;
5944 pr_cont("SandyBridge events, ");
5945 name = "sandybridge";
5948 case INTEL_FAM6_IVYBRIDGE:
5949 case INTEL_FAM6_IVYBRIDGE_X:
5950 x86_add_quirk(intel_ht_bug);
5951 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5952 sizeof(hw_cache_event_ids));
5953 /* dTLB-load-misses on IVB is different than SNB */
5954 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
5956 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5957 sizeof(hw_cache_extra_regs));
5959 intel_pmu_lbr_init_snb();
5961 x86_pmu.event_constraints = intel_ivb_event_constraints;
5962 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
5963 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5964 x86_pmu.pebs_prec_dist = true;
5965 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
5966 x86_pmu.extra_regs = intel_snbep_extra_regs;
5968 x86_pmu.extra_regs = intel_snb_extra_regs;
5969 /* all extra regs are per-cpu when HT is on */
5970 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5971 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5973 td_attr = snb_events_attrs;
5974 mem_attr = snb_mem_events_attrs;
5976 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5977 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5978 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5980 extra_attr = nhm_format_attr;
5982 pr_cont("IvyBridge events, ");
5987 case INTEL_FAM6_HASWELL:
5988 case INTEL_FAM6_HASWELL_X:
5989 case INTEL_FAM6_HASWELL_L:
5990 case INTEL_FAM6_HASWELL_G:
5991 x86_add_quirk(intel_ht_bug);
5992 x86_add_quirk(intel_pebs_isolation_quirk);
5993 x86_pmu.late_ack = true;
5994 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5995 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5997 intel_pmu_lbr_init_hsw();
5999 x86_pmu.event_constraints = intel_hsw_event_constraints;
6000 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
6001 x86_pmu.extra_regs = intel_snbep_extra_regs;
6002 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6003 x86_pmu.pebs_prec_dist = true;
6004 /* all extra regs are per-cpu when HT is on */
6005 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6006 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6008 x86_pmu.hw_config = hsw_hw_config;
6009 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6010 x86_pmu.lbr_double_abort = true;
6011 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6012 hsw_format_attr : nhm_format_attr;
6013 td_attr = hsw_events_attrs;
6014 mem_attr = hsw_mem_events_attrs;
6015 tsx_attr = hsw_tsx_events_attrs;
6016 pr_cont("Haswell events, ");
6020 case INTEL_FAM6_BROADWELL:
6021 case INTEL_FAM6_BROADWELL_D:
6022 case INTEL_FAM6_BROADWELL_G:
6023 case INTEL_FAM6_BROADWELL_X:
6024 x86_add_quirk(intel_pebs_isolation_quirk);
6025 x86_pmu.late_ack = true;
6026 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6027 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6029 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
6030 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
6031 BDW_L3_MISS|HSW_SNOOP_DRAM;
6032 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
6034 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
6035 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6036 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
6037 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6039 intel_pmu_lbr_init_hsw();
6041 x86_pmu.event_constraints = intel_bdw_event_constraints;
6042 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
6043 x86_pmu.extra_regs = intel_snbep_extra_regs;
6044 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6045 x86_pmu.pebs_prec_dist = true;
6046 /* all extra regs are per-cpu when HT is on */
6047 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6048 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6050 x86_pmu.hw_config = hsw_hw_config;
6051 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6052 x86_pmu.limit_period = bdw_limit_period;
6053 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6054 hsw_format_attr : nhm_format_attr;
6055 td_attr = hsw_events_attrs;
6056 mem_attr = hsw_mem_events_attrs;
6057 tsx_attr = hsw_tsx_events_attrs;
6058 pr_cont("Broadwell events, ");
6062 case INTEL_FAM6_XEON_PHI_KNL:
6063 case INTEL_FAM6_XEON_PHI_KNM:
6064 memcpy(hw_cache_event_ids,
6065 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6066 memcpy(hw_cache_extra_regs,
6067 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6068 intel_pmu_lbr_init_knl();
6070 x86_pmu.event_constraints = intel_slm_event_constraints;
6071 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6072 x86_pmu.extra_regs = intel_knl_extra_regs;
6074 /* all extra regs are per-cpu when HT is on */
6075 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6076 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6077 extra_attr = slm_format_attr;
6078 pr_cont("Knights Landing/Mill events, ");
6079 name = "knights-landing";
6082 case INTEL_FAM6_SKYLAKE_X:
6085 case INTEL_FAM6_SKYLAKE_L:
6086 case INTEL_FAM6_SKYLAKE:
6087 case INTEL_FAM6_KABYLAKE_L:
6088 case INTEL_FAM6_KABYLAKE:
6089 case INTEL_FAM6_COMETLAKE_L:
6090 case INTEL_FAM6_COMETLAKE:
6091 x86_add_quirk(intel_pebs_isolation_quirk);
6092 x86_pmu.late_ack = true;
6093 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6094 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6095 intel_pmu_lbr_init_skl();
6097 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
6098 event_attr_td_recovery_bubbles.event_str_noht =
6099 "event=0xd,umask=0x1,cmask=1";
6100 event_attr_td_recovery_bubbles.event_str_ht =
6101 "event=0xd,umask=0x1,cmask=1,any=1";
6103 x86_pmu.event_constraints = intel_skl_event_constraints;
6104 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
6105 x86_pmu.extra_regs = intel_skl_extra_regs;
6106 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
6107 x86_pmu.pebs_prec_dist = true;
6108 /* all extra regs are per-cpu when HT is on */
6109 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6110 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6112 x86_pmu.hw_config = hsw_hw_config;
6113 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6114 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6115 hsw_format_attr : nhm_format_attr;
6116 extra_skl_attr = skl_format_attr;
6117 td_attr = hsw_events_attrs;
6118 mem_attr = hsw_mem_events_attrs;
6119 tsx_attr = hsw_tsx_events_attrs;
6120 intel_pmu_pebs_data_source_skl(pmem);
6123 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
6124 * TSX force abort hooks are not required on these systems. Only deploy
6125 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
6127 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
6128 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
6129 x86_pmu.flags |= PMU_FL_TFA;
6130 x86_pmu.get_event_constraints = tfa_get_event_constraints;
6131 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
6132 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
6135 pr_cont("Skylake events, ");
6139 case INTEL_FAM6_ICELAKE_X:
6140 case INTEL_FAM6_ICELAKE_D:
6143 case INTEL_FAM6_ICELAKE_L:
6144 case INTEL_FAM6_ICELAKE:
6145 case INTEL_FAM6_TIGERLAKE_L:
6146 case INTEL_FAM6_TIGERLAKE:
6147 case INTEL_FAM6_ROCKETLAKE:
6148 x86_pmu.late_ack = true;
6149 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6150 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6151 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6152 intel_pmu_lbr_init_skl();
6154 x86_pmu.event_constraints = intel_icl_event_constraints;
6155 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
6156 x86_pmu.extra_regs = intel_icl_extra_regs;
6157 x86_pmu.pebs_aliases = NULL;
6158 x86_pmu.pebs_prec_dist = true;
6159 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6160 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6162 x86_pmu.hw_config = hsw_hw_config;
6163 x86_pmu.get_event_constraints = icl_get_event_constraints;
6164 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6165 hsw_format_attr : nhm_format_attr;
6166 extra_skl_attr = skl_format_attr;
6167 mem_attr = icl_events_attrs;
6168 td_attr = icl_td_events_attrs;
6169 tsx_attr = icl_tsx_events_attrs;
6170 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6171 x86_pmu.lbr_pt_coexist = true;
6172 intel_pmu_pebs_data_source_skl(pmem);
6173 x86_pmu.num_topdown_events = 4;
6174 x86_pmu.update_topdown_event = icl_update_topdown_event;
6175 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
6176 pr_cont("Icelake events, ");
6180 case INTEL_FAM6_SAPPHIRERAPIDS_X:
6182 x86_pmu.late_ack = true;
6183 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6184 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6186 x86_pmu.event_constraints = intel_spr_event_constraints;
6187 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
6188 x86_pmu.extra_regs = intel_spr_extra_regs;
6189 x86_pmu.limit_period = spr_limit_period;
6190 x86_pmu.pebs_aliases = NULL;
6191 x86_pmu.pebs_prec_dist = true;
6192 x86_pmu.pebs_block = true;
6193 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6194 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6195 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6196 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6197 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6199 x86_pmu.hw_config = hsw_hw_config;
6200 x86_pmu.get_event_constraints = spr_get_event_constraints;
6201 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6202 hsw_format_attr : nhm_format_attr;
6203 extra_skl_attr = skl_format_attr;
6204 mem_attr = spr_events_attrs;
6205 td_attr = spr_td_events_attrs;
6206 tsx_attr = spr_tsx_events_attrs;
6207 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6208 x86_pmu.lbr_pt_coexist = true;
6209 intel_pmu_pebs_data_source_skl(pmem);
6210 x86_pmu.num_topdown_events = 8;
6211 x86_pmu.update_topdown_event = icl_update_topdown_event;
6212 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
6213 pr_cont("Sapphire Rapids events, ");
6214 name = "sapphire_rapids";
6217 case INTEL_FAM6_ALDERLAKE:
6218 case INTEL_FAM6_ALDERLAKE_L:
6219 case INTEL_FAM6_ALDERLAKE_N:
6220 case INTEL_FAM6_RAPTORLAKE:
6221 case INTEL_FAM6_RAPTORLAKE_P:
6223 * Alder Lake has 2 types of CPU, core and atom.
6225 * Initialize the common PerfMon capabilities here.
6227 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS,
6228 sizeof(struct x86_hybrid_pmu),
6230 if (!x86_pmu.hybrid_pmu)
6232 static_branch_enable(&perf_is_hybrid);
6233 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS;
6235 x86_pmu.pebs_aliases = NULL;
6236 x86_pmu.pebs_prec_dist = true;
6237 x86_pmu.pebs_block = true;
6238 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6239 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6240 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6241 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6242 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6243 x86_pmu.lbr_pt_coexist = true;
6244 intel_pmu_pebs_data_source_adl();
6245 x86_pmu.pebs_latency_data = adl_latency_data_small;
6246 x86_pmu.num_topdown_events = 8;
6247 x86_pmu.update_topdown_event = adl_update_topdown_event;
6248 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period;
6250 x86_pmu.filter_match = intel_pmu_filter_match;
6251 x86_pmu.get_event_constraints = adl_get_event_constraints;
6252 x86_pmu.hw_config = adl_hw_config;
6253 x86_pmu.limit_period = spr_limit_period;
6254 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
6256 * The rtm_abort_event is used to check whether to enable GPRs
6257 * for the RTM abort event. Atom doesn't have the RTM abort
6258 * event. There is no harmful to set it in the common
6259 * x86_pmu.rtm_abort_event.
6261 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6263 td_attr = adl_hybrid_events_attrs;
6264 mem_attr = adl_hybrid_mem_attrs;
6265 tsx_attr = adl_hybrid_tsx_attrs;
6266 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6267 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
6269 /* Initialize big core specific PerfMon capabilities.*/
6270 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
6271 pmu->name = "cpu_core";
6272 pmu->cpu_type = hybrid_big;
6273 pmu->late_ack = true;
6274 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
6275 pmu->num_counters = x86_pmu.num_counters + 2;
6276 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1;
6278 pmu->num_counters = x86_pmu.num_counters;
6279 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6283 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
6284 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
6285 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
6286 * mistakenly add extra counters for P-cores. Correct the number of
6289 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) {
6290 pmu->num_counters = x86_pmu.num_counters;
6291 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6294 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
6295 pmu->unconstrained = (struct event_constraint)
6296 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6297 0, pmu->num_counters, 0, 0);
6298 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6299 pmu->intel_cap.perf_metrics = 1;
6300 pmu->intel_cap.pebs_output_pt_available = 0;
6302 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6303 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6304 pmu->event_constraints = intel_spr_event_constraints;
6305 pmu->pebs_constraints = intel_spr_pebs_event_constraints;
6306 pmu->extra_regs = intel_spr_extra_regs;
6308 /* Initialize Atom core specific PerfMon capabilities.*/
6309 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
6310 pmu->name = "cpu_atom";
6311 pmu->cpu_type = hybrid_small;
6312 pmu->mid_ack = true;
6313 pmu->num_counters = x86_pmu.num_counters;
6314 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6315 pmu->max_pebs_events = x86_pmu.max_pebs_events;
6316 pmu->unconstrained = (struct event_constraint)
6317 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6318 0, pmu->num_counters, 0, 0);
6319 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6320 pmu->intel_cap.perf_metrics = 0;
6321 pmu->intel_cap.pebs_output_pt_available = 1;
6323 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6324 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6325 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6326 pmu->event_constraints = intel_slm_event_constraints;
6327 pmu->pebs_constraints = intel_grt_pebs_event_constraints;
6328 pmu->extra_regs = intel_grt_extra_regs;
6329 pr_cont("Alderlake Hybrid events, ");
6330 name = "alderlake_hybrid";
6334 switch (x86_pmu.version) {
6336 x86_pmu.event_constraints = intel_v1_event_constraints;
6337 pr_cont("generic architected perfmon v1, ");
6338 name = "generic_arch_v1";
6344 * default constraints for v2 and up
6346 x86_pmu.event_constraints = intel_gen_event_constraints;
6347 pr_cont("generic architected perfmon, ");
6348 name = "generic_arch_v2+";
6352 * The default constraints for v5 and up can support up to
6353 * 16 fixed counters. For the fixed counters 4 and later,
6354 * the pseudo-encoding is applied.
6355 * The constraints may be cut according to the CPUID enumeration
6356 * by inserting the EVENT_CONSTRAINT_END.
6358 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED)
6359 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
6360 intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1;
6361 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
6362 pr_cont("generic architected perfmon, ");
6363 name = "generic_arch_v5+";
6368 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
6371 group_events_td.attrs = td_attr;
6372 group_events_mem.attrs = mem_attr;
6373 group_events_tsx.attrs = tsx_attr;
6374 group_format_extra.attrs = extra_attr;
6375 group_format_extra_skl.attrs = extra_skl_attr;
6377 x86_pmu.attr_update = attr_update;
6379 hybrid_group_events_td.attrs = td_attr;
6380 hybrid_group_events_mem.attrs = mem_attr;
6381 hybrid_group_events_tsx.attrs = tsx_attr;
6382 hybrid_group_format_extra.attrs = extra_attr;
6384 x86_pmu.attr_update = hybrid_attr_update;
6387 intel_pmu_check_num_counters(&x86_pmu.num_counters,
6388 &x86_pmu.num_counters_fixed,
6389 &x86_pmu.intel_ctrl,
6392 /* AnyThread may be deprecated on arch perfmon v5 or later */
6393 if (x86_pmu.intel_cap.anythread_deprecated)
6394 x86_pmu.format_attrs = intel_arch_formats_attr;
6396 intel_pmu_check_event_constraints(x86_pmu.event_constraints,
6397 x86_pmu.num_counters,
6398 x86_pmu.num_counters_fixed,
6399 x86_pmu.intel_ctrl);
6401 * Access LBR MSR may cause #GP under certain circumstances.
6402 * E.g. KVM doesn't support LBR MSR
6403 * Check all LBT MSR here.
6404 * Disable LBR access if any LBR MSRs can not be accessed.
6406 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
6408 for (i = 0; i < x86_pmu.lbr_nr; i++) {
6409 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
6410 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
6414 if (x86_pmu.lbr_nr) {
6415 intel_pmu_lbr_init();
6417 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
6419 /* only support branch_stack snapshot for perfmon >= v2 */
6420 if (x86_pmu.disable_all == intel_pmu_disable_all) {
6421 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
6422 static_call_update(perf_snapshot_branch_stack,
6423 intel_pmu_snapshot_arch_branch_stack);
6425 static_call_update(perf_snapshot_branch_stack,
6426 intel_pmu_snapshot_branch_stack);
6431 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
6433 /* Support full width counters using alternative MSR range */
6434 if (x86_pmu.intel_cap.full_width_write) {
6435 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
6436 x86_pmu.perfctr = MSR_IA32_PMC0;
6437 pr_cont("full-width counters, ");
6440 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
6441 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
6444 intel_pmu_check_hybrid_pmus((u64)fixed_mask);
6446 intel_aux_output_init();
6452 * HT bug: phase 2 init
6453 * Called once we have valid topology information to check
6454 * whether or not HT is enabled
6455 * If HT is off, then we disable the workaround
6457 static __init int fixup_ht_bug(void)
6461 * problem not present on this CPU model, nothing to do
6463 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
6466 if (topology_max_smt_threads() > 1) {
6467 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
6473 hardlockup_detector_perf_stop();
6475 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
6477 x86_pmu.start_scheduling = NULL;
6478 x86_pmu.commit_scheduling = NULL;
6479 x86_pmu.stop_scheduling = NULL;
6481 hardlockup_detector_perf_restart();
6483 for_each_online_cpu(c)
6484 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
6487 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
6490 subsys_initcall(fixup_ht_bug)