1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/x86/entry_64.rst
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - SYM_FUNC_START/END:Define functions in the symbol table.
19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
20 * - idtentry: Define exception entry points.
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/frame.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
46 .section .entry.text, "ax"
48 #ifdef CONFIG_PARAVIRT
49 SYM_CODE_START(native_usergs_sysret64)
53 SYM_CODE_END(native_usergs_sysret64)
54 #endif /* CONFIG_PARAVIRT */
56 .macro TRACE_IRQS_FLAGS flags:req
57 #ifdef CONFIG_TRACE_IRQFLAGS
58 btl $9, \flags /* interrupts off? */
65 .macro TRACE_IRQS_IRETQ
66 TRACE_IRQS_FLAGS EFLAGS(%rsp)
70 * When dynamic function tracer is enabled it will add a breakpoint
71 * to all locations that it is about to modify, sync CPUs, update
72 * all the code, sync CPUs, then remove the breakpoints. In this time
73 * if lockdep is enabled, it might jump back into the debug handler
74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
77 * make sure the stack pointer does not get reset back to the top
78 * of the debug stack, and instead just reuses the current stack.
80 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
82 .macro TRACE_IRQS_OFF_DEBUG
83 call debug_stack_set_zero
85 call debug_stack_reset
88 .macro TRACE_IRQS_ON_DEBUG
89 call debug_stack_set_zero
91 call debug_stack_reset
94 .macro TRACE_IRQS_IRETQ_DEBUG
95 btl $9, EFLAGS(%rsp) /* interrupts off? */
102 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
103 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
104 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
110 * This is the only entry point used for 64-bit system calls. The
111 * hardware interface is reasonably well designed and the register to
112 * argument mapping Linux uses fits well with the registers that are
113 * available when SYSCALL is used.
115 * SYSCALL instructions can be found inlined in libc implementations as
116 * well as some other programs and libraries. There are also a handful
117 * of SYSCALL instructions in the vDSO used, for example, as a
118 * clock_gettimeofday fallback.
120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
121 * then loads new ss, cs, and rip from previously programmed MSRs.
122 * rflags gets masked by a value from another MSR (so CLD and CLAC
123 * are not needed). SYSCALL does not save anything on the stack
124 * and does not change rsp.
126 * Registers on entry:
127 * rax system call number
129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
133 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
138 * Only called from user space.
140 * When user can change pt_regs->foo always force IRET. That is because
141 * it deals with uncanonical addresses better. SYSRET has trouble
142 * with them due to bugs in both AMD and Intel CPUs.
145 SYM_CODE_START(entry_SYSCALL_64)
148 * Interrupts are off on entry.
149 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
150 * it is too small to ever cause noticeable irq latency.
154 /* tss.sp2 is scratch space. */
155 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2)
156 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
157 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
159 /* Construct struct pt_regs on stack */
160 pushq $__USER_DS /* pt_regs->ss */
161 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */
162 pushq %r11 /* pt_regs->flags */
163 pushq $__USER_CS /* pt_regs->cs */
164 pushq %rcx /* pt_regs->ip */
165 SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL)
166 pushq %rax /* pt_regs->orig_ax */
168 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
175 call do_syscall_64 /* returns with IRQs disabled */
177 TRACE_IRQS_ON /* return enables interrupts */
180 * Try to use SYSRET instead of IRET if we're returning to
181 * a completely clean 64-bit userspace context. If we're not,
182 * go to the slow exit path.
187 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
188 jne swapgs_restore_regs_and_return_to_usermode
191 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
192 * in kernel space. This essentially lets the user take over
193 * the kernel, since userspace controls RSP.
195 * If width of "canonical tail" ever becomes variable, this will need
196 * to be updated to remain correct on both old and new CPUs.
198 * Change top bits to match most significant bit (47th or 56th bit
199 * depending on paging mode) in the address.
201 #ifdef CONFIG_X86_5LEVEL
202 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
203 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
205 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
206 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
209 /* If this changed %rcx, it was not canonical */
211 jne swapgs_restore_regs_and_return_to_usermode
213 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
214 jne swapgs_restore_regs_and_return_to_usermode
217 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
218 jne swapgs_restore_regs_and_return_to_usermode
221 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
222 * restore RF properly. If the slowpath sets it for whatever reason, we
223 * need to restore it correctly.
225 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
226 * trap from userspace immediately after SYSRET. This would cause an
227 * infinite loop whenever #DB happens with register state that satisfies
228 * the opportunistic SYSRET conditions. For example, single-stepping
231 * movq $stuck_here, %rcx
236 * would never get past 'stuck_here'.
238 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
239 jnz swapgs_restore_regs_and_return_to_usermode
241 /* nothing to check for RSP */
243 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
244 jne swapgs_restore_regs_and_return_to_usermode
247 * We win! This label is here just for ease of understanding
248 * perf profiles. Nothing jumps here.
250 syscall_return_via_sysret:
251 /* rcx and r11 are already restored (see code above) */
252 POP_REGS pop_rdi=0 skip_r11rcx=1
255 * Now all regs are restored except RSP and RDI.
256 * Save old stack pointer and switch to trampoline stack.
259 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
262 pushq RSP-RDI(%rdi) /* RSP */
263 pushq (%rdi) /* RDI */
266 * We are on the trampoline stack. All regs except RDI are live.
267 * We can do future final exit work right here.
269 STACKLEAK_ERASE_NOCLOBBER
271 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
276 SYM_CODE_END(entry_SYSCALL_64)
282 .pushsection .text, "ax"
283 SYM_FUNC_START(__switch_to_asm)
285 * Save callee-saved registers
286 * This must match the order in inactive_task_frame
296 movq %rsp, TASK_threadsp(%rdi)
297 movq TASK_threadsp(%rsi), %rsp
299 #ifdef CONFIG_STACKPROTECTOR
300 movq TASK_stack_canary(%rsi), %rbx
301 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset
304 #ifdef CONFIG_RETPOLINE
306 * When switching from a shallower to a deeper call stack
307 * the RSB may either underflow or use entries populated
308 * with userspace addresses. On CPUs where those concerns
309 * exist, overwrite the RSB with entries which capture
310 * speculative execution to prevent attack.
312 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
315 /* restore callee-saved registers */
324 SYM_FUNC_END(__switch_to_asm)
328 * A newly forked process directly context switches into this address.
330 * rax: prev task we switched from
331 * rbx: kernel thread func (NULL for user thread)
332 * r12: kernel thread arg
334 .pushsection .text, "ax"
335 SYM_CODE_START(ret_from_fork)
338 call schedule_tail /* rdi: 'prev' task parameter */
340 testq %rbx, %rbx /* from kernel_thread? */
341 jnz 1f /* kernel threads are uncommon */
346 call syscall_return_slowpath /* returns with IRQs disabled */
347 TRACE_IRQS_ON /* user mode is traced as IRQS on */
348 jmp swapgs_restore_regs_and_return_to_usermode
356 * A kernel thread is allowed to return here after successfully
357 * calling do_execve(). Exit to userspace to complete the execve()
362 SYM_CODE_END(ret_from_fork)
366 * Build the entry stubs with some assembler magic.
367 * We pack 1 stub into every 8-byte block.
370 SYM_CODE_START(irq_entries_start)
371 vector=FIRST_EXTERNAL_VECTOR
372 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
373 UNWIND_HINT_IRET_REGS
374 pushq $(~vector+0x80) /* Note: always in signed byte range */
379 SYM_CODE_END(irq_entries_start)
382 SYM_CODE_START(spurious_entries_start)
383 vector=FIRST_SYSTEM_VECTOR
384 .rept (NR_VECTORS - FIRST_SYSTEM_VECTOR)
385 UNWIND_HINT_IRET_REGS
386 pushq $(~vector+0x80) /* Note: always in signed byte range */
391 SYM_CODE_END(spurious_entries_start)
393 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
394 #ifdef CONFIG_DEBUG_ENTRY
397 testl $X86_EFLAGS_IF, %eax
406 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
407 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
408 * Requires kernel GSBASE.
410 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
412 .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0
413 DEBUG_ENTRY_ASSERT_IRQS_OFF
417 * If save_ret is set, the original stack contains one additional
418 * entry -- the return address. Therefore, move the address one
419 * entry below %rsp to \old_rsp.
421 leaq 8(%rsp), \old_rsp
427 UNWIND_HINT_REGS base=\old_rsp
430 incl PER_CPU_VAR(irq_count)
431 jnz .Lirq_stack_push_old_rsp_\@
434 * Right now, if we just incremented irq_count to zero, we've
435 * claimed the IRQ stack but we haven't switched to it yet.
437 * If anything is added that can interrupt us here without using IST,
438 * it must be *extremely* careful to limit its stack usage. This
439 * could include kprobes and a hypothetical future IST-less #DB
442 * The OOPS unwinder relies on the word at the top of the IRQ
443 * stack linking back to the previous RSP for the entire time we're
444 * on the IRQ stack. For this to work reliably, we need to write
445 * it before we actually move ourselves to the IRQ stack.
448 movq \old_rsp, PER_CPU_VAR(irq_stack_backing_store + IRQ_STACK_SIZE - 8)
449 movq PER_CPU_VAR(hardirq_stack_ptr), %rsp
451 #ifdef CONFIG_DEBUG_ENTRY
453 * If the first movq above becomes wrong due to IRQ stack layout
454 * changes, the only way we'll notice is if we try to unwind right
455 * here. Assert that we set up the stack right to catch this type
458 cmpq -8(%rsp), \old_rsp
459 je .Lirq_stack_okay\@
464 .Lirq_stack_push_old_rsp_\@:
468 UNWIND_HINT_REGS indirect=1
473 * Push the return address to the stack. This return address can
474 * be found at the "real" original RSP, which was offset by 8 at
475 * the beginning of this macro.
482 * Undoes ENTER_IRQ_STACK.
484 .macro LEAVE_IRQ_STACK regs=1
485 DEBUG_ENTRY_ASSERT_IRQS_OFF
486 /* We need to be off the IRQ stack before decrementing irq_count. */
494 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
495 * the irq stack but we're not on it.
498 decl PER_CPU_VAR(irq_count)
502 * Interrupt entry helper function.
504 * Entry runs with interrupts off. Stack layout at entry:
505 * +----------------------------------------------------+
511 * +----------------------------------------------------+
512 * | regs->orig_ax = ~(interrupt number) |
513 * +----------------------------------------------------+
515 * +----------------------------------------------------+
517 SYM_CODE_START(interrupt_entry)
518 UNWIND_HINT_IRET_REGS offset=16
522 testb $3, CS-ORIG_RAX+8(%rsp)
525 FENCE_SWAPGS_USER_ENTRY
527 * Switch to the thread stack. The IRET frame and orig_ax are
528 * on the stack, as well as the return address. RDI..R12 are
529 * not (yet) on the stack and space has not (yet) been
530 * allocated for them.
534 /* Need to switch before accessing the thread stack. */
535 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
537 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
540 * We have RDI, return address, and orig_ax on the stack on
541 * top of the IRET frame. That means offset=24
543 UNWIND_HINT_IRET_REGS base=%rdi offset=24
545 pushq 7*8(%rdi) /* regs->ss */
546 pushq 6*8(%rdi) /* regs->rsp */
547 pushq 5*8(%rdi) /* regs->eflags */
548 pushq 4*8(%rdi) /* regs->cs */
549 pushq 3*8(%rdi) /* regs->ip */
550 UNWIND_HINT_IRET_REGS
551 pushq 2*8(%rdi) /* regs->orig_ax */
552 pushq 8(%rdi) /* return address */
557 FENCE_SWAPGS_KERNEL_ENTRY
559 PUSH_AND_CLEAR_REGS save_ret=1
560 ENCODE_FRAME_POINTER 8
566 * IRQ from user mode.
568 * We need to tell lockdep that IRQs are off. We can't do this until
569 * we fix gsbase, and we should do it before enter_from_user_mode
570 * (which can take locks). Since TRACE_IRQS_OFF is idempotent,
571 * the simplest way to handle it is to just call it twice if
572 * we enter from user mode. There's no reason to optimize this since
573 * TRACE_IRQS_OFF is a no-op if lockdep is off.
577 CALL_enter_from_user_mode
580 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1
581 /* We entered an interrupt context - irqs are off: */
585 SYM_CODE_END(interrupt_entry)
586 _ASM_NOKPROBE(interrupt_entry)
589 /* Interrupt entry/exit. */
592 * The interrupt stubs push (~vector+0x80) onto the stack and
593 * then jump to common_spurious/interrupt.
595 SYM_CODE_START_LOCAL(common_spurious)
596 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
598 UNWIND_HINT_REGS indirect=1
599 call smp_spurious_interrupt /* rdi points to pt_regs */
601 SYM_CODE_END(common_spurious)
602 _ASM_NOKPROBE(common_spurious)
604 /* common_interrupt is a hotpath. Align it */
605 .p2align CONFIG_X86_L1_CACHE_SHIFT
606 SYM_CODE_START_LOCAL(common_interrupt)
607 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
609 UNWIND_HINT_REGS indirect=1
610 call do_IRQ /* rdi points to pt_regs */
611 /* 0(%rsp): old RSP */
613 DISABLE_INTERRUPTS(CLBR_ANY)
621 /* Interrupt came from user space */
624 call prepare_exit_to_usermode
627 SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL)
628 #ifdef CONFIG_DEBUG_ENTRY
629 /* Assert that pt_regs indicates user mode. */
638 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
639 * Save old stack pointer and switch to trampoline stack.
642 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
645 /* Copy the IRET frame to the trampoline stack. */
646 pushq 6*8(%rdi) /* SS */
647 pushq 5*8(%rdi) /* RSP */
648 pushq 4*8(%rdi) /* EFLAGS */
649 pushq 3*8(%rdi) /* CS */
650 pushq 2*8(%rdi) /* RIP */
652 /* Push user RDI on the trampoline stack. */
656 * We are on the trampoline stack. All regs except RDI are live.
657 * We can do future final exit work right here.
659 STACKLEAK_ERASE_NOCLOBBER
661 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
669 /* Returning to kernel space */
671 #ifdef CONFIG_PREEMPTION
672 /* Interrupts are off */
673 /* Check if we need preemption */
674 btl $9, EFLAGS(%rsp) /* were interrupts off? */
676 cmpl $0, PER_CPU_VAR(__preempt_count)
678 call preempt_schedule_irq
682 * The iretq could re-enable interrupts:
686 SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL)
687 #ifdef CONFIG_DEBUG_ENTRY
688 /* Assert that pt_regs indicates kernel mode. */
695 addq $8, %rsp /* skip regs->orig_ax */
697 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
698 * when returning from IPI handler.
702 SYM_INNER_LABEL_ALIGN(native_iret, SYM_L_GLOBAL)
703 UNWIND_HINT_IRET_REGS
705 * Are we returning to a stack segment from the LDT? Note: in
706 * 64-bit mode SS:RSP on the exception stack is always valid.
708 #ifdef CONFIG_X86_ESPFIX64
709 testb $4, (SS-RIP)(%rsp)
710 jnz native_irq_return_ldt
713 SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL)
715 * This may fault. Non-paranoid faults on return to userspace are
716 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
717 * Double-faults due to espfix64 are handled in do_double_fault.
718 * Other faults here are fatal.
722 #ifdef CONFIG_X86_ESPFIX64
723 native_irq_return_ldt:
725 * We are running with user GSBASE. All GPRs contain their user
726 * values. We have a percpu ESPFIX stack that is eight slots
727 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
728 * of the ESPFIX stack.
730 * We clobber RAX and RDI in this code. We stash RDI on the
731 * normal stack and RAX on the ESPFIX stack.
733 * The ESPFIX stack layout we set up looks like this:
735 * --- top of ESPFIX stack ---
740 * RIP <-- RSP points here when we're done
741 * RAX <-- espfix_waddr points here
742 * --- bottom of ESPFIX stack ---
745 pushq %rdi /* Stash user RDI */
746 SWAPGS /* to kernel GS */
747 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
749 movq PER_CPU_VAR(espfix_waddr), %rdi
750 movq %rax, (0*8)(%rdi) /* user RAX */
751 movq (1*8)(%rsp), %rax /* user RIP */
752 movq %rax, (1*8)(%rdi)
753 movq (2*8)(%rsp), %rax /* user CS */
754 movq %rax, (2*8)(%rdi)
755 movq (3*8)(%rsp), %rax /* user RFLAGS */
756 movq %rax, (3*8)(%rdi)
757 movq (5*8)(%rsp), %rax /* user SS */
758 movq %rax, (5*8)(%rdi)
759 movq (4*8)(%rsp), %rax /* user RSP */
760 movq %rax, (4*8)(%rdi)
761 /* Now RAX == RSP. */
763 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
766 * espfix_stack[31:16] == 0. The page tables are set up such that
767 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
768 * espfix_waddr for any X. That is, there are 65536 RO aliases of
769 * the same page. Set up RSP so that RSP[31:16] contains the
770 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
771 * still points to an RO alias of the ESPFIX stack.
773 orq PER_CPU_VAR(espfix_stack), %rax
775 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
776 SWAPGS /* to user GS */
777 popq %rdi /* Restore user RDI */
780 UNWIND_HINT_IRET_REGS offset=8
783 * At this point, we cannot write to the stack any more, but we can
786 popq %rax /* Restore user RAX */
789 * RSP now points to an ordinary IRET frame, except that the page
790 * is read-only and RSP[31:16] are preloaded with the userspace
791 * values. We can now IRET back to userspace.
793 jmp native_irq_return_iret
795 SYM_CODE_END(common_interrupt)
796 _ASM_NOKPROBE(common_interrupt)
801 .macro apicinterrupt3 num sym do_sym
803 UNWIND_HINT_IRET_REGS
806 UNWIND_HINT_REGS indirect=1
807 call \do_sym /* rdi points to pt_regs */
813 /* Make sure APIC interrupt handlers end up in the irqentry section: */
814 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
815 #define POP_SECTION_IRQENTRY .popsection
817 .macro apicinterrupt num sym do_sym
818 PUSH_SECTION_IRQENTRY
819 apicinterrupt3 \num \sym \do_sym
824 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
825 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
829 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
832 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
833 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
835 #ifdef CONFIG_HAVE_KVM
836 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
837 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
838 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
841 #ifdef CONFIG_X86_MCE_THRESHOLD
842 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
845 #ifdef CONFIG_X86_MCE_AMD
846 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
849 #ifdef CONFIG_X86_THERMAL_VECTOR
850 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
854 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
855 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
856 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
859 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
860 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
862 #ifdef CONFIG_IRQ_WORK
863 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
867 * Exception entry points.
869 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + (x) * 8)
871 .macro idtentry_part do_sym, has_error_code:req, read_cr2:req, paranoid:req, shift_ist=-1, ist_offset=0
875 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
883 * Store CR2 early so subsequent faults cannot clobber it. Use R12 as
884 * intermediate storage as RDX can be clobbered in enter_from_user_mode().
885 * GET_CR2_INTO can clobber RAX.
891 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
896 #ifdef CONFIG_CONTEXT_TRACKING
899 jz .Lfrom_kernel_no_context_tracking_\@
900 CALL_enter_from_user_mode
901 .Lfrom_kernel_no_context_tracking_\@:
905 movq %rsp, %rdi /* pt_regs pointer */
908 movq ORIG_RAX(%rsp), %rsi /* get error code */
909 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
911 xorl %esi, %esi /* no error code */
915 subq $\ist_offset, CPU_TSS_IST(\shift_ist)
919 movq %r12, %rdx /* Move CR2 into 3rd argument */
925 addq $\ist_offset, CPU_TSS_IST(\shift_ist)
929 /* this procedure expect "no swapgs" flag in ebx */
938 * idtentry - Generate an IDT entry stub
939 * @sym: Name of the generated entry point
940 * @do_sym: C function to be called
941 * @has_error_code: True if this IDT vector has an error code on the stack
942 * @paranoid: non-zero means that this vector may be invoked from
943 * kernel mode with user GSBASE and/or user CR3.
944 * 2 is special -- see below.
945 * @shift_ist: Set to an IST index if entries from kernel mode should
946 * decrement the IST stack so that nested entries get a
947 * fresh stack. (This is for #DB, which has a nasty habit
949 * @create_gap: create a 6-word stack gap when coming from kernel mode.
950 * @read_cr2: load CR2 into the 3rd argument; done before calling any C code
952 * idtentry generates an IDT stub that sets up a usable kernel context,
953 * creates struct pt_regs, and calls @do_sym. The stub has the following
956 * On an entry from user mode, the stub switches from the trampoline or
957 * IST stack to the normal thread stack. On an exit to user mode, the
958 * normal exit-to-usermode path is invoked.
960 * On an exit to kernel mode, if @paranoid == 0, we check for preemption,
961 * whereas we omit the preemption check if @paranoid != 0. This is purely
962 * because the implementation is simpler this way. The kernel only needs
963 * to check for asynchronous kernel preemption when IRQ handlers return.
965 * If @paranoid == 0, then the stub will handle IRET faults by pretending
966 * that the fault came from user mode. It will handle gs_change faults by
967 * pretending that the fault happened with kernel GSBASE. Since this handling
968 * is omitted for @paranoid != 0, the #GP, #SS, and #NP stubs must have
969 * @paranoid == 0. This special handling will do the wrong thing for
970 * espfix-induced #DF on IRET, so #DF must not use @paranoid == 0.
972 * @paranoid == 2 is special: the stub will never switch stacks. This is for
973 * #DF: if the thread stack is somehow unusable, we'll still get a useful OOPS.
975 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 ist_offset=0 create_gap=0 read_cr2=0
977 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
980 .if \shift_ist != -1 && \paranoid != 1
981 .error "using shift_ist requires paranoid=1"
984 .if \create_gap && \paranoid
985 .error "using create_gap requires paranoid=0"
990 .if \has_error_code == 0
991 pushq $-1 /* ORIG_RAX: no syscall to restart */
995 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */
996 jnz .Lfrom_usermode_switch_stack_\@
1001 * If coming from kernel space, create a 6-word gap to allow the
1002 * int3 handler to emulate a call instruction.
1004 testb $3, CS-ORIG_RAX(%rsp)
1005 jnz .Lfrom_usermode_no_gap_\@
1009 UNWIND_HINT_IRET_REGS offset=8
1010 .Lfrom_usermode_no_gap_\@:
1013 idtentry_part \do_sym, \has_error_code, \read_cr2, \paranoid, \shift_ist, \ist_offset
1017 * Entry from userspace. Switch stacks and treat it
1018 * as a normal entry. This means that paranoid handlers
1019 * run in real process context if user_mode(regs).
1021 .Lfrom_usermode_switch_stack_\@:
1022 idtentry_part \do_sym, \has_error_code, \read_cr2, paranoid=0
1029 idtentry divide_error do_divide_error has_error_code=0
1030 idtentry overflow do_overflow has_error_code=0
1031 idtentry bounds do_bounds has_error_code=0
1032 idtentry invalid_op do_invalid_op has_error_code=0
1033 idtentry device_not_available do_device_not_available has_error_code=0
1034 idtentry double_fault do_double_fault has_error_code=1 paranoid=2 read_cr2=1
1035 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
1036 idtentry invalid_TSS do_invalid_TSS has_error_code=1
1037 idtentry segment_not_present do_segment_not_present has_error_code=1
1038 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
1039 idtentry coprocessor_error do_coprocessor_error has_error_code=0
1040 idtentry alignment_check do_alignment_check has_error_code=1
1041 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
1045 * Reload gs selector with exception handling
1048 * Is in entry.text as it shouldn't be instrumented.
1050 SYM_FUNC_START(native_load_gs_index)
1053 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
1058 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
1060 TRACE_IRQS_FLAGS (%rsp)
1064 SYM_FUNC_END(native_load_gs_index)
1065 EXPORT_SYMBOL(native_load_gs_index)
1067 _ASM_EXTABLE(.Lgs_change, .Lbad_gs)
1068 .section .fixup, "ax"
1069 /* running with kernelgs */
1070 SYM_CODE_START_LOCAL_NOALIGN(.Lbad_gs)
1071 SWAPGS /* switch back to user gs */
1073 /* This can't be a string because the preprocessor needs to see it. */
1074 movl $__USER_DS, %eax
1077 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1081 SYM_CODE_END(.Lbad_gs)
1084 /* Call softirq on interrupt stack. Interrupts are off. */
1085 .pushsection .text, "ax"
1086 SYM_FUNC_START(do_softirq_own_stack)
1089 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1091 LEAVE_IRQ_STACK regs=0
1094 SYM_FUNC_END(do_softirq_own_stack)
1097 #ifdef CONFIG_XEN_PV
1098 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1101 * A note on the "critical region" in our callback handler.
1102 * We want to avoid stacking callback handlers due to events occurring
1103 * during handling of the last event. To do this, we keep events disabled
1104 * until we've done all processing. HOWEVER, we must enable events before
1105 * popping the stack frame (can't be done atomically) and so it would still
1106 * be possible to get enough handler activations to overflow the stack.
1107 * Although unlikely, bugs of that kind are hard to track down, so we'd
1108 * like to avoid the possibility.
1109 * So, on entry to the handler we detect whether we interrupted an
1110 * existing activation in its critical region -- if so, we pop the current
1111 * activation and restart the handler using the previous one.
1113 /* do_hypervisor_callback(struct *pt_regs) */
1114 SYM_CODE_START_LOCAL(xen_do_hypervisor_callback)
1117 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1118 * see the correct pointer to the pt_regs
1121 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1124 ENTER_IRQ_STACK old_rsp=%r10
1125 call xen_evtchn_do_upcall
1128 #ifndef CONFIG_PREEMPTION
1129 call xen_maybe_preempt_hcall
1132 SYM_CODE_END(xen_do_hypervisor_callback)
1135 * Hypervisor uses this for application faults while it executes.
1136 * We get here for two reasons:
1137 * 1. Fault while reloading DS, ES, FS or GS
1138 * 2. Fault while executing IRET
1139 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1140 * registers that could be reloaded and zeroed the others.
1141 * Category 2 we fix up by killing the current process. We cannot use the
1142 * normal Linux return path in this case because if we use the IRET hypercall
1143 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1144 * We distinguish between categories by comparing each saved segment register
1145 * with its current contents: any discrepancy means we in category 1.
1147 SYM_CODE_START(xen_failsafe_callback)
1150 cmpw %cx, 0x10(%rsp)
1153 cmpw %cx, 0x18(%rsp)
1156 cmpw %cx, 0x20(%rsp)
1159 cmpw %cx, 0x28(%rsp)
1161 /* All segments match their saved values => Category 2 (Bad IRET). */
1166 UNWIND_HINT_IRET_REGS offset=8
1167 jmp general_protection
1168 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1172 UNWIND_HINT_IRET_REGS
1173 pushq $-1 /* orig_ax = -1 => not a system call */
1175 ENCODE_FRAME_POINTER
1177 SYM_CODE_END(xen_failsafe_callback)
1178 #endif /* CONFIG_XEN_PV */
1180 #ifdef CONFIG_XEN_PVHVM
1181 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1182 xen_hvm_callback_vector xen_evtchn_do_upcall
1186 #if IS_ENABLED(CONFIG_HYPERV)
1187 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1188 hyperv_callback_vector hyperv_vector_handler
1190 apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \
1191 hyperv_reenlightenment_vector hyperv_reenlightenment_intr
1193 apicinterrupt3 HYPERV_STIMER0_VECTOR \
1194 hv_stimer0_callback_vector hv_stimer0_vector_handler
1195 #endif /* CONFIG_HYPERV */
1197 #if IS_ENABLED(CONFIG_ACRN_GUEST)
1198 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1199 acrn_hv_callback_vector acrn_hv_vector_handler
1202 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=IST_INDEX_DB ist_offset=DB_STACK_OFFSET
1203 idtentry int3 do_int3 has_error_code=0 create_gap=1
1204 idtentry stack_segment do_stack_segment has_error_code=1
1206 #ifdef CONFIG_XEN_PV
1207 idtentry xennmi do_nmi has_error_code=0
1208 idtentry xendebug do_debug has_error_code=0
1211 idtentry general_protection do_general_protection has_error_code=1
1212 idtentry page_fault do_page_fault has_error_code=1 read_cr2=1
1214 #ifdef CONFIG_X86_MCE
1215 idtentry machine_check do_mce has_error_code=0 paranoid=1
1219 * Save all registers in pt_regs, and switch gs if needed.
1220 * Use slow, but surefire "are we in kernel?" check.
1221 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1223 SYM_CODE_START_LOCAL(paranoid_entry)
1226 PUSH_AND_CLEAR_REGS save_ret=1
1227 ENCODE_FRAME_POINTER 8
1229 movl $MSR_GS_BASE, %ecx
1232 js 1f /* negative -> in kernel */
1238 * Always stash CR3 in %r14. This value will be restored,
1239 * verbatim, at exit. Needed if paranoid_entry interrupted
1240 * another entry that already switched to the user CR3 value
1241 * but has not yet returned to userspace.
1243 * This is also why CS (stashed in the "iret frame" by the
1244 * hardware at entry) can not be used: this may be a return
1245 * to kernel code, but with a user CR3 value.
1247 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1250 * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an
1251 * unconditional CR3 write, even in the PTI case. So do an lfence
1252 * to prevent GS speculation, regardless of whether PTI is enabled.
1254 FENCE_SWAPGS_KERNEL_ENTRY
1257 SYM_CODE_END(paranoid_entry)
1260 * "Paranoid" exit path from exception stack. This is invoked
1261 * only on return from non-NMI IST interrupts that came
1262 * from kernel space.
1264 * We may be returning to very strange contexts (e.g. very early
1265 * in syscall entry), so checking for preemption here would
1266 * be complicated. Fortunately, we there's no good reason
1267 * to try to handle preemption here.
1269 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1271 SYM_CODE_START_LOCAL(paranoid_exit)
1273 DISABLE_INTERRUPTS(CLBR_ANY)
1274 TRACE_IRQS_OFF_DEBUG
1275 testl %ebx, %ebx /* swapgs needed? */
1276 jnz .Lparanoid_exit_no_swapgs
1278 /* Always restore stashed CR3 value (see paranoid_entry) */
1279 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1281 jmp restore_regs_and_return_to_kernel
1282 .Lparanoid_exit_no_swapgs:
1283 TRACE_IRQS_IRETQ_DEBUG
1284 /* Always restore stashed CR3 value (see paranoid_entry) */
1285 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1286 jmp restore_regs_and_return_to_kernel
1287 SYM_CODE_END(paranoid_exit)
1290 * Save all registers in pt_regs, and switch GS if needed.
1292 SYM_CODE_START_LOCAL(error_entry)
1295 PUSH_AND_CLEAR_REGS save_ret=1
1296 ENCODE_FRAME_POINTER 8
1297 testb $3, CS+8(%rsp)
1298 jz .Lerror_kernelspace
1301 * We entered from user mode or we're pretending to have entered
1302 * from user mode due to an IRET fault.
1305 FENCE_SWAPGS_USER_ENTRY
1306 /* We have user CR3. Change to kernel CR3. */
1307 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1309 .Lerror_entry_from_usermode_after_swapgs:
1310 /* Put us onto the real thread stack. */
1311 popq %r12 /* save return addr in %12 */
1312 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1314 movq %rax, %rsp /* switch stack */
1315 ENCODE_FRAME_POINTER
1319 .Lerror_entry_done_lfence:
1320 FENCE_SWAPGS_KERNEL_ENTRY
1325 * There are two places in the kernel that can potentially fault with
1326 * usergs. Handle them here. B stepping K8s sometimes report a
1327 * truncated RIP for IRET exceptions returning to compat mode. Check
1328 * for these here too.
1330 .Lerror_kernelspace:
1331 leaq native_irq_return_iret(%rip), %rcx
1332 cmpq %rcx, RIP+8(%rsp)
1334 movl %ecx, %eax /* zero extend */
1335 cmpq %rax, RIP+8(%rsp)
1337 cmpq $.Lgs_change, RIP+8(%rsp)
1338 jne .Lerror_entry_done_lfence
1341 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1342 * gsbase and proceed. We'll fix up the exception and land in
1343 * .Lgs_change's error handler with kernel gsbase.
1346 FENCE_SWAPGS_USER_ENTRY
1347 jmp .Lerror_entry_done
1350 /* Fix truncated RIP */
1351 movq %rcx, RIP+8(%rsp)
1356 * We came from an IRET to user mode, so we have user
1357 * gsbase and CR3. Switch to kernel gsbase and CR3:
1360 FENCE_SWAPGS_USER_ENTRY
1361 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1364 * Pretend that the exception came from user mode: set up pt_regs
1365 * as if we faulted immediately after IRET.
1370 jmp .Lerror_entry_from_usermode_after_swapgs
1371 SYM_CODE_END(error_entry)
1373 SYM_CODE_START_LOCAL(error_exit)
1375 DISABLE_INTERRUPTS(CLBR_ANY)
1380 SYM_CODE_END(error_exit)
1383 * Runs on exception stack. Xen PV does not go through this path at all,
1384 * so we can use real assembly here.
1387 * %r14: Used to save/restore the CR3 of the interrupted context
1388 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1391 UNWIND_HINT_IRET_REGS
1394 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1395 * the iretq it performs will take us out of NMI context.
1396 * This means that we can have nested NMIs where the next
1397 * NMI is using the top of the stack of the previous NMI. We
1398 * can't let it execute because the nested NMI will corrupt the
1399 * stack of the previous NMI. NMI handlers are not re-entrant
1402 * To handle this case we do the following:
1403 * Check the a special location on the stack that contains
1404 * a variable that is set when NMIs are executing.
1405 * The interrupted task's stack is also checked to see if it
1407 * If the variable is not set and the stack is not the NMI
1409 * o Set the special variable on the stack
1410 * o Copy the interrupt frame into an "outermost" location on the
1412 * o Copy the interrupt frame into an "iret" location on the stack
1413 * o Continue processing the NMI
1414 * If the variable is set or the previous stack is the NMI stack:
1415 * o Modify the "iret" location to jump to the repeat_nmi
1416 * o return back to the first NMI
1418 * Now on exit of the first NMI, we first clear the stack variable
1419 * The NMI stack will tell any nested NMIs at that point that it is
1420 * nested. Then we pop the stack normally with iret, and if there was
1421 * a nested NMI that updated the copy interrupt stack frame, a
1422 * jump will be made to the repeat_nmi code that will handle the second
1425 * However, espfix prevents us from directly returning to userspace
1426 * with a single IRET instruction. Similarly, IRET to user mode
1427 * can fault. We therefore handle NMIs from user space like
1428 * other IST entries.
1433 /* Use %rdx as our temp variable throughout */
1436 testb $3, CS-RIP+8(%rsp)
1437 jz .Lnmi_from_kernel
1440 * NMI from user mode. We need to run on the thread stack, but we
1441 * can't go through the normal entry paths: NMIs are masked, and
1442 * we don't want to enable interrupts, because then we'll end
1443 * up in an awkward situation in which IRQs are on but NMIs
1446 * We also must not push anything to the stack before switching
1447 * stacks lest we corrupt the "NMI executing" variable.
1452 FENCE_SWAPGS_USER_ENTRY
1453 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1455 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1456 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1457 pushq 5*8(%rdx) /* pt_regs->ss */
1458 pushq 4*8(%rdx) /* pt_regs->rsp */
1459 pushq 3*8(%rdx) /* pt_regs->flags */
1460 pushq 2*8(%rdx) /* pt_regs->cs */
1461 pushq 1*8(%rdx) /* pt_regs->rip */
1462 UNWIND_HINT_IRET_REGS
1463 pushq $-1 /* pt_regs->orig_ax */
1464 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1465 ENCODE_FRAME_POINTER
1468 * At this point we no longer need to worry about stack damage
1469 * due to nesting -- we're on the normal thread stack and we're
1470 * done with the NMI stack.
1478 * Return back to user mode. We must *not* do the normal exit
1479 * work, because we don't want to enable interrupts.
1481 jmp swapgs_restore_regs_and_return_to_usermode
1485 * Here's what our stack frame will look like:
1486 * +---------------------------------------------------------+
1488 * | original Return RSP |
1489 * | original RFLAGS |
1492 * +---------------------------------------------------------+
1493 * | temp storage for rdx |
1494 * +---------------------------------------------------------+
1495 * | "NMI executing" variable |
1496 * +---------------------------------------------------------+
1497 * | iret SS } Copied from "outermost" frame |
1498 * | iret Return RSP } on each loop iteration; overwritten |
1499 * | iret RFLAGS } by a nested NMI to force another |
1500 * | iret CS } iteration if needed. |
1502 * +---------------------------------------------------------+
1503 * | outermost SS } initialized in first_nmi; |
1504 * | outermost Return RSP } will not be changed before |
1505 * | outermost RFLAGS } NMI processing is done. |
1506 * | outermost CS } Copied to "iret" frame on each |
1507 * | outermost RIP } iteration. |
1508 * +---------------------------------------------------------+
1510 * +---------------------------------------------------------+
1512 * The "original" frame is used by hardware. Before re-enabling
1513 * NMIs, we need to be done with it, and we need to leave enough
1514 * space for the asm code here.
1516 * We return by executing IRET while RSP points to the "iret" frame.
1517 * That will either return for real or it will loop back into NMI
1520 * The "outermost" frame is copied to the "iret" frame on each
1521 * iteration of the loop, so each iteration starts with the "iret"
1522 * frame pointing to the final return target.
1526 * Determine whether we're a nested NMI.
1528 * If we interrupted kernel code between repeat_nmi and
1529 * end_repeat_nmi, then we are a nested NMI. We must not
1530 * modify the "iret" frame because it's being written by
1531 * the outer NMI. That's okay; the outer NMI handler is
1532 * about to about to call do_nmi anyway, so we can just
1533 * resume the outer NMI.
1536 movq $repeat_nmi, %rdx
1539 movq $end_repeat_nmi, %rdx
1545 * Now check "NMI executing". If it's set, then we're nested.
1546 * This will not detect if we interrupted an outer NMI just
1553 * Now test if the previous stack was an NMI stack. This covers
1554 * the case where we interrupt an outer NMI after it clears
1555 * "NMI executing" but before IRET. We need to be careful, though:
1556 * there is one case in which RSP could point to the NMI stack
1557 * despite there being no NMI active: naughty userspace controls
1558 * RSP at the very beginning of the SYSCALL targets. We can
1559 * pull a fast one on naughty userspace, though: we program
1560 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1561 * if it controls the kernel's RSP. We set DF before we clear
1565 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1566 cmpq %rdx, 4*8(%rsp)
1567 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1570 subq $EXCEPTION_STKSZ, %rdx
1571 cmpq %rdx, 4*8(%rsp)
1572 /* If it is below the NMI stack, it is a normal NMI */
1575 /* Ah, it is within the NMI stack. */
1577 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1578 jz first_nmi /* RSP was user controlled. */
1580 /* This is a nested NMI. */
1584 * Modify the "iret" frame to point to repeat_nmi, forcing another
1585 * iteration of NMI handling.
1588 leaq -10*8(%rsp), %rdx
1595 /* Put stack back */
1601 /* We are returning to kernel mode, so this cannot result in a fault. */
1608 /* Make room for "NMI executing". */
1611 /* Leave room for the "iret" frame */
1614 /* Copy the "original" frame to the "outermost" frame */
1618 UNWIND_HINT_IRET_REGS
1620 /* Everything up to here is safe from nested NMIs */
1622 #ifdef CONFIG_DEBUG_ENTRY
1624 * For ease of testing, unmask NMIs right away. Disabled by
1625 * default because IRET is very expensive.
1628 pushq %rsp /* RSP (minus 8 because of the previous push) */
1629 addq $8, (%rsp) /* Fix up RSP */
1631 pushq $__KERNEL_CS /* CS */
1633 iretq /* continues at repeat_nmi below */
1634 UNWIND_HINT_IRET_REGS
1640 * If there was a nested NMI, the first NMI's iret will return
1641 * here. But NMIs are still enabled and we can take another
1642 * nested NMI. The nested NMI checks the interrupted RIP to see
1643 * if it is between repeat_nmi and end_repeat_nmi, and if so
1644 * it will just return, as we are about to repeat an NMI anyway.
1645 * This makes it safe to copy to the stack frame that a nested
1648 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1649 * we're repeating an NMI, gsbase has the same value that it had on
1650 * the first iteration. paranoid_entry will load the kernel
1651 * gsbase if needed before we call do_nmi. "NMI executing"
1654 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1657 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1658 * here must not modify the "iret" frame while we're writing to
1659 * it or it will end up containing garbage.
1669 * Everything below this point can be preempted by a nested NMI.
1670 * If this happens, then the inner NMI will change the "iret"
1671 * frame to point back to repeat_nmi.
1673 pushq $-1 /* ORIG_RAX: no syscall to restart */
1676 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1677 * as we should not be calling schedule in NMI context.
1678 * Even with normal interrupts enabled. An NMI should not be
1679 * setting NEED_RESCHED or anything that normal interrupts and
1680 * exceptions might do.
1685 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1690 /* Always restore stashed CR3 value (see paranoid_entry) */
1691 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1693 testl %ebx, %ebx /* swapgs needed? */
1701 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1702 * at the "iret" frame.
1707 * Clear "NMI executing". Set DF first so that we can easily
1708 * distinguish the remaining code between here and IRET from
1709 * the SYSCALL entry and exit paths.
1711 * We arguably should just inspect RIP instead, but I (Andy) wrote
1712 * this code when I had the misapprehension that Xen PV supported
1713 * NMIs, and Xen PV would break that approach.
1716 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1719 * iretq reads the "iret" frame and exits the NMI stack in a
1720 * single instruction. We are returning to kernel mode, so this
1721 * cannot result in a fault. Similarly, we don't need to worry
1722 * about espfix64 on the way back to kernel mode.
1727 #ifndef CONFIG_IA32_EMULATION
1729 * This handles SYSCALL from 32-bit code. There is no way to program
1730 * MSRs to fully disable 32-bit SYSCALL.
1732 SYM_CODE_START(ignore_sysret)
1736 SYM_CODE_END(ignore_sysret)
1739 .pushsection .text, "ax"
1740 SYM_CODE_START(rewind_stack_do_exit)
1742 /* Prevent any naive code from trying to unwind to our caller. */
1745 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1746 leaq -PTREGS_SIZE(%rax), %rsp
1750 SYM_CODE_END(rewind_stack_do_exit)