2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
13 #include <asm/spitfire.h>
15 #include <asm/processor.h>
18 #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
19 #define ETRAP_PSTATE1 (PSTATE_TSO | PSTATE_PRIV)
20 #define ETRAP_PSTATE2 \
21 (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
24 * On entry, %g7 is return address - 0x4.
25 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
30 .globl etrap_syscall, etrap, etrap_irq, etraptl1
33 etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
37 andcc %g1, TSTATE_PRIV, %g0
40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
41 661: wrpr %g0, 7, %cleanwin
42 .section .fast_win_ctrl_1insn_patch, "ax"
44 .word 0x85880000 ! allclean
47 sethi %hi(TASK_REGOFF), %g2
48 sethi %hi(TSTATE_PEF), %g3
49 or %g2, %lo(TASK_REGOFF), %g2
56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
58 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
60 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
62 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
63 sethi %hi(PT_REGS_MAGIC), %g3
65 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
68 brnz,pt %g1, etrap_save
74 be,pt %xcc, etrap_user_spill
78 brz %g3, etrap_kernel_spill
84 ldx [%g6 + TI_FLAGS], %g3
85 and %g3, _TIF_32BIT, %g3
86 brnz,pt %g3, etrap_user_spill_32bit
88 ba,a,pt %xcc, etrap_user_spill_64bit
90 etrap_save: save %g2, -STACK_BIAS, %sp
94 mov PRIMARY_CONTEXT, %l4
95 661: rdpr %canrestore, %g3
96 .section .fast_win_ctrl_1insn_patch, "ax"
102 661: wrpr %g0, 0, %canrestore
103 .section .fast_win_ctrl_1insn_patch, "ax"
109 /* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR. */
111 sth %l5, [%l6 + TI_SYS_NOERROR]
113 661: wrpr %g3, 0, %otherwin
114 .section .fast_win_ctrl_1insn_patch, "ax"
116 .word 0x87880000 ! otherw
120 sethi %hi(sparc64_kern_pri_context), %g2
121 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
123 661: stxa %g3, [%l4] ASI_DMMU
124 .section .sun4v_1insn_patch, "ax"
126 stxa %g3, [%l4] ASI_MMU
129 sethi %hi(KERNBASE), %l4
136 /* Go to trap time globals so we can save them. */
137 661: wrpr %g0, ETRAP_PSTATE1, %pstate
138 .section .sun4v_1insn_patch, "ax"
143 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
144 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
146 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
148 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
149 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
150 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
151 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
153 sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0
156 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
157 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
158 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
159 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
160 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
161 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
162 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
163 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
165 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
166 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
167 ldx [%g6 + TI_TASK], %g4
171 ldub [%l6 + TI_FPDEPTH], %l5
172 add %l6, TI_FPSAVED + 1, %l4
176 /* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR. */
177 sth %l5, [%l6 + TI_SYS_NOERROR]
182 etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
183 * We place this right after pt_regs on the trap stack.
193 TRAP_LOAD_THREAD_REG(%g6, %g1)
194 sub %sp, ((4 * 8) * 4) + 8, %g2
199 stx %g3, [%g2 + STACK_BIAS + 0x00]
201 stx %g3, [%g2 + STACK_BIAS + 0x08]
203 stx %g3, [%g2 + STACK_BIAS + 0x10]
205 stx %g3, [%g2 + STACK_BIAS + 0x18]
209 stx %g3, [%g2 + STACK_BIAS + 0x20]
211 stx %g3, [%g2 + STACK_BIAS + 0x28]
213 stx %g3, [%g2 + STACK_BIAS + 0x30]
215 stx %g3, [%g2 + STACK_BIAS + 0x38]
217 sethi %hi(is_sun4v), %g3
218 lduw [%g3 + %lo(is_sun4v)], %g3
219 brnz,pn %g3, finish_tl1_capture
224 stx %g3, [%g2 + STACK_BIAS + 0x40]
226 stx %g3, [%g2 + STACK_BIAS + 0x48]
228 stx %g3, [%g2 + STACK_BIAS + 0x50]
230 stx %g3, [%g2 + STACK_BIAS + 0x58]
234 stx %g3, [%g2 + STACK_BIAS + 0x60]
236 stx %g3, [%g2 + STACK_BIAS + 0x68]
238 stx %g3, [%g2 + STACK_BIAS + 0x70]
240 stx %g3, [%g2 + STACK_BIAS + 0x78]
242 stx %g1, [%g2 + STACK_BIAS + 0x80]
247 .section .sun4v_1insn_patch, "ax"
253 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
255 andcc %g1, TSTATE_PRIV, %g0