2 * arch/sh/kernel/cpu/clock.c - SuperH clock framework
4 * Copyright (C) 2005, 2006 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2005 Nokia Corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/kref.h>
23 #include <linux/seq_file.h>
24 #include <linux/err.h>
25 #include <linux/platform_device.h>
26 #include <asm/clock.h>
27 #include <asm/timer.h>
29 static LIST_HEAD(clock_list);
30 static DEFINE_SPINLOCK(clock_lock);
31 static DEFINE_MUTEX(clock_list_sem);
34 * Each subtype is expected to define the init routines for these clocks,
35 * as each subtype (or processor family) will have these clocks at the
36 * very least. These are all provided through the CPG, which even some of
37 * the more quirky parts (such as ST40, SH4-202, etc.) still have.
39 * The processor-specific code is expected to register any additional
40 * clock sources that are of interest.
42 static struct clk master_clk = {
44 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
45 .rate = CONFIG_SH_PCLK_FREQ,
48 static struct clk module_clk = {
50 .parent = &master_clk,
51 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
54 static struct clk bus_clk = {
56 .parent = &master_clk,
57 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
60 static struct clk cpu_clk = {
62 .parent = &master_clk,
63 .flags = CLK_ALWAYS_ENABLED,
67 * The ordering of these clocks matters, do not change it.
69 static struct clk *onchip_clocks[] = {
76 static void propagate_rate(struct clk *clk)
80 list_for_each_entry(clkp, &clock_list, node) {
81 if (likely(clkp->parent != clk))
83 if (likely(clkp->ops && clkp->ops->recalc))
84 clkp->ops->recalc(clkp);
88 int __clk_enable(struct clk *clk)
91 * See if this is the first time we're enabling the clock, some
92 * clocks that are always enabled still require "special"
93 * initialization. This is especially true if the clock mode
94 * changes and the clock needs to hunt for the proper set of
95 * divisors to use before it can effectively recalc.
97 if (unlikely(atomic_read(&clk->kref.refcount) == 1))
98 if (clk->ops && clk->ops->init)
101 kref_get(&clk->kref);
103 if (clk->flags & CLK_ALWAYS_ENABLED)
106 if (likely(clk->ops && clk->ops->enable))
107 clk->ops->enable(clk);
112 int clk_enable(struct clk *clk)
117 spin_lock_irqsave(&clock_lock, flags);
118 ret = __clk_enable(clk);
119 spin_unlock_irqrestore(&clock_lock, flags);
124 static void clk_kref_release(struct kref *kref)
129 void __clk_disable(struct clk *clk)
131 int count = kref_put(&clk->kref, clk_kref_release);
133 if (clk->flags & CLK_ALWAYS_ENABLED)
136 if (!count) { /* count reaches zero, disable the clock */
137 if (likely(clk->ops && clk->ops->disable))
138 clk->ops->disable(clk);
142 void clk_disable(struct clk *clk)
146 spin_lock_irqsave(&clock_lock, flags);
148 spin_unlock_irqrestore(&clock_lock, flags);
151 int clk_register(struct clk *clk)
153 mutex_lock(&clock_list_sem);
155 list_add(&clk->node, &clock_list);
156 kref_init(&clk->kref);
158 mutex_unlock(&clock_list_sem);
160 if (clk->flags & CLK_ALWAYS_ENABLED) {
161 pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
162 if (clk->ops && clk->ops->init)
164 if (clk->ops && clk->ops->enable)
165 clk->ops->enable(clk);
166 pr_debug( "Enabled.");
172 void clk_unregister(struct clk *clk)
174 mutex_lock(&clock_list_sem);
175 list_del(&clk->node);
176 mutex_unlock(&clock_list_sem);
179 inline unsigned long clk_get_rate(struct clk *clk)
184 int clk_set_rate(struct clk *clk, unsigned long rate)
186 return clk_set_rate_ex(clk, rate, 0);
189 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
191 int ret = -EOPNOTSUPP;
193 if (likely(clk->ops && clk->ops->set_rate)) {
196 spin_lock_irqsave(&clock_lock, flags);
197 ret = clk->ops->set_rate(clk, rate, algo_id);
198 spin_unlock_irqrestore(&clock_lock, flags);
201 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
207 void clk_recalc_rate(struct clk *clk)
209 if (likely(clk->ops && clk->ops->recalc)) {
212 spin_lock_irqsave(&clock_lock, flags);
213 clk->ops->recalc(clk);
214 spin_unlock_irqrestore(&clock_lock, flags);
217 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
222 * Returns a clock. Note that we first try to use device id on the bus
223 * and clock name. If this fails, we try to use clock name only.
225 struct clk *clk_get(struct device *dev, const char *id)
227 struct clk *p, *clk = ERR_PTR(-ENOENT);
230 if (dev == NULL || dev->bus != &platform_bus_type)
233 idno = to_platform_device(dev)->id;
235 mutex_lock(&clock_list_sem);
236 list_for_each_entry(p, &clock_list, node) {
238 strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
244 list_for_each_entry(p, &clock_list, node) {
245 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
252 mutex_unlock(&clock_list_sem);
257 void clk_put(struct clk *clk)
259 if (clk && !IS_ERR(clk))
260 module_put(clk->owner);
263 void __init __attribute__ ((weak))
264 arch_init_clk_ops(struct clk_ops **ops, int type)
268 int __init clk_init(void)
272 BUG_ON(!master_clk.rate);
274 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
275 struct clk *clk = onchip_clocks[i];
277 arch_init_clk_ops(&clk->ops, i);
278 ret |= clk_register(clk);
281 /* Kick the child clocks.. */
282 propagate_rate(&master_clk);
283 propagate_rate(&bus_clk);
288 int show_clocks(struct seq_file *m)
292 list_for_each_entry_reverse(clk, &clock_list, node) {
293 unsigned long rate = clk_get_rate(clk);
296 * Don't bother listing dummy clocks with no ancestry
297 * that only support enable and disable ops.
299 if (unlikely(!rate && !clk->parent))
302 seq_printf(m, "%-12s\t: %ld.%02ldMHz\n", clk->name,
303 rate / 1000000, (rate % 1000000) / 10000);
309 EXPORT_SYMBOL_GPL(clk_register);
310 EXPORT_SYMBOL_GPL(clk_unregister);
311 EXPORT_SYMBOL_GPL(clk_get);
312 EXPORT_SYMBOL_GPL(clk_put);
313 EXPORT_SYMBOL_GPL(clk_enable);
314 EXPORT_SYMBOL_GPL(clk_disable);
315 EXPORT_SYMBOL_GPL(__clk_enable);
316 EXPORT_SYMBOL_GPL(__clk_disable);
317 EXPORT_SYMBOL_GPL(clk_get_rate);
318 EXPORT_SYMBOL_GPL(clk_set_rate);
319 EXPORT_SYMBOL_GPL(clk_recalc_rate);
320 EXPORT_SYMBOL_GPL(clk_set_rate_ex);