arch/powerpc/platforms/powermac/nvram.c

   1 /*
   2  *  Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Todo: - add support for the OF persistent properties
  10  */
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/stddef.h>
  14 #include <linux/string.h>
  15 #include <linux/nvram.h>
  16 #include <linux/init.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/errno.h>
  20 #include <linux/adb.h>
  21 #include <linux/pmu.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/completion.h>
  24 #include <linux/spinlock.h>
  25 #include <asm/sections.h>
  26 #include <asm/io.h>
  27 #include <asm/system.h>
  28 #include <asm/prom.h>
  29 #include <asm/machdep.h>
  30 #include <asm/nvram.h>
  31
  32 #define DEBUG
  33
  34 #ifdef DEBUG
  35 #define DBG(x...) printk(x)
  36 #else
  37 #define DBG(x...)
  38 #endif
  39
  40 #define NVRAM_SIZE              0x2000  /* 8kB of non-volatile RAM */
  41
  42 #define CORE99_SIGNATURE        0x5a
  43 #define CORE99_ADLER_START      0x14
  44
  45 /* On Core99, nvram is either a sharp, a micron or an AMD flash */
  46 #define SM_FLASH_STATUS_DONE    0x80
  47 #define SM_FLASH_STATUS_ERR     0x38
  48
  49 #define SM_FLASH_CMD_ERASE_CONFIRM      0xd0
  50 #define SM_FLASH_CMD_ERASE_SETUP        0x20
  51 #define SM_FLASH_CMD_RESET              0xff
  52 #define SM_FLASH_CMD_WRITE_SETUP        0x40
  53 #define SM_FLASH_CMD_CLEAR_STATUS       0x50
  54 #define SM_FLASH_CMD_READ_STATUS        0x70
  55
  56 /* CHRP NVRAM header */
  57 struct chrp_header {
  58   u8            signature;
  59   u8            cksum;
  60   u16           len;
  61   char          name[12];
  62   u8            data[0];
  63 };
  64
  65 struct core99_header {
  66   struct chrp_header    hdr;
  67   u32                   adler;
  68   u32                   generation;
  69   u32                   reserved[2];
  70 };
  71
  72 /*
  73  * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
  74  */
  75 static int nvram_naddrs;
  76 static volatile unsigned char __iomem *nvram_data;
  77 static int is_core_99;
  78 static int core99_bank = 0;
  79 static int nvram_partitions[3];
  80 // XXX Turn that into a sem
  81 static DEFINE_SPINLOCK(nv_lock);
  82
  83 extern int pmac_newworld;
  84 extern int system_running;
  85
  86 static int (*core99_write_bank)(int bank, u8* datas);
  87 static int (*core99_erase_bank)(int bank);
  88
  89 static char *nvram_image;
  90
  91
  92 static unsigned char core99_nvram_read_byte(int addr)
  93 {
  94         if (nvram_image == NULL)
  95                 return 0xff;
  96         return nvram_image[addr];
  97 }
  98
  99 static void core99_nvram_write_byte(int addr, unsigned char val)
 100 {
 101         if (nvram_image == NULL)
 102                 return;
 103         nvram_image[addr] = val;
 104 }
 105
 106 static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
 107 {
 108         int i;
 109
 110         if (nvram_image == NULL)
 111                 return -ENODEV;
 112         if (*index > NVRAM_SIZE)
 113                 return 0;
 114
 115         i = *index;
 116         if (i + count > NVRAM_SIZE)
 117                 count = NVRAM_SIZE - i;
 118
 119         memcpy(buf, &nvram_image[i], count);
 120         *index = i + count;
 121         return count;
 122 }
 123
 124 static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
 125 {
 126         int i;
 127
 128         if (nvram_image == NULL)
 129                 return -ENODEV;
 130         if (*index > NVRAM_SIZE)
 131                 return 0;
 132
 133         i = *index;
 134         if (i + count > NVRAM_SIZE)
 135                 count = NVRAM_SIZE - i;
 136
 137         memcpy(&nvram_image[i], buf, count);
 138         *index = i + count;
 139         return count;
 140 }
 141
 142 static ssize_t core99_nvram_size(void)
 143 {
 144         if (nvram_image == NULL)
 145                 return -ENODEV;
 146         return NVRAM_SIZE;
 147 }
 148
 149 #ifdef CONFIG_PPC32
 150 static volatile unsigned char __iomem *nvram_addr;
 151 static int nvram_mult;
 152
 153 static unsigned char direct_nvram_read_byte(int addr)
 154 {
 155         return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
 156 }
 157
 158 static void direct_nvram_write_byte(int addr, unsigned char val)
 159 {
 160         out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
 161 }
 162
 163
 164 static unsigned char indirect_nvram_read_byte(int addr)
 165 {
 166         unsigned char val;
 167         unsigned long flags;
 168
 169         spin_lock_irqsave(&nv_lock, flags);
 170         out_8(nvram_addr, addr >> 5);
 171         val = in_8(&nvram_data[(addr & 0x1f) << 4]);
 172         spin_unlock_irqrestore(&nv_lock, flags);
 173
 174         return val;
 175 }
 176
 177 static void indirect_nvram_write_byte(int addr, unsigned char val)
 178 {
 179         unsigned long flags;
 180
 181         spin_lock_irqsave(&nv_lock, flags);
 182         out_8(nvram_addr, addr >> 5);
 183         out_8(&nvram_data[(addr & 0x1f) << 4], val);
 184         spin_unlock_irqrestore(&nv_lock, flags);
 185 }
 186
 187
 188 #ifdef CONFIG_ADB_PMU
 189
 190 static void pmu_nvram_complete(struct adb_request *req)
 191 {
 192         if (req->arg)
 193                 complete((struct completion *)req->arg);
 194 }
 195
 196 static unsigned char pmu_nvram_read_byte(int addr)
 197 {
 198         struct adb_request req;
 199         DECLARE_COMPLETION(req_complete);
 200
 201         req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
 202         if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
 203                         (addr >> 8) & 0xff, addr & 0xff))
 204                 return 0xff;
 205         if (system_state == SYSTEM_RUNNING)
 206                 wait_for_completion(&req_complete);
 207         while (!req.complete)
 208                 pmu_poll();
 209         return req.reply[0];
 210 }
 211
 212 static void pmu_nvram_write_byte(int addr, unsigned char val)
 213 {
 214         struct adb_request req;
 215         DECLARE_COMPLETION(req_complete);
 216
 217         req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
 218         if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
 219                         (addr >> 8) & 0xff, addr & 0xff, val))
 220                 return;
 221         if (system_state == SYSTEM_RUNNING)
 222                 wait_for_completion(&req_complete);
 223         while (!req.complete)
 224                 pmu_poll();
 225 }
 226
 227 #endif /* CONFIG_ADB_PMU */
 228 #endif /* CONFIG_PPC32 */
 229
 230 static u8 chrp_checksum(struct chrp_header* hdr)
 231 {
 232         u8 *ptr;
 233         u16 sum = hdr->signature;
 234         for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
 235                 sum += *ptr;
 236         while (sum > 0xFF)
 237                 sum = (sum & 0xFF) + (sum>>8);
 238         return sum;
 239 }
 240
 241 static u32 core99_calc_adler(u8 *buffer)
 242 {
 243         int cnt;
 244         u32 low, high;
 245
 246         buffer += CORE99_ADLER_START;
 247         low = 1;
 248         high = 0;
 249         for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
 250                 if ((cnt % 5000) == 0) {
 251                         high  %= 65521UL;
 252                         high %= 65521UL;
 253                 }
 254                 low += buffer[cnt];
 255                 high += low;
 256         }
 257         low  %= 65521UL;
 258         high %= 65521UL;
 259
 260         return (high << 16) | low;
 261 }
 262
 263 static u32 core99_check(u8* datas)
 264 {
 265         struct core99_header* hdr99 = (struct core99_header*)datas;
 266
 267         if (hdr99->hdr.signature != CORE99_SIGNATURE) {
 268                 DBG("Invalid signature\n");
 269                 return 0;
 270         }
 271         if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
 272                 DBG("Invalid checksum\n");
 273                 return 0;
 274         }
 275         if (hdr99->adler != core99_calc_adler(datas)) {
 276                 DBG("Invalid adler\n");
 277                 return 0;
 278         }
 279         return hdr99->generation;
 280 }
 281
 282 static int sm_erase_bank(int bank)
 283 {
 284         int stat, i;
 285         unsigned long timeout;
 286
 287         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 288
 289         DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
 290
 291         out_8(base, SM_FLASH_CMD_ERASE_SETUP);
 292         out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
 293         timeout = 0;
 294         do {
 295                 if (++timeout > 1000000) {
 296                         printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
 297                         break;
 298                 }
 299                 out_8(base, SM_FLASH_CMD_READ_STATUS);
 300                 stat = in_8(base);
 301         } while (!(stat & SM_FLASH_STATUS_DONE));
 302
 303         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
 304         out_8(base, SM_FLASH_CMD_RESET);
 305
 306         for (i=0; i<NVRAM_SIZE; i++)
 307                 if (base[i] != 0xff) {
 308                         printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
 309                         return -ENXIO;
 310                 }
 311         return 0;
 312 }
 313
 314 static int sm_write_bank(int bank, u8* datas)
 315 {
 316         int i, stat = 0;
 317         unsigned long timeout;
 318
 319         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 320
 321         DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
 322
 323         for (i=0; i<NVRAM_SIZE; i++) {
 324                 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
 325                 udelay(1);
 326                 out_8(base+i, datas[i]);
 327                 timeout = 0;
 328                 do {
 329                         if (++timeout > 1000000) {
 330                                 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
 331                                 break;
 332                         }
 333                         out_8(base, SM_FLASH_CMD_READ_STATUS);
 334                         stat = in_8(base);
 335                 } while (!(stat & SM_FLASH_STATUS_DONE));
 336                 if (!(stat & SM_FLASH_STATUS_DONE))
 337                         break;
 338         }
 339         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
 340         out_8(base, SM_FLASH_CMD_RESET);
 341         for (i=0; i<NVRAM_SIZE; i++)
 342                 if (base[i] != datas[i]) {
 343                         printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
 344                         return -ENXIO;
 345                 }
 346         return 0;
 347 }
 348
 349 static int amd_erase_bank(int bank)
 350 {
 351         int i, stat = 0;
 352         unsigned long timeout;
 353
 354         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 355
 356         DBG("nvram: AMD Erasing bank %d...\n", bank);
 357
 358         /* Unlock 1 */
 359         out_8(base+0x555, 0xaa);
 360         udelay(1);
 361         /* Unlock 2 */
 362         out_8(base+0x2aa, 0x55);
 363         udelay(1);
 364
 365         /* Sector-Erase */
 366         out_8(base+0x555, 0x80);
 367         udelay(1);
 368         out_8(base+0x555, 0xaa);
 369         udelay(1);
 370         out_8(base+0x2aa, 0x55);
 371         udelay(1);
 372         out_8(base, 0x30);
 373         udelay(1);
 374
 375         timeout = 0;
 376         do {
 377                 if (++timeout > 1000000) {
 378                         printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
 379                         break;
 380                 }
 381                 stat = in_8(base) ^ in_8(base);
 382         } while (stat != 0);
 383
 384         /* Reset */
 385         out_8(base, 0xf0);
 386         udelay(1);
 387
 388         for (i=0; i<NVRAM_SIZE; i++)
 389                 if (base[i] != 0xff) {
 390                         printk(KERN_ERR "nvram: AMD flash erase failed !\n");
 391                         return -ENXIO;
 392                 }
 393         return 0;
 394 }
 395
 396 static int amd_write_bank(int bank, u8* datas)
 397 {
 398         int i, stat = 0;
 399         unsigned long timeout;
 400
 401         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 402
 403         DBG("nvram: AMD Writing bank %d...\n", bank);
 404
 405         for (i=0; i<NVRAM_SIZE; i++) {
 406                 /* Unlock 1 */
 407                 out_8(base+0x555, 0xaa);
 408                 udelay(1);
 409                 /* Unlock 2 */
 410                 out_8(base+0x2aa, 0x55);
 411                 udelay(1);
 412
 413                 /* Write single word */
 414                 out_8(base+0x555, 0xa0);
 415                 udelay(1);
 416                 out_8(base+i, datas[i]);
 417
 418                 timeout = 0;
 419                 do {
 420                         if (++timeout > 1000000) {
 421                                 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
 422                                 break;
 423                         }
 424                         stat = in_8(base) ^ in_8(base);
 425                 } while (stat != 0);
 426                 if (stat != 0)
 427                         break;
 428         }
 429
 430         /* Reset */
 431         out_8(base, 0xf0);
 432         udelay(1);
 433
 434         for (i=0; i<NVRAM_SIZE; i++)
 435                 if (base[i] != datas[i]) {
 436                         printk(KERN_ERR "nvram: AMD flash write failed !\n");
 437                         return -ENXIO;
 438                 }
 439         return 0;
 440 }
 441
 442 static void __init lookup_partitions(void)
 443 {
 444         u8 buffer[17];
 445         int i, offset;
 446         struct chrp_header* hdr;
 447
 448         if (pmac_newworld) {
 449                 nvram_partitions[pmac_nvram_OF] = -1;
 450                 nvram_partitions[pmac_nvram_XPRAM] = -1;
 451                 nvram_partitions[pmac_nvram_NR] = -1;
 452                 hdr = (struct chrp_header *)buffer;
 453
 454                 offset = 0;
 455                 buffer[16] = 0;
 456                 do {
 457                         for (i=0;i<16;i++)
 458                                 buffer[i] = ppc_md.nvram_read_val(offset+i);
 459                         if (!strcmp(hdr->name, "common"))
 460                                 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
 461                         if (!strcmp(hdr->name, "APL,MacOS75")) {
 462                                 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
 463                                 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
 464                         }
 465                         offset += (hdr->len * 0x10);
 466                 } while(offset < NVRAM_SIZE);
 467         } else {
 468                 nvram_partitions[pmac_nvram_OF] = 0x1800;
 469                 nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
 470                 nvram_partitions[pmac_nvram_NR] = 0x1400;
 471         }
 472         DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
 473         DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
 474         DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
 475 }
 476
 477 static void core99_nvram_sync(void)
 478 {
 479         struct core99_header* hdr99;
 480         unsigned long flags;
 481
 482         if (!is_core_99 || !nvram_data || !nvram_image)
 483                 return;
 484
 485         spin_lock_irqsave(&nv_lock, flags);
 486         if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
 487                 NVRAM_SIZE))
 488                 goto bail;
 489
 490         DBG("Updating nvram...\n");
 491
 492         hdr99 = (struct core99_header*)nvram_image;
 493         hdr99->generation++;
 494         hdr99->hdr.signature = CORE99_SIGNATURE;
 495         hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
 496         hdr99->adler = core99_calc_adler(nvram_image);
 497         core99_bank = core99_bank ? 0 : 1;
 498         if (core99_erase_bank)
 499                 if (core99_erase_bank(core99_bank)) {
 500                         printk("nvram: Error erasing bank %d\n", core99_bank);
 501                         goto bail;
 502                 }
 503         if (core99_write_bank)
 504                 if (core99_write_bank(core99_bank, nvram_image))
 505                         printk("nvram: Error writing bank %d\n", core99_bank);
 506  bail:
 507         spin_unlock_irqrestore(&nv_lock, flags);
 508
 509 #ifdef DEBUG
 510         mdelay(2000);
 511 #endif
 512 }
 513
 514 static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
 515 {
 516         int i;
 517         u32 gen_bank0, gen_bank1;
 518
 519         if (nvram_naddrs < 1) {
 520                 printk(KERN_ERR "nvram: no address\n");
 521                 return -EINVAL;
 522         }
 523         nvram_image = alloc_bootmem(NVRAM_SIZE);
 524         if (nvram_image == NULL) {
 525                 printk(KERN_ERR "nvram: can't allocate ram image\n");
 526                 return -ENOMEM;
 527         }
 528         nvram_data = ioremap(addr, NVRAM_SIZE*2);
 529         nvram_naddrs = 1; /* Make sure we get the correct case */
 530
 531         DBG("nvram: Checking bank 0...\n");
 532
 533         gen_bank0 = core99_check((u8 *)nvram_data);
 534         gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
 535         core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
 536
 537         DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
 538         DBG("nvram: Active bank is: %d\n", core99_bank);
 539
 540         for (i=0; i<NVRAM_SIZE; i++)
 541                 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
 542
 543         ppc_md.nvram_read_val   = core99_nvram_read_byte;
 544         ppc_md.nvram_write_val  = core99_nvram_write_byte;
 545         ppc_md.nvram_read       = core99_nvram_read;
 546         ppc_md.nvram_write      = core99_nvram_write;
 547         ppc_md.nvram_size       = core99_nvram_size;
 548         ppc_md.nvram_sync       = core99_nvram_sync;
 549         ppc_md.machine_shutdown = core99_nvram_sync;
 550         /*
 551          * Maybe we could be smarter here though making an exclusive list
 552          * of known flash chips is a bit nasty as older OF didn't provide us
 553          * with a useful "compatible" entry. A solution would be to really
 554          * identify the chip using flash id commands and base ourselves on
 555          * a list of known chips IDs
 556          */
 557         if (device_is_compatible(dp, "amd-0137")) {
 558                 core99_erase_bank = amd_erase_bank;
 559                 core99_write_bank = amd_write_bank;
 560         } else {
 561                 core99_erase_bank = sm_erase_bank;
 562                 core99_write_bank = sm_write_bank;
 563         }
 564         return 0;
 565 }
 566
 567 int __init pmac_nvram_init(void)
 568 {
 569         struct device_node *dp;
 570         struct resource r1, r2;
 571         unsigned int s1 = 0, s2 = 0;
 572         int err = 0;
 573
 574         nvram_naddrs = 0;
 575
 576         dp = of_find_node_by_name(NULL, "nvram");
 577         if (dp == NULL) {
 578                 printk(KERN_ERR "Can't find NVRAM device\n");
 579                 return -ENODEV;
 580         }
 581
 582         /* Try to obtain an address */
 583         if (of_address_to_resource(dp, 0, &r1) == 0) {
 584                 nvram_naddrs = 1;
 585                 s1 = (r1.end - r1.start) + 1;
 586                 if (of_address_to_resource(dp, 1, &r2) == 0) {
 587                         nvram_naddrs = 2;
 588                         s2 = (r2.end - r2.start) + 1;
 589                 }
 590         }
 591
 592         is_core_99 = device_is_compatible(dp, "nvram,flash");
 593         if (is_core_99) {
 594                 err = core99_nvram_setup(dp, r1.start);
 595                 goto bail;
 596         }
 597
 598 #ifdef CONFIG_PPC32
 599         if (machine_is(chrp) && nvram_naddrs == 1) {
 600                 nvram_data = ioremap(r1.start, s1);
 601                 nvram_mult = 1;
 602                 ppc_md.nvram_read_val   = direct_nvram_read_byte;
 603                 ppc_md.nvram_write_val  = direct_nvram_write_byte;
 604         } else if (nvram_naddrs == 1) {
 605                 nvram_data = ioremap(r1.start, s1);
 606                 nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
 607                 ppc_md.nvram_read_val   = direct_nvram_read_byte;
 608                 ppc_md.nvram_write_val  = direct_nvram_write_byte;
 609         } else if (nvram_naddrs == 2) {
 610                 nvram_addr = ioremap(r1.start, s1);
 611                 nvram_data = ioremap(r2.start, s2);
 612                 ppc_md.nvram_read_val   = indirect_nvram_read_byte;
 613                 ppc_md.nvram_write_val  = indirect_nvram_write_byte;
 614         } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
 615 #ifdef CONFIG_ADB_PMU
 616                 nvram_naddrs = -1;
 617                 ppc_md.nvram_read_val   = pmu_nvram_read_byte;
 618                 ppc_md.nvram_write_val  = pmu_nvram_write_byte;
 619 #endif /* CONFIG_ADB_PMU */
 620         } else {
 621                 printk(KERN_ERR "Incompatible type of NVRAM\n");
 622                 err = -ENXIO;
 623         }
 624 #endif /* CONFIG_PPC32 */
 625 bail:
 626         of_node_put(dp);
 627         if (err == 0)
 628                 lookup_partitions();
 629         return err;
 630 }
 631
 632 int pmac_get_partition(int partition)
 633 {
 634         return nvram_partitions[partition];
 635 }
 636
 637 u8 pmac_xpram_read(int xpaddr)
 638 {
 639         int offset = pmac_get_partition(pmac_nvram_XPRAM);
 640
 641         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
 642                 return 0xff;
 643
 644         return ppc_md.nvram_read_val(xpaddr + offset);
 645 }
 646
 647 void pmac_xpram_write(int xpaddr, u8 data)
 648 {
 649         int offset = pmac_get_partition(pmac_nvram_XPRAM);
 650
 651         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
 652                 return;
 653
 654         ppc_md.nvram_write_val(xpaddr + offset, data);
 655 }
 656
 657 EXPORT_SYMBOL(pmac_get_partition);
 658 EXPORT_SYMBOL(pmac_xpram_read);
 659 EXPORT_SYMBOL(pmac_xpram_write);