1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1995 Linus Torvalds
4 * Adapted from 'alpha' version by Gary Thomas
5 * Modified by Cort Dougan (cort@cs.nmt.edu)
12 #include <linux/errno.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
16 #include <linux/stddef.h>
17 #include <linux/unistd.h>
18 #include <linux/ptrace.h>
19 #include <linux/user.h>
20 #include <linux/tty.h>
21 #include <linux/major.h>
22 #include <linux/interrupt.h>
23 #include <linux/reboot.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <generated/utsrelease.h>
27 #include <linux/adb.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/console.h>
31 #include <linux/seq_file.h>
32 #include <linux/root_dev.h>
33 #include <linux/initrd.h>
34 #include <linux/timer.h>
37 #include <asm/pgtable.h>
39 #include <asm/pci-bridge.h>
41 #include <asm/machdep.h>
43 #include <asm/hydra.h>
44 #include <asm/sections.h>
46 #include <asm/i8259.h>
54 void rtas_indicator_progress(char *, unsigned short);
57 EXPORT_SYMBOL(_chrp_type);
59 static struct mpic *chrp_mpic;
61 /* Used for doing CHRP event-scans */
62 DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
63 unsigned long event_scan_interval;
65 extern unsigned long loops_per_jiffy;
67 /* To be replaced by RTAS when available */
68 static unsigned int __iomem *briq_SPOR;
71 extern struct smp_ops_t chrp_smp_ops;
74 static const char *gg2_memtypes[4] = {
75 "FPM", "SDRAM", "EDO", "BEDO"
77 static const char *gg2_cachesizes[4] = {
78 "256 KB", "512 KB", "1 MB", "Reserved"
80 static const char *gg2_cachetypes[4] = {
81 "Asynchronous", "Reserved", "Flow-Through Synchronous",
82 "Pipelined Synchronous"
84 static const char *gg2_cachemodes[4] = {
85 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
88 static const char *chrp_names[] = {
97 static void chrp_show_cpuinfo(struct seq_file *m)
101 struct device_node *root;
102 const char *model = "";
104 root = of_find_node_by_path("/");
106 model = of_get_property(root, "model", NULL);
107 seq_printf(m, "machine\t\t: CHRP %s\n", model);
109 /* longtrail (goldengate) stuff */
110 if (model && !strncmp(model, "IBM,LongTrail", 13)) {
111 /* VLSI VAS96011/12 `Golden Gate 2' */
113 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
115 for (i = 0; i < (sdramen ? 4 : 6); i++) {
116 t = in_le32(gg2_pci_config_base+
121 switch ((t>>8) & 0x1f) {
144 seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
145 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
148 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
149 seq_printf(m, "board l2\t: %s %s (%s)\n",
150 gg2_cachesizes[(t>>7) & 3],
151 gg2_cachetypes[(t>>2) & 3],
152 gg2_cachemodes[t & 3]);
158 * Fixes for the National Semiconductor PC78308VUL SuperI/O
160 * Some versions of Open Firmware incorrectly initialize the IRQ settings
161 * for keyboard and mouse
163 static inline void __init sio_write(u8 val, u8 index)
169 static inline u8 __init sio_read(u8 index)
175 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
178 u8 level0, type0, active;
180 /* select logical device */
181 sio_write(device, 0x07);
182 active = sio_read(0x30);
183 level0 = sio_read(0x70);
184 type0 = sio_read(0x71);
185 if (level0 != level || type0 != type || !active) {
186 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
187 "remapping to level %d, type %d, active\n",
188 name, level0, type0, !active ? "in" : "", level, type);
189 sio_write(0x01, 0x30);
190 sio_write(level, 0x70);
191 sio_write(type, 0x71);
195 static void __init sio_init(void)
197 struct device_node *root;
200 root = of_find_node_by_path("/");
204 model = of_get_property(root, "model", NULL);
205 if (model && !strncmp(model, "IBM,LongTrail", 13)) {
206 /* logical device 0 (KBC/Keyboard) */
207 sio_fixup_irq("keyboard", 0, 1, 2);
208 /* select logical device 1 (KBC/Mouse) */
209 sio_fixup_irq("mouse", 1, 12, 2);
216 static void __init pegasos_set_l2cr(void)
218 struct device_node *np;
220 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
221 if (_chrp_type != _CHRP_Pegasos)
224 /* Enable L2 cache if needed */
225 np = of_find_node_by_type(NULL, "cpu");
227 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
229 printk ("Pegasos l2cr : no cpu l2cr property found\n");
232 if (!((*l2cr) & 0x80000000)) {
233 printk ("Pegasos l2cr : L2 cache was not active, "
236 _set_L2CR((*l2cr) | 0x80000000);
243 static void __noreturn briq_restart(char *cmd)
247 out_be32(briq_SPOR, 0);
252 * Per default, input/output-device points to the keyboard/screen
253 * If no card is installed, the built-in serial port is used as a fallback.
254 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
255 * the the built-in serial node. Instead, a /failsafe node is created.
257 static __init void chrp_init(void)
259 struct device_node *node;
260 const char *property;
262 if (strstr(boot_command_line, "console="))
264 /* find the boot console from /chosen/stdout */
267 node = of_find_node_by_path("/");
270 property = of_get_property(node, "model", NULL);
273 if (strcmp(property, "Pegasos2"))
275 /* this is a Pegasos2 */
276 property = of_get_property(of_chosen, "linux,stdout-path", NULL);
280 node = of_find_node_by_path(property);
283 if (!of_node_is_type(node, "serial"))
286 * The 9pin connector is either /failsafe
287 * or /pci@80000000/isa@C/serial@i2F8
288 * The optional graphics card has also type 'serial' in VGA mode.
290 if (of_node_name_eq(node, "failsafe") || of_node_name_eq(node, "serial"))
291 add_preferred_console("ttyS", 0, NULL);
296 static void __init chrp_setup_arch(void)
298 struct device_node *root = of_find_node_by_path("/");
299 const char *machine = NULL;
301 /* init to some ~sane value until calibrate_delay() runs */
302 loops_per_jiffy = 50000000/HZ;
305 machine = of_get_property(root, "model", NULL);
306 if (machine && strncmp(machine, "Pegasos", 7) == 0) {
307 _chrp_type = _CHRP_Pegasos;
308 } else if (machine && strncmp(machine, "IBM", 3) == 0) {
309 _chrp_type = _CHRP_IBM;
310 } else if (machine && strncmp(machine, "MOT", 3) == 0) {
311 _chrp_type = _CHRP_Motorola;
312 } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
313 _chrp_type = _CHRP_briq;
314 /* Map the SPOR register on briq and change the restart hook */
315 briq_SPOR = ioremap(0xff0000e8, 4);
316 ppc_md.restart = briq_restart;
318 /* Let's assume it is an IBM chrp if all else fails */
319 _chrp_type = _CHRP_IBM;
322 printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
325 if (rtas_token("display-character") >= 0)
326 ppc_md.progress = rtas_progress;
328 /* use RTAS time-of-day routines if available */
329 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
330 ppc_md.get_boot_time = rtas_get_boot_time;
331 ppc_md.get_rtc_time = rtas_get_rtc_time;
332 ppc_md.set_rtc_time = rtas_set_rtc_time;
335 /* On pegasos, enable the L2 cache if not already done by OF */
338 /* Lookup PCI host bridges */
342 * Temporary fixes for PCI devices.
345 hydra_init(); /* Mac I/O */
348 * Fix the Super I/O configuration
352 pci_create_OF_bus_map();
355 * Print the banner, then scroll down so boot progress
356 * can be printed. -- Cort
358 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
361 static void chrp_8259_cascade(struct irq_desc *desc)
363 struct irq_chip *chip = irq_desc_get_chip(desc);
364 unsigned int cascade_irq = i8259_irq();
367 generic_handle_irq(cascade_irq);
369 chip->irq_eoi(&desc->irq_data);
373 * Finds the open-pic node and sets up the mpic driver.
375 static void __init chrp_find_openpic(void)
377 struct device_node *np, *root;
380 const unsigned int *iranges, *opprop = NULL;
382 unsigned long opaddr;
385 np = of_find_node_by_type(NULL, "open-pic");
388 root = of_find_node_by_path("/");
390 opprop = of_get_property(root, "platform-open-pic", &oplen);
391 na = of_n_addr_cells(root);
393 if (opprop && oplen >= na * sizeof(unsigned int)) {
394 opaddr = opprop[na-1]; /* assume 32-bit */
395 oplen /= na * sizeof(unsigned int);
398 if (of_address_to_resource(np, 0, &r)) {
405 printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
407 iranges = of_get_property(np, "interrupt-ranges", &len);
409 len = 0; /* non-distributed mpic */
411 len /= 2 * sizeof(unsigned int);
414 * The first pair of cells in interrupt-ranges refers to the
415 * IDU; subsequent pairs refer to the ISUs.
418 printk(KERN_ERR "Insufficient addresses for distributed"
419 " OpenPIC (%d < %d)\n", oplen, len);
424 if (len > 0 && iranges[1] != 0) {
425 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
426 iranges[0], iranges[0] + iranges[1] - 1);
429 isu_size = iranges[3];
431 chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
432 isu_size, 0, " MPIC ");
433 if (chrp_mpic == NULL) {
434 printk(KERN_ERR "Failed to allocate MPIC structure\n");
438 for (i = 1; i < len; ++i) {
441 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
442 iranges[0], iranges[0] + iranges[1] - 1,
444 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
447 mpic_init(chrp_mpic);
448 ppc_md.get_irq = mpic_get_irq;
454 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
455 static struct irqaction xmon_irqaction = {
457 .name = "XMON break",
461 static void __init chrp_find_8259(void)
463 struct device_node *np, *pic = NULL;
464 unsigned long chrp_int_ack = 0;
465 unsigned int cascade_irq;
467 /* Look for cascade */
468 for_each_node_by_type(np, "interrupt-controller")
469 if (of_device_is_compatible(np, "chrp,iic")) {
473 /* Ok, 8259 wasn't found. We need to handle the case where
474 * we have a pegasos that claims to be chrp but doesn't have
475 * a proper interrupt tree
477 if (pic == NULL && chrp_mpic != NULL) {
478 printk(KERN_ERR "i8259: Not found in device-tree"
479 " assuming no legacy interrupts\n");
483 /* Look for intack. In a perfect world, we would look for it on
484 * the ISA bus that holds the 8259 but heh... Works that way. If
485 * we ever see a problem, we can try to re-use the pSeries code here.
486 * Also, Pegasos-type platforms don't have a proper node to start
489 for_each_node_by_name(np, "pci") {
490 const unsigned int *addrp = of_get_property(np,
491 "8259-interrupt-acknowledge", NULL);
495 chrp_int_ack = addrp[of_n_addr_cells(np)-1];
500 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
501 " address, polling\n");
503 i8259_init(pic, chrp_int_ack);
504 if (ppc_md.get_irq == NULL) {
505 ppc_md.get_irq = i8259_irq;
506 irq_set_default_host(i8259_get_host());
508 if (chrp_mpic != NULL) {
509 cascade_irq = irq_of_parse_and_map(pic, 0);
511 printk(KERN_ERR "i8259: failed to map cascade irq\n");
513 irq_set_chained_handler(cascade_irq,
518 static void __init chrp_init_IRQ(void)
520 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
521 struct device_node *kbd;
527 /* Pegasos has no MPIC, those ops would make it crash. It might be an
528 * option to move setting them to after we probe the PIC though
530 if (chrp_mpic != NULL)
531 smp_ops = &chrp_smp_ops;
532 #endif /* CONFIG_SMP */
534 if (_chrp_type == _CHRP_Pegasos)
535 ppc_md.get_irq = i8259_irq;
537 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
538 /* see if there is a keyboard in the device tree
539 with a parent of type "adb" */
540 for_each_node_by_name(kbd, "keyboard")
541 if (of_node_is_type(kbd->parent, "adb"))
545 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
556 request_region(0x20,0x20,"pic1");
557 request_region(0xa0,0x20,"pic2");
558 request_region(0x00,0x20,"dma1");
559 request_region(0x40,0x20,"timer");
560 request_region(0x80,0x10,"dma page reg");
561 request_region(0xc0,0x20,"dma2");
564 ppc_md.progress(" Have fun! ", 0x7777);
567 static int __init chrp_probe(void)
569 const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
570 "device_type", NULL);
573 if (strcmp(dtype, "chrp"))
576 ISA_DMA_THRESHOLD = ~0L;
577 DMA_MODE_READ = 0x44;
578 DMA_MODE_WRITE = 0x48;
580 pm_power_off = rtas_power_off;
587 define_machine(chrp) {
590 .setup_arch = chrp_setup_arch,
592 .show_cpuinfo = chrp_show_cpuinfo,
593 .init_IRQ = chrp_init_IRQ,
594 .restart = rtas_restart,
596 .time_init = chrp_time_init,
597 .set_rtc_time = chrp_set_rtc_time,
598 .get_rtc_time = chrp_get_rtc_time,
599 .calibrate_decr = generic_calibrate_decr,
600 .phys_mem_access_prot = pci_phys_mem_access_prot,