arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41
  42 #include <asm/pgtable.h>
  43 #include <asm/io.h>
  44 #include <asm/processor.h>
  45 #include <asm/mmu.h>
  46 #include <asm/prom.h>
  47 #include <asm/machdep.h>
  48 #include <asm/time.h>
  49 #include <asm/runlatch.h>
  50 #include <asm/syscalls.h>
  51 #include <asm/switch_to.h>
  52 #include <asm/tm.h>
  53 #include <asm/debug.h>
  54 #ifdef CONFIG_PPC64
  55 #include <asm/firmware.h>
  56 #endif
  57 #include <asm/code-patching.h>
  58 #include <linux/kprobes.h>
  59 #include <linux/kdebug.h>
  60
  61 /* Transactional Memory debug */
  62 #ifdef TM_DEBUG_SW
  63 #define TM_DEBUG(x...) printk(KERN_INFO x)
  64 #else
  65 #define TM_DEBUG(x...) do { } while(0)
  66 #endif
  67
  68 extern unsigned long _get_SP(void);
  69
  70 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  71 static void check_if_tm_restore_required(struct task_struct *tsk)
  72 {
  73         /*
  74          * If we are saving the current thread's registers, and the
  75          * thread is in a transactional state, set the TIF_RESTORE_TM
  76          * bit so that we know to restore the registers before
  77          * returning to userspace.
  78          */
  79         if (tsk == current && tsk->thread.regs &&
  80             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  81             !test_thread_flag(TIF_RESTORE_TM)) {
  82                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  83                 set_thread_flag(TIF_RESTORE_TM);
  84         }
  85 }
  86 #else
  87 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
  88 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  89
  90 bool strict_msr_control;
  91 EXPORT_SYMBOL(strict_msr_control);
  92
  93 static int __init enable_strict_msr_control(char *str)
  94 {
  95         strict_msr_control = true;
  96         pr_info("Enabling strict facility control\n");
  97
  98         return 0;
  99 }
 100 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 101
 102 void msr_check_and_set(unsigned long bits)
 103 {
 104         unsigned long oldmsr = mfmsr();
 105         unsigned long newmsr;
 106
 107         newmsr = oldmsr | bits;
 108
 109 #ifdef CONFIG_VSX
 110         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 111                 newmsr |= MSR_VSX;
 112 #endif
 113
 114         if (oldmsr != newmsr)
 115                 mtmsr_isync(newmsr);
 116 }
 117
 118 void __msr_check_and_clear(unsigned long bits)
 119 {
 120         unsigned long oldmsr = mfmsr();
 121         unsigned long newmsr;
 122
 123         newmsr = oldmsr & ~bits;
 124
 125 #ifdef CONFIG_VSX
 126         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 127                 newmsr &= ~MSR_VSX;
 128 #endif
 129
 130         if (oldmsr != newmsr)
 131                 mtmsr_isync(newmsr);
 132 }
 133 EXPORT_SYMBOL(__msr_check_and_clear);
 134
 135 #ifdef CONFIG_PPC_FPU
 136 void giveup_fpu(struct task_struct *tsk)
 137 {
 138         check_if_tm_restore_required(tsk);
 139
 140         msr_check_and_set(MSR_FP);
 141         __giveup_fpu(tsk);
 142         msr_check_and_clear(MSR_FP);
 143 }
 144 EXPORT_SYMBOL(giveup_fpu);
 145
 146 /*
 147  * Make sure the floating-point register state in the
 148  * the thread_struct is up to date for task tsk.
 149  */
 150 void flush_fp_to_thread(struct task_struct *tsk)
 151 {
 152         if (tsk->thread.regs) {
 153                 /*
 154                  * We need to disable preemption here because if we didn't,
 155                  * another process could get scheduled after the regs->msr
 156                  * test but before we have finished saving the FP registers
 157                  * to the thread_struct.  That process could take over the
 158                  * FPU, and then when we get scheduled again we would store
 159                  * bogus values for the remaining FP registers.
 160                  */
 161                 preempt_disable();
 162                 if (tsk->thread.regs->msr & MSR_FP) {
 163                         /*
 164                          * This should only ever be called for current or
 165                          * for a stopped child process.  Since we save away
 166                          * the FP register state on context switch,
 167                          * there is something wrong if a stopped child appears
 168                          * to still have its FP state in the CPU registers.
 169                          */
 170                         BUG_ON(tsk != current);
 171                         giveup_fpu(tsk);
 172                 }
 173                 preempt_enable();
 174         }
 175 }
 176 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 177 #endif /* CONFIG_PPC_FPU */
 178
 179 void enable_kernel_fp(void)
 180 {
 181         WARN_ON(preemptible());
 182
 183         msr_check_and_set(MSR_FP);
 184
 185         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
 186                 __giveup_fpu(current);
 187 }
 188 EXPORT_SYMBOL(enable_kernel_fp);
 189
 190 #ifdef CONFIG_ALTIVEC
 191 void giveup_altivec(struct task_struct *tsk)
 192 {
 193         check_if_tm_restore_required(tsk);
 194
 195         msr_check_and_set(MSR_VEC);
 196         __giveup_altivec(tsk);
 197         msr_check_and_clear(MSR_VEC);
 198 }
 199 EXPORT_SYMBOL(giveup_altivec);
 200
 201 void enable_kernel_altivec(void)
 202 {
 203         WARN_ON(preemptible());
 204
 205         msr_check_and_set(MSR_VEC);
 206
 207         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
 208                 __giveup_altivec(current);
 209 }
 210 EXPORT_SYMBOL(enable_kernel_altivec);
 211
 212 /*
 213  * Make sure the VMX/Altivec register state in the
 214  * the thread_struct is up to date for task tsk.
 215  */
 216 void flush_altivec_to_thread(struct task_struct *tsk)
 217 {
 218         if (tsk->thread.regs) {
 219                 preempt_disable();
 220                 if (tsk->thread.regs->msr & MSR_VEC) {
 221                         BUG_ON(tsk != current);
 222                         giveup_altivec(tsk);
 223                 }
 224                 preempt_enable();
 225         }
 226 }
 227 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 228 #endif /* CONFIG_ALTIVEC */
 229
 230 #ifdef CONFIG_VSX
 231 void giveup_vsx(struct task_struct *tsk)
 232 {
 233         check_if_tm_restore_required(tsk);
 234
 235         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 236         if (tsk->thread.regs->msr & MSR_FP)
 237                 __giveup_fpu(tsk);
 238         if (tsk->thread.regs->msr & MSR_VEC)
 239                 __giveup_altivec(tsk);
 240         __giveup_vsx(tsk);
 241         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 242 }
 243 EXPORT_SYMBOL(giveup_vsx);
 244
 245 void enable_kernel_vsx(void)
 246 {
 247         WARN_ON(preemptible());
 248
 249         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 250
 251         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 252                 if (current->thread.regs->msr & MSR_FP)
 253                         __giveup_fpu(current);
 254                 if (current->thread.regs->msr & MSR_VEC)
 255                         __giveup_altivec(current);
 256                 __giveup_vsx(current);
 257         }
 258 }
 259 EXPORT_SYMBOL(enable_kernel_vsx);
 260
 261 void flush_vsx_to_thread(struct task_struct *tsk)
 262 {
 263         if (tsk->thread.regs) {
 264                 preempt_disable();
 265                 if (tsk->thread.regs->msr & MSR_VSX) {
 266                         BUG_ON(tsk != current);
 267                         giveup_vsx(tsk);
 268                 }
 269                 preempt_enable();
 270         }
 271 }
 272 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 273 #endif /* CONFIG_VSX */
 274
 275 #ifdef CONFIG_SPE
 276 void giveup_spe(struct task_struct *tsk)
 277 {
 278         check_if_tm_restore_required(tsk);
 279
 280         msr_check_and_set(MSR_SPE);
 281         __giveup_spe(tsk);
 282         msr_check_and_clear(MSR_SPE);
 283 }
 284 EXPORT_SYMBOL(giveup_spe);
 285
 286 void enable_kernel_spe(void)
 287 {
 288         WARN_ON(preemptible());
 289
 290         msr_check_and_set(MSR_SPE);
 291
 292         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
 293                 __giveup_spe(current);
 294 }
 295 EXPORT_SYMBOL(enable_kernel_spe);
 296
 297 void flush_spe_to_thread(struct task_struct *tsk)
 298 {
 299         if (tsk->thread.regs) {
 300                 preempt_disable();
 301                 if (tsk->thread.regs->msr & MSR_SPE) {
 302                         BUG_ON(tsk != current);
 303                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 304                         giveup_spe(tsk);
 305                 }
 306                 preempt_enable();
 307         }
 308 }
 309 #endif /* CONFIG_SPE */
 310
 311 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 312 void do_send_trap(struct pt_regs *regs, unsigned long address,
 313                   unsigned long error_code, int signal_code, int breakpt)
 314 {
 315         siginfo_t info;
 316
 317         current->thread.trap_nr = signal_code;
 318         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 319                         11, SIGSEGV) == NOTIFY_STOP)
 320                 return;
 321
 322         /* Deliver the signal to userspace */
 323         info.si_signo = SIGTRAP;
 324         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 325         info.si_code = signal_code;
 326         info.si_addr = (void __user *)address;
 327         force_sig_info(SIGTRAP, &info, current);
 328 }
 329 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 330 void do_break (struct pt_regs *regs, unsigned long address,
 331                     unsigned long error_code)
 332 {
 333         siginfo_t info;
 334
 335         current->thread.trap_nr = TRAP_HWBKPT;
 336         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 337                         11, SIGSEGV) == NOTIFY_STOP)
 338                 return;
 339
 340         if (debugger_break_match(regs))
 341                 return;
 342
 343         /* Clear the breakpoint */
 344         hw_breakpoint_disable();
 345
 346         /* Deliver the signal to userspace */
 347         info.si_signo = SIGTRAP;
 348         info.si_errno = 0;
 349         info.si_code = TRAP_HWBKPT;
 350         info.si_addr = (void __user *)address;
 351         force_sig_info(SIGTRAP, &info, current);
 352 }
 353 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 354
 355 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 356
 357 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 358 /*
 359  * Set the debug registers back to their default "safe" values.
 360  */
 361 static void set_debug_reg_defaults(struct thread_struct *thread)
 362 {
 363         thread->debug.iac1 = thread->debug.iac2 = 0;
 364 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 365         thread->debug.iac3 = thread->debug.iac4 = 0;
 366 #endif
 367         thread->debug.dac1 = thread->debug.dac2 = 0;
 368 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 369         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 370 #endif
 371         thread->debug.dbcr0 = 0;
 372 #ifdef CONFIG_BOOKE
 373         /*
 374          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 375          */
 376         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 377                         DBCR1_IAC3US | DBCR1_IAC4US;
 378         /*
 379          * Force Data Address Compare User/Supervisor bits to be User-only
 380          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 381          */
 382         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 383 #else
 384         thread->debug.dbcr1 = 0;
 385 #endif
 386 }
 387
 388 static void prime_debug_regs(struct debug_reg *debug)
 389 {
 390         /*
 391          * We could have inherited MSR_DE from userspace, since
 392          * it doesn't get cleared on exception entry.  Make sure
 393          * MSR_DE is clear before we enable any debug events.
 394          */
 395         mtmsr(mfmsr() & ~MSR_DE);
 396
 397         mtspr(SPRN_IAC1, debug->iac1);
 398         mtspr(SPRN_IAC2, debug->iac2);
 399 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 400         mtspr(SPRN_IAC3, debug->iac3);
 401         mtspr(SPRN_IAC4, debug->iac4);
 402 #endif
 403         mtspr(SPRN_DAC1, debug->dac1);
 404         mtspr(SPRN_DAC2, debug->dac2);
 405 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 406         mtspr(SPRN_DVC1, debug->dvc1);
 407         mtspr(SPRN_DVC2, debug->dvc2);
 408 #endif
 409         mtspr(SPRN_DBCR0, debug->dbcr0);
 410         mtspr(SPRN_DBCR1, debug->dbcr1);
 411 #ifdef CONFIG_BOOKE
 412         mtspr(SPRN_DBCR2, debug->dbcr2);
 413 #endif
 414 }
 415 /*
 416  * Unless neither the old or new thread are making use of the
 417  * debug registers, set the debug registers from the values
 418  * stored in the new thread.
 419  */
 420 void switch_booke_debug_regs(struct debug_reg *new_debug)
 421 {
 422         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 423                 || (new_debug->dbcr0 & DBCR0_IDM))
 424                         prime_debug_regs(new_debug);
 425 }
 426 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 427 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 428 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 429 static void set_debug_reg_defaults(struct thread_struct *thread)
 430 {
 431         thread->hw_brk.address = 0;
 432         thread->hw_brk.type = 0;
 433         set_breakpoint(&thread->hw_brk);
 434 }
 435 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 436 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 437
 438 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 439 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 440 {
 441         mtspr(SPRN_DAC1, dabr);
 442 #ifdef CONFIG_PPC_47x
 443         isync();
 444 #endif
 445         return 0;
 446 }
 447 #elif defined(CONFIG_PPC_BOOK3S)
 448 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 449 {
 450         mtspr(SPRN_DABR, dabr);
 451         if (cpu_has_feature(CPU_FTR_DABRX))
 452                 mtspr(SPRN_DABRX, dabrx);
 453         return 0;
 454 }
 455 #else
 456 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 457 {
 458         return -EINVAL;
 459 }
 460 #endif
 461
 462 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 463 {
 464         unsigned long dabr, dabrx;
 465
 466         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 467         dabrx = ((brk->type >> 3) & 0x7);
 468
 469         if (ppc_md.set_dabr)
 470                 return ppc_md.set_dabr(dabr, dabrx);
 471
 472         return __set_dabr(dabr, dabrx);
 473 }
 474
 475 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 476 {
 477         unsigned long dawr, dawrx, mrd;
 478
 479         dawr = brk->address;
 480
 481         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 482                                    << (63 - 58); //* read/write bits */
 483         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 484                                    << (63 - 59); //* translate */
 485         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 486                                    >> 3; //* PRIM bits */
 487         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 488            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 489            0b111111=64DW.
 490            brk->len is in bytes.
 491            This aligns up to double word size, shifts and does the bias.
 492         */
 493         mrd = ((brk->len + 7) >> 3) - 1;
 494         dawrx |= (mrd & 0x3f) << (63 - 53);
 495
 496         if (ppc_md.set_dawr)
 497                 return ppc_md.set_dawr(dawr, dawrx);
 498         mtspr(SPRN_DAWR, dawr);
 499         mtspr(SPRN_DAWRX, dawrx);
 500         return 0;
 501 }
 502
 503 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 504 {
 505         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 506
 507         if (cpu_has_feature(CPU_FTR_DAWR))
 508                 set_dawr(brk);
 509         else
 510                 set_dabr(brk);
 511 }
 512
 513 void set_breakpoint(struct arch_hw_breakpoint *brk)
 514 {
 515         preempt_disable();
 516         __set_breakpoint(brk);
 517         preempt_enable();
 518 }
 519
 520 #ifdef CONFIG_PPC64
 521 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 522 #endif
 523
 524 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 525                               struct arch_hw_breakpoint *b)
 526 {
 527         if (a->address != b->address)
 528                 return false;
 529         if (a->type != b->type)
 530                 return false;
 531         if (a->len != b->len)
 532                 return false;
 533         return true;
 534 }
 535
 536 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 537 static void tm_reclaim_thread(struct thread_struct *thr,
 538                               struct thread_info *ti, uint8_t cause)
 539 {
 540         unsigned long msr_diff = 0;
 541
 542         /*
 543          * If FP/VSX registers have been already saved to the
 544          * thread_struct, move them to the transact_fp array.
 545          * We clear the TIF_RESTORE_TM bit since after the reclaim
 546          * the thread will no longer be transactional.
 547          */
 548         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 549                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 550                 if (msr_diff & MSR_FP)
 551                         memcpy(&thr->transact_fp, &thr->fp_state,
 552                                sizeof(struct thread_fp_state));
 553                 if (msr_diff & MSR_VEC)
 554                         memcpy(&thr->transact_vr, &thr->vr_state,
 555                                sizeof(struct thread_vr_state));
 556                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 557                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 558         }
 559
 560         tm_reclaim(thr, thr->regs->msr, cause);
 561
 562         /* Having done the reclaim, we now have the checkpointed
 563          * FP/VSX values in the registers.  These might be valid
 564          * even if we have previously called enable_kernel_fp() or
 565          * flush_fp_to_thread(), so update thr->regs->msr to
 566          * indicate their current validity.
 567          */
 568         thr->regs->msr |= msr_diff;
 569 }
 570
 571 void tm_reclaim_current(uint8_t cause)
 572 {
 573         tm_enable();
 574         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 575 }
 576
 577 static inline void tm_reclaim_task(struct task_struct *tsk)
 578 {
 579         /* We have to work out if we're switching from/to a task that's in the
 580          * middle of a transaction.
 581          *
 582          * In switching we need to maintain a 2nd register state as
 583          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 584          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 585          * (current) FPRs into oldtask->thread.transact_fpr[].
 586          *
 587          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 588          */
 589         struct thread_struct *thr = &tsk->thread;
 590
 591         if (!thr->regs)
 592                 return;
 593
 594         if (!MSR_TM_ACTIVE(thr->regs->msr))
 595                 goto out_and_saveregs;
 596
 597         /* Stash the original thread MSR, as giveup_fpu et al will
 598          * modify it.  We hold onto it to see whether the task used
 599          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 600          * ckpt_regs.msr is already set.
 601          */
 602         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 603                 thr->ckpt_regs.msr = thr->regs->msr;
 604
 605         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 606                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 607                  tsk->pid, thr->regs->nip,
 608                  thr->regs->ccr, thr->regs->msr,
 609                  thr->regs->trap);
 610
 611         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 612
 613         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 614                  tsk->pid);
 615
 616 out_and_saveregs:
 617         /* Always save the regs here, even if a transaction's not active.
 618          * This context-switches a thread's TM info SPRs.  We do it here to
 619          * be consistent with the restore path (in recheckpoint) which
 620          * cannot happen later in _switch().
 621          */
 622         tm_save_sprs(thr);
 623 }
 624
 625 extern void __tm_recheckpoint(struct thread_struct *thread,
 626                               unsigned long orig_msr);
 627
 628 void tm_recheckpoint(struct thread_struct *thread,
 629                      unsigned long orig_msr)
 630 {
 631         unsigned long flags;
 632
 633         /* We really can't be interrupted here as the TEXASR registers can't
 634          * change and later in the trecheckpoint code, we have a userspace R1.
 635          * So let's hard disable over this region.
 636          */
 637         local_irq_save(flags);
 638         hard_irq_disable();
 639
 640         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 641          * before the trecheckpoint and no explosion occurs.
 642          */
 643         tm_restore_sprs(thread);
 644
 645         __tm_recheckpoint(thread, orig_msr);
 646
 647         local_irq_restore(flags);
 648 }
 649
 650 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 651 {
 652         unsigned long msr;
 653
 654         if (!cpu_has_feature(CPU_FTR_TM))
 655                 return;
 656
 657         /* Recheckpoint the registers of the thread we're about to switch to.
 658          *
 659          * If the task was using FP, we non-lazily reload both the original and
 660          * the speculative FP register states.  This is because the kernel
 661          * doesn't see if/when a TM rollback occurs, so if we take an FP
 662          * unavoidable later, we are unable to determine which set of FP regs
 663          * need to be restored.
 664          */
 665         if (!new->thread.regs)
 666                 return;
 667
 668         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 669                 tm_restore_sprs(&new->thread);
 670                 return;
 671         }
 672         msr = new->thread.ckpt_regs.msr;
 673         /* Recheckpoint to restore original checkpointed register state. */
 674         TM_DEBUG("*** tm_recheckpoint of pid %d "
 675                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 676                  new->pid, new->thread.regs->msr, msr);
 677
 678         /* This loads the checkpointed FP/VEC state, if used */
 679         tm_recheckpoint(&new->thread, msr);
 680
 681         /* This loads the speculative FP/VEC state, if used */
 682         if (msr & MSR_FP) {
 683                 do_load_up_transact_fpu(&new->thread);
 684                 new->thread.regs->msr |=
 685                         (MSR_FP | new->thread.fpexc_mode);
 686         }
 687 #ifdef CONFIG_ALTIVEC
 688         if (msr & MSR_VEC) {
 689                 do_load_up_transact_altivec(&new->thread);
 690                 new->thread.regs->msr |= MSR_VEC;
 691         }
 692 #endif
 693         /* We may as well turn on VSX too since all the state is restored now */
 694         if (msr & MSR_VSX)
 695                 new->thread.regs->msr |= MSR_VSX;
 696
 697         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 698                  "(kernel msr 0x%lx)\n",
 699                  new->pid, mfmsr());
 700 }
 701
 702 static inline void __switch_to_tm(struct task_struct *prev)
 703 {
 704         if (cpu_has_feature(CPU_FTR_TM)) {
 705                 tm_enable();
 706                 tm_reclaim_task(prev);
 707         }
 708 }
 709
 710 /*
 711  * This is called if we are on the way out to userspace and the
 712  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 713  * FP and/or vector state and does so if necessary.
 714  * If userspace is inside a transaction (whether active or
 715  * suspended) and FP/VMX/VSX instructions have ever been enabled
 716  * inside that transaction, then we have to keep them enabled
 717  * and keep the FP/VMX/VSX state loaded while ever the transaction
 718  * continues.  The reason is that if we didn't, and subsequently
 719  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 720  * we don't know whether it's the same transaction, and thus we
 721  * don't know which of the checkpointed state and the transactional
 722  * state to use.
 723  */
 724 void restore_tm_state(struct pt_regs *regs)
 725 {
 726         unsigned long msr_diff;
 727
 728         clear_thread_flag(TIF_RESTORE_TM);
 729         if (!MSR_TM_ACTIVE(regs->msr))
 730                 return;
 731
 732         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 733         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 734         if (msr_diff & MSR_FP) {
 735                 fp_enable();
 736                 load_fp_state(&current->thread.fp_state);
 737                 regs->msr |= current->thread.fpexc_mode;
 738         }
 739         if (msr_diff & MSR_VEC) {
 740                 vec_enable();
 741                 load_vr_state(&current->thread.vr_state);
 742         }
 743         regs->msr |= msr_diff;
 744 }
 745
 746 #else
 747 #define tm_recheckpoint_new_task(new)
 748 #define __switch_to_tm(prev)
 749 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 750
 751 static inline void save_sprs(struct thread_struct *t)
 752 {
 753 #ifdef CONFIG_ALTIVEC
 754         if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
 755                 t->vrsave = mfspr(SPRN_VRSAVE);
 756 #endif
 757 #ifdef CONFIG_PPC_BOOK3S_64
 758         if (cpu_has_feature(CPU_FTR_DSCR))
 759                 t->dscr = mfspr(SPRN_DSCR);
 760
 761         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
 762                 t->bescr = mfspr(SPRN_BESCR);
 763                 t->ebbhr = mfspr(SPRN_EBBHR);
 764                 t->ebbrr = mfspr(SPRN_EBBRR);
 765
 766                 t->fscr = mfspr(SPRN_FSCR);
 767
 768                 /*
 769                  * Note that the TAR is not available for use in the kernel.
 770                  * (To provide this, the TAR should be backed up/restored on
 771                  * exception entry/exit instead, and be in pt_regs.  FIXME,
 772                  * this should be in pt_regs anyway (for debug).)
 773                  */
 774                 t->tar = mfspr(SPRN_TAR);
 775         }
 776 #endif
 777 }
 778
 779 static inline void restore_sprs(struct thread_struct *old_thread,
 780                                 struct thread_struct *new_thread)
 781 {
 782 #ifdef CONFIG_ALTIVEC
 783         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 784             old_thread->vrsave != new_thread->vrsave)
 785                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
 786 #endif
 787 #ifdef CONFIG_PPC_BOOK3S_64
 788         if (cpu_has_feature(CPU_FTR_DSCR)) {
 789                 u64 dscr = get_paca()->dscr_default;
 790                 u64 fscr = old_thread->fscr & ~FSCR_DSCR;
 791
 792                 if (new_thread->dscr_inherit) {
 793                         dscr = new_thread->dscr;
 794                         fscr |= FSCR_DSCR;
 795                 }
 796
 797                 if (old_thread->dscr != dscr)
 798                         mtspr(SPRN_DSCR, dscr);
 799
 800                 if (old_thread->fscr != fscr)
 801                         mtspr(SPRN_FSCR, fscr);
 802         }
 803
 804         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
 805                 if (old_thread->bescr != new_thread->bescr)
 806                         mtspr(SPRN_BESCR, new_thread->bescr);
 807                 if (old_thread->ebbhr != new_thread->ebbhr)
 808                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
 809                 if (old_thread->ebbrr != new_thread->ebbrr)
 810                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
 811
 812                 if (old_thread->tar != new_thread->tar)
 813                         mtspr(SPRN_TAR, new_thread->tar);
 814         }
 815 #endif
 816 }
 817
 818 struct task_struct *__switch_to(struct task_struct *prev,
 819         struct task_struct *new)
 820 {
 821         struct thread_struct *new_thread, *old_thread;
 822         struct task_struct *last;
 823 #ifdef CONFIG_PPC_BOOK3S_64
 824         struct ppc64_tlb_batch *batch;
 825 #endif
 826
 827         new_thread = &new->thread;
 828         old_thread = &current->thread;
 829
 830         WARN_ON(!irqs_disabled());
 831
 832         /*
 833          * We need to save SPRs before treclaim/trecheckpoint as these will
 834          * change a number of them.
 835          */
 836         save_sprs(&prev->thread);
 837
 838         __switch_to_tm(prev);
 839
 840         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
 841                 giveup_fpu(prev);
 842 #ifdef CONFIG_ALTIVEC
 843         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
 844                 giveup_altivec(prev);
 845 #endif /* CONFIG_ALTIVEC */
 846 #ifdef CONFIG_VSX
 847         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
 848                 /* VMX and FPU registers are already save here */
 849                 __giveup_vsx(prev);
 850 #endif /* CONFIG_VSX */
 851 #ifdef CONFIG_SPE
 852         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
 853                 giveup_spe(prev);
 854 #endif /* CONFIG_SPE */
 855
 856 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 857         switch_booke_debug_regs(&new->thread.debug);
 858 #else
 859 /*
 860  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
 861  * schedule DABR
 862  */
 863 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 864         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
 865                 __set_breakpoint(&new->thread.hw_brk);
 866 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 867 #endif
 868
 869 #ifdef CONFIG_PPC64
 870         /*
 871          * Collect processor utilization data per process
 872          */
 873         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
 874                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
 875                 long unsigned start_tb, current_tb;
 876                 start_tb = old_thread->start_tb;
 877                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
 878                 old_thread->accum_tb += (current_tb - start_tb);
 879                 new_thread->start_tb = current_tb;
 880         }
 881 #endif /* CONFIG_PPC64 */
 882
 883 #ifdef CONFIG_PPC_BOOK3S_64
 884         batch = this_cpu_ptr(&ppc64_tlb_batch);
 885         if (batch->active) {
 886                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
 887                 if (batch->index)
 888                         __flush_tlb_pending(batch);
 889                 batch->active = 0;
 890         }
 891 #endif /* CONFIG_PPC_BOOK3S_64 */
 892
 893         /*
 894          * We can't take a PMU exception inside _switch() since there is a
 895          * window where the kernel stack SLB and the kernel stack are out
 896          * of sync. Hard disable here.
 897          */
 898         hard_irq_disable();
 899
 900         tm_recheckpoint_new_task(new);
 901
 902         last = _switch(old_thread, new_thread);
 903
 904         /* Need to recalculate these after calling _switch() */
 905         old_thread = &last->thread;
 906         new_thread = &current->thread;
 907
 908 #ifdef CONFIG_PPC_BOOK3S_64
 909         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
 910                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
 911                 batch = this_cpu_ptr(&ppc64_tlb_batch);
 912                 batch->active = 1;
 913         }
 914 #endif /* CONFIG_PPC_BOOK3S_64 */
 915
 916         restore_sprs(old_thread, new_thread);
 917
 918         return last;
 919 }
 920
 921 static int instructions_to_print = 16;
 922
 923 static void show_instructions(struct pt_regs *regs)
 924 {
 925         int i;
 926         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
 927                         sizeof(int));
 928
 929         printk("Instruction dump:");
 930
 931         for (i = 0; i < instructions_to_print; i++) {
 932                 int instr;
 933
 934                 if (!(i % 8))
 935                         printk("\n");
 936
 937 #if !defined(CONFIG_BOOKE)
 938                 /* If executing with the IMMU off, adjust pc rather
 939                  * than print XXXXXXXX.
 940                  */
 941                 if (!(regs->msr & MSR_IR))
 942                         pc = (unsigned long)phys_to_virt(pc);
 943 #endif
 944
 945                 if (!__kernel_text_address(pc) ||
 946                      probe_kernel_address((unsigned int __user *)pc, instr)) {
 947                         printk(KERN_CONT "XXXXXXXX ");
 948                 } else {
 949                         if (regs->nip == pc)
 950                                 printk(KERN_CONT "<%08x> ", instr);
 951                         else
 952                                 printk(KERN_CONT "%08x ", instr);
 953                 }
 954
 955                 pc += sizeof(int);
 956         }
 957
 958         printk("\n");
 959 }
 960
 961 static struct regbit {
 962         unsigned long bit;
 963         const char *name;
 964 } msr_bits[] = {
 965 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
 966         {MSR_SF,        "SF"},
 967         {MSR_HV,        "HV"},
 968 #endif
 969         {MSR_VEC,       "VEC"},
 970         {MSR_VSX,       "VSX"},
 971 #ifdef CONFIG_BOOKE
 972         {MSR_CE,        "CE"},
 973 #endif
 974         {MSR_EE,        "EE"},
 975         {MSR_PR,        "PR"},
 976         {MSR_FP,        "FP"},
 977         {MSR_ME,        "ME"},
 978 #ifdef CONFIG_BOOKE
 979         {MSR_DE,        "DE"},
 980 #else
 981         {MSR_SE,        "SE"},
 982         {MSR_BE,        "BE"},
 983 #endif
 984         {MSR_IR,        "IR"},
 985         {MSR_DR,        "DR"},
 986         {MSR_PMM,       "PMM"},
 987 #ifndef CONFIG_BOOKE
 988         {MSR_RI,        "RI"},
 989         {MSR_LE,        "LE"},
 990 #endif
 991         {0,             NULL}
 992 };
 993
 994 static void printbits(unsigned long val, struct regbit *bits)
 995 {
 996         const char *sep = "";
 997
 998         printk("<");
 999         for (; bits->bit; ++bits)
1000                 if (val & bits->bit) {
1001                         printk("%s%s", sep, bits->name);
1002                         sep = ",";
1003                 }
1004         printk(">");
1005 }
1006
1007 #ifdef CONFIG_PPC64
1008 #define REG             "%016lx"
1009 #define REGS_PER_LINE   4
1010 #define LAST_VOLATILE   13
1011 #else
1012 #define REG             "%08lx"
1013 #define REGS_PER_LINE   8
1014 #define LAST_VOLATILE   12
1015 #endif
1016
1017 void show_regs(struct pt_regs * regs)
1018 {
1019         int i, trap;
1020
1021         show_regs_print_info(KERN_DEFAULT);
1022
1023         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1024                regs->nip, regs->link, regs->ctr);
1025         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1026                regs, regs->trap, print_tainted(), init_utsname()->release);
1027         printk("MSR: "REG" ", regs->msr);
1028         printbits(regs->msr, msr_bits);
1029         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1030         trap = TRAP(regs);
1031         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1032                 printk("CFAR: "REG" ", regs->orig_gpr3);
1033         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1034 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1035                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1036 #else
1037                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1038 #endif
1039 #ifdef CONFIG_PPC64
1040         printk("SOFTE: %ld ", regs->softe);
1041 #endif
1042 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1043         if (MSR_TM_ACTIVE(regs->msr))
1044                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1045 #endif
1046
1047         for (i = 0;  i < 32;  i++) {
1048                 if ((i % REGS_PER_LINE) == 0)
1049                         printk("\nGPR%02d: ", i);
1050                 printk(REG " ", regs->gpr[i]);
1051                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1052                         break;
1053         }
1054         printk("\n");
1055 #ifdef CONFIG_KALLSYMS
1056         /*
1057          * Lookup NIP late so we have the best change of getting the
1058          * above info out without failing
1059          */
1060         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1061         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1062 #endif
1063         show_stack(current, (unsigned long *) regs->gpr[1]);
1064         if (!user_mode(regs))
1065                 show_instructions(regs);
1066 }
1067
1068 void exit_thread(void)
1069 {
1070 }
1071
1072 void flush_thread(void)
1073 {
1074 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1075         flush_ptrace_hw_breakpoint(current);
1076 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1077         set_debug_reg_defaults(&current->thread);
1078 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1079 }
1080
1081 void
1082 release_thread(struct task_struct *t)
1083 {
1084 }
1085
1086 /*
1087  * this gets called so that we can store coprocessor state into memory and
1088  * copy the current task into the new thread.
1089  */
1090 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1091 {
1092         flush_fp_to_thread(src);
1093         flush_altivec_to_thread(src);
1094         flush_vsx_to_thread(src);
1095         flush_spe_to_thread(src);
1096         /*
1097          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1098          * flush but it removes the checkpointed state from the current CPU and
1099          * transitions the CPU out of TM mode.  Hence we need to call
1100          * tm_recheckpoint_new_task() (on the same task) to restore the
1101          * checkpointed state back and the TM mode.
1102          */
1103         __switch_to_tm(src);
1104         tm_recheckpoint_new_task(src);
1105
1106         *dst = *src;
1107
1108         clear_task_ebb(dst);
1109
1110         return 0;
1111 }
1112
1113 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1114 {
1115 #ifdef CONFIG_PPC_STD_MMU_64
1116         unsigned long sp_vsid;
1117         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1118
1119         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1120                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1121                         << SLB_VSID_SHIFT_1T;
1122         else
1123                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1124                         << SLB_VSID_SHIFT;
1125         sp_vsid |= SLB_VSID_KERNEL | llp;
1126         p->thread.ksp_vsid = sp_vsid;
1127 #endif
1128 }
1129
1130 /*
1131  * Copy a thread..
1132  */
1133
1134 /*
1135  * Copy architecture-specific thread state
1136  */
1137 int copy_thread(unsigned long clone_flags, unsigned long usp,
1138                 unsigned long kthread_arg, struct task_struct *p)
1139 {
1140         struct pt_regs *childregs, *kregs;
1141         extern void ret_from_fork(void);
1142         extern void ret_from_kernel_thread(void);
1143         void (*f)(void);
1144         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1145
1146         /* Copy registers */
1147         sp -= sizeof(struct pt_regs);
1148         childregs = (struct pt_regs *) sp;
1149         if (unlikely(p->flags & PF_KTHREAD)) {
1150                 /* kernel thread */
1151                 struct thread_info *ti = (void *)task_stack_page(p);
1152                 memset(childregs, 0, sizeof(struct pt_regs));
1153                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1154                 /* function */
1155                 if (usp)
1156                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1157 #ifdef CONFIG_PPC64
1158                 clear_tsk_thread_flag(p, TIF_32BIT);
1159                 childregs->softe = 1;
1160 #endif
1161                 childregs->gpr[15] = kthread_arg;
1162                 p->thread.regs = NULL;  /* no user register state */
1163                 ti->flags |= _TIF_RESTOREALL;
1164                 f = ret_from_kernel_thread;
1165         } else {
1166                 /* user thread */
1167                 struct pt_regs *regs = current_pt_regs();
1168                 CHECK_FULL_REGS(regs);
1169                 *childregs = *regs;
1170                 if (usp)
1171                         childregs->gpr[1] = usp;
1172                 p->thread.regs = childregs;
1173                 childregs->gpr[3] = 0;  /* Result from fork() */
1174                 if (clone_flags & CLONE_SETTLS) {
1175 #ifdef CONFIG_PPC64
1176                         if (!is_32bit_task())
1177                                 childregs->gpr[13] = childregs->gpr[6];
1178                         else
1179 #endif
1180                                 childregs->gpr[2] = childregs->gpr[6];
1181                 }
1182
1183                 f = ret_from_fork;
1184         }
1185         sp -= STACK_FRAME_OVERHEAD;
1186
1187         /*
1188          * The way this works is that at some point in the future
1189          * some task will call _switch to switch to the new task.
1190          * That will pop off the stack frame created below and start
1191          * the new task running at ret_from_fork.  The new task will
1192          * do some house keeping and then return from the fork or clone
1193          * system call, using the stack frame created above.
1194          */
1195         ((unsigned long *)sp)[0] = 0;
1196         sp -= sizeof(struct pt_regs);
1197         kregs = (struct pt_regs *) sp;
1198         sp -= STACK_FRAME_OVERHEAD;
1199         p->thread.ksp = sp;
1200 #ifdef CONFIG_PPC32
1201         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1202                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1203 #endif
1204 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1205         p->thread.ptrace_bps[0] = NULL;
1206 #endif
1207
1208         p->thread.fp_save_area = NULL;
1209 #ifdef CONFIG_ALTIVEC
1210         p->thread.vr_save_area = NULL;
1211 #endif
1212
1213         setup_ksp_vsid(p, sp);
1214
1215 #ifdef CONFIG_PPC64
1216         if (cpu_has_feature(CPU_FTR_DSCR)) {
1217                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1218                 p->thread.dscr = current->thread.dscr;
1219         }
1220         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1221                 p->thread.ppr = INIT_PPR;
1222 #endif
1223         kregs->nip = ppc_function_entry(f);
1224         return 0;
1225 }
1226
1227 /*
1228  * Set up a thread for executing a new program
1229  */
1230 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1231 {
1232 #ifdef CONFIG_PPC64
1233         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1234 #endif
1235
1236         /*
1237          * If we exec out of a kernel thread then thread.regs will not be
1238          * set.  Do it now.
1239          */
1240         if (!current->thread.regs) {
1241                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1242                 current->thread.regs = regs - 1;
1243         }
1244
1245         memset(regs->gpr, 0, sizeof(regs->gpr));
1246         regs->ctr = 0;
1247         regs->link = 0;
1248         regs->xer = 0;
1249         regs->ccr = 0;
1250         regs->gpr[1] = sp;
1251
1252         /*
1253          * We have just cleared all the nonvolatile GPRs, so make
1254          * FULL_REGS(regs) return true.  This is necessary to allow
1255          * ptrace to examine the thread immediately after exec.
1256          */
1257         regs->trap &= ~1UL;
1258
1259 #ifdef CONFIG_PPC32
1260         regs->mq = 0;
1261         regs->nip = start;
1262         regs->msr = MSR_USER;
1263 #else
1264         if (!is_32bit_task()) {
1265                 unsigned long entry;
1266
1267                 if (is_elf2_task()) {
1268                         /* Look ma, no function descriptors! */
1269                         entry = start;
1270
1271                         /*
1272                          * Ulrich says:
1273                          *   The latest iteration of the ABI requires that when
1274                          *   calling a function (at its global entry point),
1275                          *   the caller must ensure r12 holds the entry point
1276                          *   address (so that the function can quickly
1277                          *   establish addressability).
1278                          */
1279                         regs->gpr[12] = start;
1280                         /* Make sure that's restored on entry to userspace. */
1281                         set_thread_flag(TIF_RESTOREALL);
1282                 } else {
1283                         unsigned long toc;
1284
1285                         /* start is a relocated pointer to the function
1286                          * descriptor for the elf _start routine.  The first
1287                          * entry in the function descriptor is the entry
1288                          * address of _start and the second entry is the TOC
1289                          * value we need to use.
1290                          */
1291                         __get_user(entry, (unsigned long __user *)start);
1292                         __get_user(toc, (unsigned long __user *)start+1);
1293
1294                         /* Check whether the e_entry function descriptor entries
1295                          * need to be relocated before we can use them.
1296                          */
1297                         if (load_addr != 0) {
1298                                 entry += load_addr;
1299                                 toc   += load_addr;
1300                         }
1301                         regs->gpr[2] = toc;
1302                 }
1303                 regs->nip = entry;
1304                 regs->msr = MSR_USER64;
1305         } else {
1306                 regs->nip = start;
1307                 regs->gpr[2] = 0;
1308                 regs->msr = MSR_USER32;
1309         }
1310 #endif
1311 #ifdef CONFIG_VSX
1312         current->thread.used_vsr = 0;
1313 #endif
1314         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1315         current->thread.fp_save_area = NULL;
1316 #ifdef CONFIG_ALTIVEC
1317         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1318         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1319         current->thread.vr_save_area = NULL;
1320         current->thread.vrsave = 0;
1321         current->thread.used_vr = 0;
1322 #endif /* CONFIG_ALTIVEC */
1323 #ifdef CONFIG_SPE
1324         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1325         current->thread.acc = 0;
1326         current->thread.spefscr = 0;
1327         current->thread.used_spe = 0;
1328 #endif /* CONFIG_SPE */
1329 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1330         if (cpu_has_feature(CPU_FTR_TM))
1331                 regs->msr |= MSR_TM;
1332         current->thread.tm_tfhar = 0;
1333         current->thread.tm_texasr = 0;
1334         current->thread.tm_tfiar = 0;
1335 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1336 }
1337 EXPORT_SYMBOL(start_thread);
1338
1339 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1340                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1341
1342 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1343 {
1344         struct pt_regs *regs = tsk->thread.regs;
1345
1346         /* This is a bit hairy.  If we are an SPE enabled  processor
1347          * (have embedded fp) we store the IEEE exception enable flags in
1348          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1349          * mode (asyn, precise, disabled) for 'Classic' FP. */
1350         if (val & PR_FP_EXC_SW_ENABLE) {
1351 #ifdef CONFIG_SPE
1352                 if (cpu_has_feature(CPU_FTR_SPE)) {
1353                         /*
1354                          * When the sticky exception bits are set
1355                          * directly by userspace, it must call prctl
1356                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1357                          * in the existing prctl settings) or
1358                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1359                          * the bits being set).  <fenv.h> functions
1360                          * saving and restoring the whole
1361                          * floating-point environment need to do so
1362                          * anyway to restore the prctl settings from
1363                          * the saved environment.
1364                          */
1365                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1366                         tsk->thread.fpexc_mode = val &
1367                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1368                         return 0;
1369                 } else {
1370                         return -EINVAL;
1371                 }
1372 #else
1373                 return -EINVAL;
1374 #endif
1375         }
1376
1377         /* on a CONFIG_SPE this does not hurt us.  The bits that
1378          * __pack_fe01 use do not overlap with bits used for
1379          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1380          * on CONFIG_SPE implementations are reserved so writing to
1381          * them does not change anything */
1382         if (val > PR_FP_EXC_PRECISE)
1383                 return -EINVAL;
1384         tsk->thread.fpexc_mode = __pack_fe01(val);
1385         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1386                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1387                         | tsk->thread.fpexc_mode;
1388         return 0;
1389 }
1390
1391 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1392 {
1393         unsigned int val;
1394
1395         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1396 #ifdef CONFIG_SPE
1397                 if (cpu_has_feature(CPU_FTR_SPE)) {
1398                         /*
1399                          * When the sticky exception bits are set
1400                          * directly by userspace, it must call prctl
1401                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1402                          * in the existing prctl settings) or
1403                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1404                          * the bits being set).  <fenv.h> functions
1405                          * saving and restoring the whole
1406                          * floating-point environment need to do so
1407                          * anyway to restore the prctl settings from
1408                          * the saved environment.
1409                          */
1410                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1411                         val = tsk->thread.fpexc_mode;
1412                 } else
1413                         return -EINVAL;
1414 #else
1415                 return -EINVAL;
1416 #endif
1417         else
1418                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1419         return put_user(val, (unsigned int __user *) adr);
1420 }
1421
1422 int set_endian(struct task_struct *tsk, unsigned int val)
1423 {
1424         struct pt_regs *regs = tsk->thread.regs;
1425
1426         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1427             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1428                 return -EINVAL;
1429
1430         if (regs == NULL)
1431                 return -EINVAL;
1432
1433         if (val == PR_ENDIAN_BIG)
1434                 regs->msr &= ~MSR_LE;
1435         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1436                 regs->msr |= MSR_LE;
1437         else
1438                 return -EINVAL;
1439
1440         return 0;
1441 }
1442
1443 int get_endian(struct task_struct *tsk, unsigned long adr)
1444 {
1445         struct pt_regs *regs = tsk->thread.regs;
1446         unsigned int val;
1447
1448         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1449             !cpu_has_feature(CPU_FTR_REAL_LE))
1450                 return -EINVAL;
1451
1452         if (regs == NULL)
1453                 return -EINVAL;
1454
1455         if (regs->msr & MSR_LE) {
1456                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1457                         val = PR_ENDIAN_LITTLE;
1458                 else
1459                         val = PR_ENDIAN_PPC_LITTLE;
1460         } else
1461                 val = PR_ENDIAN_BIG;
1462
1463         return put_user(val, (unsigned int __user *)adr);
1464 }
1465
1466 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1467 {
1468         tsk->thread.align_ctl = val;
1469         return 0;
1470 }
1471
1472 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1473 {
1474         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1475 }
1476
1477 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1478                                   unsigned long nbytes)
1479 {
1480         unsigned long stack_page;
1481         unsigned long cpu = task_cpu(p);
1482
1483         /*
1484          * Avoid crashing if the stack has overflowed and corrupted
1485          * task_cpu(p), which is in the thread_info struct.
1486          */
1487         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1488                 stack_page = (unsigned long) hardirq_ctx[cpu];
1489                 if (sp >= stack_page + sizeof(struct thread_struct)
1490                     && sp <= stack_page + THREAD_SIZE - nbytes)
1491                         return 1;
1492
1493                 stack_page = (unsigned long) softirq_ctx[cpu];
1494                 if (sp >= stack_page + sizeof(struct thread_struct)
1495                     && sp <= stack_page + THREAD_SIZE - nbytes)
1496                         return 1;
1497         }
1498         return 0;
1499 }
1500
1501 int validate_sp(unsigned long sp, struct task_struct *p,
1502                        unsigned long nbytes)
1503 {
1504         unsigned long stack_page = (unsigned long)task_stack_page(p);
1505
1506         if (sp >= stack_page + sizeof(struct thread_struct)
1507             && sp <= stack_page + THREAD_SIZE - nbytes)
1508                 return 1;
1509
1510         return valid_irq_stack(sp, p, nbytes);
1511 }
1512
1513 EXPORT_SYMBOL(validate_sp);
1514
1515 unsigned long get_wchan(struct task_struct *p)
1516 {
1517         unsigned long ip, sp;
1518         int count = 0;
1519
1520         if (!p || p == current || p->state == TASK_RUNNING)
1521                 return 0;
1522
1523         sp = p->thread.ksp;
1524         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1525                 return 0;
1526
1527         do {
1528                 sp = *(unsigned long *)sp;
1529                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1530                         return 0;
1531                 if (count > 0) {
1532                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1533                         if (!in_sched_functions(ip))
1534                                 return ip;
1535                 }
1536         } while (count++ < 16);
1537         return 0;
1538 }
1539
1540 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1541
1542 void show_stack(struct task_struct *tsk, unsigned long *stack)
1543 {
1544         unsigned long sp, ip, lr, newsp;
1545         int count = 0;
1546         int firstframe = 1;
1547 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1548         int curr_frame = current->curr_ret_stack;
1549         extern void return_to_handler(void);
1550         unsigned long rth = (unsigned long)return_to_handler;
1551 #endif
1552
1553         sp = (unsigned long) stack;
1554         if (tsk == NULL)
1555                 tsk = current;
1556         if (sp == 0) {
1557                 if (tsk == current)
1558                         sp = current_stack_pointer();
1559                 else
1560                         sp = tsk->thread.ksp;
1561         }
1562
1563         lr = 0;
1564         printk("Call Trace:\n");
1565         do {
1566                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1567                         return;
1568
1569                 stack = (unsigned long *) sp;
1570                 newsp = stack[0];
1571                 ip = stack[STACK_FRAME_LR_SAVE];
1572                 if (!firstframe || ip != lr) {
1573                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1574 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1575                         if ((ip == rth) && curr_frame >= 0) {
1576                                 printk(" (%pS)",
1577                                        (void *)current->ret_stack[curr_frame].ret);
1578                                 curr_frame--;
1579                         }
1580 #endif
1581                         if (firstframe)
1582                                 printk(" (unreliable)");
1583                         printk("\n");
1584                 }
1585                 firstframe = 0;
1586
1587                 /*
1588                  * See if this is an exception frame.
1589                  * We look for the "regshere" marker in the current frame.
1590                  */
1591                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1592                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1593                         struct pt_regs *regs = (struct pt_regs *)
1594                                 (sp + STACK_FRAME_OVERHEAD);
1595                         lr = regs->link;
1596                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1597                                regs->trap, (void *)regs->nip, (void *)lr);
1598                         firstframe = 1;
1599                 }
1600
1601                 sp = newsp;
1602         } while (count++ < kstack_depth_to_print);
1603 }
1604
1605 #ifdef CONFIG_PPC64
1606 /* Called with hard IRQs off */
1607 void notrace __ppc64_runlatch_on(void)
1608 {
1609         struct thread_info *ti = current_thread_info();
1610         unsigned long ctrl;
1611
1612         ctrl = mfspr(SPRN_CTRLF);
1613         ctrl |= CTRL_RUNLATCH;
1614         mtspr(SPRN_CTRLT, ctrl);
1615
1616         ti->local_flags |= _TLF_RUNLATCH;
1617 }
1618
1619 /* Called with hard IRQs off */
1620 void notrace __ppc64_runlatch_off(void)
1621 {
1622         struct thread_info *ti = current_thread_info();
1623         unsigned long ctrl;
1624
1625         ti->local_flags &= ~_TLF_RUNLATCH;
1626
1627         ctrl = mfspr(SPRN_CTRLF);
1628         ctrl &= ~CTRL_RUNLATCH;
1629         mtspr(SPRN_CTRLT, ctrl);
1630 }
1631 #endif /* CONFIG_PPC64 */
1632
1633 unsigned long arch_align_stack(unsigned long sp)
1634 {
1635         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1636                 sp -= get_random_int() & ~PAGE_MASK;
1637         return sp & ~0xf;
1638 }
1639
1640 static inline unsigned long brk_rnd(void)
1641 {
1642         unsigned long rnd = 0;
1643
1644         /* 8MB for 32bit, 1GB for 64bit */
1645         if (is_32bit_task())
1646                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1647         else
1648                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1649
1650         return rnd << PAGE_SHIFT;
1651 }
1652
1653 unsigned long arch_randomize_brk(struct mm_struct *mm)
1654 {
1655         unsigned long base = mm->brk;
1656         unsigned long ret;
1657
1658 #ifdef CONFIG_PPC_STD_MMU_64
1659         /*
1660          * If we are using 1TB segments and we are allowed to randomise
1661          * the heap, we can put it above 1TB so it is backed by a 1TB
1662          * segment. Otherwise the heap will be in the bottom 1TB
1663          * which always uses 256MB segments and this may result in a
1664          * performance penalty.
1665          */
1666         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1667                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1668 #endif
1669
1670         ret = PAGE_ALIGN(base + brk_rnd());
1671
1672         if (ret < mm->brk)
1673                 return mm->brk;
1674
1675         return ret;
1676 }
1677