2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 #include "../../../drivers/pci/pci.h"
47 /* hose_spinlock protects accesses to the the phb_bitmap. */
48 static DEFINE_SPINLOCK(hose_spinlock);
51 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
52 #define MAX_PHBS 0x10000
55 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
56 * Accesses to this bitmap should be protected by hose_spinlock.
58 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
60 /* ISA Memory physical address */
61 resource_size_t isa_mem_base;
62 EXPORT_SYMBOL(isa_mem_base);
65 static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops;
67 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
69 pci_dma_ops = dma_ops;
72 const struct dma_map_ops *get_pci_dma_ops(void)
76 EXPORT_SYMBOL(get_pci_dma_ops);
79 * This function should run under locking protection, specifically
82 static int get_phb_number(struct device_node *dn)
89 * Try fixed PHB numbering first, by checking archs and reading
90 * the respective device-tree properties. Firstly, try powernv by
91 * reading "ibm,opal-phbid", only present in OPAL environment.
93 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
95 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
100 phb_id = (int)(prop & (MAX_PHBS - 1));
102 /* We need to be sure to not use the same PHB number twice. */
103 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
107 * If not pseries nor powernv, or if fixed PHB numbering tried to add
108 * the same PHB number twice, then fallback to dynamic PHB numbering.
110 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
111 BUG_ON(phb_id >= MAX_PHBS);
112 set_bit(phb_id, phb_bitmap);
117 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
119 struct pci_controller *phb;
121 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
124 spin_lock(&hose_spinlock);
125 phb->global_number = get_phb_number(dev);
126 list_add_tail(&phb->list_node, &hose_list);
127 spin_unlock(&hose_spinlock);
129 phb->is_dynamic = slab_is_available();
132 int nid = of_node_to_nid(dev);
134 if (nid < 0 || !node_online(nid))
137 PHB_SET_NODE(phb, nid);
142 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
144 void pcibios_free_controller(struct pci_controller *phb)
146 spin_lock(&hose_spinlock);
148 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
149 if (phb->global_number < MAX_PHBS)
150 clear_bit(phb->global_number, phb_bitmap);
152 list_del(&phb->list_node);
153 spin_unlock(&hose_spinlock);
158 EXPORT_SYMBOL_GPL(pcibios_free_controller);
161 * This function is used to call pcibios_free_controller()
162 * in a deferred manner: a callback from the PCI subsystem.
164 * _*DO NOT*_ call pcibios_free_controller() explicitly if
165 * this is used (or it may access an invalid *phb pointer).
167 * The callback occurs when all references to the root bus
168 * are dropped (e.g., child buses/devices and their users).
170 * It's called as .release_fn() of 'struct pci_host_bridge'
171 * which is associated with the 'struct pci_controller.bus'
172 * (root bus) - it expects .release_data to hold a pointer
173 * to 'struct pci_controller'.
175 * In order to use it, register .release_fn()/release_data
178 * pci_set_host_bridge_release(bridge,
179 * pcibios_free_controller_deferred
182 * e.g. in the pcibios_root_bridge_prepare() callback from
183 * pci_create_root_bus().
185 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
187 struct pci_controller *phb = (struct pci_controller *)
188 bridge->release_data;
190 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
192 pcibios_free_controller(phb);
194 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
197 * The function is used to return the minimal alignment
198 * for memory or I/O windows of the associated P2P bridge.
199 * By default, 4KiB alignment for I/O windows and 1MiB for
202 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
205 struct pci_controller *phb = pci_bus_to_host(bus);
207 if (phb->controller_ops.window_alignment)
208 return phb->controller_ops.window_alignment(bus, type);
211 * PCI core will figure out the default
212 * alignment: 4KiB for I/O and 1MiB for
218 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
220 struct pci_controller *hose = pci_bus_to_host(bus);
222 if (hose->controller_ops.setup_bridge)
223 hose->controller_ops.setup_bridge(bus, type);
226 void pcibios_reset_secondary_bus(struct pci_dev *dev)
228 struct pci_controller *phb = pci_bus_to_host(dev->bus);
230 if (phb->controller_ops.reset_secondary_bus) {
231 phb->controller_ops.reset_secondary_bus(dev);
235 pci_reset_secondary_bus(dev);
238 resource_size_t pcibios_default_alignment(void)
240 if (ppc_md.pcibios_default_alignment)
241 return ppc_md.pcibios_default_alignment();
246 #ifdef CONFIG_PCI_IOV
247 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
249 if (ppc_md.pcibios_iov_resource_alignment)
250 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
252 return pci_iov_resource_size(pdev, resno);
255 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
257 if (ppc_md.pcibios_sriov_enable)
258 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
263 int pcibios_sriov_disable(struct pci_dev *pdev)
265 if (ppc_md.pcibios_sriov_disable)
266 return ppc_md.pcibios_sriov_disable(pdev);
271 #endif /* CONFIG_PCI_IOV */
273 void pcibios_bus_add_device(struct pci_dev *pdev)
275 if (ppc_md.pcibios_bus_add_device)
276 ppc_md.pcibios_bus_add_device(pdev);
279 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
282 return hose->pci_io_size;
284 return resource_size(&hose->io_resource);
288 int pcibios_vaddr_is_ioport(void __iomem *address)
291 struct pci_controller *hose;
292 resource_size_t size;
294 spin_lock(&hose_spinlock);
295 list_for_each_entry(hose, &hose_list, list_node) {
296 size = pcibios_io_size(hose);
297 if (address >= hose->io_base_virt &&
298 address < (hose->io_base_virt + size)) {
303 spin_unlock(&hose_spinlock);
307 unsigned long pci_address_to_pio(phys_addr_t address)
309 struct pci_controller *hose;
310 resource_size_t size;
311 unsigned long ret = ~0;
313 spin_lock(&hose_spinlock);
314 list_for_each_entry(hose, &hose_list, list_node) {
315 size = pcibios_io_size(hose);
316 if (address >= hose->io_base_phys &&
317 address < (hose->io_base_phys + size)) {
319 (unsigned long)hose->io_base_virt - _IO_BASE;
320 ret = base + (address - hose->io_base_phys);
324 spin_unlock(&hose_spinlock);
328 EXPORT_SYMBOL_GPL(pci_address_to_pio);
331 * Return the domain number for this bus.
333 int pci_domain_nr(struct pci_bus *bus)
335 struct pci_controller *hose = pci_bus_to_host(bus);
337 return hose->global_number;
339 EXPORT_SYMBOL(pci_domain_nr);
341 /* This routine is meant to be used early during boot, when the
342 * PCI bus numbers have not yet been assigned, and you need to
343 * issue PCI config cycles to an OF device.
344 * It could also be used to "fix" RTAS config cycles if you want
345 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
348 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
351 struct pci_controller *hose, *tmp;
352 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
353 if (hose->dn == node)
361 * Reads the interrupt pin to determine if interrupt is use by card.
362 * If the interrupt is used, then gets the interrupt line from the
363 * openfirmware and sets it in the pci_dev and pci_config line.
365 static int pci_read_irq_line(struct pci_dev *pci_dev)
369 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
372 memset(&oirq, 0xff, sizeof(oirq));
374 /* Try to get a mapping from the device-tree */
375 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
379 /* If that fails, lets fallback to what is in the config
380 * space and map that through the default controller. We
381 * also set the type to level low since that's what PCI
382 * interrupts are. If your platform does differently, then
383 * either provide a proper interrupt tree or don't use this
386 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
390 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
391 line == 0xff || line == 0) {
394 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
397 virq = irq_create_mapping(NULL, line);
399 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
403 pr_debug(" Failed to map !\n");
407 pr_debug(" Mapped to linux irq %d\n", virq);
415 * Platform support for /proc/bus/pci/X/Y mmap()s.
418 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
420 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
421 resource_size_t ioaddr = pci_resource_start(pdev, bar);
426 /* Convert to an offset within this PCI controller */
427 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
429 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
434 * This one is used by /dev/mem and fbdev who have no clue about the
435 * PCI device, it tries to find the PCI device first and calls the
438 pgprot_t pci_phys_mem_access_prot(struct file *file,
443 struct pci_dev *pdev = NULL;
444 struct resource *found = NULL;
445 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
448 if (page_is_ram(pfn))
451 prot = pgprot_noncached(prot);
452 for_each_pci_dev(pdev) {
453 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
454 struct resource *rp = &pdev->resource[i];
455 int flags = rp->flags;
457 /* Active and same type? */
458 if ((flags & IORESOURCE_MEM) == 0)
460 /* In the range of this resource? */
461 if (offset < (rp->start & PAGE_MASK) ||
471 if (found->flags & IORESOURCE_PREFETCH)
472 prot = pgprot_noncached_wc(prot);
476 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
477 (unsigned long long)offset, pgprot_val(prot));
482 /* This provides legacy IO read access on a bus */
483 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
485 unsigned long offset;
486 struct pci_controller *hose = pci_bus_to_host(bus);
487 struct resource *rp = &hose->io_resource;
490 /* Check if port can be supported by that bus. We only check
491 * the ranges of the PHB though, not the bus itself as the rules
492 * for forwarding legacy cycles down bridges are not our problem
493 * here. So if the host bridge supports it, we do it.
495 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
498 if (!(rp->flags & IORESOURCE_IO))
500 if (offset < rp->start || (offset + size) > rp->end)
502 addr = hose->io_base_virt + port;
506 *((u8 *)val) = in_8(addr);
511 *((u16 *)val) = in_le16(addr);
516 *((u32 *)val) = in_le32(addr);
522 /* This provides legacy IO write access on a bus */
523 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
525 unsigned long offset;
526 struct pci_controller *hose = pci_bus_to_host(bus);
527 struct resource *rp = &hose->io_resource;
530 /* Check if port can be supported by that bus. We only check
531 * the ranges of the PHB though, not the bus itself as the rules
532 * for forwarding legacy cycles down bridges are not our problem
533 * here. So if the host bridge supports it, we do it.
535 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
538 if (!(rp->flags & IORESOURCE_IO))
540 if (offset < rp->start || (offset + size) > rp->end)
542 addr = hose->io_base_virt + port;
544 /* WARNING: The generic code is idiotic. It gets passed a pointer
545 * to what can be a 1, 2 or 4 byte quantity and always reads that
546 * as a u32, which means that we have to correct the location of
547 * the data read within those 32 bits for size 1 and 2
551 out_8(addr, val >> 24);
556 out_le16(addr, val >> 16);
567 /* This provides legacy IO or memory mmap access on a bus */
568 int pci_mmap_legacy_page_range(struct pci_bus *bus,
569 struct vm_area_struct *vma,
570 enum pci_mmap_state mmap_state)
572 struct pci_controller *hose = pci_bus_to_host(bus);
573 resource_size_t offset =
574 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
575 resource_size_t size = vma->vm_end - vma->vm_start;
578 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
579 pci_domain_nr(bus), bus->number,
580 mmap_state == pci_mmap_mem ? "MEM" : "IO",
581 (unsigned long long)offset,
582 (unsigned long long)(offset + size - 1));
584 if (mmap_state == pci_mmap_mem) {
587 * Because X is lame and can fail starting if it gets an error trying
588 * to mmap legacy_mem (instead of just moving on without legacy memory
589 * access) we fake it here by giving it anonymous memory, effectively
590 * behaving just like /dev/zero
592 if ((offset + size) > hose->isa_mem_size) {
594 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
595 current->comm, current->pid, pci_domain_nr(bus), bus->number);
596 if (vma->vm_flags & VM_SHARED)
597 return shmem_zero_setup(vma);
600 offset += hose->isa_mem_phys;
602 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
603 unsigned long roffset = offset + io_offset;
604 rp = &hose->io_resource;
605 if (!(rp->flags & IORESOURCE_IO))
607 if (roffset < rp->start || (roffset + size) > rp->end)
609 offset += hose->io_base_phys;
611 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
613 vma->vm_pgoff = offset >> PAGE_SHIFT;
614 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
615 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
616 vma->vm_end - vma->vm_start,
620 void pci_resource_to_user(const struct pci_dev *dev, int bar,
621 const struct resource *rsrc,
622 resource_size_t *start, resource_size_t *end)
624 struct pci_bus_region region;
626 if (rsrc->flags & IORESOURCE_IO) {
627 pcibios_resource_to_bus(dev->bus, ®ion,
628 (struct resource *) rsrc);
629 *start = region.start;
634 /* We pass a CPU physical address to userland for MMIO instead of a
635 * BAR value because X is lame and expects to be able to use that
636 * to pass to /dev/mem!
638 * That means we may have 64-bit values where some apps only expect
639 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
641 *start = rsrc->start;
646 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
647 * @hose: newly allocated pci_controller to be setup
648 * @dev: device node of the host bridge
649 * @primary: set if primary bus (32 bits only, soon to be deprecated)
651 * This function will parse the "ranges" property of a PCI host bridge device
652 * node and setup the resource mapping of a pci controller based on its
655 * Life would be boring if it wasn't for a few issues that we have to deal
658 * - We can only cope with one IO space range and up to 3 Memory space
659 * ranges. However, some machines (thanks Apple !) tend to split their
660 * space into lots of small contiguous ranges. So we have to coalesce.
662 * - Some busses have IO space not starting at 0, which causes trouble with
663 * the way we do our IO resource renumbering. The code somewhat deals with
664 * it for 64 bits but I would expect problems on 32 bits.
666 * - Some 32 bits platforms such as 4xx can have physical space larger than
667 * 32 bits so we need to use 64 bits values for the parsing
669 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
670 struct device_node *dev, int primary)
673 struct resource *res;
674 struct of_pci_range range;
675 struct of_pci_range_parser parser;
677 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
678 dev, primary ? "(primary)" : "");
680 /* Check for ranges property */
681 if (of_pci_range_parser_init(&parser, dev))
685 for_each_of_pci_range(&parser, &range) {
686 /* If we failed translation or got a zero-sized region
687 * (some FW try to feed us with non sensical zero sized regions
688 * such as power3 which look like some kind of attempt at exposing
689 * the VGA memory hole)
691 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
694 /* Act based on address space type */
696 switch (range.flags & IORESOURCE_TYPE_BITS) {
699 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
700 range.cpu_addr, range.cpu_addr + range.size - 1,
703 /* We support only one IO range */
704 if (hose->pci_io_size) {
706 " \\--> Skipped (too many) !\n");
710 /* On 32 bits, limit I/O space to 16MB */
711 if (range.size > 0x01000000)
712 range.size = 0x01000000;
714 /* 32 bits needs to map IOs here */
715 hose->io_base_virt = ioremap(range.cpu_addr,
718 /* Expect trouble if pci_addr is not 0 */
721 (unsigned long)hose->io_base_virt;
722 #endif /* CONFIG_PPC32 */
723 /* pci_io_size and io_base_phys always represent IO
724 * space starting at 0 so we factor in pci_addr
726 hose->pci_io_size = range.pci_addr + range.size;
727 hose->io_base_phys = range.cpu_addr - range.pci_addr;
730 res = &hose->io_resource;
731 range.cpu_addr = range.pci_addr;
735 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
736 range.cpu_addr, range.cpu_addr + range.size - 1,
738 (range.pci_space & 0x40000000) ?
741 /* We support only 3 memory ranges */
744 " \\--> Skipped (too many) !\n");
747 /* Handles ISA memory hole space here */
748 if (range.pci_addr == 0) {
749 if (primary || isa_mem_base == 0)
750 isa_mem_base = range.cpu_addr;
751 hose->isa_mem_phys = range.cpu_addr;
752 hose->isa_mem_size = range.size;
756 hose->mem_offset[memno] = range.cpu_addr -
758 res = &hose->mem_resources[memno++];
762 res->name = dev->full_name;
763 res->flags = range.flags;
764 res->start = range.cpu_addr;
765 res->end = range.cpu_addr + range.size - 1;
766 res->parent = res->child = res->sibling = NULL;
771 /* Decide whether to display the domain number in /proc */
772 int pci_proc_domain(struct pci_bus *bus)
774 struct pci_controller *hose = pci_bus_to_host(bus);
776 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
778 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
779 return hose->global_number != 0;
783 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
785 if (ppc_md.pcibios_root_bridge_prepare)
786 return ppc_md.pcibios_root_bridge_prepare(bridge);
791 /* This header fixup will do the resource fixup for all devices as they are
792 * probed, but not for bridge ranges
794 static void pcibios_fixup_resources(struct pci_dev *dev)
796 struct pci_controller *hose = pci_bus_to_host(dev->bus);
800 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
808 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
809 struct resource *res = dev->resource + i;
810 struct pci_bus_region reg;
814 /* If we're going to re-assign everything, we mark all resources
815 * as unset (and 0-base them). In addition, we mark BARs starting
816 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
817 * since in that case, we don't want to re-assign anything
819 pcibios_resource_to_bus(dev->bus, ®, res);
820 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
821 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
822 /* Only print message if not re-assigning */
823 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
824 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
825 pci_name(dev), i, res);
826 res->end -= res->start;
828 res->flags |= IORESOURCE_UNSET;
832 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
835 /* Call machine specific resource fixup */
836 if (ppc_md.pcibios_fixup_resources)
837 ppc_md.pcibios_fixup_resources(dev);
839 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
841 /* This function tries to figure out if a bridge resource has been initialized
842 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
843 * things go more smoothly when it gets it right. It should covers cases such
844 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
846 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
847 struct resource *res)
849 struct pci_controller *hose = pci_bus_to_host(bus);
850 struct pci_dev *dev = bus->self;
851 resource_size_t offset;
852 struct pci_bus_region region;
856 /* We don't do anything if PCI_PROBE_ONLY is set */
857 if (pci_has_flag(PCI_PROBE_ONLY))
860 /* Job is a bit different between memory and IO */
861 if (res->flags & IORESOURCE_MEM) {
862 pcibios_resource_to_bus(dev->bus, ®ion, res);
864 /* If the BAR is non-0 then it's probably been initialized */
865 if (region.start != 0)
868 /* The BAR is 0, let's check if memory decoding is enabled on
869 * the bridge. If not, we consider it unassigned
871 pci_read_config_word(dev, PCI_COMMAND, &command);
872 if ((command & PCI_COMMAND_MEMORY) == 0)
875 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
876 * resources covers that starting address (0 then it's good enough for
877 * us for memory space)
879 for (i = 0; i < 3; i++) {
880 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
881 hose->mem_resources[i].start == hose->mem_offset[i])
885 /* Well, it starts at 0 and we know it will collide so we may as
886 * well consider it as unassigned. That covers the Apple case.
890 /* If the BAR is non-0, then we consider it assigned */
891 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
892 if (((res->start - offset) & 0xfffffffful) != 0)
895 /* Here, we are a bit different than memory as typically IO space
896 * starting at low addresses -is- valid. What we do instead if that
897 * we consider as unassigned anything that doesn't have IO enabled
898 * in the PCI command register, and that's it.
900 pci_read_config_word(dev, PCI_COMMAND, &command);
901 if (command & PCI_COMMAND_IO)
904 /* It's starting at 0 and IO is disabled in the bridge, consider
911 /* Fixup resources of a PCI<->PCI bridge */
912 static void pcibios_fixup_bridge(struct pci_bus *bus)
914 struct resource *res;
917 struct pci_dev *dev = bus->self;
919 pci_bus_for_each_resource(bus, res, i) {
920 if (!res || !res->flags)
922 if (i >= 3 && bus->self->transparent)
925 /* If we're going to reassign everything, we can
926 * shrink the P2P resource to have size as being
927 * of 0 in order to save space.
929 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
930 res->flags |= IORESOURCE_UNSET;
936 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
938 /* Try to detect uninitialized P2P bridge resources,
939 * and clear them out so they get re-assigned later
941 if (pcibios_uninitialized_bridge_resource(bus, res)) {
943 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
948 void pcibios_setup_bus_self(struct pci_bus *bus)
950 struct pci_controller *phb;
952 /* Fix up the bus resources for P2P bridges */
953 if (bus->self != NULL)
954 pcibios_fixup_bridge(bus);
956 /* Platform specific bus fixups. This is currently only used
957 * by fsl_pci and I'm hoping to get rid of it at some point
959 if (ppc_md.pcibios_fixup_bus)
960 ppc_md.pcibios_fixup_bus(bus);
962 /* Setup bus DMA mappings */
963 phb = pci_bus_to_host(bus);
964 if (phb->controller_ops.dma_bus_setup)
965 phb->controller_ops.dma_bus_setup(bus);
968 static void pcibios_setup_device(struct pci_dev *dev)
970 struct pci_controller *phb;
971 /* Fixup NUMA node as it may not be setup yet by the generic
972 * code and is needed by the DMA init
974 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
976 /* Hook up default DMA ops */
977 set_dma_ops(&dev->dev, pci_dma_ops);
978 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
980 /* Additional platform DMA/iommu setup */
981 phb = pci_bus_to_host(dev->bus);
982 if (phb->controller_ops.dma_dev_setup)
983 phb->controller_ops.dma_dev_setup(dev);
985 /* Read default IRQs and fixup if necessary */
986 pci_read_irq_line(dev);
987 if (ppc_md.pci_irq_fixup)
988 ppc_md.pci_irq_fixup(dev);
991 int pcibios_add_device(struct pci_dev *dev)
994 * We can only call pcibios_setup_device() after bus setup is complete,
995 * since some of the platform specific DMA setup code depends on it.
997 if (dev->bus->is_added)
998 pcibios_setup_device(dev);
1000 #ifdef CONFIG_PCI_IOV
1001 if (ppc_md.pcibios_fixup_sriov)
1002 ppc_md.pcibios_fixup_sriov(dev);
1003 #endif /* CONFIG_PCI_IOV */
1008 void pcibios_setup_bus_devices(struct pci_bus *bus)
1010 struct pci_dev *dev;
1012 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1013 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1015 list_for_each_entry(dev, &bus->devices, bus_list) {
1016 /* Cardbus can call us to add new devices to a bus, so ignore
1017 * those who are already fully discovered
1019 if (pci_dev_is_added(dev))
1022 pcibios_setup_device(dev);
1026 void pcibios_set_master(struct pci_dev *dev)
1028 /* No special bus mastering setup handling */
1031 void pcibios_fixup_bus(struct pci_bus *bus)
1033 /* When called from the generic PCI probe, read PCI<->PCI bridge
1034 * bases. This is -not- called when generating the PCI tree from
1035 * the OF device-tree.
1037 pci_read_bridge_bases(bus);
1039 /* Now fixup the bus bus */
1040 pcibios_setup_bus_self(bus);
1042 /* Now fixup devices on that bus */
1043 pcibios_setup_bus_devices(bus);
1045 EXPORT_SYMBOL(pcibios_fixup_bus);
1047 void pci_fixup_cardbus(struct pci_bus *bus)
1049 /* Now fixup devices on that bus */
1050 pcibios_setup_bus_devices(bus);
1054 static int skip_isa_ioresource_align(struct pci_dev *dev)
1056 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1057 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1063 * We need to avoid collisions with `mirrored' VGA ports
1064 * and other strange ISA hardware, so we always want the
1065 * addresses to be allocated in the 0x000-0x0ff region
1068 * Why? Because some silly external IO cards only decode
1069 * the low 10 bits of the IO address. The 0x00-0xff region
1070 * is reserved for motherboard devices that decode all 16
1071 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1072 * but we want to try to avoid allocating at 0x2900-0x2bff
1073 * which might have be mirrored at 0x0100-0x03ff..
1075 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1076 resource_size_t size, resource_size_t align)
1078 struct pci_dev *dev = data;
1079 resource_size_t start = res->start;
1081 if (res->flags & IORESOURCE_IO) {
1082 if (skip_isa_ioresource_align(dev))
1085 start = (start + 0x3ff) & ~0x3ff;
1090 EXPORT_SYMBOL(pcibios_align_resource);
1093 * Reparent resource children of pr that conflict with res
1094 * under res, and make res replace those children.
1096 static int reparent_resources(struct resource *parent,
1097 struct resource *res)
1099 struct resource *p, **pp;
1100 struct resource **firstpp = NULL;
1102 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1103 if (p->end < res->start)
1105 if (res->end < p->start)
1107 if (p->start < res->start || p->end > res->end)
1108 return -1; /* not completely contained */
1109 if (firstpp == NULL)
1112 if (firstpp == NULL)
1113 return -1; /* didn't find any conflicting entries? */
1114 res->parent = parent;
1115 res->child = *firstpp;
1119 for (p = res->child; p != NULL; p = p->sibling) {
1121 pr_debug("PCI: Reparented %s %pR under %s\n",
1122 p->name, p, res->name);
1128 * Handle resources of PCI devices. If the world were perfect, we could
1129 * just allocate all the resource regions and do nothing more. It isn't.
1130 * On the other hand, we cannot just re-allocate all devices, as it would
1131 * require us to know lots of host bridge internals. So we attempt to
1132 * keep as much of the original configuration as possible, but tweak it
1133 * when it's found to be wrong.
1135 * Known BIOS problems we have to work around:
1136 * - I/O or memory regions not configured
1137 * - regions configured, but not enabled in the command register
1138 * - bogus I/O addresses above 64K used
1139 * - expansion ROMs left enabled (this may sound harmless, but given
1140 * the fact the PCI specs explicitly allow address decoders to be
1141 * shared between expansion ROMs and other resource regions, it's
1142 * at least dangerous)
1145 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1146 * This gives us fixed barriers on where we can allocate.
1147 * (2) Allocate resources for all enabled devices. If there is
1148 * a collision, just mark the resource as unallocated. Also
1149 * disable expansion ROMs during this step.
1150 * (3) Try to allocate resources for disabled devices. If the
1151 * resources were assigned correctly, everything goes well,
1152 * if they weren't, they won't disturb allocation of other
1154 * (4) Assign new addresses to resources which were either
1155 * not configured at all or misconfigured. If explicitly
1156 * requested by the user, configure expansion ROM address
1160 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1164 struct resource *res, *pr;
1166 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1167 pci_domain_nr(bus), bus->number);
1169 pci_bus_for_each_resource(bus, res, i) {
1170 if (!res || !res->flags || res->start > res->end || res->parent)
1173 /* If the resource was left unset at this point, we clear it */
1174 if (res->flags & IORESOURCE_UNSET)
1175 goto clear_resource;
1177 if (bus->parent == NULL)
1178 pr = (res->flags & IORESOURCE_IO) ?
1179 &ioport_resource : &iomem_resource;
1181 pr = pci_find_parent_resource(bus->self, res);
1183 /* this happens when the generic PCI
1184 * code (wrongly) decides that this
1185 * bridge is transparent -- paulus
1191 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1192 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1193 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1195 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1196 struct pci_dev *dev = bus->self;
1198 if (request_resource(pr, res) == 0)
1201 * Must be a conflict with an existing entry.
1202 * Move that entry (or entries) under the
1203 * bridge resource and try again.
1205 if (reparent_resources(pr, res) == 0)
1208 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1209 pci_claim_bridge_resource(dev,
1210 i + PCI_BRIDGE_RESOURCES) == 0)
1213 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1216 /* The resource might be figured out when doing
1217 * reassignment based on the resources required
1218 * by the downstream PCI devices. Here we set
1219 * the size of the resource to be 0 in order to
1227 list_for_each_entry(b, &bus->children, node)
1228 pcibios_allocate_bus_resources(b);
1231 static inline void alloc_resource(struct pci_dev *dev, int idx)
1233 struct resource *pr, *r = &dev->resource[idx];
1235 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1236 pci_name(dev), idx, r);
1238 pr = pci_find_parent_resource(dev, r);
1239 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1240 request_resource(pr, r) < 0) {
1241 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1242 " of device %s, will remap\n", idx, pci_name(dev));
1244 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1245 /* We'll assign a new address later */
1246 r->flags |= IORESOURCE_UNSET;
1252 static void __init pcibios_allocate_resources(int pass)
1254 struct pci_dev *dev = NULL;
1259 for_each_pci_dev(dev) {
1260 pci_read_config_word(dev, PCI_COMMAND, &command);
1261 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1262 r = &dev->resource[idx];
1263 if (r->parent) /* Already allocated */
1265 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1266 continue; /* Not assigned at all */
1267 /* We only allocate ROMs on pass 1 just in case they
1268 * have been screwed up by firmware
1270 if (idx == PCI_ROM_RESOURCE )
1272 if (r->flags & IORESOURCE_IO)
1273 disabled = !(command & PCI_COMMAND_IO);
1275 disabled = !(command & PCI_COMMAND_MEMORY);
1276 if (pass == disabled)
1277 alloc_resource(dev, idx);
1281 r = &dev->resource[PCI_ROM_RESOURCE];
1283 /* Turn the ROM off, leave the resource region,
1284 * but keep it unregistered.
1287 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1288 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1289 pr_debug("PCI: Switching off ROM of %s\n",
1291 r->flags &= ~IORESOURCE_ROM_ENABLE;
1292 pci_write_config_dword(dev, dev->rom_base_reg,
1293 reg & ~PCI_ROM_ADDRESS_ENABLE);
1299 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1301 struct pci_controller *hose = pci_bus_to_host(bus);
1302 resource_size_t offset;
1303 struct resource *res, *pres;
1306 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1309 if (!(hose->io_resource.flags & IORESOURCE_IO))
1311 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1312 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1313 BUG_ON(res == NULL);
1314 res->name = "Legacy IO";
1315 res->flags = IORESOURCE_IO;
1316 res->start = offset;
1317 res->end = (offset + 0xfff) & 0xfffffffful;
1318 pr_debug("Candidate legacy IO: %pR\n", res);
1319 if (request_resource(&hose->io_resource, res)) {
1321 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1322 pci_domain_nr(bus), bus->number, res);
1327 /* Check for memory */
1328 for (i = 0; i < 3; i++) {
1329 pres = &hose->mem_resources[i];
1330 offset = hose->mem_offset[i];
1331 if (!(pres->flags & IORESOURCE_MEM))
1333 pr_debug("hose mem res: %pR\n", pres);
1334 if ((pres->start - offset) <= 0xa0000 &&
1335 (pres->end - offset) >= 0xbffff)
1340 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1341 BUG_ON(res == NULL);
1342 res->name = "Legacy VGA memory";
1343 res->flags = IORESOURCE_MEM;
1344 res->start = 0xa0000 + offset;
1345 res->end = 0xbffff + offset;
1346 pr_debug("Candidate VGA memory: %pR\n", res);
1347 if (request_resource(pres, res)) {
1349 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1350 pci_domain_nr(bus), bus->number, res);
1355 void __init pcibios_resource_survey(void)
1359 /* Allocate and assign resources */
1360 list_for_each_entry(b, &pci_root_buses, node)
1361 pcibios_allocate_bus_resources(b);
1362 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1363 pcibios_allocate_resources(0);
1364 pcibios_allocate_resources(1);
1367 /* Before we start assigning unassigned resource, we try to reserve
1368 * the low IO area and the VGA memory area if they intersect the
1369 * bus available resources to avoid allocating things on top of them
1371 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1372 list_for_each_entry(b, &pci_root_buses, node)
1373 pcibios_reserve_legacy_regions(b);
1376 /* Now, if the platform didn't decide to blindly trust the firmware,
1377 * we proceed to assigning things that were left unassigned
1379 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1380 pr_debug("PCI: Assigning unassigned resources...\n");
1381 pci_assign_unassigned_resources();
1384 /* Call machine dependent fixup */
1385 if (ppc_md.pcibios_fixup)
1386 ppc_md.pcibios_fixup();
1389 /* This is used by the PCI hotplug driver to allocate resource
1390 * of newly plugged busses. We can try to consolidate with the
1391 * rest of the code later, for now, keep it as-is as our main
1392 * resource allocation function doesn't deal with sub-trees yet.
1394 void pcibios_claim_one_bus(struct pci_bus *bus)
1396 struct pci_dev *dev;
1397 struct pci_bus *child_bus;
1399 list_for_each_entry(dev, &bus->devices, bus_list) {
1402 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1403 struct resource *r = &dev->resource[i];
1405 if (r->parent || !r->start || !r->flags)
1408 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1409 pci_name(dev), i, r);
1411 if (pci_claim_resource(dev, i) == 0)
1414 pci_claim_bridge_resource(dev, i);
1418 list_for_each_entry(child_bus, &bus->children, node)
1419 pcibios_claim_one_bus(child_bus);
1421 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1424 /* pcibios_finish_adding_to_bus
1426 * This is to be called by the hotplug code after devices have been
1427 * added to a bus, this include calling it for a PHB that is just
1430 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1432 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1433 pci_domain_nr(bus), bus->number);
1435 /* Allocate bus and devices resources */
1436 pcibios_allocate_bus_resources(bus);
1437 pcibios_claim_one_bus(bus);
1438 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1440 pci_assign_unassigned_bridge_resources(bus->self);
1442 pci_assign_unassigned_bus_resources(bus);
1446 eeh_add_device_tree_late(bus);
1448 /* Add new devices to global lists. Register in proc, sysfs. */
1449 pci_bus_add_devices(bus);
1451 /* sysfs files should only be added after devices are added */
1452 eeh_add_sysfs_files(bus);
1454 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1456 int pcibios_enable_device(struct pci_dev *dev, int mask)
1458 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1460 if (phb->controller_ops.enable_device_hook)
1461 if (!phb->controller_ops.enable_device_hook(dev))
1464 return pci_enable_resources(dev, mask);
1467 void pcibios_disable_device(struct pci_dev *dev)
1469 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1471 if (phb->controller_ops.disable_device)
1472 phb->controller_ops.disable_device(dev);
1475 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1477 return (unsigned long) hose->io_base_virt - _IO_BASE;
1480 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1481 struct list_head *resources)
1483 struct resource *res;
1484 resource_size_t offset;
1487 /* Hookup PHB IO resource */
1488 res = &hose->io_resource;
1491 pr_debug("PCI: I/O resource not set for host"
1492 " bridge %pOF (domain %d)\n",
1493 hose->dn, hose->global_number);
1495 offset = pcibios_io_space_offset(hose);
1497 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1498 res, (unsigned long long)offset);
1499 pci_add_resource_offset(resources, res, offset);
1502 /* Hookup PHB Memory resources */
1503 for (i = 0; i < 3; ++i) {
1504 res = &hose->mem_resources[i];
1508 offset = hose->mem_offset[i];
1509 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1510 res, (unsigned long long)offset);
1512 pci_add_resource_offset(resources, res, offset);
1517 * Null PCI config access functions, for the case when we can't
1520 #define NULL_PCI_OP(rw, size, type) \
1522 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1524 return PCIBIOS_DEVICE_NOT_FOUND; \
1528 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1531 return PCIBIOS_DEVICE_NOT_FOUND;
1535 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1538 return PCIBIOS_DEVICE_NOT_FOUND;
1541 static struct pci_ops null_pci_ops =
1543 .read = null_read_config,
1544 .write = null_write_config,
1548 * These functions are used early on before PCI scanning is done
1549 * and all of the pci_dev and pci_bus structures have been created.
1551 static struct pci_bus *
1552 fake_pci_bus(struct pci_controller *hose, int busnr)
1554 static struct pci_bus bus;
1557 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1561 bus.ops = hose? hose->ops: &null_pci_ops;
1565 #define EARLY_PCI_OP(rw, size, type) \
1566 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1567 int devfn, int offset, type value) \
1569 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1570 devfn, offset, value); \
1573 EARLY_PCI_OP(read, byte, u8 *)
1574 EARLY_PCI_OP(read, word, u16 *)
1575 EARLY_PCI_OP(read, dword, u32 *)
1576 EARLY_PCI_OP(write, byte, u8)
1577 EARLY_PCI_OP(write, word, u16)
1578 EARLY_PCI_OP(write, dword, u32)
1580 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1583 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1586 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1588 struct pci_controller *hose = bus->sysdata;
1590 return of_node_get(hose->dn);
1594 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1595 * @hose: Pointer to the PCI host controller instance structure
1597 void pcibios_scan_phb(struct pci_controller *hose)
1599 LIST_HEAD(resources);
1600 struct pci_bus *bus;
1601 struct device_node *node = hose->dn;
1604 pr_debug("PCI: Scanning PHB %pOF\n", node);
1606 /* Get some IO space for the new PHB */
1607 pcibios_setup_phb_io_space(hose);
1609 /* Wire up PHB bus resources */
1610 pcibios_setup_phb_resources(hose, &resources);
1612 hose->busn.start = hose->first_busno;
1613 hose->busn.end = hose->last_busno;
1614 hose->busn.flags = IORESOURCE_BUS;
1615 pci_add_resource(&resources, &hose->busn);
1617 /* Create an empty bus for the toplevel */
1618 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1619 hose->ops, hose, &resources);
1621 pr_err("Failed to create bus for PCI domain %04x\n",
1622 hose->global_number);
1623 pci_free_resource_list(&resources);
1628 /* Get probe mode and perform scan */
1629 mode = PCI_PROBE_NORMAL;
1630 if (node && hose->controller_ops.probe_mode)
1631 mode = hose->controller_ops.probe_mode(bus);
1632 pr_debug(" probe mode: %d\n", mode);
1633 if (mode == PCI_PROBE_DEVTREE)
1634 of_scan_bus(node, bus);
1636 if (mode == PCI_PROBE_NORMAL) {
1637 pci_bus_update_busn_res_end(bus, 255);
1638 hose->last_busno = pci_scan_child_bus(bus);
1639 pci_bus_update_busn_res_end(bus, hose->last_busno);
1642 /* Platform gets a chance to do some global fixups before
1643 * we proceed to resource allocation
1645 if (ppc_md.pcibios_fixup_phb)
1646 ppc_md.pcibios_fixup_phb(hose);
1648 /* Configure PCI Express settings */
1649 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1650 struct pci_bus *child;
1651 list_for_each_entry(child, &bus->children, node)
1652 pcie_bus_configure_settings(child);
1655 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1657 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1659 int i, class = dev->class >> 8;
1660 /* When configured as agent, programing interface = 1 */
1661 int prog_if = dev->class & 0xf;
1663 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1664 class == PCI_CLASS_BRIDGE_OTHER) &&
1665 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1667 (dev->bus->parent == NULL)) {
1668 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1669 dev->resource[i].start = 0;
1670 dev->resource[i].end = 0;
1671 dev->resource[i].flags = 0;
1675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1676 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);