2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
82 int nid = of_node_to_nid(dev);
84 if (nid < 0 || !node_online(nid))
87 PHB_SET_NODE(phb, nid);
93 void pcibios_free_controller(struct pci_controller *phb)
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
104 * The function is used to return the minimal alignment
105 * for memory or I/O windows of the associated P2P bridge.
106 * By default, 4KiB alignment for I/O windows and 1MiB for
109 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
112 if (ppc_md.pcibios_window_alignment)
113 return ppc_md.pcibios_window_alignment(bus, type);
116 * PCI core will figure out the default
117 * alignment: 4KiB for I/O and 1MiB for
123 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
126 return hose->pci_io_size;
128 return resource_size(&hose->io_resource);
132 int pcibios_vaddr_is_ioport(void __iomem *address)
135 struct pci_controller *hose;
136 resource_size_t size;
138 spin_lock(&hose_spinlock);
139 list_for_each_entry(hose, &hose_list, list_node) {
140 size = pcibios_io_size(hose);
141 if (address >= hose->io_base_virt &&
142 address < (hose->io_base_virt + size)) {
147 spin_unlock(&hose_spinlock);
151 unsigned long pci_address_to_pio(phys_addr_t address)
153 struct pci_controller *hose;
154 resource_size_t size;
155 unsigned long ret = ~0;
157 spin_lock(&hose_spinlock);
158 list_for_each_entry(hose, &hose_list, list_node) {
159 size = pcibios_io_size(hose);
160 if (address >= hose->io_base_phys &&
161 address < (hose->io_base_phys + size)) {
163 (unsigned long)hose->io_base_virt - _IO_BASE;
164 ret = base + (address - hose->io_base_phys);
168 spin_unlock(&hose_spinlock);
172 EXPORT_SYMBOL_GPL(pci_address_to_pio);
175 * Return the domain number for this bus.
177 int pci_domain_nr(struct pci_bus *bus)
179 struct pci_controller *hose = pci_bus_to_host(bus);
181 return hose->global_number;
183 EXPORT_SYMBOL(pci_domain_nr);
185 /* This routine is meant to be used early during boot, when the
186 * PCI bus numbers have not yet been assigned, and you need to
187 * issue PCI config cycles to an OF device.
188 * It could also be used to "fix" RTAS config cycles if you want
189 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
192 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
195 struct pci_controller *hose, *tmp;
196 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
197 if (hose->dn == node)
204 static ssize_t pci_show_devspec(struct device *dev,
205 struct device_attribute *attr, char *buf)
207 struct pci_dev *pdev;
208 struct device_node *np;
210 pdev = to_pci_dev (dev);
211 np = pci_device_to_OF_node(pdev);
212 if (np == NULL || np->full_name == NULL)
214 return sprintf(buf, "%s", np->full_name);
216 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
218 /* Add sysfs properties */
219 int pcibios_add_platform_entries(struct pci_dev *pdev)
221 return device_create_file(&pdev->dev, &dev_attr_devspec);
225 * Reads the interrupt pin to determine if interrupt is use by card.
226 * If the interrupt is used, then gets the interrupt line from the
227 * openfirmware and sets it in the pci_dev and pci_config line.
229 static int pci_read_irq_line(struct pci_dev *pci_dev)
234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
237 memset(&oirq, 0xff, sizeof(oirq));
239 /* Try to get a mapping from the device-tree */
240 if (of_irq_map_pci(pci_dev, &oirq)) {
243 /* If that fails, lets fallback to what is in the config
244 * space and map that through the default controller. We
245 * also set the type to level low since that's what PCI
246 * interrupts are. If your platform does differently, then
247 * either provide a proper interrupt tree or don't use this
250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
255 line == 0xff || line == 0) {
258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
261 virq = irq_create_mapping(NULL, line);
263 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
266 oirq.size, oirq.specifier[0], oirq.specifier[1],
267 of_node_full_name(oirq.controller));
269 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
273 pr_debug(" Failed to map !\n");
277 pr_debug(" Mapped to linux irq %d\n", virq);
285 * Platform support for /proc/bus/pci/X/Y mmap()s,
286 * modelled on the sparc64 implementation by Dave Miller.
291 * Adjust vm_pgoff of VMA such that it is the physical page offset
292 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
294 * Basically, the user finds the base address for his device which he wishes
295 * to mmap. They read the 32-bit value from the config space base register,
296 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
297 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
299 * Returns negative error code on failure, zero on success.
301 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
302 resource_size_t *offset,
303 enum pci_mmap_state mmap_state)
305 struct pci_controller *hose = pci_bus_to_host(dev->bus);
306 unsigned long io_offset = 0;
310 return NULL; /* should never happen */
312 /* If memory, add on the PCI bridge address offset */
313 if (mmap_state == pci_mmap_mem) {
314 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
315 *offset += hose->pci_mem_offset;
317 res_bit = IORESOURCE_MEM;
319 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
320 *offset += io_offset;
321 res_bit = IORESOURCE_IO;
325 * Check that the offset requested corresponds to one of the
326 * resources of the device.
328 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
329 struct resource *rp = &dev->resource[i];
330 int flags = rp->flags;
332 /* treat ROM as memory (should be already) */
333 if (i == PCI_ROM_RESOURCE)
334 flags |= IORESOURCE_MEM;
336 /* Active and same type? */
337 if ((flags & res_bit) == 0)
340 /* In the range of this resource? */
341 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
344 /* found it! construct the final physical address */
345 if (mmap_state == pci_mmap_io)
346 *offset += hose->io_base_phys - io_offset;
354 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
357 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
359 enum pci_mmap_state mmap_state,
362 unsigned long prot = pgprot_val(protection);
364 /* Write combine is always 0 on non-memory space mappings. On
365 * memory space, if the user didn't pass 1, we check for a
366 * "prefetchable" resource. This is a bit hackish, but we use
367 * this to workaround the inability of /sysfs to provide a write
370 if (mmap_state != pci_mmap_mem)
372 else if (write_combine == 0) {
373 if (rp->flags & IORESOURCE_PREFETCH)
377 /* XXX would be nice to have a way to ask for write-through */
379 return pgprot_noncached_wc(prot);
381 return pgprot_noncached(prot);
385 * This one is used by /dev/mem and fbdev who have no clue about the
386 * PCI device, it tries to find the PCI device first and calls the
389 pgprot_t pci_phys_mem_access_prot(struct file *file,
394 struct pci_dev *pdev = NULL;
395 struct resource *found = NULL;
396 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
399 if (page_is_ram(pfn))
402 prot = pgprot_noncached(prot);
403 for_each_pci_dev(pdev) {
404 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
405 struct resource *rp = &pdev->resource[i];
406 int flags = rp->flags;
408 /* Active and same type? */
409 if ((flags & IORESOURCE_MEM) == 0)
411 /* In the range of this resource? */
412 if (offset < (rp->start & PAGE_MASK) ||
422 if (found->flags & IORESOURCE_PREFETCH)
423 prot = pgprot_noncached_wc(prot);
427 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
428 (unsigned long long)offset, pgprot_val(prot));
435 * Perform the actual remap of the pages for a PCI device mapping, as
436 * appropriate for this architecture. The region in the process to map
437 * is described by vm_start and vm_end members of VMA, the base physical
438 * address is found in vm_pgoff.
439 * The pci device structure is provided so that architectures may make mapping
440 * decisions on a per-device or per-bus basis.
442 * Returns a negative error code on failure, zero on success.
444 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
445 enum pci_mmap_state mmap_state, int write_combine)
447 resource_size_t offset =
448 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
452 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
456 vma->vm_pgoff = offset >> PAGE_SHIFT;
457 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
459 mmap_state, write_combine);
461 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
462 vma->vm_end - vma->vm_start, vma->vm_page_prot);
467 /* This provides legacy IO read access on a bus */
468 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
470 unsigned long offset;
471 struct pci_controller *hose = pci_bus_to_host(bus);
472 struct resource *rp = &hose->io_resource;
475 /* Check if port can be supported by that bus. We only check
476 * the ranges of the PHB though, not the bus itself as the rules
477 * for forwarding legacy cycles down bridges are not our problem
478 * here. So if the host bridge supports it, we do it.
480 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
483 if (!(rp->flags & IORESOURCE_IO))
485 if (offset < rp->start || (offset + size) > rp->end)
487 addr = hose->io_base_virt + port;
491 *((u8 *)val) = in_8(addr);
496 *((u16 *)val) = in_le16(addr);
501 *((u32 *)val) = in_le32(addr);
507 /* This provides legacy IO write access on a bus */
508 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
510 unsigned long offset;
511 struct pci_controller *hose = pci_bus_to_host(bus);
512 struct resource *rp = &hose->io_resource;
515 /* Check if port can be supported by that bus. We only check
516 * the ranges of the PHB though, not the bus itself as the rules
517 * for forwarding legacy cycles down bridges are not our problem
518 * here. So if the host bridge supports it, we do it.
520 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
523 if (!(rp->flags & IORESOURCE_IO))
525 if (offset < rp->start || (offset + size) > rp->end)
527 addr = hose->io_base_virt + port;
529 /* WARNING: The generic code is idiotic. It gets passed a pointer
530 * to what can be a 1, 2 or 4 byte quantity and always reads that
531 * as a u32, which means that we have to correct the location of
532 * the data read within those 32 bits for size 1 and 2
536 out_8(addr, val >> 24);
541 out_le16(addr, val >> 16);
552 /* This provides legacy IO or memory mmap access on a bus */
553 int pci_mmap_legacy_page_range(struct pci_bus *bus,
554 struct vm_area_struct *vma,
555 enum pci_mmap_state mmap_state)
557 struct pci_controller *hose = pci_bus_to_host(bus);
558 resource_size_t offset =
559 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
560 resource_size_t size = vma->vm_end - vma->vm_start;
563 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
564 pci_domain_nr(bus), bus->number,
565 mmap_state == pci_mmap_mem ? "MEM" : "IO",
566 (unsigned long long)offset,
567 (unsigned long long)(offset + size - 1));
569 if (mmap_state == pci_mmap_mem) {
572 * Because X is lame and can fail starting if it gets an error trying
573 * to mmap legacy_mem (instead of just moving on without legacy memory
574 * access) we fake it here by giving it anonymous memory, effectively
575 * behaving just like /dev/zero
577 if ((offset + size) > hose->isa_mem_size) {
579 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
580 current->comm, current->pid, pci_domain_nr(bus), bus->number);
581 if (vma->vm_flags & VM_SHARED)
582 return shmem_zero_setup(vma);
585 offset += hose->isa_mem_phys;
587 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
588 unsigned long roffset = offset + io_offset;
589 rp = &hose->io_resource;
590 if (!(rp->flags & IORESOURCE_IO))
592 if (roffset < rp->start || (roffset + size) > rp->end)
594 offset += hose->io_base_phys;
596 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
598 vma->vm_pgoff = offset >> PAGE_SHIFT;
599 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
600 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
601 vma->vm_end - vma->vm_start,
605 void pci_resource_to_user(const struct pci_dev *dev, int bar,
606 const struct resource *rsrc,
607 resource_size_t *start, resource_size_t *end)
609 struct pci_controller *hose = pci_bus_to_host(dev->bus);
610 resource_size_t offset = 0;
615 if (rsrc->flags & IORESOURCE_IO)
616 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
618 /* We pass a fully fixed up address to userland for MMIO instead of
619 * a BAR value because X is lame and expects to be able to use that
620 * to pass to /dev/mem !
622 * That means that we'll have potentially 64 bits values where some
623 * userland apps only expect 32 (like X itself since it thinks only
624 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
627 * Hopefully, the sysfs insterface is immune to that gunk. Once X
628 * has been fixed (and the fix spread enough), we can re-enable the
629 * 2 lines below and pass down a BAR value to userland. In that case
630 * we'll also have to re-enable the matching code in
631 * __pci_mmap_make_offset().
636 else if (rsrc->flags & IORESOURCE_MEM)
637 offset = hose->pci_mem_offset;
640 *start = rsrc->start - offset;
641 *end = rsrc->end - offset;
645 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
646 * @hose: newly allocated pci_controller to be setup
647 * @dev: device node of the host bridge
648 * @primary: set if primary bus (32 bits only, soon to be deprecated)
650 * This function will parse the "ranges" property of a PCI host bridge device
651 * node and setup the resource mapping of a pci controller based on its
654 * Life would be boring if it wasn't for a few issues that we have to deal
657 * - We can only cope with one IO space range and up to 3 Memory space
658 * ranges. However, some machines (thanks Apple !) tend to split their
659 * space into lots of small contiguous ranges. So we have to coalesce.
661 * - We can only cope with all memory ranges having the same offset
662 * between CPU addresses and PCI addresses. Unfortunately, some bridges
663 * are setup for a large 1:1 mapping along with a small "window" which
664 * maps PCI address 0 to some arbitrary high address of the CPU space in
665 * order to give access to the ISA memory hole.
666 * The way out of here that I've chosen for now is to always set the
667 * offset based on the first resource found, then override it if we
668 * have a different offset and the previous was set by an ISA hole.
670 * - Some busses have IO space not starting at 0, which causes trouble with
671 * the way we do our IO resource renumbering. The code somewhat deals with
672 * it for 64 bits but I would expect problems on 32 bits.
674 * - Some 32 bits platforms such as 4xx can have physical space larger than
675 * 32 bits so we need to use 64 bits values for the parsing
677 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
678 struct device_node *dev, int primary)
682 int pna = of_n_addr_cells(dev);
684 int memno = 0, isa_hole = -1;
686 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
687 unsigned long long isa_mb = 0;
688 struct resource *res;
690 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
691 dev->full_name, primary ? "(primary)" : "");
693 /* Get ranges property */
694 ranges = of_get_property(dev, "ranges", &rlen);
699 while ((rlen -= np * 4) >= 0) {
700 /* Read next ranges element */
701 pci_space = ranges[0];
702 pci_addr = of_read_number(ranges + 1, 2);
703 cpu_addr = of_translate_address(dev, ranges + 3);
704 size = of_read_number(ranges + pna + 3, 2);
707 /* If we failed translation or got a zero-sized region
708 * (some FW try to feed us with non sensical zero sized regions
709 * such as power3 which look like some kind of attempt at exposing
710 * the VGA memory hole)
712 if (cpu_addr == OF_BAD_ADDR || size == 0)
715 /* Now consume following elements while they are contiguous */
716 for (; rlen >= np * sizeof(u32);
717 ranges += np, rlen -= np * 4) {
718 if (ranges[0] != pci_space)
720 pci_next = of_read_number(ranges + 1, 2);
721 cpu_next = of_translate_address(dev, ranges + 3);
722 if (pci_next != pci_addr + size ||
723 cpu_next != cpu_addr + size)
725 size += of_read_number(ranges + pna + 3, 2);
728 /* Act based on address space type */
730 switch ((pci_space >> 24) & 0x3) {
731 case 1: /* PCI IO space */
733 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
734 cpu_addr, cpu_addr + size - 1, pci_addr);
736 /* We support only one IO range */
737 if (hose->pci_io_size) {
739 " \\--> Skipped (too many) !\n");
743 /* On 32 bits, limit I/O space to 16MB */
744 if (size > 0x01000000)
747 /* 32 bits needs to map IOs here */
748 hose->io_base_virt = ioremap(cpu_addr, size);
750 /* Expect trouble if pci_addr is not 0 */
753 (unsigned long)hose->io_base_virt;
754 #endif /* CONFIG_PPC32 */
755 /* pci_io_size and io_base_phys always represent IO
756 * space starting at 0 so we factor in pci_addr
758 hose->pci_io_size = pci_addr + size;
759 hose->io_base_phys = cpu_addr - pci_addr;
762 res = &hose->io_resource;
763 res->flags = IORESOURCE_IO;
764 res->start = pci_addr;
766 case 2: /* PCI Memory space */
767 case 3: /* PCI 64 bits Memory space */
769 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
770 cpu_addr, cpu_addr + size - 1, pci_addr,
771 (pci_space & 0x40000000) ? "Prefetch" : "");
773 /* We support only 3 memory ranges */
776 " \\--> Skipped (too many) !\n");
779 /* Handles ISA memory hole space here */
783 if (primary || isa_mem_base == 0)
784 isa_mem_base = cpu_addr;
785 hose->isa_mem_phys = cpu_addr;
786 hose->isa_mem_size = size;
790 hose->mem_offset[memno] = cpu_addr - pci_addr;
791 res = &hose->mem_resources[memno++];
792 res->flags = IORESOURCE_MEM;
793 if (pci_space & 0x40000000)
794 res->flags |= IORESOURCE_PREFETCH;
795 res->start = cpu_addr;
799 res->name = dev->full_name;
800 res->end = res->start + size - 1;
808 /* Decide whether to display the domain number in /proc */
809 int pci_proc_domain(struct pci_bus *bus)
811 struct pci_controller *hose = pci_bus_to_host(bus);
813 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
815 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
816 return hose->global_number != 0;
820 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
822 if (ppc_md.pcibios_root_bridge_prepare)
823 return ppc_md.pcibios_root_bridge_prepare(bridge);
828 /* This header fixup will do the resource fixup for all devices as they are
829 * probed, but not for bridge ranges
831 static void pcibios_fixup_resources(struct pci_dev *dev)
833 struct pci_controller *hose = pci_bus_to_host(dev->bus);
837 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
841 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
842 struct resource *res = dev->resource + i;
846 /* If we're going to re-assign everything, we mark all resources
847 * as unset (and 0-base them). In addition, we mark BARs starting
848 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
849 * since in that case, we don't want to re-assign anything
851 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
852 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
853 /* Only print message if not re-assigning */
854 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
855 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
858 (unsigned long long)res->start,
859 (unsigned long long)res->end,
860 (unsigned int)res->flags);
861 res->end -= res->start;
863 res->flags |= IORESOURCE_UNSET;
867 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
869 (unsigned long long)res->start,\
870 (unsigned long long)res->end,
871 (unsigned int)res->flags);
874 /* Call machine specific resource fixup */
875 if (ppc_md.pcibios_fixup_resources)
876 ppc_md.pcibios_fixup_resources(dev);
878 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
880 /* This function tries to figure out if a bridge resource has been initialized
881 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
882 * things go more smoothly when it gets it right. It should covers cases such
883 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
885 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
886 struct resource *res)
888 struct pci_controller *hose = pci_bus_to_host(bus);
889 struct pci_dev *dev = bus->self;
890 resource_size_t offset;
891 struct pci_bus_region region;
895 /* We don't do anything if PCI_PROBE_ONLY is set */
896 if (pci_has_flag(PCI_PROBE_ONLY))
899 /* Job is a bit different between memory and IO */
900 if (res->flags & IORESOURCE_MEM) {
901 pcibios_resource_to_bus(dev, ®ion, res);
903 /* If the BAR is non-0 then it's probably been initialized */
904 if (region.start != 0)
907 /* The BAR is 0, let's check if memory decoding is enabled on
908 * the bridge. If not, we consider it unassigned
910 pci_read_config_word(dev, PCI_COMMAND, &command);
911 if ((command & PCI_COMMAND_MEMORY) == 0)
914 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
915 * resources covers that starting address (0 then it's good enough for
916 * us for memory space)
918 for (i = 0; i < 3; i++) {
919 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
920 hose->mem_resources[i].start == hose->mem_offset[i])
924 /* Well, it starts at 0 and we know it will collide so we may as
925 * well consider it as unassigned. That covers the Apple case.
929 /* If the BAR is non-0, then we consider it assigned */
930 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
931 if (((res->start - offset) & 0xfffffffful) != 0)
934 /* Here, we are a bit different than memory as typically IO space
935 * starting at low addresses -is- valid. What we do instead if that
936 * we consider as unassigned anything that doesn't have IO enabled
937 * in the PCI command register, and that's it.
939 pci_read_config_word(dev, PCI_COMMAND, &command);
940 if (command & PCI_COMMAND_IO)
943 /* It's starting at 0 and IO is disabled in the bridge, consider
950 /* Fixup resources of a PCI<->PCI bridge */
951 static void pcibios_fixup_bridge(struct pci_bus *bus)
953 struct resource *res;
956 struct pci_dev *dev = bus->self;
958 pci_bus_for_each_resource(bus, res, i) {
959 if (!res || !res->flags)
961 if (i >= 3 && bus->self->transparent)
964 /* If we're going to reassign everything, we can
965 * shrink the P2P resource to have size as being
966 * of 0 in order to save space.
968 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
969 res->flags |= IORESOURCE_UNSET;
975 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
977 (unsigned long long)res->start,\
978 (unsigned long long)res->end,
979 (unsigned int)res->flags);
981 /* Try to detect uninitialized P2P bridge resources,
982 * and clear them out so they get re-assigned later
984 if (pcibios_uninitialized_bridge_resource(bus, res)) {
986 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
991 void pcibios_setup_bus_self(struct pci_bus *bus)
993 /* Fix up the bus resources for P2P bridges */
994 if (bus->self != NULL)
995 pcibios_fixup_bridge(bus);
997 /* Platform specific bus fixups. This is currently only used
998 * by fsl_pci and I'm hoping to get rid of it at some point
1000 if (ppc_md.pcibios_fixup_bus)
1001 ppc_md.pcibios_fixup_bus(bus);
1003 /* Setup bus DMA mappings */
1004 if (ppc_md.pci_dma_bus_setup)
1005 ppc_md.pci_dma_bus_setup(bus);
1008 void pcibios_setup_device(struct pci_dev *dev)
1010 /* Fixup NUMA node as it may not be setup yet by the generic
1011 * code and is needed by the DMA init
1013 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1015 /* Hook up default DMA ops */
1016 set_dma_ops(&dev->dev, pci_dma_ops);
1017 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1019 /* Additional platform DMA/iommu setup */
1020 if (ppc_md.pci_dma_dev_setup)
1021 ppc_md.pci_dma_dev_setup(dev);
1023 /* Read default IRQs and fixup if necessary */
1024 pci_read_irq_line(dev);
1025 if (ppc_md.pci_irq_fixup)
1026 ppc_md.pci_irq_fixup(dev);
1029 void pcibios_setup_bus_devices(struct pci_bus *bus)
1031 struct pci_dev *dev;
1033 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1034 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1036 list_for_each_entry(dev, &bus->devices, bus_list) {
1037 /* Cardbus can call us to add new devices to a bus, so ignore
1038 * those who are already fully discovered
1043 pcibios_setup_device(dev);
1047 void pcibios_set_master(struct pci_dev *dev)
1049 /* No special bus mastering setup handling */
1052 void pcibios_fixup_bus(struct pci_bus *bus)
1054 /* When called from the generic PCI probe, read PCI<->PCI bridge
1055 * bases. This is -not- called when generating the PCI tree from
1056 * the OF device-tree.
1058 if (bus->self != NULL)
1059 pci_read_bridge_bases(bus);
1061 /* Now fixup the bus bus */
1062 pcibios_setup_bus_self(bus);
1064 /* Now fixup devices on that bus */
1065 pcibios_setup_bus_devices(bus);
1067 EXPORT_SYMBOL(pcibios_fixup_bus);
1069 void pci_fixup_cardbus(struct pci_bus *bus)
1071 /* Now fixup devices on that bus */
1072 pcibios_setup_bus_devices(bus);
1076 static int skip_isa_ioresource_align(struct pci_dev *dev)
1078 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1079 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1085 * We need to avoid collisions with `mirrored' VGA ports
1086 * and other strange ISA hardware, so we always want the
1087 * addresses to be allocated in the 0x000-0x0ff region
1090 * Why? Because some silly external IO cards only decode
1091 * the low 10 bits of the IO address. The 0x00-0xff region
1092 * is reserved for motherboard devices that decode all 16
1093 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1094 * but we want to try to avoid allocating at 0x2900-0x2bff
1095 * which might have be mirrored at 0x0100-0x03ff..
1097 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1098 resource_size_t size, resource_size_t align)
1100 struct pci_dev *dev = data;
1101 resource_size_t start = res->start;
1103 if (res->flags & IORESOURCE_IO) {
1104 if (skip_isa_ioresource_align(dev))
1107 start = (start + 0x3ff) & ~0x3ff;
1112 EXPORT_SYMBOL(pcibios_align_resource);
1115 * Reparent resource children of pr that conflict with res
1116 * under res, and make res replace those children.
1118 static int reparent_resources(struct resource *parent,
1119 struct resource *res)
1121 struct resource *p, **pp;
1122 struct resource **firstpp = NULL;
1124 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1125 if (p->end < res->start)
1127 if (res->end < p->start)
1129 if (p->start < res->start || p->end > res->end)
1130 return -1; /* not completely contained */
1131 if (firstpp == NULL)
1134 if (firstpp == NULL)
1135 return -1; /* didn't find any conflicting entries? */
1136 res->parent = parent;
1137 res->child = *firstpp;
1141 for (p = res->child; p != NULL; p = p->sibling) {
1143 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1145 (unsigned long long)p->start,
1146 (unsigned long long)p->end, res->name);
1152 * Handle resources of PCI devices. If the world were perfect, we could
1153 * just allocate all the resource regions and do nothing more. It isn't.
1154 * On the other hand, we cannot just re-allocate all devices, as it would
1155 * require us to know lots of host bridge internals. So we attempt to
1156 * keep as much of the original configuration as possible, but tweak it
1157 * when it's found to be wrong.
1159 * Known BIOS problems we have to work around:
1160 * - I/O or memory regions not configured
1161 * - regions configured, but not enabled in the command register
1162 * - bogus I/O addresses above 64K used
1163 * - expansion ROMs left enabled (this may sound harmless, but given
1164 * the fact the PCI specs explicitly allow address decoders to be
1165 * shared between expansion ROMs and other resource regions, it's
1166 * at least dangerous)
1169 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1170 * This gives us fixed barriers on where we can allocate.
1171 * (2) Allocate resources for all enabled devices. If there is
1172 * a collision, just mark the resource as unallocated. Also
1173 * disable expansion ROMs during this step.
1174 * (3) Try to allocate resources for disabled devices. If the
1175 * resources were assigned correctly, everything goes well,
1176 * if they weren't, they won't disturb allocation of other
1178 * (4) Assign new addresses to resources which were either
1179 * not configured at all or misconfigured. If explicitly
1180 * requested by the user, configure expansion ROM address
1184 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1188 struct resource *res, *pr;
1190 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1191 pci_domain_nr(bus), bus->number);
1193 pci_bus_for_each_resource(bus, res, i) {
1194 if (!res || !res->flags || res->start > res->end || res->parent)
1197 /* If the resource was left unset at this point, we clear it */
1198 if (res->flags & IORESOURCE_UNSET)
1199 goto clear_resource;
1201 if (bus->parent == NULL)
1202 pr = (res->flags & IORESOURCE_IO) ?
1203 &ioport_resource : &iomem_resource;
1205 pr = pci_find_parent_resource(bus->self, res);
1207 /* this happens when the generic PCI
1208 * code (wrongly) decides that this
1209 * bridge is transparent -- paulus
1215 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1216 "[0x%x], parent %p (%s)\n",
1217 bus->self ? pci_name(bus->self) : "PHB",
1219 (unsigned long long)res->start,
1220 (unsigned long long)res->end,
1221 (unsigned int)res->flags,
1222 pr, (pr && pr->name) ? pr->name : "nil");
1224 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1225 if (request_resource(pr, res) == 0)
1228 * Must be a conflict with an existing entry.
1229 * Move that entry (or entries) under the
1230 * bridge resource and try again.
1232 if (reparent_resources(pr, res) == 0)
1235 pr_warning("PCI: Cannot allocate resource region "
1236 "%d of PCI bridge %d, will remap\n", i, bus->number);
1238 /* The resource might be figured out when doing
1239 * reassignment based on the resources required
1240 * by the downstream PCI devices. Here we set
1241 * the size of the resource to be 0 in order to
1249 list_for_each_entry(b, &bus->children, node)
1250 pcibios_allocate_bus_resources(b);
1253 static inline void alloc_resource(struct pci_dev *dev, int idx)
1255 struct resource *pr, *r = &dev->resource[idx];
1257 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1259 (unsigned long long)r->start,
1260 (unsigned long long)r->end,
1261 (unsigned int)r->flags);
1263 pr = pci_find_parent_resource(dev, r);
1264 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1265 request_resource(pr, r) < 0) {
1266 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1267 " of device %s, will remap\n", idx, pci_name(dev));
1269 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1271 (unsigned long long)pr->start,
1272 (unsigned long long)pr->end,
1273 (unsigned int)pr->flags);
1274 /* We'll assign a new address later */
1275 r->flags |= IORESOURCE_UNSET;
1281 static void __init pcibios_allocate_resources(int pass)
1283 struct pci_dev *dev = NULL;
1288 for_each_pci_dev(dev) {
1289 pci_read_config_word(dev, PCI_COMMAND, &command);
1290 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1291 r = &dev->resource[idx];
1292 if (r->parent) /* Already allocated */
1294 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1295 continue; /* Not assigned at all */
1296 /* We only allocate ROMs on pass 1 just in case they
1297 * have been screwed up by firmware
1299 if (idx == PCI_ROM_RESOURCE )
1301 if (r->flags & IORESOURCE_IO)
1302 disabled = !(command & PCI_COMMAND_IO);
1304 disabled = !(command & PCI_COMMAND_MEMORY);
1305 if (pass == disabled)
1306 alloc_resource(dev, idx);
1310 r = &dev->resource[PCI_ROM_RESOURCE];
1312 /* Turn the ROM off, leave the resource region,
1313 * but keep it unregistered.
1316 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1317 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1318 pr_debug("PCI: Switching off ROM of %s\n",
1320 r->flags &= ~IORESOURCE_ROM_ENABLE;
1321 pci_write_config_dword(dev, dev->rom_base_reg,
1322 reg & ~PCI_ROM_ADDRESS_ENABLE);
1328 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1330 struct pci_controller *hose = pci_bus_to_host(bus);
1331 resource_size_t offset;
1332 struct resource *res, *pres;
1335 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1338 if (!(hose->io_resource.flags & IORESOURCE_IO))
1340 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1341 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1342 BUG_ON(res == NULL);
1343 res->name = "Legacy IO";
1344 res->flags = IORESOURCE_IO;
1345 res->start = offset;
1346 res->end = (offset + 0xfff) & 0xfffffffful;
1347 pr_debug("Candidate legacy IO: %pR\n", res);
1348 if (request_resource(&hose->io_resource, res)) {
1350 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1351 pci_domain_nr(bus), bus->number, res);
1356 /* Check for memory */
1357 for (i = 0; i < 3; i++) {
1358 pres = &hose->mem_resources[i];
1359 offset = hose->mem_offset[i];
1360 if (!(pres->flags & IORESOURCE_MEM))
1362 pr_debug("hose mem res: %pR\n", pres);
1363 if ((pres->start - offset) <= 0xa0000 &&
1364 (pres->end - offset) >= 0xbffff)
1369 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1370 BUG_ON(res == NULL);
1371 res->name = "Legacy VGA memory";
1372 res->flags = IORESOURCE_MEM;
1373 res->start = 0xa0000 + offset;
1374 res->end = 0xbffff + offset;
1375 pr_debug("Candidate VGA memory: %pR\n", res);
1376 if (request_resource(pres, res)) {
1378 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1379 pci_domain_nr(bus), bus->number, res);
1384 void __init pcibios_resource_survey(void)
1388 /* Allocate and assign resources */
1389 list_for_each_entry(b, &pci_root_buses, node)
1390 pcibios_allocate_bus_resources(b);
1391 pcibios_allocate_resources(0);
1392 pcibios_allocate_resources(1);
1394 /* Before we start assigning unassigned resource, we try to reserve
1395 * the low IO area and the VGA memory area if they intersect the
1396 * bus available resources to avoid allocating things on top of them
1398 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1399 list_for_each_entry(b, &pci_root_buses, node)
1400 pcibios_reserve_legacy_regions(b);
1403 /* Now, if the platform didn't decide to blindly trust the firmware,
1404 * we proceed to assigning things that were left unassigned
1406 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1407 pr_debug("PCI: Assigning unassigned resources...\n");
1408 pci_assign_unassigned_resources();
1411 /* Call machine dependent fixup */
1412 if (ppc_md.pcibios_fixup)
1413 ppc_md.pcibios_fixup();
1416 /* This is used by the PCI hotplug driver to allocate resource
1417 * of newly plugged busses. We can try to consolidate with the
1418 * rest of the code later, for now, keep it as-is as our main
1419 * resource allocation function doesn't deal with sub-trees yet.
1421 void pcibios_claim_one_bus(struct pci_bus *bus)
1423 struct pci_dev *dev;
1424 struct pci_bus *child_bus;
1426 list_for_each_entry(dev, &bus->devices, bus_list) {
1429 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1430 struct resource *r = &dev->resource[i];
1432 if (r->parent || !r->start || !r->flags)
1435 pr_debug("PCI: Claiming %s: "
1436 "Resource %d: %016llx..%016llx [%x]\n",
1438 (unsigned long long)r->start,
1439 (unsigned long long)r->end,
1440 (unsigned int)r->flags);
1442 pci_claim_resource(dev, i);
1446 list_for_each_entry(child_bus, &bus->children, node)
1447 pcibios_claim_one_bus(child_bus);
1451 /* pcibios_finish_adding_to_bus
1453 * This is to be called by the hotplug code after devices have been
1454 * added to a bus, this include calling it for a PHB that is just
1457 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1459 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1460 pci_domain_nr(bus), bus->number);
1462 /* Allocate bus and devices resources */
1463 pcibios_allocate_bus_resources(bus);
1464 pcibios_claim_one_bus(bus);
1467 eeh_add_device_tree_late(bus);
1469 /* Add new devices to global lists. Register in proc, sysfs. */
1470 pci_bus_add_devices(bus);
1472 /* sysfs files should only be added after devices are added */
1473 eeh_add_sysfs_files(bus);
1475 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1477 int pcibios_enable_device(struct pci_dev *dev, int mask)
1479 if (ppc_md.pcibios_enable_device_hook)
1480 if (ppc_md.pcibios_enable_device_hook(dev))
1483 /* avoid pcie irq fix up impact on cardbus */
1484 if (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS)
1485 pcibios_setup_device(dev);
1487 return pci_enable_resources(dev, mask);
1490 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1492 return (unsigned long) hose->io_base_virt - _IO_BASE;
1495 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1496 struct list_head *resources)
1498 struct resource *res;
1499 resource_size_t offset;
1502 /* Hookup PHB IO resource */
1503 res = &hose->io_resource;
1506 printk(KERN_WARNING "PCI: I/O resource not set for host"
1507 " bridge %s (domain %d)\n",
1508 hose->dn->full_name, hose->global_number);
1510 offset = pcibios_io_space_offset(hose);
1512 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1513 (unsigned long long)res->start,
1514 (unsigned long long)res->end,
1515 (unsigned long)res->flags,
1516 (unsigned long long)offset);
1517 pci_add_resource_offset(resources, res, offset);
1520 /* Hookup PHB Memory resources */
1521 for (i = 0; i < 3; ++i) {
1522 res = &hose->mem_resources[i];
1524 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1525 "host bridge %s (domain %d)\n",
1526 hose->dn->full_name, hose->global_number);
1529 offset = hose->mem_offset[i];
1532 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1533 (unsigned long long)res->start,
1534 (unsigned long long)res->end,
1535 (unsigned long)res->flags,
1536 (unsigned long long)offset);
1538 pci_add_resource_offset(resources, res, offset);
1543 * Null PCI config access functions, for the case when we can't
1546 #define NULL_PCI_OP(rw, size, type) \
1548 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1550 return PCIBIOS_DEVICE_NOT_FOUND; \
1554 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1557 return PCIBIOS_DEVICE_NOT_FOUND;
1561 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1564 return PCIBIOS_DEVICE_NOT_FOUND;
1567 static struct pci_ops null_pci_ops =
1569 .read = null_read_config,
1570 .write = null_write_config,
1574 * These functions are used early on before PCI scanning is done
1575 * and all of the pci_dev and pci_bus structures have been created.
1577 static struct pci_bus *
1578 fake_pci_bus(struct pci_controller *hose, int busnr)
1580 static struct pci_bus bus;
1583 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1587 bus.ops = hose? hose->ops: &null_pci_ops;
1591 #define EARLY_PCI_OP(rw, size, type) \
1592 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1593 int devfn, int offset, type value) \
1595 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1596 devfn, offset, value); \
1599 EARLY_PCI_OP(read, byte, u8 *)
1600 EARLY_PCI_OP(read, word, u16 *)
1601 EARLY_PCI_OP(read, dword, u32 *)
1602 EARLY_PCI_OP(write, byte, u8)
1603 EARLY_PCI_OP(write, word, u16)
1604 EARLY_PCI_OP(write, dword, u32)
1606 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1607 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1610 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1613 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1615 struct pci_controller *hose = bus->sysdata;
1617 return of_node_get(hose->dn);
1621 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1622 * @hose: Pointer to the PCI host controller instance structure
1624 void pcibios_scan_phb(struct pci_controller *hose)
1626 LIST_HEAD(resources);
1627 struct pci_bus *bus;
1628 struct device_node *node = hose->dn;
1631 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1633 /* Get some IO space for the new PHB */
1634 pcibios_setup_phb_io_space(hose);
1636 /* Wire up PHB bus resources */
1637 pcibios_setup_phb_resources(hose, &resources);
1639 hose->busn.start = hose->first_busno;
1640 hose->busn.end = hose->last_busno;
1641 hose->busn.flags = IORESOURCE_BUS;
1642 pci_add_resource(&resources, &hose->busn);
1644 /* Create an empty bus for the toplevel */
1645 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1646 hose->ops, hose, &resources);
1648 pr_err("Failed to create bus for PCI domain %04x\n",
1649 hose->global_number);
1650 pci_free_resource_list(&resources);
1655 /* Get probe mode and perform scan */
1656 mode = PCI_PROBE_NORMAL;
1657 if (node && ppc_md.pci_probe_mode)
1658 mode = ppc_md.pci_probe_mode(bus);
1659 pr_debug(" probe mode: %d\n", mode);
1660 if (mode == PCI_PROBE_DEVTREE)
1661 of_scan_bus(node, bus);
1663 if (mode == PCI_PROBE_NORMAL) {
1664 pci_bus_update_busn_res_end(bus, 255);
1665 hose->last_busno = pci_scan_child_bus(bus);
1666 pci_bus_update_busn_res_end(bus, hose->last_busno);
1669 /* Platform gets a chance to do some global fixups before
1670 * we proceed to resource allocation
1672 if (ppc_md.pcibios_fixup_phb)
1673 ppc_md.pcibios_fixup_phb(hose);
1675 /* Configure PCI Express settings */
1676 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1677 struct pci_bus *child;
1678 list_for_each_entry(child, &bus->children, node) {
1679 struct pci_dev *self = child->self;
1682 pcie_bus_configure_settings(child, self->pcie_mpss);
1687 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1689 int i, class = dev->class >> 8;
1690 /* When configured as agent, programing interface = 1 */
1691 int prog_if = dev->class & 0xf;
1693 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1694 class == PCI_CLASS_BRIDGE_OTHER) &&
1695 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1697 (dev->bus->parent == NULL)) {
1698 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1699 dev->resource[i].start = 0;
1700 dev->resource[i].end = 0;
1701 dev->resource[i].flags = 0;
1705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1708 static void fixup_vga(struct pci_dev *pdev)
1712 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1713 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1714 vga_set_default_device(pdev);
1717 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1718 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);