2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 /* hose_spinlock protects accesses to the the phb_bitmap. */
46 static DEFINE_SPINLOCK(hose_spinlock);
49 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
50 #define MAX_PHBS 0x10000
53 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
54 * Accesses to this bitmap should be protected by hose_spinlock.
56 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
58 /* ISA Memory physical address */
59 resource_size_t isa_mem_base;
60 EXPORT_SYMBOL(isa_mem_base);
63 static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops;
65 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
67 pci_dma_ops = dma_ops;
70 const struct dma_map_ops *get_pci_dma_ops(void)
74 EXPORT_SYMBOL(get_pci_dma_ops);
77 * This function should run under locking protection, specifically
80 static int get_phb_number(struct device_node *dn)
87 * Try fixed PHB numbering first, by checking archs and reading
88 * the respective device-tree properties. Firstly, try powernv by
89 * reading "ibm,opal-phbid", only present in OPAL environment.
91 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
93 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
98 phb_id = (int)(prop & (MAX_PHBS - 1));
100 /* We need to be sure to not use the same PHB number twice. */
101 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
105 * If not pseries nor powernv, or if fixed PHB numbering tried to add
106 * the same PHB number twice, then fallback to dynamic PHB numbering.
108 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
109 BUG_ON(phb_id >= MAX_PHBS);
110 set_bit(phb_id, phb_bitmap);
115 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
117 struct pci_controller *phb;
119 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
122 spin_lock(&hose_spinlock);
123 phb->global_number = get_phb_number(dev);
124 list_add_tail(&phb->list_node, &hose_list);
125 spin_unlock(&hose_spinlock);
127 phb->is_dynamic = slab_is_available();
130 int nid = of_node_to_nid(dev);
132 if (nid < 0 || !node_online(nid))
135 PHB_SET_NODE(phb, nid);
140 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
142 void pcibios_free_controller(struct pci_controller *phb)
144 spin_lock(&hose_spinlock);
146 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
147 if (phb->global_number < MAX_PHBS)
148 clear_bit(phb->global_number, phb_bitmap);
150 list_del(&phb->list_node);
151 spin_unlock(&hose_spinlock);
156 EXPORT_SYMBOL_GPL(pcibios_free_controller);
159 * This function is used to call pcibios_free_controller()
160 * in a deferred manner: a callback from the PCI subsystem.
162 * _*DO NOT*_ call pcibios_free_controller() explicitly if
163 * this is used (or it may access an invalid *phb pointer).
165 * The callback occurs when all references to the root bus
166 * are dropped (e.g., child buses/devices and their users).
168 * It's called as .release_fn() of 'struct pci_host_bridge'
169 * which is associated with the 'struct pci_controller.bus'
170 * (root bus) - it expects .release_data to hold a pointer
171 * to 'struct pci_controller'.
173 * In order to use it, register .release_fn()/release_data
176 * pci_set_host_bridge_release(bridge,
177 * pcibios_free_controller_deferred
180 * e.g. in the pcibios_root_bridge_prepare() callback from
181 * pci_create_root_bus().
183 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
185 struct pci_controller *phb = (struct pci_controller *)
186 bridge->release_data;
188 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
190 pcibios_free_controller(phb);
192 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
195 * The function is used to return the minimal alignment
196 * for memory or I/O windows of the associated P2P bridge.
197 * By default, 4KiB alignment for I/O windows and 1MiB for
200 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
203 struct pci_controller *phb = pci_bus_to_host(bus);
205 if (phb->controller_ops.window_alignment)
206 return phb->controller_ops.window_alignment(bus, type);
209 * PCI core will figure out the default
210 * alignment: 4KiB for I/O and 1MiB for
216 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
218 struct pci_controller *hose = pci_bus_to_host(bus);
220 if (hose->controller_ops.setup_bridge)
221 hose->controller_ops.setup_bridge(bus, type);
224 void pcibios_reset_secondary_bus(struct pci_dev *dev)
226 struct pci_controller *phb = pci_bus_to_host(dev->bus);
228 if (phb->controller_ops.reset_secondary_bus) {
229 phb->controller_ops.reset_secondary_bus(dev);
233 pci_reset_secondary_bus(dev);
236 resource_size_t pcibios_default_alignment(void)
238 if (ppc_md.pcibios_default_alignment)
239 return ppc_md.pcibios_default_alignment();
244 #ifdef CONFIG_PCI_IOV
245 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
247 if (ppc_md.pcibios_iov_resource_alignment)
248 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
250 return pci_iov_resource_size(pdev, resno);
253 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
255 if (ppc_md.pcibios_sriov_enable)
256 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
261 int pcibios_sriov_disable(struct pci_dev *pdev)
263 if (ppc_md.pcibios_sriov_disable)
264 return ppc_md.pcibios_sriov_disable(pdev);
269 #endif /* CONFIG_PCI_IOV */
271 void pcibios_bus_add_device(struct pci_dev *pdev)
273 if (ppc_md.pcibios_bus_add_device)
274 ppc_md.pcibios_bus_add_device(pdev);
277 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
280 return hose->pci_io_size;
282 return resource_size(&hose->io_resource);
286 int pcibios_vaddr_is_ioport(void __iomem *address)
289 struct pci_controller *hose;
290 resource_size_t size;
292 spin_lock(&hose_spinlock);
293 list_for_each_entry(hose, &hose_list, list_node) {
294 size = pcibios_io_size(hose);
295 if (address >= hose->io_base_virt &&
296 address < (hose->io_base_virt + size)) {
301 spin_unlock(&hose_spinlock);
305 unsigned long pci_address_to_pio(phys_addr_t address)
307 struct pci_controller *hose;
308 resource_size_t size;
309 unsigned long ret = ~0;
311 spin_lock(&hose_spinlock);
312 list_for_each_entry(hose, &hose_list, list_node) {
313 size = pcibios_io_size(hose);
314 if (address >= hose->io_base_phys &&
315 address < (hose->io_base_phys + size)) {
317 (unsigned long)hose->io_base_virt - _IO_BASE;
318 ret = base + (address - hose->io_base_phys);
322 spin_unlock(&hose_spinlock);
326 EXPORT_SYMBOL_GPL(pci_address_to_pio);
329 * Return the domain number for this bus.
331 int pci_domain_nr(struct pci_bus *bus)
333 struct pci_controller *hose = pci_bus_to_host(bus);
335 return hose->global_number;
337 EXPORT_SYMBOL(pci_domain_nr);
339 /* This routine is meant to be used early during boot, when the
340 * PCI bus numbers have not yet been assigned, and you need to
341 * issue PCI config cycles to an OF device.
342 * It could also be used to "fix" RTAS config cycles if you want
343 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
346 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
349 struct pci_controller *hose, *tmp;
350 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
351 if (hose->dn == node)
359 * Reads the interrupt pin to determine if interrupt is use by card.
360 * If the interrupt is used, then gets the interrupt line from the
361 * openfirmware and sets it in the pci_dev and pci_config line.
363 static int pci_read_irq_line(struct pci_dev *pci_dev)
367 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
370 memset(&oirq, 0xff, sizeof(oirq));
372 /* Try to get a mapping from the device-tree */
373 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
377 /* If that fails, lets fallback to what is in the config
378 * space and map that through the default controller. We
379 * also set the type to level low since that's what PCI
380 * interrupts are. If your platform does differently, then
381 * either provide a proper interrupt tree or don't use this
384 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
388 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
389 line == 0xff || line == 0) {
392 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
395 virq = irq_create_mapping(NULL, line);
397 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
401 pr_debug(" Failed to map !\n");
405 pr_debug(" Mapped to linux irq %d\n", virq);
413 * Platform support for /proc/bus/pci/X/Y mmap()s.
416 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
418 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
419 resource_size_t ioaddr = pci_resource_start(pdev, bar);
424 /* Convert to an offset within this PCI controller */
425 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
427 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
432 * This one is used by /dev/mem and fbdev who have no clue about the
433 * PCI device, it tries to find the PCI device first and calls the
436 pgprot_t pci_phys_mem_access_prot(struct file *file,
441 struct pci_dev *pdev = NULL;
442 struct resource *found = NULL;
443 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
446 if (page_is_ram(pfn))
449 prot = pgprot_noncached(prot);
450 for_each_pci_dev(pdev) {
451 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
452 struct resource *rp = &pdev->resource[i];
453 int flags = rp->flags;
455 /* Active and same type? */
456 if ((flags & IORESOURCE_MEM) == 0)
458 /* In the range of this resource? */
459 if (offset < (rp->start & PAGE_MASK) ||
469 if (found->flags & IORESOURCE_PREFETCH)
470 prot = pgprot_noncached_wc(prot);
474 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
475 (unsigned long long)offset, pgprot_val(prot));
480 /* This provides legacy IO read access on a bus */
481 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
483 unsigned long offset;
484 struct pci_controller *hose = pci_bus_to_host(bus);
485 struct resource *rp = &hose->io_resource;
488 /* Check if port can be supported by that bus. We only check
489 * the ranges of the PHB though, not the bus itself as the rules
490 * for forwarding legacy cycles down bridges are not our problem
491 * here. So if the host bridge supports it, we do it.
493 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
496 if (!(rp->flags & IORESOURCE_IO))
498 if (offset < rp->start || (offset + size) > rp->end)
500 addr = hose->io_base_virt + port;
504 *((u8 *)val) = in_8(addr);
509 *((u16 *)val) = in_le16(addr);
514 *((u32 *)val) = in_le32(addr);
520 /* This provides legacy IO write access on a bus */
521 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
523 unsigned long offset;
524 struct pci_controller *hose = pci_bus_to_host(bus);
525 struct resource *rp = &hose->io_resource;
528 /* Check if port can be supported by that bus. We only check
529 * the ranges of the PHB though, not the bus itself as the rules
530 * for forwarding legacy cycles down bridges are not our problem
531 * here. So if the host bridge supports it, we do it.
533 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
536 if (!(rp->flags & IORESOURCE_IO))
538 if (offset < rp->start || (offset + size) > rp->end)
540 addr = hose->io_base_virt + port;
542 /* WARNING: The generic code is idiotic. It gets passed a pointer
543 * to what can be a 1, 2 or 4 byte quantity and always reads that
544 * as a u32, which means that we have to correct the location of
545 * the data read within those 32 bits for size 1 and 2
549 out_8(addr, val >> 24);
554 out_le16(addr, val >> 16);
565 /* This provides legacy IO or memory mmap access on a bus */
566 int pci_mmap_legacy_page_range(struct pci_bus *bus,
567 struct vm_area_struct *vma,
568 enum pci_mmap_state mmap_state)
570 struct pci_controller *hose = pci_bus_to_host(bus);
571 resource_size_t offset =
572 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
573 resource_size_t size = vma->vm_end - vma->vm_start;
576 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
577 pci_domain_nr(bus), bus->number,
578 mmap_state == pci_mmap_mem ? "MEM" : "IO",
579 (unsigned long long)offset,
580 (unsigned long long)(offset + size - 1));
582 if (mmap_state == pci_mmap_mem) {
585 * Because X is lame and can fail starting if it gets an error trying
586 * to mmap legacy_mem (instead of just moving on without legacy memory
587 * access) we fake it here by giving it anonymous memory, effectively
588 * behaving just like /dev/zero
590 if ((offset + size) > hose->isa_mem_size) {
592 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
593 current->comm, current->pid, pci_domain_nr(bus), bus->number);
594 if (vma->vm_flags & VM_SHARED)
595 return shmem_zero_setup(vma);
598 offset += hose->isa_mem_phys;
600 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
601 unsigned long roffset = offset + io_offset;
602 rp = &hose->io_resource;
603 if (!(rp->flags & IORESOURCE_IO))
605 if (roffset < rp->start || (roffset + size) > rp->end)
607 offset += hose->io_base_phys;
609 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
611 vma->vm_pgoff = offset >> PAGE_SHIFT;
612 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
613 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
614 vma->vm_end - vma->vm_start,
618 void pci_resource_to_user(const struct pci_dev *dev, int bar,
619 const struct resource *rsrc,
620 resource_size_t *start, resource_size_t *end)
622 struct pci_bus_region region;
624 if (rsrc->flags & IORESOURCE_IO) {
625 pcibios_resource_to_bus(dev->bus, ®ion,
626 (struct resource *) rsrc);
627 *start = region.start;
632 /* We pass a CPU physical address to userland for MMIO instead of a
633 * BAR value because X is lame and expects to be able to use that
634 * to pass to /dev/mem!
636 * That means we may have 64-bit values where some apps only expect
637 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
639 *start = rsrc->start;
644 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
645 * @hose: newly allocated pci_controller to be setup
646 * @dev: device node of the host bridge
647 * @primary: set if primary bus (32 bits only, soon to be deprecated)
649 * This function will parse the "ranges" property of a PCI host bridge device
650 * node and setup the resource mapping of a pci controller based on its
653 * Life would be boring if it wasn't for a few issues that we have to deal
656 * - We can only cope with one IO space range and up to 3 Memory space
657 * ranges. However, some machines (thanks Apple !) tend to split their
658 * space into lots of small contiguous ranges. So we have to coalesce.
660 * - Some busses have IO space not starting at 0, which causes trouble with
661 * the way we do our IO resource renumbering. The code somewhat deals with
662 * it for 64 bits but I would expect problems on 32 bits.
664 * - Some 32 bits platforms such as 4xx can have physical space larger than
665 * 32 bits so we need to use 64 bits values for the parsing
667 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
668 struct device_node *dev, int primary)
671 struct resource *res;
672 struct of_pci_range range;
673 struct of_pci_range_parser parser;
675 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
676 dev, primary ? "(primary)" : "");
678 /* Check for ranges property */
679 if (of_pci_range_parser_init(&parser, dev))
683 for_each_of_pci_range(&parser, &range) {
684 /* If we failed translation or got a zero-sized region
685 * (some FW try to feed us with non sensical zero sized regions
686 * such as power3 which look like some kind of attempt at exposing
687 * the VGA memory hole)
689 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
692 /* Act based on address space type */
694 switch (range.flags & IORESOURCE_TYPE_BITS) {
697 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
698 range.cpu_addr, range.cpu_addr + range.size - 1,
701 /* We support only one IO range */
702 if (hose->pci_io_size) {
704 " \\--> Skipped (too many) !\n");
708 /* On 32 bits, limit I/O space to 16MB */
709 if (range.size > 0x01000000)
710 range.size = 0x01000000;
712 /* 32 bits needs to map IOs here */
713 hose->io_base_virt = ioremap(range.cpu_addr,
716 /* Expect trouble if pci_addr is not 0 */
719 (unsigned long)hose->io_base_virt;
720 #endif /* CONFIG_PPC32 */
721 /* pci_io_size and io_base_phys always represent IO
722 * space starting at 0 so we factor in pci_addr
724 hose->pci_io_size = range.pci_addr + range.size;
725 hose->io_base_phys = range.cpu_addr - range.pci_addr;
728 res = &hose->io_resource;
729 range.cpu_addr = range.pci_addr;
733 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
734 range.cpu_addr, range.cpu_addr + range.size - 1,
736 (range.pci_space & 0x40000000) ?
739 /* We support only 3 memory ranges */
742 " \\--> Skipped (too many) !\n");
745 /* Handles ISA memory hole space here */
746 if (range.pci_addr == 0) {
747 if (primary || isa_mem_base == 0)
748 isa_mem_base = range.cpu_addr;
749 hose->isa_mem_phys = range.cpu_addr;
750 hose->isa_mem_size = range.size;
754 hose->mem_offset[memno] = range.cpu_addr -
756 res = &hose->mem_resources[memno++];
760 res->name = dev->full_name;
761 res->flags = range.flags;
762 res->start = range.cpu_addr;
763 res->end = range.cpu_addr + range.size - 1;
764 res->parent = res->child = res->sibling = NULL;
769 /* Decide whether to display the domain number in /proc */
770 int pci_proc_domain(struct pci_bus *bus)
772 struct pci_controller *hose = pci_bus_to_host(bus);
774 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
776 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
777 return hose->global_number != 0;
781 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
783 if (ppc_md.pcibios_root_bridge_prepare)
784 return ppc_md.pcibios_root_bridge_prepare(bridge);
789 /* This header fixup will do the resource fixup for all devices as they are
790 * probed, but not for bridge ranges
792 static void pcibios_fixup_resources(struct pci_dev *dev)
794 struct pci_controller *hose = pci_bus_to_host(dev->bus);
798 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
806 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
807 struct resource *res = dev->resource + i;
808 struct pci_bus_region reg;
812 /* If we're going to re-assign everything, we mark all resources
813 * as unset (and 0-base them). In addition, we mark BARs starting
814 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
815 * since in that case, we don't want to re-assign anything
817 pcibios_resource_to_bus(dev->bus, ®, res);
818 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
819 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
820 /* Only print message if not re-assigning */
821 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
822 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
823 pci_name(dev), i, res);
824 res->end -= res->start;
826 res->flags |= IORESOURCE_UNSET;
830 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
833 /* Call machine specific resource fixup */
834 if (ppc_md.pcibios_fixup_resources)
835 ppc_md.pcibios_fixup_resources(dev);
837 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
839 /* This function tries to figure out if a bridge resource has been initialized
840 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
841 * things go more smoothly when it gets it right. It should covers cases such
842 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
844 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
845 struct resource *res)
847 struct pci_controller *hose = pci_bus_to_host(bus);
848 struct pci_dev *dev = bus->self;
849 resource_size_t offset;
850 struct pci_bus_region region;
854 /* We don't do anything if PCI_PROBE_ONLY is set */
855 if (pci_has_flag(PCI_PROBE_ONLY))
858 /* Job is a bit different between memory and IO */
859 if (res->flags & IORESOURCE_MEM) {
860 pcibios_resource_to_bus(dev->bus, ®ion, res);
862 /* If the BAR is non-0 then it's probably been initialized */
863 if (region.start != 0)
866 /* The BAR is 0, let's check if memory decoding is enabled on
867 * the bridge. If not, we consider it unassigned
869 pci_read_config_word(dev, PCI_COMMAND, &command);
870 if ((command & PCI_COMMAND_MEMORY) == 0)
873 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
874 * resources covers that starting address (0 then it's good enough for
875 * us for memory space)
877 for (i = 0; i < 3; i++) {
878 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
879 hose->mem_resources[i].start == hose->mem_offset[i])
883 /* Well, it starts at 0 and we know it will collide so we may as
884 * well consider it as unassigned. That covers the Apple case.
888 /* If the BAR is non-0, then we consider it assigned */
889 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
890 if (((res->start - offset) & 0xfffffffful) != 0)
893 /* Here, we are a bit different than memory as typically IO space
894 * starting at low addresses -is- valid. What we do instead if that
895 * we consider as unassigned anything that doesn't have IO enabled
896 * in the PCI command register, and that's it.
898 pci_read_config_word(dev, PCI_COMMAND, &command);
899 if (command & PCI_COMMAND_IO)
902 /* It's starting at 0 and IO is disabled in the bridge, consider
909 /* Fixup resources of a PCI<->PCI bridge */
910 static void pcibios_fixup_bridge(struct pci_bus *bus)
912 struct resource *res;
915 struct pci_dev *dev = bus->self;
917 pci_bus_for_each_resource(bus, res, i) {
918 if (!res || !res->flags)
920 if (i >= 3 && bus->self->transparent)
923 /* If we're going to reassign everything, we can
924 * shrink the P2P resource to have size as being
925 * of 0 in order to save space.
927 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
928 res->flags |= IORESOURCE_UNSET;
934 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
936 /* Try to detect uninitialized P2P bridge resources,
937 * and clear them out so they get re-assigned later
939 if (pcibios_uninitialized_bridge_resource(bus, res)) {
941 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
946 void pcibios_setup_bus_self(struct pci_bus *bus)
948 struct pci_controller *phb;
950 /* Fix up the bus resources for P2P bridges */
951 if (bus->self != NULL)
952 pcibios_fixup_bridge(bus);
954 /* Platform specific bus fixups. This is currently only used
955 * by fsl_pci and I'm hoping to get rid of it at some point
957 if (ppc_md.pcibios_fixup_bus)
958 ppc_md.pcibios_fixup_bus(bus);
960 /* Setup bus DMA mappings */
961 phb = pci_bus_to_host(bus);
962 if (phb->controller_ops.dma_bus_setup)
963 phb->controller_ops.dma_bus_setup(bus);
966 static void pcibios_setup_device(struct pci_dev *dev)
968 struct pci_controller *phb;
969 /* Fixup NUMA node as it may not be setup yet by the generic
970 * code and is needed by the DMA init
972 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
974 /* Hook up default DMA ops */
975 set_dma_ops(&dev->dev, pci_dma_ops);
976 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
978 /* Additional platform DMA/iommu setup */
979 phb = pci_bus_to_host(dev->bus);
980 if (phb->controller_ops.dma_dev_setup)
981 phb->controller_ops.dma_dev_setup(dev);
983 /* Read default IRQs and fixup if necessary */
984 pci_read_irq_line(dev);
985 if (ppc_md.pci_irq_fixup)
986 ppc_md.pci_irq_fixup(dev);
989 int pcibios_add_device(struct pci_dev *dev)
992 * We can only call pcibios_setup_device() after bus setup is complete,
993 * since some of the platform specific DMA setup code depends on it.
995 if (dev->bus->is_added)
996 pcibios_setup_device(dev);
998 #ifdef CONFIG_PCI_IOV
999 if (ppc_md.pcibios_fixup_sriov)
1000 ppc_md.pcibios_fixup_sriov(dev);
1001 #endif /* CONFIG_PCI_IOV */
1006 void pcibios_setup_bus_devices(struct pci_bus *bus)
1008 struct pci_dev *dev;
1010 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1011 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1013 list_for_each_entry(dev, &bus->devices, bus_list) {
1014 /* Cardbus can call us to add new devices to a bus, so ignore
1015 * those who are already fully discovered
1020 pcibios_setup_device(dev);
1024 void pcibios_set_master(struct pci_dev *dev)
1026 /* No special bus mastering setup handling */
1029 void pcibios_fixup_bus(struct pci_bus *bus)
1031 /* When called from the generic PCI probe, read PCI<->PCI bridge
1032 * bases. This is -not- called when generating the PCI tree from
1033 * the OF device-tree.
1035 pci_read_bridge_bases(bus);
1037 /* Now fixup the bus bus */
1038 pcibios_setup_bus_self(bus);
1040 /* Now fixup devices on that bus */
1041 pcibios_setup_bus_devices(bus);
1043 EXPORT_SYMBOL(pcibios_fixup_bus);
1045 void pci_fixup_cardbus(struct pci_bus *bus)
1047 /* Now fixup devices on that bus */
1048 pcibios_setup_bus_devices(bus);
1052 static int skip_isa_ioresource_align(struct pci_dev *dev)
1054 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1055 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1061 * We need to avoid collisions with `mirrored' VGA ports
1062 * and other strange ISA hardware, so we always want the
1063 * addresses to be allocated in the 0x000-0x0ff region
1066 * Why? Because some silly external IO cards only decode
1067 * the low 10 bits of the IO address. The 0x00-0xff region
1068 * is reserved for motherboard devices that decode all 16
1069 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1070 * but we want to try to avoid allocating at 0x2900-0x2bff
1071 * which might have be mirrored at 0x0100-0x03ff..
1073 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1074 resource_size_t size, resource_size_t align)
1076 struct pci_dev *dev = data;
1077 resource_size_t start = res->start;
1079 if (res->flags & IORESOURCE_IO) {
1080 if (skip_isa_ioresource_align(dev))
1083 start = (start + 0x3ff) & ~0x3ff;
1088 EXPORT_SYMBOL(pcibios_align_resource);
1091 * Reparent resource children of pr that conflict with res
1092 * under res, and make res replace those children.
1094 static int reparent_resources(struct resource *parent,
1095 struct resource *res)
1097 struct resource *p, **pp;
1098 struct resource **firstpp = NULL;
1100 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1101 if (p->end < res->start)
1103 if (res->end < p->start)
1105 if (p->start < res->start || p->end > res->end)
1106 return -1; /* not completely contained */
1107 if (firstpp == NULL)
1110 if (firstpp == NULL)
1111 return -1; /* didn't find any conflicting entries? */
1112 res->parent = parent;
1113 res->child = *firstpp;
1117 for (p = res->child; p != NULL; p = p->sibling) {
1119 pr_debug("PCI: Reparented %s %pR under %s\n",
1120 p->name, p, res->name);
1126 * Handle resources of PCI devices. If the world were perfect, we could
1127 * just allocate all the resource regions and do nothing more. It isn't.
1128 * On the other hand, we cannot just re-allocate all devices, as it would
1129 * require us to know lots of host bridge internals. So we attempt to
1130 * keep as much of the original configuration as possible, but tweak it
1131 * when it's found to be wrong.
1133 * Known BIOS problems we have to work around:
1134 * - I/O or memory regions not configured
1135 * - regions configured, but not enabled in the command register
1136 * - bogus I/O addresses above 64K used
1137 * - expansion ROMs left enabled (this may sound harmless, but given
1138 * the fact the PCI specs explicitly allow address decoders to be
1139 * shared between expansion ROMs and other resource regions, it's
1140 * at least dangerous)
1143 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1144 * This gives us fixed barriers on where we can allocate.
1145 * (2) Allocate resources for all enabled devices. If there is
1146 * a collision, just mark the resource as unallocated. Also
1147 * disable expansion ROMs during this step.
1148 * (3) Try to allocate resources for disabled devices. If the
1149 * resources were assigned correctly, everything goes well,
1150 * if they weren't, they won't disturb allocation of other
1152 * (4) Assign new addresses to resources which were either
1153 * not configured at all or misconfigured. If explicitly
1154 * requested by the user, configure expansion ROM address
1158 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1162 struct resource *res, *pr;
1164 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1165 pci_domain_nr(bus), bus->number);
1167 pci_bus_for_each_resource(bus, res, i) {
1168 if (!res || !res->flags || res->start > res->end || res->parent)
1171 /* If the resource was left unset at this point, we clear it */
1172 if (res->flags & IORESOURCE_UNSET)
1173 goto clear_resource;
1175 if (bus->parent == NULL)
1176 pr = (res->flags & IORESOURCE_IO) ?
1177 &ioport_resource : &iomem_resource;
1179 pr = pci_find_parent_resource(bus->self, res);
1181 /* this happens when the generic PCI
1182 * code (wrongly) decides that this
1183 * bridge is transparent -- paulus
1189 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1190 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1191 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1193 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1194 struct pci_dev *dev = bus->self;
1196 if (request_resource(pr, res) == 0)
1199 * Must be a conflict with an existing entry.
1200 * Move that entry (or entries) under the
1201 * bridge resource and try again.
1203 if (reparent_resources(pr, res) == 0)
1206 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1207 pci_claim_bridge_resource(dev,
1208 i + PCI_BRIDGE_RESOURCES) == 0)
1211 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1214 /* The resource might be figured out when doing
1215 * reassignment based on the resources required
1216 * by the downstream PCI devices. Here we set
1217 * the size of the resource to be 0 in order to
1225 list_for_each_entry(b, &bus->children, node)
1226 pcibios_allocate_bus_resources(b);
1229 static inline void alloc_resource(struct pci_dev *dev, int idx)
1231 struct resource *pr, *r = &dev->resource[idx];
1233 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1234 pci_name(dev), idx, r);
1236 pr = pci_find_parent_resource(dev, r);
1237 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1238 request_resource(pr, r) < 0) {
1239 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1240 " of device %s, will remap\n", idx, pci_name(dev));
1242 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1243 /* We'll assign a new address later */
1244 r->flags |= IORESOURCE_UNSET;
1250 static void __init pcibios_allocate_resources(int pass)
1252 struct pci_dev *dev = NULL;
1257 for_each_pci_dev(dev) {
1258 pci_read_config_word(dev, PCI_COMMAND, &command);
1259 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1260 r = &dev->resource[idx];
1261 if (r->parent) /* Already allocated */
1263 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1264 continue; /* Not assigned at all */
1265 /* We only allocate ROMs on pass 1 just in case they
1266 * have been screwed up by firmware
1268 if (idx == PCI_ROM_RESOURCE )
1270 if (r->flags & IORESOURCE_IO)
1271 disabled = !(command & PCI_COMMAND_IO);
1273 disabled = !(command & PCI_COMMAND_MEMORY);
1274 if (pass == disabled)
1275 alloc_resource(dev, idx);
1279 r = &dev->resource[PCI_ROM_RESOURCE];
1281 /* Turn the ROM off, leave the resource region,
1282 * but keep it unregistered.
1285 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1286 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1287 pr_debug("PCI: Switching off ROM of %s\n",
1289 r->flags &= ~IORESOURCE_ROM_ENABLE;
1290 pci_write_config_dword(dev, dev->rom_base_reg,
1291 reg & ~PCI_ROM_ADDRESS_ENABLE);
1297 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1299 struct pci_controller *hose = pci_bus_to_host(bus);
1300 resource_size_t offset;
1301 struct resource *res, *pres;
1304 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1307 if (!(hose->io_resource.flags & IORESOURCE_IO))
1309 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1310 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1311 BUG_ON(res == NULL);
1312 res->name = "Legacy IO";
1313 res->flags = IORESOURCE_IO;
1314 res->start = offset;
1315 res->end = (offset + 0xfff) & 0xfffffffful;
1316 pr_debug("Candidate legacy IO: %pR\n", res);
1317 if (request_resource(&hose->io_resource, res)) {
1319 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1320 pci_domain_nr(bus), bus->number, res);
1325 /* Check for memory */
1326 for (i = 0; i < 3; i++) {
1327 pres = &hose->mem_resources[i];
1328 offset = hose->mem_offset[i];
1329 if (!(pres->flags & IORESOURCE_MEM))
1331 pr_debug("hose mem res: %pR\n", pres);
1332 if ((pres->start - offset) <= 0xa0000 &&
1333 (pres->end - offset) >= 0xbffff)
1338 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1339 BUG_ON(res == NULL);
1340 res->name = "Legacy VGA memory";
1341 res->flags = IORESOURCE_MEM;
1342 res->start = 0xa0000 + offset;
1343 res->end = 0xbffff + offset;
1344 pr_debug("Candidate VGA memory: %pR\n", res);
1345 if (request_resource(pres, res)) {
1347 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1348 pci_domain_nr(bus), bus->number, res);
1353 void __init pcibios_resource_survey(void)
1357 /* Allocate and assign resources */
1358 list_for_each_entry(b, &pci_root_buses, node)
1359 pcibios_allocate_bus_resources(b);
1360 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1361 pcibios_allocate_resources(0);
1362 pcibios_allocate_resources(1);
1365 /* Before we start assigning unassigned resource, we try to reserve
1366 * the low IO area and the VGA memory area if they intersect the
1367 * bus available resources to avoid allocating things on top of them
1369 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1370 list_for_each_entry(b, &pci_root_buses, node)
1371 pcibios_reserve_legacy_regions(b);
1374 /* Now, if the platform didn't decide to blindly trust the firmware,
1375 * we proceed to assigning things that were left unassigned
1377 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1378 pr_debug("PCI: Assigning unassigned resources...\n");
1379 pci_assign_unassigned_resources();
1382 /* Call machine dependent fixup */
1383 if (ppc_md.pcibios_fixup)
1384 ppc_md.pcibios_fixup();
1387 /* This is used by the PCI hotplug driver to allocate resource
1388 * of newly plugged busses. We can try to consolidate with the
1389 * rest of the code later, for now, keep it as-is as our main
1390 * resource allocation function doesn't deal with sub-trees yet.
1392 void pcibios_claim_one_bus(struct pci_bus *bus)
1394 struct pci_dev *dev;
1395 struct pci_bus *child_bus;
1397 list_for_each_entry(dev, &bus->devices, bus_list) {
1400 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1401 struct resource *r = &dev->resource[i];
1403 if (r->parent || !r->start || !r->flags)
1406 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1407 pci_name(dev), i, r);
1409 if (pci_claim_resource(dev, i) == 0)
1412 pci_claim_bridge_resource(dev, i);
1416 list_for_each_entry(child_bus, &bus->children, node)
1417 pcibios_claim_one_bus(child_bus);
1419 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1422 /* pcibios_finish_adding_to_bus
1424 * This is to be called by the hotplug code after devices have been
1425 * added to a bus, this include calling it for a PHB that is just
1428 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1430 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1431 pci_domain_nr(bus), bus->number);
1433 /* Allocate bus and devices resources */
1434 pcibios_allocate_bus_resources(bus);
1435 pcibios_claim_one_bus(bus);
1436 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1438 pci_assign_unassigned_bridge_resources(bus->self);
1440 pci_assign_unassigned_bus_resources(bus);
1444 eeh_add_device_tree_late(bus);
1446 /* Add new devices to global lists. Register in proc, sysfs. */
1447 pci_bus_add_devices(bus);
1449 /* sysfs files should only be added after devices are added */
1450 eeh_add_sysfs_files(bus);
1452 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1454 int pcibios_enable_device(struct pci_dev *dev, int mask)
1456 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1458 if (phb->controller_ops.enable_device_hook)
1459 if (!phb->controller_ops.enable_device_hook(dev))
1462 return pci_enable_resources(dev, mask);
1465 void pcibios_disable_device(struct pci_dev *dev)
1467 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1469 if (phb->controller_ops.disable_device)
1470 phb->controller_ops.disable_device(dev);
1473 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1475 return (unsigned long) hose->io_base_virt - _IO_BASE;
1478 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1479 struct list_head *resources)
1481 struct resource *res;
1482 resource_size_t offset;
1485 /* Hookup PHB IO resource */
1486 res = &hose->io_resource;
1489 pr_debug("PCI: I/O resource not set for host"
1490 " bridge %pOF (domain %d)\n",
1491 hose->dn, hose->global_number);
1493 offset = pcibios_io_space_offset(hose);
1495 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1496 res, (unsigned long long)offset);
1497 pci_add_resource_offset(resources, res, offset);
1500 /* Hookup PHB Memory resources */
1501 for (i = 0; i < 3; ++i) {
1502 res = &hose->mem_resources[i];
1506 offset = hose->mem_offset[i];
1507 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1508 res, (unsigned long long)offset);
1510 pci_add_resource_offset(resources, res, offset);
1515 * Null PCI config access functions, for the case when we can't
1518 #define NULL_PCI_OP(rw, size, type) \
1520 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1522 return PCIBIOS_DEVICE_NOT_FOUND; \
1526 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1529 return PCIBIOS_DEVICE_NOT_FOUND;
1533 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1536 return PCIBIOS_DEVICE_NOT_FOUND;
1539 static struct pci_ops null_pci_ops =
1541 .read = null_read_config,
1542 .write = null_write_config,
1546 * These functions are used early on before PCI scanning is done
1547 * and all of the pci_dev and pci_bus structures have been created.
1549 static struct pci_bus *
1550 fake_pci_bus(struct pci_controller *hose, int busnr)
1552 static struct pci_bus bus;
1555 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1559 bus.ops = hose? hose->ops: &null_pci_ops;
1563 #define EARLY_PCI_OP(rw, size, type) \
1564 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1565 int devfn, int offset, type value) \
1567 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1568 devfn, offset, value); \
1571 EARLY_PCI_OP(read, byte, u8 *)
1572 EARLY_PCI_OP(read, word, u16 *)
1573 EARLY_PCI_OP(read, dword, u32 *)
1574 EARLY_PCI_OP(write, byte, u8)
1575 EARLY_PCI_OP(write, word, u16)
1576 EARLY_PCI_OP(write, dword, u32)
1578 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1581 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1584 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1586 struct pci_controller *hose = bus->sysdata;
1588 return of_node_get(hose->dn);
1592 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1593 * @hose: Pointer to the PCI host controller instance structure
1595 void pcibios_scan_phb(struct pci_controller *hose)
1597 LIST_HEAD(resources);
1598 struct pci_bus *bus;
1599 struct device_node *node = hose->dn;
1602 pr_debug("PCI: Scanning PHB %pOF\n", node);
1604 /* Get some IO space for the new PHB */
1605 pcibios_setup_phb_io_space(hose);
1607 /* Wire up PHB bus resources */
1608 pcibios_setup_phb_resources(hose, &resources);
1610 hose->busn.start = hose->first_busno;
1611 hose->busn.end = hose->last_busno;
1612 hose->busn.flags = IORESOURCE_BUS;
1613 pci_add_resource(&resources, &hose->busn);
1615 /* Create an empty bus for the toplevel */
1616 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1617 hose->ops, hose, &resources);
1619 pr_err("Failed to create bus for PCI domain %04x\n",
1620 hose->global_number);
1621 pci_free_resource_list(&resources);
1626 /* Get probe mode and perform scan */
1627 mode = PCI_PROBE_NORMAL;
1628 if (node && hose->controller_ops.probe_mode)
1629 mode = hose->controller_ops.probe_mode(bus);
1630 pr_debug(" probe mode: %d\n", mode);
1631 if (mode == PCI_PROBE_DEVTREE)
1632 of_scan_bus(node, bus);
1634 if (mode == PCI_PROBE_NORMAL) {
1635 pci_bus_update_busn_res_end(bus, 255);
1636 hose->last_busno = pci_scan_child_bus(bus);
1637 pci_bus_update_busn_res_end(bus, hose->last_busno);
1640 /* Platform gets a chance to do some global fixups before
1641 * we proceed to resource allocation
1643 if (ppc_md.pcibios_fixup_phb)
1644 ppc_md.pcibios_fixup_phb(hose);
1646 /* Configure PCI Express settings */
1647 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1648 struct pci_bus *child;
1649 list_for_each_entry(child, &bus->children, node)
1650 pcie_bus_configure_settings(child);
1653 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1655 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1657 int i, class = dev->class >> 8;
1658 /* When configured as agent, programing interface = 1 */
1659 int prog_if = dev->class & 0xf;
1661 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1662 class == PCI_CLASS_BRIDGE_OTHER) &&
1663 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1665 (dev->bus->parent == NULL)) {
1666 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1667 dev->resource[i].start = 0;
1668 dev->resource[i].end = 0;
1669 dev->resource[i].flags = 0;
1673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);