2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include <asm/ptrace.h>
45 #include <asm/export.h>
46 #include <asm/feature-fixups.h>
47 #include "head_booke.h"
49 /* As with the other PowerPC ports, it is expected that when code
50 * execution begins here, the following registers contain valid, yet
51 * optional, information:
53 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
54 * r4 - Starting address of the init RAM disk
55 * r5 - Ending address of the init RAM disk
56 * r6 - Start of kernel command line string (e.g. "mem=128")
57 * r7 - End of kernel command line string
64 * Reserve a word at a fixed location to store the address
69 /* Translate device tree address to physical, save in r30/r31 */
74 li r25,0 /* phys kernel start (low) */
75 li r24,0 /* CPU number */
76 li r23,0 /* phys kernel start (high) */
78 #ifdef CONFIG_RELOCATABLE
79 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
81 /* Translate _stext address to physical, save in r23/r25 */
88 addis r3,r8,(is_second_reloc - 0b)@ha
89 lwz r19,(is_second_reloc - 0b)@l(r3)
91 /* Check if this is the second relocation. */
96 * For the second relocation, we already get the real memstart_addr
97 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
98 * then the virtual address of start kernel should be:
99 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
100 * Since the offset between kernstart_addr and memstart_addr should
101 * never be beyond 1G, so we can just use the lower 32bit of them
102 * for the calculation.
106 addis r4,r8,(kernstart_addr - 0b)@ha
107 addi r4,r4,(kernstart_addr - 0b)@l
110 addis r6,r8,(memstart_addr - 0b)@ha
111 addi r6,r6,(memstart_addr - 0b)@l
120 * We have the runtime (virutal) address of our base.
121 * We calculate our shift of offset from a 64M page.
122 * We could map the 64M page we belong to at PAGE_OFFSET and
123 * get going from there.
126 ori r4,r4,KERNELBASE@l
127 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
128 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
129 subf r3,r5,r6 /* r3 = r6 - r5 */
130 add r3,r4,r3 /* Required Virtual Address */
135 * For the second relocation, we already set the right tlb entries
136 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
142 /* We try to not make any assumptions about how the boot loader
143 * setup or used the TLBs. We invalidate all mappings from the
144 * boot loader and load a single entry in TLB1[0] to map the
145 * first 64M of kernel memory. Any boot info passed from the
146 * bootloader needs to live in this first 64M.
148 * Requirement on bootloader:
149 * - The page we're executing in needs to reside in TLB1 and
150 * have IPROT=1. If not an invalidate broadcast could
151 * evict the entry we're currently executing in.
153 * r3 = Index of TLB1 were executing in
154 * r4 = Current MSR[IS]
155 * r5 = Index of TLB1 temp mapping
157 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
161 _ENTRY(__early_start)
163 #define ENTRY_MAPPING_BOOT_SETUP
164 #include "fsl_booke_entry_mapping.S"
165 #undef ENTRY_MAPPING_BOOT_SETUP
168 /* Establish the interrupt vector offsets */
169 SET_IVOR(0, CriticalInput);
170 SET_IVOR(1, MachineCheck);
171 SET_IVOR(2, DataStorage);
172 SET_IVOR(3, InstructionStorage);
173 SET_IVOR(4, ExternalInput);
174 SET_IVOR(5, Alignment);
175 SET_IVOR(6, Program);
176 SET_IVOR(7, FloatingPointUnavailable);
177 SET_IVOR(8, SystemCall);
178 SET_IVOR(9, AuxillaryProcessorUnavailable);
179 SET_IVOR(10, Decrementer);
180 SET_IVOR(11, FixedIntervalTimer);
181 SET_IVOR(12, WatchdogTimer);
182 SET_IVOR(13, DataTLBError);
183 SET_IVOR(14, InstructionTLBError);
184 SET_IVOR(15, DebugCrit);
186 /* Establish the interrupt vector base */
187 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
190 /* Setup the defaults for TLB entries */
191 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
193 oris r2,r2,MAS4_TLBSELD(1)@h
197 #if !defined(CONFIG_BDI_SWITCH)
199 * The Abatron BDI JTAG debugger does not tolerate others
200 * mucking with the debug registers.
205 /* clear any residual debug events */
211 /* Check to see if we're the second processor, and jump
212 * to the secondary_start code if so
214 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
218 bne __secondary_start
222 * This is where the main kernel code starts.
227 ori r2,r2,init_task@l
229 /* ptr to current thread */
230 addi r4,r2,THREAD /* init task's THREAD */
231 mtspr SPRN_SPRG_THREAD,r4
234 lis r1,init_thread_union@h
235 ori r1,r1,init_thread_union@l
237 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
240 stw r24, TASK_CPU(r2)
245 #ifdef CONFIG_RELOCATABLE
248 #ifdef CONFIG_PHYS_64BIT
257 #ifdef CONFIG_DYNAMIC_MEMSTART
258 lis r3,kernstart_addr@ha
259 la r3,kernstart_addr@l(r3)
260 #ifdef CONFIG_PHYS_64BIT
269 * Decide what sort of machine this is and initialize the MMU.
279 /* Setup PTE pointers for the Abatron bdiGDB */
280 lis r6, swapper_pg_dir@h
281 ori r6, r6, swapper_pg_dir@l
282 lis r5, abatron_pteptrs@h
283 ori r5, r5, abatron_pteptrs@l
285 ori r4, r4, KERNELBASE@l
286 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
290 lis r4,start_kernel@h
291 ori r4,r4,start_kernel@l
293 ori r3,r3,MSR_KERNEL@l
296 rfi /* change context and jump to start_kernel */
298 /* Macros to hide the PTE size differences
300 * FIND_PTE -- walks the page tables given EA & pgdir pointer
302 * r11 -- PGDIR pointer
304 * label 2: is the bailout case
306 * if we find the pte (fall through):
307 * r11 is low pte word
308 * r12 is pointer to the pte
309 * r10 is the pshift from the PGD, if we're a hugepage
311 #ifdef CONFIG_PTE_64BIT
312 #ifdef CONFIG_HUGETLB_PAGE
314 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
315 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
316 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
317 blt 1000f; /* Normal non-huge page */ \
318 beq 2f; /* Bail if no table */ \
319 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
320 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
321 xor r12, r10, r11; /* drop size bits from pointer */ \
323 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
324 li r10, 0; /* clear r10 */ \
325 1001: lwz r11, 4(r12); /* Get pte entry */
328 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
329 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
330 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
331 beq 2f; /* Bail if no table */ \
332 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
333 lwz r11, 4(r12); /* Get pte entry */
334 #endif /* HUGEPAGE */
335 #else /* !PTE_64BIT */
337 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
338 lwz r11, 0(r11); /* Get L1 entry */ \
339 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
340 beq 2f; /* Bail if no table */ \
341 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
342 lwz r11, 0(r12); /* Get Linux PTE */
346 * Interrupt vector entry code
348 * The Book E MMUs are always on so we don't need to handle
349 * interrupts in real mode as with previous PPC processors. In
350 * this case we handle interrupts in the kernel virtual address
353 * Interrupt vectors are dynamically placed relative to the
354 * interrupt prefix as determined by the address of interrupt_base.
355 * The interrupt vectors offsets are programmed using the labels
356 * for each interrupt vector entry.
358 * Interrupt vectors must be aligned on a 16 byte boundary.
359 * We align on a 32 byte cache line boundary for good measure.
363 /* Critical Input Interrupt */
364 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
366 /* Machine Check Interrupt */
368 /* no RFMCI, MCSRRs on E200 */
369 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
370 machine_check_exception)
372 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
375 /* Data Storage Interrupt */
376 START_EXCEPTION(DataStorage)
377 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
378 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
380 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
381 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
383 EXC_XFER_LITE(0x0300, handle_page_fault)
385 addi r3,r1,STACK_FRAME_OVERHEAD
386 EXC_XFER_LITE(0x0300, CacheLockingException)
388 /* Instruction Storage Interrupt */
389 INSTRUCTION_STORAGE_EXCEPTION
391 /* External Input Interrupt */
392 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
394 /* Alignment Interrupt */
397 /* Program Interrupt */
400 /* Floating Point Unavailable Interrupt */
401 #ifdef CONFIG_PPC_FPU
402 FP_UNAVAILABLE_EXCEPTION
405 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
406 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
407 program_check_exception, EXC_XFER_STD)
409 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
410 unknown_exception, EXC_XFER_STD)
414 /* System Call Interrupt */
415 START_EXCEPTION(SystemCall)
416 SYSCALL_ENTRY 0xc00 SYSCALL
418 /* Auxiliary Processor Unavailable Interrupt */
419 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
420 unknown_exception, EXC_XFER_STD)
422 /* Decrementer Interrupt */
423 DECREMENTER_EXCEPTION
425 /* Fixed Internal Timer Interrupt */
426 /* TODO: Add FIT support */
427 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
428 unknown_exception, EXC_XFER_STD)
430 /* Watchdog Timer Interrupt */
431 #ifdef CONFIG_BOOKE_WDT
432 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
434 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
437 /* Data TLB Error Interrupt */
438 START_EXCEPTION(DataTLBError)
439 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
440 mfspr r10, SPRN_SPRG_THREAD
441 stw r11, THREAD_NORMSAVE(0)(r10)
442 #ifdef CONFIG_KVM_BOOKE_HV
445 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
447 stw r12, THREAD_NORMSAVE(1)(r10)
448 stw r13, THREAD_NORMSAVE(2)(r10)
450 stw r13, THREAD_NORMSAVE(3)(r10)
451 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
452 START_BTB_FLUSH_SECTION
458 END_BTB_FLUSH_SECTION
459 mfspr r10, SPRN_DEAR /* Get faulting address */
461 /* If we are faulting a kernel address, we have to use the
462 * kernel page tables.
464 lis r11, PAGE_OFFSET@h
467 lis r11, swapper_pg_dir@h
468 ori r11, r11, swapper_pg_dir@l
470 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
471 rlwinm r12,r12,0,16,1
476 /* Get the PGD for the current thread */
478 mfspr r11,SPRN_SPRG_THREAD
482 /* Mask of required permission bits. Note that while we
483 * do copy ESR:ST to _PAGE_RW position as trying to write
484 * to an RO page is pretty common, we don't do it with
485 * _PAGE_DIRTY. We could do it, but it's a fairly rare
486 * event so I'd rather take the overhead when it happens
487 * rather than adding an instruction here. We should measure
488 * whether the whole thing is worth it in the first place
489 * as we could avoid loading SPRN_ESR completely in the first
492 * TODO: Is it worth doing that mfspr & rlwimi in the first
493 * place or can we save a couple of instructions here ?
496 #ifdef CONFIG_PTE_64BIT
498 oris r13,r13,_PAGE_ACCESSED@h
500 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
502 rlwimi r13,r12,11,29,29
505 andc. r13,r13,r11 /* Check permission */
507 #ifdef CONFIG_PTE_64BIT
509 subf r13,r11,r12 /* create false data dep */
510 lwzx r13,r11,r13 /* Get upper pte bits */
512 lwz r13,0(r12) /* Get upper pte bits */
516 bne 2f /* Bail if permission/valid mismach */
518 /* Jump to common tlb load */
521 /* The bailout. Restore registers to pre-exception conditions
522 * and call the heavyweights to help us out.
524 mfspr r10, SPRN_SPRG_THREAD
525 lwz r11, THREAD_NORMSAVE(3)(r10)
527 lwz r13, THREAD_NORMSAVE(2)(r10)
528 lwz r12, THREAD_NORMSAVE(1)(r10)
529 lwz r11, THREAD_NORMSAVE(0)(r10)
530 mfspr r10, SPRN_SPRG_RSCRATCH0
533 /* Instruction TLB Error Interrupt */
535 * Nearly the same as above, except we get our
536 * information from different registers and bailout
537 * to a different point.
539 START_EXCEPTION(InstructionTLBError)
540 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
541 mfspr r10, SPRN_SPRG_THREAD
542 stw r11, THREAD_NORMSAVE(0)(r10)
543 #ifdef CONFIG_KVM_BOOKE_HV
546 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
548 stw r12, THREAD_NORMSAVE(1)(r10)
549 stw r13, THREAD_NORMSAVE(2)(r10)
551 stw r13, THREAD_NORMSAVE(3)(r10)
552 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
553 START_BTB_FLUSH_SECTION
559 END_BTB_FLUSH_SECTION
561 mfspr r10, SPRN_SRR0 /* Get faulting address */
563 /* If we are faulting a kernel address, we have to use the
564 * kernel page tables.
566 lis r11, PAGE_OFFSET@h
569 lis r11, swapper_pg_dir@h
570 ori r11, r11, swapper_pg_dir@l
572 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
573 rlwinm r12,r12,0,16,1
576 /* Make up the required permissions for kernel code */
577 #ifdef CONFIG_PTE_64BIT
578 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
579 oris r13,r13,_PAGE_ACCESSED@h
581 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
585 /* Get the PGD for the current thread */
587 mfspr r11,SPRN_SPRG_THREAD
590 /* Make up the required permissions for user code */
591 #ifdef CONFIG_PTE_64BIT
592 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
593 oris r13,r13,_PAGE_ACCESSED@h
595 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
600 andc. r13,r13,r11 /* Check permission */
602 #ifdef CONFIG_PTE_64BIT
604 subf r13,r11,r12 /* create false data dep */
605 lwzx r13,r11,r13 /* Get upper pte bits */
607 lwz r13,0(r12) /* Get upper pte bits */
611 bne 2f /* Bail if permission mismach */
613 /* Jump to common TLB load point */
617 /* The bailout. Restore registers to pre-exception conditions
618 * and call the heavyweights to help us out.
620 mfspr r10, SPRN_SPRG_THREAD
621 lwz r11, THREAD_NORMSAVE(3)(r10)
623 lwz r13, THREAD_NORMSAVE(2)(r10)
624 lwz r12, THREAD_NORMSAVE(1)(r10)
625 lwz r11, THREAD_NORMSAVE(0)(r10)
626 mfspr r10, SPRN_SPRG_RSCRATCH0
629 /* Define SPE handlers for e200 and e500v2 */
631 /* SPE Unavailable */
632 START_EXCEPTION(SPEUnavailable)
633 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
636 b fast_exception_return
637 1: addi r3,r1,STACK_FRAME_OVERHEAD
638 EXC_XFER_LITE(0x2010, KernelSPE)
639 #elif defined(CONFIG_SPE_POSSIBLE)
640 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
641 unknown_exception, EXC_XFER_STD)
642 #endif /* CONFIG_SPE_POSSIBLE */
644 /* SPE Floating Point Data */
646 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
647 SPEFloatingPointException, EXC_XFER_STD)
649 /* SPE Floating Point Round */
650 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
651 SPEFloatingPointRoundException, EXC_XFER_STD)
652 #elif defined(CONFIG_SPE_POSSIBLE)
653 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
654 unknown_exception, EXC_XFER_STD)
655 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
656 unknown_exception, EXC_XFER_STD)
657 #endif /* CONFIG_SPE_POSSIBLE */
660 /* Performance Monitor */
661 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
662 performance_monitor_exception, EXC_XFER_STD)
664 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
666 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
667 CriticalDoorbell, unknown_exception)
669 /* Debug Interrupt */
670 DEBUG_DEBUG_EXCEPTION
673 GUEST_DOORBELL_EXCEPTION
675 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
679 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_STD)
681 /* Embedded Hypervisor Privilege */
682 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_STD)
691 * Both the instruction and data TLB miss get to this
692 * point to load the TLB.
693 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
694 * r11 - TLB (info from Linux PTE)
695 * r12 - available to use
696 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
697 * CR5 - results of addr >= PAGE_OFFSET
698 * MAS0, MAS1 - loaded with proper value when we get here
699 * MAS2, MAS3 - will need additional info from Linux PTE
700 * Upon exit, we reload everything and RFI.
703 #ifdef CONFIG_HUGETLB_PAGE
704 cmpwi 6, r10, 0 /* check for huge page */
705 beq 6, finish_tlb_load_cont /* !huge */
707 /* Alas, we need more scratch registers for hugepages */
708 mfspr r12, SPRN_SPRG_THREAD
709 stw r14, THREAD_NORMSAVE(4)(r12)
710 stw r15, THREAD_NORMSAVE(5)(r12)
711 stw r16, THREAD_NORMSAVE(6)(r12)
712 stw r17, THREAD_NORMSAVE(7)(r12)
714 /* Get the next_tlbcam_idx percpu var */
716 lwz r15, TASK_CPU-THREAD(r12)
717 lis r14, __per_cpu_offset@h
718 ori r14, r14, __per_cpu_offset@l
719 rlwinm r15, r15, 2, 0, 29
724 lis r17, next_tlbcam_idx@h
725 ori r17, r17, next_tlbcam_idx@l
726 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
727 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
729 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
730 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
733 /* Extract TLB1CFG(NENTRY) */
734 mfspr r16, SPRN_TLB1CFG
735 andi. r16, r16, 0xfff
737 /* Update next_tlbcam_idx, wrapping when necessary */
741 lis r14, tlbcam_index@h
742 ori r14, r14, tlbcam_index@l
747 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
748 * tlb_enc = (pshift - 10).
752 rlwimi r16, r15, 7, 20, 24
755 /* copy the pshift for use later */
760 #endif /* CONFIG_HUGETLB_PAGE */
763 * We set execute, because we don't have the granularity to
764 * properly set this at the page level (Linux problem).
765 * Many of these bits are software only. Bits we don't set
766 * here we (properly should) assume have the appropriate value.
768 finish_tlb_load_cont:
769 #ifdef CONFIG_PTE_64BIT
770 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
771 andi. r10, r11, _PAGE_DIRTY
773 li r10, MAS3_SW | MAS3_UW
775 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
776 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
777 2: mtspr SPRN_MAS3, r12
778 BEGIN_MMU_FTR_SECTION
779 srwi r10, r13, 12 /* grab RPN[12:31] */
781 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
783 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
785 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
787 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
791 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
796 #ifdef CONFIG_PTE_64BIT
797 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
799 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
801 #ifdef CONFIG_HUGETLB_PAGE
802 beq 6, 3f /* don't mask if page isn't huge */
806 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
807 andc r12, r12, r13 /* mask off ea bits within the page */
809 3: mtspr SPRN_MAS2, r12
812 /* Round robin TLB1 entries assignment */
815 /* Extract TLB1CFG(NENTRY) */
816 mfspr r11, SPRN_TLB1CFG
817 andi. r11, r11, 0xfff
819 /* Extract MAS0(NV) */
820 andi. r13, r12, 0xfff
825 /* check if we need to wrap */
828 /* wrap back to first free tlbcam entry */
829 lis r13, tlbcam_index@ha
830 lwz r13, tlbcam_index@l(r13)
831 rlwimi r12, r13, 0, 20, 31
834 #endif /* CONFIG_E200 */
839 /* Done...restore registers and get out of here. */
840 mfspr r10, SPRN_SPRG_THREAD
841 #ifdef CONFIG_HUGETLB_PAGE
842 beq 6, 8f /* skip restore for 4k page faults */
843 lwz r14, THREAD_NORMSAVE(4)(r10)
844 lwz r15, THREAD_NORMSAVE(5)(r10)
845 lwz r16, THREAD_NORMSAVE(6)(r10)
846 lwz r17, THREAD_NORMSAVE(7)(r10)
848 8: lwz r11, THREAD_NORMSAVE(3)(r10)
850 lwz r13, THREAD_NORMSAVE(2)(r10)
851 lwz r12, THREAD_NORMSAVE(1)(r10)
852 lwz r11, THREAD_NORMSAVE(0)(r10)
853 mfspr r10, SPRN_SPRG_RSCRATCH0
854 rfi /* Force context change */
857 /* Note that the SPE support is closely modeled after the AltiVec
858 * support. Changes to one are likely to be applicable to the
862 * Disable SPE for the task which had SPE previously,
863 * and save its SPE registers in its thread_struct.
864 * Enables SPE for use in the kernel on return.
865 * On SMP we know the SPE units are free, since we give it up every
870 mtmsr r5 /* enable use of SPE now */
872 /* enable use of SPE after return */
874 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
877 stw r4,THREAD_USED_SPE(r5)
880 REST_32EVRS(0,r10,r5,THREAD_EVR0)
884 * SPE unavailable trap from kernel - print a message, but let
885 * the task use SPE in the kernel until it returns to user mode.
890 stw r3,_MSR(r1) /* enable use of SPE after return */
894 mr r4,r2 /* current */
900 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
904 #endif /* CONFIG_SPE */
907 * Translate the effec addr in r3 to phys addr. The phys addr will be put
908 * into r3(higher 32bit) and r4(lower 32bit)
913 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
914 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
917 tlbsx 0,r3 /* must succeed */
921 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
923 slw r10,r10,r9 /* r10 = page size */
925 and r11,r3,r10 /* r11 = page offset */
926 andc r4,r12,r10 /* r4 = page base */
927 or r4,r4,r11 /* r4 = devtree phys addr */
928 #ifdef CONFIG_PHYS_64BIT
938 /* Adjust or setup IVORs for e200 */
939 _GLOBAL(__setup_e200_ivors)
942 li r3,SPEUnavailable@l
944 li r3,SPEFloatingPointData@l
946 li r3,SPEFloatingPointRound@l
953 #ifndef CONFIG_PPC_E500MC
954 /* Adjust or setup IVORs for e500v1/v2 */
955 _GLOBAL(__setup_e500_ivors)
958 li r3,SPEUnavailable@l
960 li r3,SPEFloatingPointData@l
962 li r3,SPEFloatingPointRound@l
964 li r3,PerformanceMonitor@l
969 /* Adjust or setup IVORs for e500mc */
970 _GLOBAL(__setup_e500mc_ivors)
973 li r3,PerformanceMonitor@l
977 li r3,CriticalDoorbell@l
982 /* setup ehv ivors for */
983 _GLOBAL(__setup_ehv_ivors)
984 li r3,GuestDoorbell@l
986 li r3,CriticalGuestDoorbell@l
994 #endif /* CONFIG_PPC_E500MC */
995 #endif /* CONFIG_E500 */
999 * extern void __giveup_spe(struct task_struct *prev)
1002 _GLOBAL(__giveup_spe)
1003 addi r3,r3,THREAD /* want THREAD of task */
1006 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1007 evxor evr6, evr6, evr6 /* clear out evr6 */
1008 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1010 evstddx evr6, r4, r3 /* save off accumulator */
1012 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1014 andc r4,r4,r3 /* disable SPE for previous task */
1015 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1018 #endif /* CONFIG_SPE */
1021 * extern void abort(void)
1023 * At present, this routine just applies a system reset.
1027 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1030 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1033 mfspr r13,SPRN_DBCR0
1034 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1035 mtspr SPRN_DBCR0,r13
1038 _GLOBAL(set_context)
1040 #ifdef CONFIG_BDI_SWITCH
1041 /* Context switch the PTE pointer for the Abatron BDI2000.
1042 * The PGDIR is the second parameter.
1044 lis r5, abatron_pteptrs@h
1045 ori r5, r5, abatron_pteptrs@l
1049 isync /* Force context change */
1053 /* When we get here, r24 needs to hold the CPU # */
1054 .globl __secondary_start
1056 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1059 li r26,0 /* r26 safe? */
1062 mr r27,r3 /* tlb entry */
1063 /* Load each CAM entry */
1068 mr r3,r27 /* tlb entry */
1069 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1071 mr r5,r25 /* phys kernel start */
1072 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1073 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1074 li r5,0 /* no device tree */
1075 li r6,0 /* not boot cpu */
1079 lis r3,__secondary_hold_acknowledge@h
1080 ori r3,r3,__secondary_hold_acknowledge@l
1084 mr r4,r24 /* Why? */
1087 /* get current's stack and current */
1088 lis r2,secondary_current@ha
1089 lwz r2,secondary_current@l(r2)
1090 lwz r1,TASK_STACK(r2)
1093 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1097 /* ptr to current thread */
1098 addi r4,r2,THREAD /* address of our thread_struct */
1099 mtspr SPRN_SPRG_THREAD,r4
1101 /* Setup the defaults for TLB entries */
1102 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1105 /* Jump to start_secondary */
1107 ori r4,r4,MSR_KERNEL@l
1108 lis r3,start_secondary@h
1109 ori r3,r3,start_secondary@l
1116 .globl __secondary_hold_acknowledge
1117 __secondary_hold_acknowledge:
1122 * Create a tlb entry with the same effective and physical address as
1123 * the tlb entry used by the current running code. But set the TS to 1.
1124 * Then switch to the address space 1. It will return with the r3 set to
1125 * the ESEL of the new created tlb.
1127 _GLOBAL(switch_to_as1)
1130 /* Find a entry not used */
1131 mfspr r3,SPRN_TLB1CFG
1134 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1136 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1138 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1142 andis. r4,r4,MAS1_VALID@h
1145 /* Get the tlb entry used by the current running code */
1151 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1155 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1156 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1163 ori r4,r4,MSR_IS | MSR_DS
1170 * Restore to the address space 0 and also invalidate the tlb entry created
1172 * r3 - the tlb entry which should be invalidated
1173 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1174 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1177 _GLOBAL(restore_to_as0)
1185 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1186 * so we need calculate the right jump and device tree address based
1187 * on the offset passed by r4.
1194 li r8,(MSR_IS | MSR_DS)
1202 /* Invalidate the temporary tlb entry for AS1 */
1203 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1204 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1208 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1216 bne 3f /* offset != 0 && is_boot_cpu */
1221 * The PAGE_OFFSET will map to a different physical address,
1222 * jump to _start to do another relocation again.
1228 * We put a few things here that have to be page-aligned. This stuff
1229 * goes at the beginning of the data segment, which is page-aligned.
1235 .globl empty_zero_page
1238 EXPORT_SYMBOL(empty_zero_page)
1239 .globl swapper_pg_dir
1241 .space PGD_TABLE_SIZE
1244 * Room for two PTE pointers, usually the kernel and current user pointers
1245 * to their respective root page table.