2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2005 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
31 #include <linux/init.h>
32 #include <asm/processor.h>
35 #include <asm/pgtable.h>
36 #include <asm/cputable.h>
37 #include <asm/thread_info.h>
38 #include <asm/ppc_asm.h>
39 #include <asm/asm-offsets.h>
40 #include <asm/ptrace.h>
41 #include <asm/synch.h>
42 #include <asm/export.h>
43 #include <asm/code-patching-asm.h>
44 #include "head_booke.h"
47 /* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
62 * Reserve a word at a fixed location to store the address
66 mr r31,r3 /* save device tree ptr */
67 li r24,0 /* CPU number */
69 #ifdef CONFIG_RELOCATABLE
71 * Relocate ourselves to the current runtime address.
72 * This is called only by the Boot CPU.
73 * "relocate" is called with our current runtime virutal
75 * r21 will be loaded with the physical runtime address of _stext
77 bl 0f /* Get our runtime address */
78 0: mflr r21 /* Make it accessible */
79 addis r21,r21,(_stext - 0b)@ha
80 addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */
83 * We have the runtime (virutal) address of our base.
84 * We calculate our shift of offset from a 256M page.
85 * We could map the 256M page we belong to at PAGE_OFFSET and
86 * get going from there.
89 ori r4,r4,KERNELBASE@l
90 rlwinm r6,r21,0,4,31 /* r6 = PHYS_START % 256M */
91 rlwinm r5,r4,0,4,31 /* r5 = KERNELBASE % 256M */
92 subf r3,r5,r6 /* r3 = r6 - r5 */
93 add r3,r4,r3 /* Required Virutal Address */
101 * This is where the main kernel code starts.
106 ori r2,r2,init_task@l
108 /* ptr to current thread */
109 addi r4,r2,THREAD /* init task's THREAD */
110 mtspr SPRN_SPRG_THREAD,r4
113 lis r1,init_thread_union@h
114 ori r1,r1,init_thread_union@l
116 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
120 #ifdef CONFIG_RELOCATABLE
122 * Relocatable kernel support based on processing of dynamic
123 * relocation entries.
125 * r25 will contain RPN/ERPN for the start address of memory
126 * r21 will contain the current offset of _stext
128 lis r3,kernstart_addr@ha
129 la r3,kernstart_addr@l(r3)
132 * Compute the kernstart_addr.
133 * kernstart_addr => (r6,r8)
134 * kernstart_addr & ~0xfffffff => (r6,r7)
136 rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */
137 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
138 rlwinm r8,r21,0,4,31 /* r8 = (_stext & 0xfffffff) */
139 or r8,r7,r8 /* Compute the lower 32bit of kernstart_addr */
141 /* Store kernstart_addr */
142 stw r6,0(r3) /* higher 32bit */
143 stw r8,4(r3) /* lower 32bit */
146 * Compute the virt_phys_offset :
147 * virt_phys_offset = stext.run - kernstart_addr
149 * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff)
150 * When we relocate, we have :
152 * (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff)
155 * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff)
159 /* KERNELBASE&~0xfffffff => (r4,r5) */
160 li r4, 0 /* higer 32bit */
162 rlwinm r5,r5,0,0,3 /* Align to 256M, lower 32bit */
170 /* Store virt_phys_offset */
171 lis r3,virt_phys_offset@ha
172 la r3,virt_phys_offset@l(r3)
177 #elif defined(CONFIG_DYNAMIC_MEMSTART)
179 * Mapping based, page aligned dynamic kernel loading.
181 * r25 will contain RPN/ERPN for the start address of memory
183 * Add the difference between KERNELBASE and PAGE_OFFSET to the
184 * start of physical memory to get kernstart_addr.
186 lis r3,kernstart_addr@ha
187 la r3,kernstart_addr@l(r3)
190 ori r4,r4,KERNELBASE@l
192 ori r5,r5,PAGE_OFFSET@l
195 rlwinm r6,r25,0,28,31 /* ERPN */
196 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
204 * Decide what sort of machine this is and initialize the MMU.
214 /* Setup PTE pointers for the Abatron bdiGDB */
215 lis r6, swapper_pg_dir@h
216 ori r6, r6, swapper_pg_dir@l
217 lis r5, abatron_pteptrs@h
218 ori r5, r5, abatron_pteptrs@l
220 ori r4, r4, KERNELBASE@l
221 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
224 /* Clear the Machine Check Syndrome Register */
229 lis r4,start_kernel@h
230 ori r4,r4,start_kernel@l
232 ori r3,r3,MSR_KERNEL@l
235 rfi /* change context and jump to start_kernel */
238 * Interrupt vector entry code
240 * The Book E MMUs are always on so we don't need to handle
241 * interrupts in real mode as with previous PPC processors. In
242 * this case we handle interrupts in the kernel virtual address
245 * Interrupt vectors are dynamically placed relative to the
246 * interrupt prefix as determined by the address of interrupt_base.
247 * The interrupt vectors offsets are programmed using the labels
248 * for each interrupt vector entry.
250 * Interrupt vectors must be aligned on a 16 byte boundary.
251 * We align on a 32 byte cache line boundary for good measure.
255 /* Critical Input Interrupt */
256 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
258 /* Machine Check Interrupt */
259 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
260 machine_check_exception)
261 MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
263 /* Data Storage Interrupt */
264 DATA_STORAGE_EXCEPTION
266 /* Instruction Storage Interrupt */
267 INSTRUCTION_STORAGE_EXCEPTION
269 /* External Input Interrupt */
270 EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTERNAL, ExternalInput, \
271 do_IRQ, EXC_XFER_LITE)
273 /* Alignment Interrupt */
276 /* Program Interrupt */
279 /* Floating Point Unavailable Interrupt */
280 #ifdef CONFIG_PPC_FPU
281 FP_UNAVAILABLE_EXCEPTION
283 EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_UNAVAIL, \
284 FloatingPointUnavailable, unknown_exception, EXC_XFER_STD)
286 /* System Call Interrupt */
287 START_EXCEPTION(SystemCall)
288 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL
290 /* Auxiliary Processor Unavailable Interrupt */
291 EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_UNAVAIL, \
292 AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_STD)
294 /* Decrementer Interrupt */
295 DECREMENTER_EXCEPTION
297 /* Fixed Internal Timer Interrupt */
298 /* TODO: Add FIT support */
299 EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT, FixedIntervalTimer, \
300 unknown_exception, EXC_XFER_STD)
302 /* Watchdog Timer Interrupt */
303 /* TODO: Add watchdog support */
304 #ifdef CONFIG_BOOKE_WDT
305 CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, WatchdogException)
307 CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, unknown_exception)
310 /* Data TLB Error Interrupt */
311 START_EXCEPTION(DataTLBError44x)
312 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
313 mtspr SPRN_SPRG_WSCRATCH1, r11
314 mtspr SPRN_SPRG_WSCRATCH2, r12
315 mtspr SPRN_SPRG_WSCRATCH3, r13
317 mtspr SPRN_SPRG_WSCRATCH4, r11
318 mfspr r10, SPRN_DEAR /* Get faulting address */
320 /* If we are faulting a kernel address, we have to use the
321 * kernel page tables.
323 lis r11, PAGE_OFFSET@h
326 lis r11, swapper_pg_dir@h
327 ori r11, r11, swapper_pg_dir@l
330 rlwinm r12,r12,0,0,23 /* Clear TID */
334 /* Get the PGD for the current thread */
336 mfspr r11,SPRN_SPRG_THREAD
339 /* Load PID into MMUCR TID */
341 mfspr r13,SPRN_PID /* Get PID */
342 rlwimi r12,r13,0,24,31 /* Set TID */
347 /* Mask of required permission bits. Note that while we
348 * do copy ESR:ST to _PAGE_RW position as trying to write
349 * to an RO page is pretty common, we don't do it with
350 * _PAGE_DIRTY. We could do it, but it's a fairly rare
351 * event so I'd rather take the overhead when it happens
352 * rather than adding an instruction here. We should measure
353 * whether the whole thing is worth it in the first place
354 * as we could avoid loading SPRN_ESR completely in the first
357 * TODO: Is it worth doing that mfspr & rlwimi in the first
358 * place or can we save a couple of instructions here ?
361 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
362 rlwimi r13,r12,10,30,30
365 /* Compute pgdir/pmd offset */
366 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
367 lwzx r11, r12, r11 /* Get pgd/pmd entry */
368 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
369 beq 2f /* Bail if no table */
371 /* Compute pte address */
372 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
373 lwz r11, 0(r12) /* Get high word of pte entry */
374 lwz r12, 4(r12) /* Get low word of pte entry */
376 lis r10,tlb_44x_index@ha
378 andc. r13,r13,r12 /* Check permission */
380 /* Load the next available TLB index */
381 lwz r13,tlb_44x_index@l(r10)
383 bne 2f /* Bail if permission mismach */
385 /* Increment, rollover, and store TLB index */
388 patch_site 0f, patch__tlb_44x_hwater_D
389 /* Compare with watermark (instruction gets patched) */
390 0: cmpwi 0,r13,1 /* reserve entries */
394 /* Store the next available TLB index */
395 stw r13,tlb_44x_index@l(r10)
397 /* Re-load the faulting address */
400 /* Jump to common tlb load */
401 b finish_tlb_load_44x
404 /* The bailout. Restore registers to pre-exception conditions
405 * and call the heavyweights to help us out.
407 mfspr r11, SPRN_SPRG_RSCRATCH4
409 mfspr r13, SPRN_SPRG_RSCRATCH3
410 mfspr r12, SPRN_SPRG_RSCRATCH2
411 mfspr r11, SPRN_SPRG_RSCRATCH1
412 mfspr r10, SPRN_SPRG_RSCRATCH0
415 /* Instruction TLB Error Interrupt */
417 * Nearly the same as above, except we get our
418 * information from different registers and bailout
419 * to a different point.
421 START_EXCEPTION(InstructionTLBError44x)
422 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
423 mtspr SPRN_SPRG_WSCRATCH1, r11
424 mtspr SPRN_SPRG_WSCRATCH2, r12
425 mtspr SPRN_SPRG_WSCRATCH3, r13
427 mtspr SPRN_SPRG_WSCRATCH4, r11
428 mfspr r10, SPRN_SRR0 /* Get faulting address */
430 /* If we are faulting a kernel address, we have to use the
431 * kernel page tables.
433 lis r11, PAGE_OFFSET@h
436 lis r11, swapper_pg_dir@h
437 ori r11, r11, swapper_pg_dir@l
440 rlwinm r12,r12,0,0,23 /* Clear TID */
444 /* Get the PGD for the current thread */
446 mfspr r11,SPRN_SPRG_THREAD
449 /* Load PID into MMUCR TID */
451 mfspr r13,SPRN_PID /* Get PID */
452 rlwimi r12,r13,0,24,31 /* Set TID */
457 /* Make up the required permissions */
458 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
460 /* Compute pgdir/pmd offset */
461 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
462 lwzx r11, r12, r11 /* Get pgd/pmd entry */
463 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
464 beq 2f /* Bail if no table */
466 /* Compute pte address */
467 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
468 lwz r11, 0(r12) /* Get high word of pte entry */
469 lwz r12, 4(r12) /* Get low word of pte entry */
471 lis r10,tlb_44x_index@ha
473 andc. r13,r13,r12 /* Check permission */
475 /* Load the next available TLB index */
476 lwz r13,tlb_44x_index@l(r10)
478 bne 2f /* Bail if permission mismach */
480 /* Increment, rollover, and store TLB index */
483 patch_site 0f, patch__tlb_44x_hwater_I
484 /* Compare with watermark (instruction gets patched) */
485 0: cmpwi 0,r13,1 /* reserve entries */
489 /* Store the next available TLB index */
490 stw r13,tlb_44x_index@l(r10)
492 /* Re-load the faulting address */
495 /* Jump to common TLB load point */
496 b finish_tlb_load_44x
499 /* The bailout. Restore registers to pre-exception conditions
500 * and call the heavyweights to help us out.
502 mfspr r11, SPRN_SPRG_RSCRATCH4
504 mfspr r13, SPRN_SPRG_RSCRATCH3
505 mfspr r12, SPRN_SPRG_RSCRATCH2
506 mfspr r11, SPRN_SPRG_RSCRATCH1
507 mfspr r10, SPRN_SPRG_RSCRATCH0
511 * Both the instruction and data TLB miss get to this
512 * point to load the TLB.
514 * r11 - PTE high word value
515 * r12 - PTE low word value
517 * MMUCR - loaded with proper value when we get here
518 * Upon exit, we reload everything and RFI.
521 /* Combine RPN & ERPN an write WS 0 */
522 rlwimi r11,r12,0,0,31-PAGE_SHIFT
523 tlbwe r11,r13,PPC44x_TLB_XLAT
526 * Create WS1. This is the faulting address (EPN),
527 * page size, and valid flag.
529 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
530 /* Insert valid and page size */
531 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
532 tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
535 li r10,0xf85 /* Mask to apply from PTE */
536 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
537 and r11,r12,r10 /* Mask PTE bits to keep */
538 andi. r10,r12,_PAGE_USER /* User page ? */
539 beq 1f /* nope, leave U bits empty */
540 rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
541 1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */
543 /* Done...restore registers and get out of here.
545 mfspr r11, SPRN_SPRG_RSCRATCH4
547 mfspr r13, SPRN_SPRG_RSCRATCH3
548 mfspr r12, SPRN_SPRG_RSCRATCH2
549 mfspr r11, SPRN_SPRG_RSCRATCH1
550 mfspr r10, SPRN_SPRG_RSCRATCH0
551 rfi /* Force context change */
553 /* TLB error interrupts for 476
555 #ifdef CONFIG_PPC_47x
556 START_EXCEPTION(DataTLBError47x)
557 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
558 mtspr SPRN_SPRG_WSCRATCH1,r11
559 mtspr SPRN_SPRG_WSCRATCH2,r12
560 mtspr SPRN_SPRG_WSCRATCH3,r13
562 mtspr SPRN_SPRG_WSCRATCH4,r11
563 mfspr r10,SPRN_DEAR /* Get faulting address */
565 /* If we are faulting a kernel address, we have to use the
566 * kernel page tables.
568 lis r11,PAGE_OFFSET@h
571 lis r11,swapper_pg_dir@h
572 ori r11,r11, swapper_pg_dir@l
573 li r12,0 /* MMUCR = 0 */
576 /* Get the PGD for the current thread and setup MMUCR */
577 3: mfspr r11,SPRN_SPRG3
579 mfspr r12,SPRN_PID /* Get PID */
580 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
582 /* Mask of required permission bits. Note that while we
583 * do copy ESR:ST to _PAGE_RW position as trying to write
584 * to an RO page is pretty common, we don't do it with
585 * _PAGE_DIRTY. We could do it, but it's a fairly rare
586 * event so I'd rather take the overhead when it happens
587 * rather than adding an instruction here. We should measure
588 * whether the whole thing is worth it in the first place
589 * as we could avoid loading SPRN_ESR completely in the first
592 * TODO: Is it worth doing that mfspr & rlwimi in the first
593 * place or can we save a couple of instructions here ?
596 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
597 rlwimi r13,r12,10,30,30
600 /* Compute pgdir/pmd offset */
601 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
602 lwzx r11,r12,r11 /* Get pgd/pmd entry */
604 /* Word 0 is EPN,V,TS,DSIZ */
605 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
606 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
610 /* XXX can we do better ? Need to make sure tlbwe has established
611 * latch V bit in MMUCR0 before the PTE is loaded further down */
616 rlwinm. r12,r11,0,0,20 /* Extract pt base address */
617 /* Compute pte address */
618 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
619 beq 2f /* Bail if no table */
620 lwz r11,0(r12) /* Get high word of pte entry */
622 /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
623 * bottom of r12 to create a data dependency... We can also use r10
624 * as destination nowadays
629 lwz r12,4(r12) /* Get low word of pte entry */
631 andc. r13,r13,r12 /* Check permission */
633 /* Jump to common tlb load */
634 beq finish_tlb_load_47x
636 2: /* The bailout. Restore registers to pre-exception conditions
637 * and call the heavyweights to help us out.
639 mfspr r11,SPRN_SPRG_RSCRATCH4
641 mfspr r13,SPRN_SPRG_RSCRATCH3
642 mfspr r12,SPRN_SPRG_RSCRATCH2
643 mfspr r11,SPRN_SPRG_RSCRATCH1
644 mfspr r10,SPRN_SPRG_RSCRATCH0
647 /* Instruction TLB Error Interrupt */
649 * Nearly the same as above, except we get our
650 * information from different registers and bailout
651 * to a different point.
653 START_EXCEPTION(InstructionTLBError47x)
654 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
655 mtspr SPRN_SPRG_WSCRATCH1,r11
656 mtspr SPRN_SPRG_WSCRATCH2,r12
657 mtspr SPRN_SPRG_WSCRATCH3,r13
659 mtspr SPRN_SPRG_WSCRATCH4,r11
660 mfspr r10,SPRN_SRR0 /* Get faulting address */
662 /* If we are faulting a kernel address, we have to use the
663 * kernel page tables.
665 lis r11,PAGE_OFFSET@h
668 lis r11,swapper_pg_dir@h
669 ori r11,r11, swapper_pg_dir@l
670 li r12,0 /* MMUCR = 0 */
673 /* Get the PGD for the current thread and setup MMUCR */
674 3: mfspr r11,SPRN_SPRG_THREAD
676 mfspr r12,SPRN_PID /* Get PID */
677 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
679 /* Make up the required permissions */
680 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
683 /* Compute pgdir/pmd offset */
684 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
685 lwzx r11,r12,r11 /* Get pgd/pmd entry */
687 /* Word 0 is EPN,V,TS,DSIZ */
688 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
689 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
693 /* XXX can we do better ? Need to make sure tlbwe has established
694 * latch V bit in MMUCR0 before the PTE is loaded further down */
699 rlwinm. r12,r11,0,0,20 /* Extract pt base address */
700 /* Compute pte address */
701 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
702 beq 2f /* Bail if no table */
704 lwz r11,0(r12) /* Get high word of pte entry */
705 /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
706 * bottom of r12 to create a data dependency... We can also use r10
707 * as destination nowadays
712 lwz r12,4(r12) /* Get low word of pte entry */
714 andc. r13,r13,r12 /* Check permission */
716 /* Jump to common TLB load point */
717 beq finish_tlb_load_47x
719 2: /* The bailout. Restore registers to pre-exception conditions
720 * and call the heavyweights to help us out.
722 mfspr r11, SPRN_SPRG_RSCRATCH4
724 mfspr r13, SPRN_SPRG_RSCRATCH3
725 mfspr r12, SPRN_SPRG_RSCRATCH2
726 mfspr r11, SPRN_SPRG_RSCRATCH1
727 mfspr r10, SPRN_SPRG_RSCRATCH0
731 * Both the instruction and data TLB miss get to this
732 * point to load the TLB.
734 * r11 - PTE high word value
735 * r12 - PTE low word value
737 * MMUCR - loaded with proper value when we get here
738 * Upon exit, we reload everything and RFI.
741 /* Combine RPN & ERPN an write WS 1 */
742 rlwimi r11,r12,0,0,31-PAGE_SHIFT
745 /* And make up word 2 */
746 li r10,0xf85 /* Mask to apply from PTE */
747 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
748 and r11,r12,r10 /* Mask PTE bits to keep */
749 andi. r10,r12,_PAGE_USER /* User page ? */
750 beq 1f /* nope, leave U bits empty */
751 rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
754 /* Done...restore registers and get out of here.
756 mfspr r11, SPRN_SPRG_RSCRATCH4
758 mfspr r13, SPRN_SPRG_RSCRATCH3
759 mfspr r12, SPRN_SPRG_RSCRATCH2
760 mfspr r11, SPRN_SPRG_RSCRATCH1
761 mfspr r10, SPRN_SPRG_RSCRATCH0
764 #endif /* CONFIG_PPC_47x */
766 /* Debug Interrupt */
768 * This statement needs to exist at the end of the IVPR
769 * definition just in case you end up taking a debug
770 * exception within another exception.
781 * Adjust the machine check IVOR on 440A cores
783 _GLOBAL(__fixup_440A_mcheck)
784 li r3,MachineCheckA@l
791 #ifdef CONFIG_BDI_SWITCH
792 /* Context switch the PTE pointer for the Abatron BDI2000.
793 * The PGDIR is the second parameter.
795 lis r5, abatron_pteptrs@h
796 ori r5, r5, abatron_pteptrs@l
800 isync /* Force context change */
804 * Init CPU state. This is called at boot time or for secondary CPUs
805 * to setup initial TLB entries, setup IVORs, etc...
808 _GLOBAL(init_cpu_state)
810 #ifdef CONFIG_PPC_47x
811 /* We use the PVR to differentiate 44x cores from 476 */
814 cmplwi cr0,r3,PVR_476FPE@h
816 cmplwi cr0,r3,PVR_476@h
818 cmplwi cr0,r3,PVR_476_ISS@h
820 #endif /* CONFIG_PPC_47x */
823 * In case the firmware didn't do it, we apply some workarounds
824 * that are good for all 440 core variants here
827 rlwinm r3,r3,0,0,27 /* disable icache prefetch */
834 * Set up the initial MMU state for 44x
836 * We are still executing code at the virtual address
837 * mappings set by the firmware for the base of RAM.
839 * We first invalidate all TLB entries but the one
840 * we are running from. We then load the KERNELBASE
841 * mappings so we can begin to use kernel addresses
842 * natively and so the interrupt vector locations are
843 * permanently pinned (necessary since Book E
844 * implementations always have translation enabled).
846 * TODO: Use the known TLB entry we are running from to
847 * determine which physical region we are located
848 * in. This can be used to determine where in RAM
849 * (on a shared CPU system) or PCI memory space
850 * (on a DRAMless system) we are located.
851 * For now, we assume a perfect world which means
852 * we are located at the base of DRAM (physical 0).
856 * Search TLB for entry that we are currently using.
857 * Invalidate all entries but the one we are using.
859 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
860 mfspr r3,SPRN_PID /* Get PID */
861 mfmsr r4 /* Get MSR */
862 andi. r4,r4,MSR_IS@l /* TS=1? */
863 beq wmmucr /* If not, leave STS=0 */
864 oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
865 wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
868 bl invstr /* Find our address */
869 invstr: mflr r5 /* Make it accessible */
870 tlbsx r23,0,r5 /* Find entry we are in */
871 li r4,0 /* Start at TLB entry 0 */
872 li r3,0 /* Set PAGEID inval value */
873 1: cmpw r23,r4 /* Is this our entry? */
874 beq skpinv /* If so, skip the inval */
875 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
876 skpinv: addi r4,r4,1 /* Increment */
877 cmpwi r4,64 /* Are we done? */
878 bne 1b /* If not, repeat */
879 isync /* If so, context change */
882 * Configure and load pinned entry into TLB slot 63.
884 #ifdef CONFIG_NONSTATIC_KERNEL
886 * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT
887 * entries of the initial mapping set by the boot loader.
888 * The XLAT entry is stored in r25
891 /* Read the XLAT entry for our current mapping */
892 tlbre r25,r23,PPC44x_TLB_XLAT
895 ori r3,r3,KERNELBASE@l
897 /* Use our current RPN entry */
902 ori r3,r3,PAGE_OFFSET@l
904 /* Kernel is at the base of RAM */
905 li r4, 0 /* Load the kernel physical address */
908 /* Load the kernel PID = 0 */
913 /* Initialize MMUCR */
919 clrrwi r3,r3,10 /* Mask off the effective page number */
920 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
923 clrrwi r4,r4,10 /* Mask off the real page number */
924 /* ERPN is 0 for first 4GB page */
927 /* Added guarded bit to protect against speculative loads/stores */
929 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
931 li r0,63 /* TLB slot 63 */
933 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
934 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
935 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
937 /* Force context change */
946 /* If necessary, invalidate original entry we used */
950 tlbwe r6,r23,PPC44x_TLB_PAGEID
954 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
955 /* Add UART mapping for early debug. */
958 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
959 ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K
962 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
963 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
966 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
967 li r0,62 /* TLB slot 0 */
969 tlbwe r3,r0,PPC44x_TLB_PAGEID
970 tlbwe r4,r0,PPC44x_TLB_XLAT
971 tlbwe r5,r0,PPC44x_TLB_ATTRIB
973 /* Force context change */
975 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
977 /* Establish the interrupt vector offsets */
978 SET_IVOR(0, CriticalInput);
979 SET_IVOR(1, MachineCheck);
980 SET_IVOR(2, DataStorage);
981 SET_IVOR(3, InstructionStorage);
982 SET_IVOR(4, ExternalInput);
983 SET_IVOR(5, Alignment);
984 SET_IVOR(6, Program);
985 SET_IVOR(7, FloatingPointUnavailable);
986 SET_IVOR(8, SystemCall);
987 SET_IVOR(9, AuxillaryProcessorUnavailable);
988 SET_IVOR(10, Decrementer);
989 SET_IVOR(11, FixedIntervalTimer);
990 SET_IVOR(12, WatchdogTimer);
991 SET_IVOR(13, DataTLBError44x);
992 SET_IVOR(14, InstructionTLBError44x);
993 SET_IVOR(15, DebugCrit);
998 #ifdef CONFIG_PPC_47x
1002 /* Entry point for secondary 47x processors */
1003 _GLOBAL(start_secondary_47x)
1004 mr r24,r3 /* CPU number */
1008 /* Now we need to bolt the rest of kernel memory which
1009 * is done in C code. We must be careful because our task
1010 * struct or our stack can (and will probably) be out
1011 * of reach of the initial 256M TLB entry, so we use a
1012 * small temporary stack in .bss for that. This works
1013 * because only one CPU at a time can be in this code
1015 lis r1,temp_boot_stack@h
1016 ori r1,r1,temp_boot_stack@l
1017 addi r1,r1,1024-STACK_FRAME_OVERHEAD
1020 bl mmu_init_secondary
1022 /* Now we can get our task struct and real stack pointer */
1024 /* Get current's stack and current */
1025 lis r2,secondary_current@ha
1026 lwz r2,secondary_current@l(r2)
1027 lwz r1,TASK_STACK(r2)
1029 /* Current stack pointer */
1030 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1034 /* Kernel stack for exception entry in SPRG3 */
1035 addi r4,r2,THREAD /* init task's THREAD */
1040 #endif /* CONFIG_SMP */
1043 * Set up the initial MMU state for 44x
1045 * We are still executing code at the virtual address
1046 * mappings set by the firmware for the base of RAM.
1050 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
1051 mfspr r3,SPRN_PID /* Get PID */
1052 mfmsr r4 /* Get MSR */
1053 andi. r4,r4,MSR_IS@l /* TS=1? */
1054 beq 1f /* If not, leave STS=0 */
1055 oris r3,r3,PPC47x_MMUCR_STS@h /* Set STS=1 */
1056 1: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
1059 /* Find the entry we are running from */
1071 /* Initialize MMUCR */
1076 clear_all_utlb_entries:
1078 #; Set initial values.
1085 #; Align the loop to speed things up.
1096 bne clear_utlb_entry
1100 bne clear_utlb_entry
1102 #; Restore original entry.
1104 oris r23,r23,0x8000 /* specify the way */
1110 * Configure and load pinned entry into TLB for the kernel core
1113 lis r3,PAGE_OFFSET@h
1114 ori r3,r3,PAGE_OFFSET@l
1116 /* Load the kernel PID = 0 */
1122 clrrwi r3,r3,12 /* Mask off the effective page number */
1123 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
1125 /* Word 1 - use r25. RPN is the same as the original entry */
1129 ori r5,r5,PPC47x_TLB2_S_RWX
1131 ori r5,r5,PPC47x_TLB2_M
1134 /* We write to way 0 and bolted 0 */
1141 * Configure SSPCR, ISPCR and USPCR for now to search everything, we can fix
1144 LOAD_REG_IMMEDIATE(r3, 0x9abcdef0)
1147 LOAD_REG_IMMEDIATE(r3, 0x12345670)
1150 /* Force context change */
1159 /* Invalidate original entry we used */
1161 rlwinm r24,r24,0,21,19 /* clear the "valid" bit */
1166 isync /* Clear out the shadow TLB entries */
1168 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
1169 /* Add UART mapping for early debug. */
1172 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
1173 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M
1176 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
1177 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
1180 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)
1182 /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same
1183 * congruence class as the kernel, we need to make sure of it at
1191 /* Force context change */
1193 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
1195 /* Establish the interrupt vector offsets */
1196 SET_IVOR(0, CriticalInput);
1197 SET_IVOR(1, MachineCheckA);
1198 SET_IVOR(2, DataStorage);
1199 SET_IVOR(3, InstructionStorage);
1200 SET_IVOR(4, ExternalInput);
1201 SET_IVOR(5, Alignment);
1202 SET_IVOR(6, Program);
1203 SET_IVOR(7, FloatingPointUnavailable);
1204 SET_IVOR(8, SystemCall);
1205 SET_IVOR(9, AuxillaryProcessorUnavailable);
1206 SET_IVOR(10, Decrementer);
1207 SET_IVOR(11, FixedIntervalTimer);
1208 SET_IVOR(12, WatchdogTimer);
1209 SET_IVOR(13, DataTLBError47x);
1210 SET_IVOR(14, InstructionTLBError47x);
1211 SET_IVOR(15, DebugCrit);
1213 /* We configure icbi to invalidate 128 bytes at a time since the
1214 * current 32-bit kernel code isn't too happy with icache != dcache
1215 * block size. We also disable the BTAC as this can cause errors
1216 * in some circumstances (see IBM Erratum 47).
1224 #endif /* CONFIG_PPC_47x */
1227 * Here we are back to code that is common between 44x and 47x
1229 * We proceed to further kernel initialization and return to the
1233 /* Establish the interrupt vector base */
1234 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
1238 * If the kernel was loaded at a non-zero 256 MB page, we need to
1239 * mask off the most significant 4 bits to get the relative address
1240 * from the start of physical memory
1242 rlwinm r22,r22,0,4,31
1243 addis r22,r22,PAGE_OFFSET@h
1249 * We put a few things here that have to be page-aligned. This stuff
1250 * goes at the beginning of the data segment, which is page-aligned.
1256 .globl empty_zero_page
1259 EXPORT_SYMBOL(empty_zero_page)
1262 * To support >32-bit physical addresses, we use an 8KB pgdir.
1264 .globl swapper_pg_dir
1266 .space PGD_TABLE_SIZE
1269 * Room for two PTE pointers, usually the kernel and current user pointers
1270 * to their respective root page table.
1279 #endif /* CONFIG_SMP */