arch/powerpc/kernel/exceptions-64s.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * This file contains the 64-bit "server" PowerPC variant
   4  * of the low level exception handling including exception
   5  * vectors, exception return, part of the slb and stab
   6  * handling and other fixed offset specific things.
   7  *
   8  * This file is meant to be #included from head_64.S due to
   9  * position dependent assembly.
  10  *
  11  * Most of this originates from head_64.S and thus has the same
  12  * copyright history.
  13  *
  14  */
  15
  16 #include <asm/hw_irq.h>
  17 #include <asm/exception-64s.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/cpuidle.h>
  20 #include <asm/head-64.h>
  21 #include <asm/feature-fixups.h>
  22 #include <asm/kup.h>
  23
  24 /*
  25  * There are a few constraints to be concerned with.
  26  * - Real mode exceptions code/data must be located at their physical location.
  27  * - Virtual mode exceptions must be mapped at their 0xc000... location.
  28  * - Fixed location code must not call directly beyond the __end_interrupts
  29  *   area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
  30  *   must be used.
  31  * - LOAD_HANDLER targets must be within first 64K of physical 0 /
  32  *   virtual 0xc00...
  33  * - Conditional branch targets must be within +/-32K of caller.
  34  *
  35  * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
  36  * therefore don't have to run in physically located code or rfid to
  37  * virtual mode kernel code. However on relocatable kernels they do have
  38  * to branch to KERNELBASE offset because the rest of the kernel (outside
  39  * the exception vectors) may be located elsewhere.
  40  *
  41  * Virtual exceptions correspond with physical, except their entry points
  42  * are offset by 0xc000000000000000 and also tend to get an added 0x4000
  43  * offset applied. Virtual exceptions are enabled with the Alternate
  44  * Interrupt Location (AIL) bit set in the LPCR. However this does not
  45  * guarantee they will be delivered virtually. Some conditions (see the ISA)
  46  * cause exceptions to be delivered in real mode.
  47  *
  48  * It's impossible to receive interrupts below 0x300 via AIL.
  49  *
  50  * KVM: None of the virtual exceptions are from the guest. Anything that
  51  * escalated to HV=1 from HV=0 is delivered via real mode handlers.
  52  *
  53  *
  54  * We layout physical memory as follows:
  55  * 0x0000 - 0x00ff : Secondary processor spin code
  56  * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
  57  * 0x1900 - 0x3fff : Real mode trampolines
  58  * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
  59  * 0x5900 - 0x6fff : Relon mode trampolines
  60  * 0x7000 - 0x7fff : FWNMI data area
  61  * 0x8000 -   .... : Common interrupt handlers, remaining early
  62  *                   setup code, rest of kernel.
  63  *
  64  * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
  65  * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
  66  * vectors there.
  67  */
  68 OPEN_FIXED_SECTION(real_vectors,        0x0100, 0x1900)
  69 OPEN_FIXED_SECTION(real_trampolines,    0x1900, 0x4000)
  70 OPEN_FIXED_SECTION(virt_vectors,        0x4000, 0x5900)
  71 OPEN_FIXED_SECTION(virt_trampolines,    0x5900, 0x7000)
  72
  73 #ifdef CONFIG_PPC_POWERNV
  74         .globl start_real_trampolines
  75         .globl end_real_trampolines
  76         .globl start_virt_trampolines
  77         .globl end_virt_trampolines
  78 #endif
  79
  80 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
  81 /*
  82  * Data area reserved for FWNMI option.
  83  * This address (0x7000) is fixed by the RPA.
  84  * pseries and powernv need to keep the whole page from
  85  * 0x7000 to 0x8000 free for use by the firmware
  86  */
  87 ZERO_FIXED_SECTION(fwnmi_page,          0x7000, 0x8000)
  88 OPEN_TEXT_SECTION(0x8000)
  89 #else
  90 OPEN_TEXT_SECTION(0x7000)
  91 #endif
  92
  93 USE_FIXED_SECTION(real_vectors)
  94
  95 /*
  96  * This is the start of the interrupt handlers for pSeries
  97  * This code runs with relocation off.
  98  * Code from here to __end_interrupts gets copied down to real
  99  * address 0x100 when we are running a relocatable kernel.
 100  * Therefore any relative branches in this section must only
 101  * branch to labels in this section.
 102  */
 103         .globl __start_interrupts
 104 __start_interrupts:
 105
 106 /* No virt vectors corresponding with 0x0..0x100 */
 107 EXC_VIRT_NONE(0x4000, 0x100)
 108
 109
 110 #ifdef CONFIG_PPC_P7_NAP
 111         /*
 112          * If running native on arch 2.06 or later, check if we are waking up
 113          * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
 114          * bits 46:47. A non-0 value indicates that we are coming from a power
 115          * saving state. The idle wakeup handler initially runs in real mode,
 116          * but we branch to the 0xc000... address so we can turn on relocation
 117          * with mtmsr.
 118          */
 119 #define IDLETEST(n)                                                     \
 120         BEGIN_FTR_SECTION ;                                             \
 121         mfspr   r10,SPRN_SRR1 ;                                         \
 122         rlwinm. r10,r10,47-31,30,31 ;                                   \
 123         beq-    1f ;                                                    \
 124         cmpwi   cr1,r10,2 ;                                             \
 125         mfspr   r3,SPRN_SRR1 ;                                          \
 126         bltlr   cr1 ;   /* no state loss, return to idle caller */      \
 127         BRANCH_TO_C000(r10, system_reset_idle_common) ;                 \
 128 1:                                                                      \
 129         KVMTEST_PR(n) ;                                                 \
 130         END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 131 #else
 132 #define IDLETEST NOTEST
 133 #endif
 134
 135 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
 136         SET_SCRATCH0(r13)
 137         /*
 138          * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
 139          * being used, so a nested NMI exception would corrupt it.
 140          */
 141         EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
 142                               IDLETEST, 0x100)
 143
 144 EXC_REAL_END(system_reset, 0x100, 0x100)
 145 EXC_VIRT_NONE(0x4100, 0x100)
 146 TRAMP_KVM(PACA_EXNMI, 0x100)
 147
 148 #ifdef CONFIG_PPC_P7_NAP
 149 EXC_COMMON_BEGIN(system_reset_idle_common)
 150         /*
 151          * This must be a direct branch (without linker branch stub) because
 152          * we can not use TOC at this point as r2 may not be restored yet.
 153          */
 154         b       idle_return_gpr_loss
 155 #endif
 156
 157 /*
 158  * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does
 159  * the right thing. We do not want to reconcile because that goes
 160  * through irq tracing which we don't want in NMI.
 161  *
 162  * Save PACAIRQHAPPENED because some code will do a hard disable
 163  * (e.g., xmon). So we want to restore this back to where it was
 164  * when we return. DAR is unused in the stack, so save it there.
 165  */
 166 #define ADD_RECONCILE_NMI                                               \
 167         li      r10,IRQS_ALL_DISABLED;                                  \
 168         stb     r10,PACAIRQSOFTMASK(r13);                               \
 169         lbz     r10,PACAIRQHAPPENED(r13);                               \
 170         std     r10,_DAR(r1)
 171
 172 EXC_COMMON_BEGIN(system_reset_common)
 173         /*
 174          * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
 175          * to recover, but nested NMI will notice in_nmi and not recover
 176          * because of the use of the NMI stack. in_nmi reentrancy is tested in
 177          * system_reset_exception.
 178          */
 179         lhz     r10,PACA_IN_NMI(r13)
 180         addi    r10,r10,1
 181         sth     r10,PACA_IN_NMI(r13)
 182         li      r10,MSR_RI
 183         mtmsrd  r10,1
 184
 185         mr      r10,r1
 186         ld      r1,PACA_NMI_EMERG_SP(r13)
 187         subi    r1,r1,INT_FRAME_SIZE
 188         EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
 189                         system_reset, system_reset_exception,
 190                         ADD_NVGPRS;ADD_RECONCILE_NMI)
 191
 192         /* This (and MCE) can be simplified with mtmsrd L=1 */
 193         /* Clear MSR_RI before setting SRR0 and SRR1. */
 194         li      r0,MSR_RI
 195         mfmsr   r9
 196         andc    r9,r9,r0
 197         mtmsrd  r9,1
 198
 199         /*
 200          * MSR_RI is clear, now we can decrement paca->in_nmi.
 201          */
 202         lhz     r10,PACA_IN_NMI(r13)
 203         subi    r10,r10,1
 204         sth     r10,PACA_IN_NMI(r13)
 205
 206         /*
 207          * Restore soft mask settings.
 208          */
 209         ld      r10,_DAR(r1)
 210         stb     r10,PACAIRQHAPPENED(r13)
 211         ld      r10,SOFTE(r1)
 212         stb     r10,PACAIRQSOFTMASK(r13)
 213
 214         /*
 215          * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP.
 216          * Should share common bits...
 217          */
 218
 219         /* Move original SRR0 and SRR1 into the respective regs */
 220         ld      r9,_MSR(r1)
 221         mtspr   SPRN_SRR1,r9
 222         ld      r3,_NIP(r1)
 223         mtspr   SPRN_SRR0,r3
 224         ld      r9,_CTR(r1)
 225         mtctr   r9
 226         ld      r9,_XER(r1)
 227         mtxer   r9
 228         ld      r9,_LINK(r1)
 229         mtlr    r9
 230         REST_GPR(0, r1)
 231         REST_8GPRS(2, r1)
 232         REST_GPR(10, r1)
 233         ld      r11,_CCR(r1)
 234         mtcr    r11
 235         REST_GPR(11, r1)
 236         REST_2GPRS(12, r1)
 237         /* restore original r1. */
 238         ld      r1,GPR1(r1)
 239         RFI_TO_USER_OR_KERNEL
 240
 241 #ifdef CONFIG_PPC_PSERIES
 242 /*
 243  * Vectors for the FWNMI option.  Share common code.
 244  */
 245 TRAMP_REAL_BEGIN(system_reset_fwnmi)
 246         SET_SCRATCH0(r13)               /* save r13 */
 247         /* See comment at system_reset exception */
 248         EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
 249                               NOTEST, 0x100)
 250 #endif /* CONFIG_PPC_PSERIES */
 251
 252
 253 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
 254         /* This is moved out of line as it can be patched by FW, but
 255          * some code path might still want to branch into the original
 256          * vector
 257          */
 258         SET_SCRATCH0(r13)               /* save r13 */
 259         EXCEPTION_PROLOG_0(PACA_EXMC)
 260 BEGIN_FTR_SECTION
 261         b       machine_check_common_early
 262 FTR_SECTION_ELSE
 263         b       machine_check_pSeries_0
 264 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 265 EXC_REAL_END(machine_check, 0x200, 0x100)
 266 EXC_VIRT_NONE(0x4200, 0x100)
 267 TRAMP_REAL_BEGIN(machine_check_common_early)
 268         EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
 269         /*
 270          * Register contents:
 271          * R13          = PACA
 272          * R9           = CR
 273          * Original R9 to R13 is saved on PACA_EXMC
 274          *
 275          * Switch to mc_emergency stack and handle re-entrancy (we limit
 276          * the nested MCE upto level 4 to avoid stack overflow).
 277          * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
 278          *
 279          * We use paca->in_mce to check whether this is the first entry or
 280          * nested machine check. We increment paca->in_mce to track nested
 281          * machine checks.
 282          *
 283          * If this is the first entry then set stack pointer to
 284          * paca->mc_emergency_sp, otherwise r1 is already pointing to
 285          * stack frame on mc_emergency stack.
 286          *
 287          * NOTE: We are here with MSR_ME=0 (off), which means we risk a
 288          * checkstop if we get another machine check exception before we do
 289          * rfid with MSR_ME=1.
 290          *
 291          * This interrupt can wake directly from idle. If that is the case,
 292          * the machine check is handled then the idle wakeup code is called
 293          * to restore state.
 294          */
 295         mr      r11,r1                  /* Save r1 */
 296         lhz     r10,PACA_IN_MCE(r13)
 297         cmpwi   r10,0                   /* Are we in nested machine check */
 298         bne     0f                      /* Yes, we are. */
 299         /* First machine check entry */
 300         ld      r1,PACAMCEMERGSP(r13)   /* Use MC emergency stack */
 301 0:      subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame */
 302         addi    r10,r10,1               /* increment paca->in_mce */
 303         sth     r10,PACA_IN_MCE(r13)
 304         /* Limit nested MCE to level 4 to avoid stack overflow */
 305         cmpwi   r10,MAX_MCE_DEPTH
 306         bgt     2f                      /* Check if we hit limit of 4 */
 307         std     r11,GPR1(r1)            /* Save r1 on the stack. */
 308         std     r11,0(r1)               /* make stack chain pointer */
 309         mfspr   r11,SPRN_SRR0           /* Save SRR0 */
 310         std     r11,_NIP(r1)
 311         mfspr   r11,SPRN_SRR1           /* Save SRR1 */
 312         std     r11,_MSR(r1)
 313         mfspr   r11,SPRN_DAR            /* Save DAR */
 314         std     r11,_DAR(r1)
 315         mfspr   r11,SPRN_DSISR          /* Save DSISR */
 316         std     r11,_DSISR(r1)
 317         std     r9,_CCR(r1)             /* Save CR in stackframe */
 318         kuap_save_amr_and_lock r9, r10, cr1
 319         /* Save r9 through r13 from EXMC save area to stack frame. */
 320         EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
 321         mfmsr   r11                     /* get MSR value */
 322 BEGIN_FTR_SECTION
 323         ori     r11,r11,MSR_ME          /* turn on ME bit */
 324 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 325         ori     r11,r11,MSR_RI          /* turn on RI bit */
 326         LOAD_HANDLER(r12, machine_check_handle_early)
 327 1:      mtspr   SPRN_SRR0,r12
 328         mtspr   SPRN_SRR1,r11
 329         RFI_TO_KERNEL
 330         b       .       /* prevent speculative execution */
 331 2:
 332         /* Stack overflow. Stay on emergency stack and panic.
 333          * Keep the ME bit off while panic-ing, so that if we hit
 334          * another machine check we checkstop.
 335          */
 336         addi    r1,r1,INT_FRAME_SIZE    /* go back to previous stack frame */
 337         ld      r11,PACAKMSR(r13)
 338         LOAD_HANDLER(r12, unrecover_mce)
 339         li      r10,MSR_ME
 340         andc    r11,r11,r10             /* Turn off MSR_ME */
 341         b       1b
 342         b       .       /* prevent speculative execution */
 343
 344 TRAMP_REAL_BEGIN(machine_check_pSeries)
 345         .globl machine_check_fwnmi
 346 machine_check_fwnmi:
 347         SET_SCRATCH0(r13)               /* save r13 */
 348         EXCEPTION_PROLOG_0(PACA_EXMC)
 349 BEGIN_FTR_SECTION
 350         b       machine_check_common_early
 351 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
 352 machine_check_pSeries_0:
 353         EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
 354         /*
 355          * MSR_RI is not enabled, because PACA_EXMC is being used, so a
 356          * nested machine check corrupts it. machine_check_common enables
 357          * MSR_RI.
 358          */
 359         EXCEPTION_PROLOG_2_NORI(machine_check_common, EXC_STD)
 360
 361 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
 362
 363 EXC_COMMON_BEGIN(machine_check_common)
 364         /*
 365          * Machine check is different because we use a different
 366          * save area: PACA_EXMC instead of PACA_EXGEN.
 367          */
 368         mfspr   r10,SPRN_DAR
 369         std     r10,PACA_EXMC+EX_DAR(r13)
 370         mfspr   r10,SPRN_DSISR
 371         stw     r10,PACA_EXMC+EX_DSISR(r13)
 372         EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
 373         FINISH_NAP
 374         RECONCILE_IRQ_STATE(r10, r11)
 375         ld      r3,PACA_EXMC+EX_DAR(r13)
 376         lwz     r4,PACA_EXMC+EX_DSISR(r13)
 377         /* Enable MSR_RI when finished with PACA_EXMC */
 378         li      r10,MSR_RI
 379         mtmsrd  r10,1
 380         std     r3,_DAR(r1)
 381         std     r4,_DSISR(r1)
 382         bl      save_nvgprs
 383         addi    r3,r1,STACK_FRAME_OVERHEAD
 384         bl      machine_check_exception
 385         b       ret_from_except
 386
 387 #define MACHINE_CHECK_HANDLER_WINDUP                    \
 388         /* Clear MSR_RI before setting SRR0 and SRR1. */\
 389         li      r0,MSR_RI;                              \
 390         mfmsr   r9;             /* get MSR value */     \
 391         andc    r9,r9,r0;                               \
 392         mtmsrd  r9,1;           /* Clear MSR_RI */      \
 393         /* Move original SRR0 and SRR1 into the respective regs */      \
 394         ld      r9,_MSR(r1);                            \
 395         mtspr   SPRN_SRR1,r9;                           \
 396         ld      r3,_NIP(r1);                            \
 397         mtspr   SPRN_SRR0,r3;                           \
 398         ld      r9,_CTR(r1);                            \
 399         mtctr   r9;                                     \
 400         ld      r9,_XER(r1);                            \
 401         mtxer   r9;                                     \
 402         ld      r9,_LINK(r1);                           \
 403         mtlr    r9;                                     \
 404         REST_GPR(0, r1);                                \
 405         REST_8GPRS(2, r1);                              \
 406         REST_GPR(10, r1);                               \
 407         ld      r11,_CCR(r1);                           \
 408         mtcr    r11;                                    \
 409         /* Decrement paca->in_mce. */                   \
 410         lhz     r12,PACA_IN_MCE(r13);                   \
 411         subi    r12,r12,1;                              \
 412         sth     r12,PACA_IN_MCE(r13);                   \
 413         REST_GPR(11, r1);                               \
 414         REST_2GPRS(12, r1);                             \
 415         /* restore original r1. */                      \
 416         ld      r1,GPR1(r1)
 417
 418 #ifdef CONFIG_PPC_P7_NAP
 419 /*
 420  * This is an idle wakeup. Low level machine check has already been
 421  * done. Queue the event then call the idle code to do the wake up.
 422  */
 423 EXC_COMMON_BEGIN(machine_check_idle_common)
 424         bl      machine_check_queue_event
 425
 426         /*
 427          * We have not used any non-volatile GPRs here, and as a rule
 428          * most exception code including machine check does not.
 429          * Therefore PACA_NAPSTATELOST does not need to be set. Idle
 430          * wakeup will restore volatile registers.
 431          *
 432          * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
 433          *
 434          * Then decrement MCE nesting after finishing with the stack.
 435          */
 436         ld      r3,_MSR(r1)
 437         ld      r4,_LINK(r1)
 438
 439         lhz     r11,PACA_IN_MCE(r13)
 440         subi    r11,r11,1
 441         sth     r11,PACA_IN_MCE(r13)
 442
 443         mtlr    r4
 444         rlwinm  r10,r3,47-31,30,31
 445         cmpwi   cr1,r10,2
 446         bltlr   cr1     /* no state loss, return to idle caller */
 447         b       idle_return_gpr_loss
 448 #endif
 449         /*
 450          * Handle machine check early in real mode. We come here with
 451          * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
 452          */
 453 EXC_COMMON_BEGIN(machine_check_handle_early)
 454         std     r0,GPR0(r1)     /* Save r0 */
 455         EXCEPTION_PROLOG_COMMON_3(0x200)
 456         bl      save_nvgprs
 457         addi    r3,r1,STACK_FRAME_OVERHEAD
 458         bl      machine_check_early
 459         std     r3,RESULT(r1)   /* Save result */
 460         ld      r12,_MSR(r1)
 461 BEGIN_FTR_SECTION
 462         b       4f
 463 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
 464
 465 #ifdef  CONFIG_PPC_P7_NAP
 466         /*
 467          * Check if thread was in power saving mode. We come here when any
 468          * of the following is true:
 469          * a. thread wasn't in power saving mode
 470          * b. thread was in power saving mode with no state loss,
 471          *    supervisor state loss or hypervisor state loss.
 472          *
 473          * Go back to nap/sleep/winkle mode again if (b) is true.
 474          */
 475         BEGIN_FTR_SECTION
 476         rlwinm. r11,r12,47-31,30,31
 477         bne     machine_check_idle_common
 478         END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 479 #endif
 480
 481         /*
 482          * Check if we are coming from hypervisor userspace. If yes then we
 483          * continue in host kernel in V mode to deliver the MC event.
 484          */
 485         rldicl. r11,r12,4,63            /* See if MC hit while in HV mode. */
 486         beq     5f
 487 4:      andi.   r11,r12,MSR_PR          /* See if coming from user. */
 488         bne     9f                      /* continue in V mode if we are. */
 489
 490 5:
 491 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 492 BEGIN_FTR_SECTION
 493         /*
 494          * We are coming from kernel context. Check if we are coming from
 495          * guest. if yes, then we can continue. We will fall through
 496          * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
 497          */
 498         lbz     r11,HSTATE_IN_GUEST(r13)
 499         cmpwi   r11,0                   /* Check if coming from guest */
 500         bne     9f                      /* continue if we are. */
 501 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 502 #endif
 503         /*
 504          * At this point we are not sure about what context we come from.
 505          * Queue up the MCE event and return from the interrupt.
 506          * But before that, check if this is an un-recoverable exception.
 507          * If yes, then stay on emergency stack and panic.
 508          */
 509         andi.   r11,r12,MSR_RI
 510         bne     2f
 511 1:      mfspr   r11,SPRN_SRR0
 512         LOAD_HANDLER(r10,unrecover_mce)
 513         mtspr   SPRN_SRR0,r10
 514         ld      r10,PACAKMSR(r13)
 515         /*
 516          * We are going down. But there are chances that we might get hit by
 517          * another MCE during panic path and we may run into unstable state
 518          * with no way out. Hence, turn ME bit off while going down, so that
 519          * when another MCE is hit during panic path, system will checkstop
 520          * and hypervisor will get restarted cleanly by SP.
 521          */
 522         li      r3,MSR_ME
 523         andc    r10,r10,r3              /* Turn off MSR_ME */
 524         mtspr   SPRN_SRR1,r10
 525         RFI_TO_KERNEL
 526         b       .
 527 2:
 528         /*
 529          * Check if we have successfully handled/recovered from error, if not
 530          * then stay on emergency stack and panic.
 531          */
 532         ld      r3,RESULT(r1)   /* Load result */
 533         cmpdi   r3,0            /* see if we handled MCE successfully */
 534
 535         beq     1b              /* if !handled then panic */
 536 BEGIN_FTR_SECTION
 537         /*
 538          * Return from MC interrupt.
 539          * Queue up the MCE event so that we can log it later, while
 540          * returning from kernel or opal call.
 541          */
 542         bl      machine_check_queue_event
 543         MACHINE_CHECK_HANDLER_WINDUP
 544         RFI_TO_USER_OR_KERNEL
 545 FTR_SECTION_ELSE
 546         /*
 547          * pSeries: Return from MC interrupt. Before that stay on emergency
 548          * stack and call machine_check_exception to log the MCE event.
 549          */
 550         LOAD_HANDLER(r10,mce_return)
 551         mtspr   SPRN_SRR0,r10
 552         ld      r10,PACAKMSR(r13)
 553         mtspr   SPRN_SRR1,r10
 554         RFI_TO_KERNEL
 555         b       .
 556 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 557 9:
 558         /* Deliver the machine check to host kernel in V mode. */
 559         MACHINE_CHECK_HANDLER_WINDUP
 560         SET_SCRATCH0(r13)               /* save r13 */
 561         EXCEPTION_PROLOG_0(PACA_EXMC)
 562         b       machine_check_pSeries_0
 563
 564 EXC_COMMON_BEGIN(unrecover_mce)
 565         /* Invoke machine_check_exception to print MCE event and panic. */
 566         addi    r3,r1,STACK_FRAME_OVERHEAD
 567         bl      machine_check_exception
 568         /*
 569          * We will not reach here. Even if we did, there is no way out. Call
 570          * unrecoverable_exception and die.
 571          */
 572 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 573         bl      unrecoverable_exception
 574         b       1b
 575
 576 EXC_COMMON_BEGIN(mce_return)
 577         /* Invoke machine_check_exception to print MCE event and return. */
 578         addi    r3,r1,STACK_FRAME_OVERHEAD
 579         bl      machine_check_exception
 580         MACHINE_CHECK_HANDLER_WINDUP
 581         RFI_TO_KERNEL
 582         b       .
 583
 584 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
 585 SET_SCRATCH0(r13)               /* save r13 */
 586 EXCEPTION_PROLOG_0(PACA_EXGEN)
 587         b       tramp_real_data_access
 588 EXC_REAL_END(data_access, 0x300, 0x80)
 589
 590 TRAMP_REAL_BEGIN(tramp_real_data_access)
 591 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, 0x300)
 592         /*
 593          * DAR/DSISR must be read before setting MSR[RI], because
 594          * a d-side MCE will clobber those registers so is not
 595          * recoverable if they are live.
 596          */
 597         mfspr   r10,SPRN_DAR
 598         mfspr   r11,SPRN_DSISR
 599         std     r10,PACA_EXGEN+EX_DAR(r13)
 600         stw     r11,PACA_EXGEN+EX_DSISR(r13)
 601 EXCEPTION_PROLOG_2(data_access_common, EXC_STD)
 602
 603 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
 604 SET_SCRATCH0(r13)               /* save r13 */
 605 EXCEPTION_PROLOG_0(PACA_EXGEN)
 606 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x300)
 607         mfspr   r10,SPRN_DAR
 608         mfspr   r11,SPRN_DSISR
 609         std     r10,PACA_EXGEN+EX_DAR(r13)
 610         stw     r11,PACA_EXGEN+EX_DSISR(r13)
 611 EXCEPTION_PROLOG_2_RELON(data_access_common, EXC_STD)
 612 EXC_VIRT_END(data_access, 0x4300, 0x80)
 613
 614 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
 615
 616 EXC_COMMON_BEGIN(data_access_common)
 617         /*
 618          * Here r13 points to the paca, r9 contains the saved CR,
 619          * SRR0 and SRR1 are saved in r11 and r12,
 620          * r9 - r13 are saved in paca->exgen.
 621          * EX_DAR and EX_DSISR have saved DAR/DSISR
 622          */
 623         EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
 624         RECONCILE_IRQ_STATE(r10, r11)
 625         ld      r12,_MSR(r1)
 626         ld      r3,PACA_EXGEN+EX_DAR(r13)
 627         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
 628         li      r5,0x300
 629         std     r3,_DAR(r1)
 630         std     r4,_DSISR(r1)
 631 BEGIN_MMU_FTR_SECTION
 632         b       do_hash_page            /* Try to handle as hpte fault */
 633 MMU_FTR_SECTION_ELSE
 634         b       handle_page_fault
 635 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 636
 637
 638 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
 639 SET_SCRATCH0(r13)               /* save r13 */
 640 EXCEPTION_PROLOG_0(PACA_EXSLB)
 641         b       tramp_real_data_access_slb
 642 EXC_REAL_END(data_access_slb, 0x380, 0x80)
 643
 644 TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
 645 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
 646         mfspr   r10,SPRN_DAR
 647         std     r10,PACA_EXSLB+EX_DAR(r13)
 648 EXCEPTION_PROLOG_2(data_access_slb_common, EXC_STD)
 649
 650 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
 651 SET_SCRATCH0(r13)               /* save r13 */
 652 EXCEPTION_PROLOG_0(PACA_EXSLB)
 653 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
 654         mfspr   r10,SPRN_DAR
 655         std     r10,PACA_EXSLB+EX_DAR(r13)
 656 EXCEPTION_PROLOG_2_RELON(data_access_slb_common, EXC_STD)
 657 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
 658
 659 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
 660
 661 EXC_COMMON_BEGIN(data_access_slb_common)
 662         EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
 663         ld      r4,PACA_EXSLB+EX_DAR(r13)
 664         std     r4,_DAR(r1)
 665         addi    r3,r1,STACK_FRAME_OVERHEAD
 666 BEGIN_MMU_FTR_SECTION
 667         /* HPT case, do SLB fault */
 668         bl      do_slb_fault
 669         cmpdi   r3,0
 670         bne-    1f
 671         b       fast_exception_return
 672 1:      /* Error case */
 673 MMU_FTR_SECTION_ELSE
 674         /* Radix case, access is outside page table range */
 675         li      r3,-EFAULT
 676 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 677         std     r3,RESULT(r1)
 678         bl      save_nvgprs
 679         RECONCILE_IRQ_STATE(r10, r11)
 680         ld      r4,_DAR(r1)
 681         ld      r5,RESULT(r1)
 682         addi    r3,r1,STACK_FRAME_OVERHEAD
 683         bl      do_bad_slb_fault
 684         b       ret_from_except
 685
 686
 687 EXC_REAL(instruction_access, 0x400, 0x80)
 688 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
 689 TRAMP_KVM(PACA_EXGEN, 0x400)
 690
 691 EXC_COMMON_BEGIN(instruction_access_common)
 692         EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
 693         RECONCILE_IRQ_STATE(r10, r11)
 694         ld      r12,_MSR(r1)
 695         ld      r3,_NIP(r1)
 696         andis.  r4,r12,DSISR_SRR1_MATCH_64S@h
 697         li      r5,0x400
 698         std     r3,_DAR(r1)
 699         std     r4,_DSISR(r1)
 700 BEGIN_MMU_FTR_SECTION
 701         b       do_hash_page            /* Try to handle as hpte fault */
 702 MMU_FTR_SECTION_ELSE
 703         b       handle_page_fault
 704 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 705
 706
 707 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
 708 EXCEPTION_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, KVMTEST_PR, 0x480);
 709 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
 710
 711 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
 712 EXCEPTION_RELON_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, NOTEST, 0x480);
 713 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
 714
 715 TRAMP_KVM(PACA_EXSLB, 0x480)
 716
 717 EXC_COMMON_BEGIN(instruction_access_slb_common)
 718         EXCEPTION_PROLOG_COMMON(0x480, PACA_EXSLB)
 719         ld      r4,_NIP(r1)
 720         addi    r3,r1,STACK_FRAME_OVERHEAD
 721 BEGIN_MMU_FTR_SECTION
 722         /* HPT case, do SLB fault */
 723         bl      do_slb_fault
 724         cmpdi   r3,0
 725         bne-    1f
 726         b       fast_exception_return
 727 1:      /* Error case */
 728 MMU_FTR_SECTION_ELSE
 729         /* Radix case, access is outside page table range */
 730         li      r3,-EFAULT
 731 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 732         std     r3,RESULT(r1)
 733         bl      save_nvgprs
 734         RECONCILE_IRQ_STATE(r10, r11)
 735         ld      r4,_NIP(r1)
 736         ld      r5,RESULT(r1)
 737         addi    r3,r1,STACK_FRAME_OVERHEAD
 738         bl      do_bad_slb_fault
 739         b       ret_from_except
 740
 741
 742 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
 743         .globl hardware_interrupt_hv;
 744 hardware_interrupt_hv:
 745         BEGIN_FTR_SECTION
 746                 MASKABLE_EXCEPTION_HV(0x500, hardware_interrupt_common, IRQS_DISABLED)
 747         FTR_SECTION_ELSE
 748                 MASKABLE_EXCEPTION(0x500, hardware_interrupt_common, IRQS_DISABLED)
 749         ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 750 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
 751
 752 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
 753         .globl hardware_interrupt_relon_hv;
 754 hardware_interrupt_relon_hv:
 755         BEGIN_FTR_SECTION
 756                 MASKABLE_RELON_EXCEPTION_HV(0x500, hardware_interrupt_common,
 757                                             IRQS_DISABLED)
 758         FTR_SECTION_ELSE
 759                 __MASKABLE_RELON_EXCEPTION(0x500, hardware_interrupt_common,
 760                                            EXC_STD, SOFTEN_TEST_PR, IRQS_DISABLED)
 761         ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 762 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
 763
 764 TRAMP_KVM(PACA_EXGEN, 0x500)
 765 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
 766 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
 767
 768
 769 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
 770 SET_SCRATCH0(r13)               /* save r13 */
 771 EXCEPTION_PROLOG_0(PACA_EXGEN)
 772 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, 0x600)
 773         mfspr   r10,SPRN_DAR
 774         mfspr   r11,SPRN_DSISR
 775         std     r10,PACA_EXGEN+EX_DAR(r13)
 776         stw     r11,PACA_EXGEN+EX_DSISR(r13)
 777 EXCEPTION_PROLOG_2(alignment_common, EXC_STD)
 778 EXC_REAL_END(alignment, 0x600, 0x100)
 779
 780 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
 781 SET_SCRATCH0(r13)               /* save r13 */
 782 EXCEPTION_PROLOG_0(PACA_EXGEN)
 783 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x600)
 784         mfspr   r10,SPRN_DAR
 785         mfspr   r11,SPRN_DSISR
 786         std     r10,PACA_EXGEN+EX_DAR(r13)
 787         stw     r11,PACA_EXGEN+EX_DSISR(r13)
 788 EXCEPTION_PROLOG_2_RELON(alignment_common, EXC_STD)
 789 EXC_VIRT_END(alignment, 0x4600, 0x100)
 790
 791 TRAMP_KVM(PACA_EXGEN, 0x600)
 792 EXC_COMMON_BEGIN(alignment_common)
 793         EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
 794         ld      r3,PACA_EXGEN+EX_DAR(r13)
 795         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
 796         std     r3,_DAR(r1)
 797         std     r4,_DSISR(r1)
 798         bl      save_nvgprs
 799         RECONCILE_IRQ_STATE(r10, r11)
 800         addi    r3,r1,STACK_FRAME_OVERHEAD
 801         bl      alignment_exception
 802         b       ret_from_except
 803
 804
 805 EXC_REAL(program_check, 0x700, 0x100)
 806 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
 807 TRAMP_KVM(PACA_EXGEN, 0x700)
 808 EXC_COMMON_BEGIN(program_check_common)
 809         /*
 810          * It's possible to receive a TM Bad Thing type program check with
 811          * userspace register values (in particular r1), but with SRR1 reporting
 812          * that we came from the kernel. Normally that would confuse the bad
 813          * stack logic, and we would report a bad kernel stack pointer. Instead
 814          * we switch to the emergency stack if we're taking a TM Bad Thing from
 815          * the kernel.
 816          */
 817         li      r10,MSR_PR              /* Build a mask of MSR_PR ..    */
 818         oris    r10,r10,0x200000@h      /* .. and SRR1_PROGTM           */
 819         and     r10,r10,r12             /* Mask SRR1 with that.         */
 820         srdi    r10,r10,8               /* Shift it so we can compare   */
 821         cmpldi  r10,(0x200000 >> 8)     /* .. with an immediate.        */
 822         bne 1f                          /* If != go to normal path.     */
 823
 824         /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack  */
 825         andi.   r10,r12,MSR_PR;         /* Set CR0 correctly for label  */
 826                                         /* 3 in EXCEPTION_PROLOG_COMMON */
 827         mr      r10,r1                  /* Save r1                      */
 828         ld      r1,PACAEMERGSP(r13)     /* Use emergency stack          */
 829         subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame            */
 830         b 3f                            /* Jump into the macro !!       */
 831 1:      EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
 832         bl      save_nvgprs
 833         RECONCILE_IRQ_STATE(r10, r11)
 834         addi    r3,r1,STACK_FRAME_OVERHEAD
 835         bl      program_check_exception
 836         b       ret_from_except
 837
 838
 839 EXC_REAL(fp_unavailable, 0x800, 0x100)
 840 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
 841 TRAMP_KVM(PACA_EXGEN, 0x800)
 842 EXC_COMMON_BEGIN(fp_unavailable_common)
 843         EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
 844         bne     1f                      /* if from user, just load it up */
 845         bl      save_nvgprs
 846         RECONCILE_IRQ_STATE(r10, r11)
 847         addi    r3,r1,STACK_FRAME_OVERHEAD
 848         bl      kernel_fp_unavailable_exception
 849         BUG_OPCODE
 850 1:
 851 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 852 BEGIN_FTR_SECTION
 853         /* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
 854          * transaction), go do TM stuff
 855          */
 856         rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
 857         bne-    2f
 858 END_FTR_SECTION_IFSET(CPU_FTR_TM)
 859 #endif
 860         bl      load_up_fpu
 861         b       fast_exception_return
 862 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 863 2:      /* User process was in a transaction */
 864         bl      save_nvgprs
 865         RECONCILE_IRQ_STATE(r10, r11)
 866         addi    r3,r1,STACK_FRAME_OVERHEAD
 867         bl      fp_unavailable_tm
 868         b       ret_from_except
 869 #endif
 870
 871
 872 EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED)
 873 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED)
 874 TRAMP_KVM(PACA_EXGEN, 0x900)
 875 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
 876
 877
 878 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
 879 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
 880 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
 881 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
 882
 883
 884 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED)
 885 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED)
 886 TRAMP_KVM(PACA_EXGEN, 0xa00)
 887 #ifdef CONFIG_PPC_DOORBELL
 888 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
 889 #else
 890 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
 891 #endif
 892
 893
 894 EXC_REAL(trap_0b, 0xb00, 0x100)
 895 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
 896 TRAMP_KVM(PACA_EXGEN, 0xb00)
 897 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
 898
 899 /*
 900  * system call / hypercall (0xc00, 0x4c00)
 901  *
 902  * The system call exception is invoked with "sc 0" and does not alter HV bit.
 903  * There is support for kernel code to invoke system calls but there are no
 904  * in-tree users.
 905  *
 906  * The hypercall is invoked with "sc 1" and sets HV=1.
 907  *
 908  * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
 909  * 0x4c00 virtual mode.
 910  *
 911  * Call convention:
 912  *
 913  * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
 914  *
 915  * For hypercalls, the register convention is as follows:
 916  * r0 volatile
 917  * r1-2 nonvolatile
 918  * r3 volatile parameter and return value for status
 919  * r4-r10 volatile input and output value
 920  * r11 volatile hypercall number and output value
 921  * r12 volatile input and output value
 922  * r13-r31 nonvolatile
 923  * LR nonvolatile
 924  * CTR volatile
 925  * XER volatile
 926  * CR0-1 CR5-7 volatile
 927  * CR2-4 nonvolatile
 928  * Other registers nonvolatile
 929  *
 930  * The intersection of volatile registers that don't contain possible
 931  * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
 932  * without saving, though xer is not a good idea to use, as hardware may
 933  * interpret some bits so it may be costly to change them.
 934  */
 935 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 936         /*
 937          * There is a little bit of juggling to get syscall and hcall
 938          * working well. Save r13 in ctr to avoid using SPRG scratch
 939          * register.
 940          *
 941          * Userspace syscalls have already saved the PPR, hcalls must save
 942          * it before setting HMT_MEDIUM.
 943          */
 944 #define SYSCALL_KVMTEST                                                 \
 945         mtctr   r13;                                                    \
 946         GET_PACA(r13);                                                  \
 947         std     r10,PACA_EXGEN+EX_R10(r13);                             \
 948         INTERRUPT_TO_KERNEL;                                            \
 949         KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
 950         HMT_MEDIUM;                                                     \
 951         mfctr   r9;
 952
 953 #else
 954 #define SYSCALL_KVMTEST                                                 \
 955         HMT_MEDIUM;                                                     \
 956         mr      r9,r13;                                                 \
 957         GET_PACA(r13);                                                  \
 958         INTERRUPT_TO_KERNEL;
 959 #endif
 960
 961 #define LOAD_SYSCALL_HANDLER(reg)                                       \
 962         __LOAD_HANDLER(reg, system_call_common)
 963
 964 /*
 965  * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
 966  * and HMT_MEDIUM.
 967  */
 968 #define SYSCALL_REAL                                            \
 969         mfspr   r11,SPRN_SRR0 ;                                 \
 970         mfspr   r12,SPRN_SRR1 ;                                 \
 971         LOAD_SYSCALL_HANDLER(r10) ;                             \
 972         mtspr   SPRN_SRR0,r10 ;                                 \
 973         ld      r10,PACAKMSR(r13) ;                             \
 974         mtspr   SPRN_SRR1,r10 ;                                 \
 975         RFI_TO_KERNEL ;                                         \
 976         b       . ;     /* prevent speculative execution */
 977
 978 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
 979 #define SYSCALL_FASTENDIAN_TEST                                 \
 980 BEGIN_FTR_SECTION                                               \
 981         cmpdi   r0,0x1ebe ;                                     \
 982         beq-    1f ;                                            \
 983 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)                          \
 984
 985 #define SYSCALL_FASTENDIAN                                      \
 986         /* Fast LE/BE switch system call */                     \
 987 1:      mfspr   r12,SPRN_SRR1 ;                                 \
 988         xori    r12,r12,MSR_LE ;                                \
 989         mtspr   SPRN_SRR1,r12 ;                                 \
 990         mr      r13,r9 ;                                        \
 991         RFI_TO_USER ;   /* return to userspace */               \
 992         b       . ;     /* prevent speculative execution */
 993 #else
 994 #define SYSCALL_FASTENDIAN_TEST
 995 #define SYSCALL_FASTENDIAN
 996 #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */
 997
 998 #if defined(CONFIG_RELOCATABLE)
 999         /*
1000          * We can't branch directly so we do it via the CTR which
1001          * is volatile across system calls.
1002          */
1003 #define SYSCALL_VIRT                                            \
1004         LOAD_SYSCALL_HANDLER(r10) ;                             \
1005         mtctr   r10 ;                                           \
1006         mfspr   r11,SPRN_SRR0 ;                                 \
1007         mfspr   r12,SPRN_SRR1 ;                                 \
1008         li      r10,MSR_RI ;                                    \
1009         mtmsrd  r10,1 ;                                         \
1010         bctr ;
1011 #else
1012         /* We can branch directly */
1013 #define SYSCALL_VIRT                                            \
1014         mfspr   r11,SPRN_SRR0 ;                                 \
1015         mfspr   r12,SPRN_SRR1 ;                                 \
1016         li      r10,MSR_RI ;                                    \
1017         mtmsrd  r10,1 ;                 /* Set RI (EE=0) */     \
1018         b       system_call_common ;
1019 #endif
1020
1021 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1022         SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1023         SYSCALL_FASTENDIAN_TEST
1024         SYSCALL_REAL
1025         SYSCALL_FASTENDIAN
1026 EXC_REAL_END(system_call, 0xc00, 0x100)
1027
1028 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1029         SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1030         SYSCALL_FASTENDIAN_TEST
1031         SYSCALL_VIRT
1032         SYSCALL_FASTENDIAN
1033 EXC_VIRT_END(system_call, 0x4c00, 0x100)
1034
1035 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1036         /*
1037          * This is a hcall, so register convention is as above, with these
1038          * differences:
1039          * r13 = PACA
1040          * ctr = orig r13
1041          * orig r10 saved in PACA
1042          */
1043 TRAMP_KVM_BEGIN(do_kvm_0xc00)
1044          /*
1045           * Save the PPR (on systems that support it) before changing to
1046           * HMT_MEDIUM. That allows the KVM code to save that value into the
1047           * guest state (it is the guest's PPR value).
1048           */
1049         OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1050         HMT_MEDIUM
1051         OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1052         mfctr   r10
1053         SET_SCRATCH0(r10)
1054         std     r9,PACA_EXGEN+EX_R9(r13)
1055         mfcr    r9
1056         KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
1057 #endif
1058
1059
1060 EXC_REAL(single_step, 0xd00, 0x100)
1061 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
1062 TRAMP_KVM(PACA_EXGEN, 0xd00)
1063 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1064
1065 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
1066 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
1067 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
1068 EXC_COMMON_BEGIN(h_data_storage_common)
1069         mfspr   r10,SPRN_HDAR
1070         std     r10,PACA_EXGEN+EX_DAR(r13)
1071         mfspr   r10,SPRN_HDSISR
1072         stw     r10,PACA_EXGEN+EX_DSISR(r13)
1073         EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1074         bl      save_nvgprs
1075         RECONCILE_IRQ_STATE(r10, r11)
1076         addi    r3,r1,STACK_FRAME_OVERHEAD
1077 BEGIN_MMU_FTR_SECTION
1078         ld      r4,PACA_EXGEN+EX_DAR(r13)
1079         lwz     r5,PACA_EXGEN+EX_DSISR(r13)
1080         std     r4,_DAR(r1)
1081         std     r5,_DSISR(r1)
1082         li      r5,SIGSEGV
1083         bl      bad_page_fault
1084 MMU_FTR_SECTION_ELSE
1085         bl      unknown_exception
1086 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
1087         b       ret_from_except
1088
1089
1090 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1091 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1092 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1093 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1094
1095
1096 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1097 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1098 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1099 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1100
1101
1102 /*
1103  * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1104  * first, and then eventaully from there to the trampoline to get into virtual
1105  * mode.
1106  */
1107 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1108 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
1109 EXC_VIRT_NONE(0x4e60, 0x20)
1110 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1111 TRAMP_REAL_BEGIN(hmi_exception_early)
1112         EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1113         mr      r10,r1                  /* Save r1 */
1114         ld      r1,PACAEMERGSP(r13)     /* Use emergency stack for realmode */
1115         subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame            */
1116         mfspr   r11,SPRN_HSRR0          /* Save HSRR0 */
1117         mfspr   r12,SPRN_HSRR1          /* Save HSRR1 */
1118         EXCEPTION_PROLOG_COMMON_1()
1119         /* We don't touch AMR here, we never go to virtual mode */
1120         EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1121         EXCEPTION_PROLOG_COMMON_3(0xe60)
1122         addi    r3,r1,STACK_FRAME_OVERHEAD
1123         BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */
1124         cmpdi   cr0,r3,0
1125
1126         /* Windup the stack. */
1127         /* Move original HSRR0 and HSRR1 into the respective regs */
1128         ld      r9,_MSR(r1)
1129         mtspr   SPRN_HSRR1,r9
1130         ld      r3,_NIP(r1)
1131         mtspr   SPRN_HSRR0,r3
1132         ld      r9,_CTR(r1)
1133         mtctr   r9
1134         ld      r9,_XER(r1)
1135         mtxer   r9
1136         ld      r9,_LINK(r1)
1137         mtlr    r9
1138         REST_GPR(0, r1)
1139         REST_8GPRS(2, r1)
1140         REST_GPR(10, r1)
1141         ld      r11,_CCR(r1)
1142         REST_2GPRS(12, r1)
1143         bne     1f
1144         mtcr    r11
1145         REST_GPR(11, r1)
1146         ld      r1,GPR1(r1)
1147         HRFI_TO_USER_OR_KERNEL
1148
1149 1:      mtcr    r11
1150         REST_GPR(11, r1)
1151         ld      r1,GPR1(r1)
1152
1153         /*
1154          * Go to virtual mode and pull the HMI event information from
1155          * firmware.
1156          */
1157         .globl hmi_exception_after_realmode
1158 hmi_exception_after_realmode:
1159         SET_SCRATCH0(r13)
1160         EXCEPTION_PROLOG_0(PACA_EXGEN)
1161         b       tramp_real_hmi_exception
1162
1163 EXC_COMMON_BEGIN(hmi_exception_common)
1164 EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception,
1165         ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON)
1166
1167 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED)
1168 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED)
1169 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1170 #ifdef CONFIG_PPC_DOORBELL
1171 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1172 #else
1173 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1174 #endif
1175
1176
1177 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED)
1178 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED)
1179 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1180 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1181
1182
1183 EXC_REAL_NONE(0xec0, 0x20)
1184 EXC_VIRT_NONE(0x4ec0, 0x20)
1185 EXC_REAL_NONE(0xee0, 0x20)
1186 EXC_VIRT_NONE(0x4ee0, 0x20)
1187
1188
1189 EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED)
1190 EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED)
1191 TRAMP_KVM(PACA_EXGEN, 0xf00)
1192 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1193
1194
1195 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1196 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1197 TRAMP_KVM(PACA_EXGEN, 0xf20)
1198 EXC_COMMON_BEGIN(altivec_unavailable_common)
1199         EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1200 #ifdef CONFIG_ALTIVEC
1201 BEGIN_FTR_SECTION
1202         beq     1f
1203 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1204   BEGIN_FTR_SECTION_NESTED(69)
1205         /* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1206          * transaction), go do TM stuff
1207          */
1208         rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1209         bne-    2f
1210   END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1211 #endif
1212         bl      load_up_altivec
1213         b       fast_exception_return
1214 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1215 2:      /* User process was in a transaction */
1216         bl      save_nvgprs
1217         RECONCILE_IRQ_STATE(r10, r11)
1218         addi    r3,r1,STACK_FRAME_OVERHEAD
1219         bl      altivec_unavailable_tm
1220         b       ret_from_except
1221 #endif
1222 1:
1223 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1224 #endif
1225         bl      save_nvgprs
1226         RECONCILE_IRQ_STATE(r10, r11)
1227         addi    r3,r1,STACK_FRAME_OVERHEAD
1228         bl      altivec_unavailable_exception
1229         b       ret_from_except
1230
1231
1232 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1233 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1234 TRAMP_KVM(PACA_EXGEN, 0xf40)
1235 EXC_COMMON_BEGIN(vsx_unavailable_common)
1236         EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1237 #ifdef CONFIG_VSX
1238 BEGIN_FTR_SECTION
1239         beq     1f
1240 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1241   BEGIN_FTR_SECTION_NESTED(69)
1242         /* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1243          * transaction), go do TM stuff
1244          */
1245         rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1246         bne-    2f
1247   END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1248 #endif
1249         b       load_up_vsx
1250 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1251 2:      /* User process was in a transaction */
1252         bl      save_nvgprs
1253         RECONCILE_IRQ_STATE(r10, r11)
1254         addi    r3,r1,STACK_FRAME_OVERHEAD
1255         bl      vsx_unavailable_tm
1256         b       ret_from_except
1257 #endif
1258 1:
1259 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1260 #endif
1261         bl      save_nvgprs
1262         RECONCILE_IRQ_STATE(r10, r11)
1263         addi    r3,r1,STACK_FRAME_OVERHEAD
1264         bl      vsx_unavailable_exception
1265         b       ret_from_except
1266
1267
1268 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1269 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1270 TRAMP_KVM(PACA_EXGEN, 0xf60)
1271 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1272
1273
1274 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1275 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1276 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1277 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1278
1279
1280 EXC_REAL_NONE(0xfa0, 0x20)
1281 EXC_VIRT_NONE(0x4fa0, 0x20)
1282 EXC_REAL_NONE(0xfc0, 0x20)
1283 EXC_VIRT_NONE(0x4fc0, 0x20)
1284 EXC_REAL_NONE(0xfe0, 0x20)
1285 EXC_VIRT_NONE(0x4fe0, 0x20)
1286
1287 EXC_REAL_NONE(0x1000, 0x100)
1288 EXC_VIRT_NONE(0x5000, 0x100)
1289 EXC_REAL_NONE(0x1100, 0x100)
1290 EXC_VIRT_NONE(0x5100, 0x100)
1291
1292 #ifdef CONFIG_CBE_RAS
1293 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1294 EXC_VIRT_NONE(0x5200, 0x100)
1295 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1296 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1297 #else /* CONFIG_CBE_RAS */
1298 EXC_REAL_NONE(0x1200, 0x100)
1299 EXC_VIRT_NONE(0x5200, 0x100)
1300 #endif
1301
1302
1303 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1304 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1305 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1306 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1307
1308 EXC_REAL_NONE(0x1400, 0x100)
1309 EXC_VIRT_NONE(0x5400, 0x100)
1310
1311 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1312         mtspr   SPRN_SPRG_HSCRATCH0,r13
1313         EXCEPTION_PROLOG_0(PACA_EXGEN)
1314         EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1315
1316 #ifdef CONFIG_PPC_DENORMALISATION
1317         mfspr   r10,SPRN_HSRR1
1318         andis.  r10,r10,(HSRR1_DENORM)@h /* denorm? */
1319         bne+    denorm_assist
1320 #endif
1321
1322         KVMTEST_HV(0x1500)
1323         EXCEPTION_PROLOG_2(denorm_common, EXC_HV)
1324 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1325
1326 #ifdef CONFIG_PPC_DENORMALISATION
1327 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1328         b       exc_real_0x1500_denorm_exception_hv
1329 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1330 #else
1331 EXC_VIRT_NONE(0x5500, 0x100)
1332 #endif
1333
1334 TRAMP_KVM_HV(PACA_EXGEN, 0x1500)
1335
1336 #ifdef CONFIG_PPC_DENORMALISATION
1337 TRAMP_REAL_BEGIN(denorm_assist)
1338 BEGIN_FTR_SECTION
1339 /*
1340  * To denormalise we need to move a copy of the register to itself.
1341  * For POWER6 do that here for all FP regs.
1342  */
1343         mfmsr   r10
1344         ori     r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1345         xori    r10,r10,(MSR_FE0|MSR_FE1)
1346         mtmsrd  r10
1347         sync
1348
1349 #define FMR2(n)  fmr (n), (n) ; fmr n+1, n+1
1350 #define FMR4(n)  FMR2(n) ; FMR2(n+2)
1351 #define FMR8(n)  FMR4(n) ; FMR4(n+4)
1352 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1353 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1354         FMR32(0)
1355
1356 FTR_SECTION_ELSE
1357 /*
1358  * To denormalise we need to move a copy of the register to itself.
1359  * For POWER7 do that here for the first 32 VSX registers only.
1360  */
1361         mfmsr   r10
1362         oris    r10,r10,MSR_VSX@h
1363         mtmsrd  r10
1364         sync
1365
1366 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1367 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1368 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1369 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1370 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1371         XVCPSGNDP32(0)
1372
1373 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1374
1375 BEGIN_FTR_SECTION
1376         b       denorm_done
1377 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1378 /*
1379  * To denormalise we need to move a copy of the register to itself.
1380  * For POWER8 we need to do that for all 64 VSX registers
1381  */
1382         XVCPSGNDP32(32)
1383 denorm_done:
1384         mfspr   r11,SPRN_HSRR0
1385         subi    r11,r11,4
1386         mtspr   SPRN_HSRR0,r11
1387         mtcrf   0x80,r9
1388         ld      r9,PACA_EXGEN+EX_R9(r13)
1389         RESTORE_PPR_PACA(PACA_EXGEN, r10)
1390 BEGIN_FTR_SECTION
1391         ld      r10,PACA_EXGEN+EX_CFAR(r13)
1392         mtspr   SPRN_CFAR,r10
1393 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1394         ld      r10,PACA_EXGEN+EX_R10(r13)
1395         ld      r11,PACA_EXGEN+EX_R11(r13)
1396         ld      r12,PACA_EXGEN+EX_R12(r13)
1397         ld      r13,PACA_EXGEN+EX_R13(r13)
1398         HRFI_TO_UNKNOWN
1399         b       .
1400 #endif
1401
1402 EXC_COMMON(denorm_common, 0x1500, unknown_exception)
1403
1404
1405 #ifdef CONFIG_CBE_RAS
1406 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1407 EXC_VIRT_NONE(0x5600, 0x100)
1408 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1409 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1410 #else /* CONFIG_CBE_RAS */
1411 EXC_REAL_NONE(0x1600, 0x100)
1412 EXC_VIRT_NONE(0x5600, 0x100)
1413 #endif
1414
1415
1416 EXC_REAL(altivec_assist, 0x1700, 0x100)
1417 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1418 TRAMP_KVM(PACA_EXGEN, 0x1700)
1419 #ifdef CONFIG_ALTIVEC
1420 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1421 #else
1422 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1423 #endif
1424
1425
1426 #ifdef CONFIG_CBE_RAS
1427 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1428 EXC_VIRT_NONE(0x5800, 0x100)
1429 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1430 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1431 #else /* CONFIG_CBE_RAS */
1432 EXC_REAL_NONE(0x1800, 0x100)
1433 EXC_VIRT_NONE(0x5800, 0x100)
1434 #endif
1435
1436 #ifdef CONFIG_PPC_WATCHDOG
1437
1438 #define MASKED_DEC_HANDLER_LABEL 3f
1439
1440 #define MASKED_DEC_HANDLER(_H)                          \
1441 3: /* soft-nmi */                                       \
1442         std     r12,PACA_EXGEN+EX_R12(r13);             \
1443         GET_SCRATCH0(r10);                              \
1444         std     r10,PACA_EXGEN+EX_R13(r13);             \
1445         EXCEPTION_PROLOG_2(soft_nmi_common, _H)
1446
1447 /*
1448  * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1449  * stack is one that is usable by maskable interrupts so long as MSR_EE
1450  * remains off. It is used for recovery when something has corrupted the
1451  * normal kernel stack, for example. The "soft NMI" must not use the process
1452  * stack because we want irq disabled sections to avoid touching the stack
1453  * at all (other than PMU interrupts), so use the emergency stack for this,
1454  * and run it entirely with interrupts hard disabled.
1455  */
1456 EXC_COMMON_BEGIN(soft_nmi_common)
1457         mr      r10,r1
1458         ld      r1,PACAEMERGSP(r13)
1459         subi    r1,r1,INT_FRAME_SIZE
1460         EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
1461                         system_reset, soft_nmi_interrupt,
1462                         ADD_NVGPRS;ADD_RECONCILE)
1463         b       ret_from_except
1464
1465 #else /* CONFIG_PPC_WATCHDOG */
1466 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1467 #define MASKED_DEC_HANDLER(_H)
1468 #endif /* CONFIG_PPC_WATCHDOG */
1469
1470 /*
1471  * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1472  * - If it was a decrementer interrupt, we bump the dec to max and and return.
1473  * - If it was a doorbell we return immediately since doorbells are edge
1474  *   triggered and won't automatically refire.
1475  * - If it was a HMI we return immediately since we handled it in realmode
1476  *   and it won't refire.
1477  * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
1478  * This is called with r10 containing the value to OR to the paca field.
1479  */
1480 #define MASKED_INTERRUPT(_H)                            \
1481 masked_##_H##interrupt:                                 \
1482         std     r11,PACA_EXGEN+EX_R11(r13);             \
1483         lbz     r11,PACAIRQHAPPENED(r13);               \
1484         or      r11,r11,r10;                            \
1485         stb     r11,PACAIRQHAPPENED(r13);               \
1486         cmpwi   r10,PACA_IRQ_DEC;                       \
1487         bne     1f;                                     \
1488         lis     r10,0x7fff;                             \
1489         ori     r10,r10,0xffff;                         \
1490         mtspr   SPRN_DEC,r10;                           \
1491         b       MASKED_DEC_HANDLER_LABEL;               \
1492 1:      andi.   r10,r10,PACA_IRQ_MUST_HARD_MASK;        \
1493         beq     2f;                                     \
1494         mfspr   r10,SPRN_##_H##SRR1;                    \
1495         xori    r10,r10,MSR_EE; /* clear MSR_EE */      \
1496         mtspr   SPRN_##_H##SRR1,r10;                    \
1497         ori     r11,r11,PACA_IRQ_HARD_DIS;              \
1498         stb     r11,PACAIRQHAPPENED(r13);               \
1499 2:      /* done */                                      \
1500         mtcrf   0x80,r9;                                \
1501         std     r1,PACAR1(r13);                         \
1502         ld      r9,PACA_EXGEN+EX_R9(r13);               \
1503         ld      r10,PACA_EXGEN+EX_R10(r13);             \
1504         ld      r11,PACA_EXGEN+EX_R11(r13);             \
1505         /* returns to kernel where r13 must be set up, so don't restore it */ \
1506         ##_H##RFI_TO_KERNEL;                            \
1507         b       .;                                      \
1508         MASKED_DEC_HANDLER(_H)
1509
1510 TRAMP_REAL_BEGIN(stf_barrier_fallback)
1511         std     r9,PACA_EXRFI+EX_R9(r13)
1512         std     r10,PACA_EXRFI+EX_R10(r13)
1513         sync
1514         ld      r9,PACA_EXRFI+EX_R9(r13)
1515         ld      r10,PACA_EXRFI+EX_R10(r13)
1516         ori     31,31,0
1517         .rept 14
1518         b       1f
1519 1:
1520         .endr
1521         blr
1522
1523 TRAMP_REAL_BEGIN(rfi_flush_fallback)
1524         SET_SCRATCH0(r13);
1525         GET_PACA(r13);
1526         std     r1,PACA_EXRFI+EX_R12(r13)
1527         ld      r1,PACAKSAVE(r13)
1528         std     r9,PACA_EXRFI+EX_R9(r13)
1529         std     r10,PACA_EXRFI+EX_R10(r13)
1530         std     r11,PACA_EXRFI+EX_R11(r13)
1531         mfctr   r9
1532         ld      r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1533         ld      r11,PACA_L1D_FLUSH_SIZE(r13)
1534         srdi    r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1535         mtctr   r11
1536         DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1537
1538         /* order ld/st prior to dcbt stop all streams with flushing */
1539         sync
1540
1541         /*
1542          * The load adresses are at staggered offsets within cachelines,
1543          * which suits some pipelines better (on others it should not
1544          * hurt).
1545          */
1546 1:
1547         ld      r11,(0x80 + 8)*0(r10)
1548         ld      r11,(0x80 + 8)*1(r10)
1549         ld      r11,(0x80 + 8)*2(r10)
1550         ld      r11,(0x80 + 8)*3(r10)
1551         ld      r11,(0x80 + 8)*4(r10)
1552         ld      r11,(0x80 + 8)*5(r10)
1553         ld      r11,(0x80 + 8)*6(r10)
1554         ld      r11,(0x80 + 8)*7(r10)
1555         addi    r10,r10,0x80*8
1556         bdnz    1b
1557
1558         mtctr   r9
1559         ld      r9,PACA_EXRFI+EX_R9(r13)
1560         ld      r10,PACA_EXRFI+EX_R10(r13)
1561         ld      r11,PACA_EXRFI+EX_R11(r13)
1562         ld      r1,PACA_EXRFI+EX_R12(r13)
1563         GET_SCRATCH0(r13);
1564         rfid
1565
1566 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
1567         SET_SCRATCH0(r13);
1568         GET_PACA(r13);
1569         std     r1,PACA_EXRFI+EX_R12(r13)
1570         ld      r1,PACAKSAVE(r13)
1571         std     r9,PACA_EXRFI+EX_R9(r13)
1572         std     r10,PACA_EXRFI+EX_R10(r13)
1573         std     r11,PACA_EXRFI+EX_R11(r13)
1574         mfctr   r9
1575         ld      r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1576         ld      r11,PACA_L1D_FLUSH_SIZE(r13)
1577         srdi    r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1578         mtctr   r11
1579         DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1580
1581         /* order ld/st prior to dcbt stop all streams with flushing */
1582         sync
1583
1584         /*
1585          * The load adresses are at staggered offsets within cachelines,
1586          * which suits some pipelines better (on others it should not
1587          * hurt).
1588          */
1589 1:
1590         ld      r11,(0x80 + 8)*0(r10)
1591         ld      r11,(0x80 + 8)*1(r10)
1592         ld      r11,(0x80 + 8)*2(r10)
1593         ld      r11,(0x80 + 8)*3(r10)
1594         ld      r11,(0x80 + 8)*4(r10)
1595         ld      r11,(0x80 + 8)*5(r10)
1596         ld      r11,(0x80 + 8)*6(r10)
1597         ld      r11,(0x80 + 8)*7(r10)
1598         addi    r10,r10,0x80*8
1599         bdnz    1b
1600
1601         mtctr   r9
1602         ld      r9,PACA_EXRFI+EX_R9(r13)
1603         ld      r10,PACA_EXRFI+EX_R10(r13)
1604         ld      r11,PACA_EXRFI+EX_R11(r13)
1605         ld      r1,PACA_EXRFI+EX_R12(r13)
1606         GET_SCRATCH0(r13);
1607         hrfid
1608
1609 /*
1610  * Real mode exceptions actually use this too, but alternate
1611  * instruction code patches (which end up in the common .text area)
1612  * cannot reach these if they are put there.
1613  */
1614 USE_FIXED_SECTION(virt_trampolines)
1615         MASKED_INTERRUPT()
1616         MASKED_INTERRUPT(H)
1617
1618 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1619 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1620         /*
1621          * Here all GPRs are unchanged from when the interrupt happened
1622          * except for r13, which is saved in SPRG_SCRATCH0.
1623          */
1624         mfspr   r13, SPRN_SRR0
1625         addi    r13, r13, 4
1626         mtspr   SPRN_SRR0, r13
1627         GET_SCRATCH0(r13)
1628         RFI_TO_KERNEL
1629         b       .
1630
1631 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1632         /*
1633          * Here all GPRs are unchanged from when the interrupt happened
1634          * except for r13, which is saved in SPRG_SCRATCH0.
1635          */
1636         mfspr   r13, SPRN_HSRR0
1637         addi    r13, r13, 4
1638         mtspr   SPRN_HSRR0, r13
1639         GET_SCRATCH0(r13)
1640         HRFI_TO_KERNEL
1641         b       .
1642 #endif
1643
1644 /*
1645  * Ensure that any handlers that get invoked from the exception prologs
1646  * above are below the first 64KB (0x10000) of the kernel image because
1647  * the prologs assemble the addresses of these handlers using the
1648  * LOAD_HANDLER macro, which uses an ori instruction.
1649  */
1650
1651 /*** Common interrupt handlers ***/
1652
1653
1654         /*
1655          * Relocation-on interrupts: A subset of the interrupts can be delivered
1656          * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1657          * it.  Addresses are the same as the original interrupt addresses, but
1658          * offset by 0xc000000000004000.
1659          * It's impossible to receive interrupts below 0x300 via this mechanism.
1660          * KVM: None of these traps are from the guest ; anything that escalated
1661          * to HV=1 from HV=0 is delivered via real mode handlers.
1662          */
1663
1664         /*
1665          * This uses the standard macro, since the original 0x300 vector
1666          * only has extra guff for STAB-based processors -- which never
1667          * come here.
1668          */
1669
1670 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1671         b       __ppc64_runlatch_on
1672
1673 USE_FIXED_SECTION(virt_trampolines)
1674         /*
1675          * The __end_interrupts marker must be past the out-of-line (OOL)
1676          * handlers, so that they are copied to real address 0x100 when running
1677          * a relocatable kernel. This ensures they can be reached from the short
1678          * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1679          * directly, without using LOAD_HANDLER().
1680          */
1681         .align  7
1682         .globl  __end_interrupts
1683 __end_interrupts:
1684 DEFINE_FIXED_SYMBOL(__end_interrupts)
1685
1686 #ifdef CONFIG_PPC_970_NAP
1687 EXC_COMMON_BEGIN(power4_fixup_nap)
1688         andc    r9,r9,r10
1689         std     r9,TI_LOCAL_FLAGS(r11)
1690         ld      r10,_LINK(r1)           /* make idle task do the */
1691         std     r10,_NIP(r1)            /* equivalent of a blr */
1692         blr
1693 #endif
1694
1695 CLOSE_FIXED_SECTION(real_vectors);
1696 CLOSE_FIXED_SECTION(real_trampolines);
1697 CLOSE_FIXED_SECTION(virt_vectors);
1698 CLOSE_FIXED_SECTION(virt_trampolines);
1699
1700 USE_TEXT_SECTION()
1701
1702 /*
1703  * Hash table stuff
1704  */
1705         .balign IFETCH_ALIGN_BYTES
1706 do_hash_page:
1707 #ifdef CONFIG_PPC_BOOK3S_64
1708         lis     r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
1709         ori     r0,r0,DSISR_BAD_FAULT_64S@l
1710         and.    r0,r4,r0                /* weird error? */
1711         bne-    handle_page_fault       /* if not, try to insert a HPTE */
1712         ld      r11, PACA_THREAD_INFO(r13)
1713         lwz     r0,TI_PREEMPT(r11)      /* If we're in an "NMI" */
1714         andis.  r0,r0,NMI_MASK@h        /* (i.e. an irq when soft-disabled) */
1715         bne     77f                     /* then don't call hash_page now */
1716
1717         /*
1718          * r3 contains the faulting address
1719          * r4 msr
1720          * r5 contains the trap number
1721          * r6 contains dsisr
1722          *
1723          * at return r3 = 0 for success, 1 for page fault, negative for error
1724          */
1725         mr      r4,r12
1726         ld      r6,_DSISR(r1)
1727         bl      __hash_page             /* build HPTE if possible */
1728         cmpdi   r3,0                    /* see if __hash_page succeeded */
1729
1730         /* Success */
1731         beq     fast_exc_return_irq     /* Return from exception on success */
1732
1733         /* Error */
1734         blt-    13f
1735
1736         /* Reload DSISR into r4 for the DABR check below */
1737         ld      r4,_DSISR(r1)
1738 #endif /* CONFIG_PPC_BOOK3S_64 */
1739
1740 /* Here we have a page fault that hash_page can't handle. */
1741 handle_page_fault:
1742 11:     andis.  r0,r4,DSISR_DABRMATCH@h
1743         bne-    handle_dabr_fault
1744         ld      r4,_DAR(r1)
1745         ld      r5,_DSISR(r1)
1746         addi    r3,r1,STACK_FRAME_OVERHEAD
1747         bl      do_page_fault
1748         cmpdi   r3,0
1749         beq+    12f
1750         bl      save_nvgprs
1751         mr      r5,r3
1752         addi    r3,r1,STACK_FRAME_OVERHEAD
1753         lwz     r4,_DAR(r1)
1754         bl      bad_page_fault
1755         b       ret_from_except
1756
1757 /* We have a data breakpoint exception - handle it */
1758 handle_dabr_fault:
1759         bl      save_nvgprs
1760         ld      r4,_DAR(r1)
1761         ld      r5,_DSISR(r1)
1762         addi    r3,r1,STACK_FRAME_OVERHEAD
1763         bl      do_break
1764 12:     b       ret_from_except_lite
1765
1766
1767 #ifdef CONFIG_PPC_BOOK3S_64
1768 /* We have a page fault that hash_page could handle but HV refused
1769  * the PTE insertion
1770  */
1771 13:     bl      save_nvgprs
1772         mr      r5,r3
1773         addi    r3,r1,STACK_FRAME_OVERHEAD
1774         ld      r4,_DAR(r1)
1775         bl      low_hash_fault
1776         b       ret_from_except
1777 #endif
1778
1779 /*
1780  * We come here as a result of a DSI at a point where we don't want
1781  * to call hash_page, such as when we are accessing memory (possibly
1782  * user memory) inside a PMU interrupt that occurred while interrupts
1783  * were soft-disabled.  We want to invoke the exception handler for
1784  * the access, or panic if there isn't a handler.
1785  */
1786 77:     bl      save_nvgprs
1787         mr      r4,r3
1788         addi    r3,r1,STACK_FRAME_OVERHEAD
1789         li      r5,SIGSEGV
1790         bl      bad_page_fault
1791         b       ret_from_except
1792
1793 /*
1794  * Here we have detected that the kernel stack pointer is bad.
1795  * R9 contains the saved CR, r13 points to the paca,
1796  * r10 contains the (bad) kernel stack pointer,
1797  * r11 and r12 contain the saved SRR0 and SRR1.
1798  * We switch to using an emergency stack, save the registers there,
1799  * and call kernel_bad_stack(), which panics.
1800  */
1801 bad_stack:
1802         ld      r1,PACAEMERGSP(r13)
1803         subi    r1,r1,64+INT_FRAME_SIZE
1804         std     r9,_CCR(r1)
1805         std     r10,GPR1(r1)
1806         std     r11,_NIP(r1)
1807         std     r12,_MSR(r1)
1808         mfspr   r11,SPRN_DAR
1809         mfspr   r12,SPRN_DSISR
1810         std     r11,_DAR(r1)
1811         std     r12,_DSISR(r1)
1812         mflr    r10
1813         mfctr   r11
1814         mfxer   r12
1815         std     r10,_LINK(r1)
1816         std     r11,_CTR(r1)
1817         std     r12,_XER(r1)
1818         SAVE_GPR(0,r1)
1819         SAVE_GPR(2,r1)
1820         ld      r10,EX_R3(r3)
1821         std     r10,GPR3(r1)
1822         SAVE_GPR(4,r1)
1823         SAVE_4GPRS(5,r1)
1824         ld      r9,EX_R9(r3)
1825         ld      r10,EX_R10(r3)
1826         SAVE_2GPRS(9,r1)
1827         ld      r9,EX_R11(r3)
1828         ld      r10,EX_R12(r3)
1829         ld      r11,EX_R13(r3)
1830         std     r9,GPR11(r1)
1831         std     r10,GPR12(r1)
1832         std     r11,GPR13(r1)
1833 BEGIN_FTR_SECTION
1834         ld      r10,EX_CFAR(r3)
1835         std     r10,ORIG_GPR3(r1)
1836 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1837         SAVE_8GPRS(14,r1)
1838         SAVE_10GPRS(22,r1)
1839         lhz     r12,PACA_TRAP_SAVE(r13)
1840         std     r12,_TRAP(r1)
1841         addi    r11,r1,INT_FRAME_SIZE
1842         std     r11,0(r1)
1843         li      r12,0
1844         std     r12,0(r11)
1845         ld      r2,PACATOC(r13)
1846         ld      r11,exception_marker@toc(r2)
1847         std     r12,RESULT(r1)
1848         std     r11,STACK_FRAME_OVERHEAD-16(r1)
1849 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1850         bl      kernel_bad_stack
1851         b       1b
1852 _ASM_NOKPROBE_SYMBOL(bad_stack);
1853
1854 /*
1855  * When doorbell is triggered from system reset wakeup, the message is
1856  * not cleared, so it would fire again when EE is enabled.
1857  *
1858  * When coming from local_irq_enable, there may be the same problem if
1859  * we were hard disabled.
1860  *
1861  * Execute msgclr to clear pending exceptions before handling it.
1862  */
1863 h_doorbell_common_msgclr:
1864         LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1865         PPC_MSGCLR(3)
1866         b       h_doorbell_common
1867
1868 doorbell_super_common_msgclr:
1869         LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1870         PPC_MSGCLRP(3)
1871         b       doorbell_super_common
1872
1873 /*
1874  * Called from arch_local_irq_enable when an interrupt needs
1875  * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1876  * which kind of interrupt. MSR:EE is already off. We generate a
1877  * stackframe like if a real interrupt had happened.
1878  *
1879  * Note: While MSR:EE is off, we need to make sure that _MSR
1880  * in the generated frame has EE set to 1 or the exception
1881  * handler will not properly re-enable them.
1882  *
1883  * Note that we don't specify LR as the NIP (return address) for
1884  * the interrupt because that would unbalance the return branch
1885  * predictor.
1886  */
1887 _GLOBAL(__replay_interrupt)
1888         /* We are going to jump to the exception common code which
1889          * will retrieve various register values from the PACA which
1890          * we don't give a damn about, so we don't bother storing them.
1891          */
1892         mfmsr   r12
1893         LOAD_REG_ADDR(r11, replay_interrupt_return)
1894         mfcr    r9
1895         ori     r12,r12,MSR_EE
1896         cmpwi   r3,0x900
1897         beq     decrementer_common
1898         cmpwi   r3,0x500
1899 BEGIN_FTR_SECTION
1900         beq     h_virt_irq_common
1901 FTR_SECTION_ELSE
1902         beq     hardware_interrupt_common
1903 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
1904         cmpwi   r3,0xf00
1905         beq     performance_monitor_common
1906 BEGIN_FTR_SECTION
1907         cmpwi   r3,0xa00
1908         beq     h_doorbell_common_msgclr
1909         cmpwi   r3,0xe60
1910         beq     hmi_exception_common
1911 FTR_SECTION_ELSE
1912         cmpwi   r3,0xa00
1913         beq     doorbell_super_common_msgclr
1914 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1915 replay_interrupt_return:
1916         blr
1917
1918 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)