1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
3 #define _ASM_POWERPC_NOHASH_PGTABLE_H
5 #if defined(CONFIG_PPC64)
6 #include <asm/nohash/64/pgtable.h>
8 #include <asm/nohash/32/pgtable.h>
11 /* Permission masks used for kernel mappings */
12 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
13 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE)
14 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
15 _PAGE_NO_CACHE | _PAGE_GUARDED)
16 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
17 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
18 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
21 * Protection used for kernel text. We want the debuggers to be able to
22 * set breakpoints anywhere, so don't write protect the kernel text
23 * on platforms where such control is possible.
25 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
26 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
27 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
29 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
32 /* Make modules code happy. We don't set RO yet */
33 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
35 /* Advertise special mapping type for AGP */
36 #define PAGE_AGP (PAGE_KERNEL_NC)
41 /* Generic accessors to PTE bits */
42 static inline int pte_write(pte_t pte)
44 return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO;
46 static inline int pte_read(pte_t pte) { return 1; }
47 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
48 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
49 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
50 static inline bool pte_hashpte(pte_t pte) { return false; }
51 static inline bool pte_ci(pte_t pte) { return pte_val(pte) & _PAGE_NO_CACHE; }
52 static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
53 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
55 #ifdef CONFIG_NUMA_BALANCING
57 * These work without NUMA balancing but the kernel does not care. See the
58 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
59 * work for user pages and always return true for kernel pages.
61 static inline int pte_protnone(pte_t pte)
63 return pte_present(pte) && !pte_user(pte);
66 static inline int pmd_protnone(pmd_t pmd)
68 return pte_protnone(pmd_pte(pmd));
70 #endif /* CONFIG_NUMA_BALANCING */
72 static inline int pte_present(pte_t pte)
74 return pte_val(pte) & _PAGE_PRESENT;
77 static inline bool pte_hw_valid(pte_t pte)
79 return pte_val(pte) & _PAGE_PRESENT;
83 * Don't just check for any non zero bits in __PAGE_USER, since for book3e
84 * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in
85 * _PAGE_USER. Need to explicitly match _PAGE_BAP_UR bit in that case too.
87 static inline bool pte_user(pte_t pte)
89 return (pte_val(pte) & (_PAGE_USER | _PAGE_PRIVILEGED)) == _PAGE_USER;
93 * We only find page table entry in the last level
94 * Hence no need for other accessors
96 #define pte_access_permitted pte_access_permitted
97 static inline bool pte_access_permitted(pte_t pte, bool write)
100 * A read-only access is controlled by _PAGE_USER bit.
101 * We have _PAGE_READ set for WRITE and EXECUTE
103 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
106 if (write && !pte_write(pte))
112 /* Conversion functions: convert a page and protection to a page entry,
113 * and a page entry and page directory to the page they refer to.
115 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
118 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
119 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
120 pgprot_val(pgprot)); }
121 static inline unsigned long pte_pfn(pte_t pte) {
122 return pte_val(pte) >> PTE_RPN_SHIFT; }
124 /* Generic modifiers for PTE bits */
125 static inline pte_t pte_exprotect(pte_t pte)
127 return __pte(pte_val(pte) & ~_PAGE_EXEC);
130 static inline pte_t pte_mkclean(pte_t pte)
132 return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
135 static inline pte_t pte_mkold(pte_t pte)
137 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
140 static inline pte_t pte_mkpte(pte_t pte)
145 static inline pte_t pte_mkspecial(pte_t pte)
147 return __pte(pte_val(pte) | _PAGE_SPECIAL);
150 static inline pte_t pte_mkhuge(pte_t pte)
152 return __pte(pte_val(pte) | _PAGE_HUGE);
155 static inline pte_t pte_mkprivileged(pte_t pte)
157 return __pte((pte_val(pte) & ~_PAGE_USER) | _PAGE_PRIVILEGED);
160 static inline pte_t pte_mkuser(pte_t pte)
162 return __pte((pte_val(pte) & ~_PAGE_PRIVILEGED) | _PAGE_USER);
165 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
167 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
170 /* Insert a PTE, top-level function is out of line. It uses an inline
171 * low level function in the respective pgtable-* files
173 extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
176 /* This low level function performs the actual PTE insertion
177 * Setting the PTE depends on the MMU type and other factors. It's
178 * an horrible mess that I'm not going to try to clean up now but
179 * I'm keeping it in one place rather than spread around
181 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
182 pte_t *ptep, pte_t pte, int percpu)
184 /* Second case is 32-bit with 64-bit PTE. In this case, we
185 * can just store as long as we do the two halves in the right order
186 * with a barrier in between.
187 * In the percpu case, we also fallback to the simple update
189 if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) {
190 __asm__ __volatile__("\
194 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
195 : "r" (pte) : "memory");
198 /* Anything else just stores the PTE normally. That covers all 64-bit
199 * cases, and 32-bit non-hash with 32-bit PTEs.
204 * With hardware tablewalk, a sync is needed to ensure that
205 * subsequent accesses see the PTE we just wrote. Unlike userspace
206 * mappings, we can't tolerate spurious faults, so make sure
207 * the new PTE will be seen the first time.
209 if (IS_ENABLED(CONFIG_PPC_BOOK3E_64) && is_kernel_addr(addr))
214 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
215 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
216 pte_t *ptep, pte_t entry, int dirty);
219 * Macro to mark a page protection value as "uncacheable".
222 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
225 #define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
226 _PAGE_NO_CACHE | _PAGE_GUARDED))
228 #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
231 #define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
234 #if _PAGE_WRITETHRU != 0
235 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
236 _PAGE_COHERENT | _PAGE_WRITETHRU))
238 #define pgprot_cached_wthru(prot) pgprot_noncached(prot)
241 #define pgprot_cached_noncoherent(prot) \
242 (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
244 #define pgprot_writecombine pgprot_noncached_wc
247 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
248 unsigned long size, pgprot_t vma_prot);
249 #define __HAVE_PHYS_MEM_ACCESS_PROT
251 #ifdef CONFIG_HUGETLB_PAGE
252 static inline int hugepd_ok(hugepd_t hpd)
254 #ifdef CONFIG_PPC_8xx
255 return ((hpd_val(hpd) & 0x4) != 0);
257 /* We clear the top bit to indicate hugepd */
258 return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0);
262 static inline int pmd_huge(pmd_t pmd)
267 static inline int pud_huge(pud_t pud)
272 static inline int pgd_huge(pgd_t pgd)
276 #define pgd_huge pgd_huge
278 #define is_hugepd(hpd) (hugepd_ok(hpd))
281 #endif /* __ASSEMBLY__ */