arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/cpu_pm.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/init.h>
  13 #include <linux/highmem.h>
  14 #include <linux/kernel.h>
  15 #include <linux/linkage.h>
  16 #include <linux/preempt.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/bitops.h>
  22
  23 #include <asm/bcache.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/cache.h>
  26 #include <asm/cacheops.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpu-features.h>
  29 #include <asm/cpu-type.h>
  30 #include <asm/io.h>
  31 #include <asm/page.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/r4kcache.h>
  34 #include <asm/sections.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/war.h>
  37 #include <asm/cacheflush.h> /* for run_uncached() */
  38 #include <asm/traps.h>
  39 #include <asm/dma-coherence.h>
  40 #include <asm/mips-cm.h>
  41
  42 /*
  43  * Bits describing what cache ops an SMP callback function may perform.
  44  *
  45  * R4K_HIT   -  Virtual user or kernel address based cache operations. The
  46  *              active_mm must be checked before using user addresses, falling
  47  *              back to kmap.
  48  * R4K_INDEX -  Index based cache operations.
  49  */
  50
  51 #define R4K_HIT         BIT(0)
  52 #define R4K_INDEX       BIT(1)
  53
  54 /**
  55  * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
  56  * @type:       Type of cache operations (R4K_HIT or R4K_INDEX).
  57  *
  58  * Decides whether a cache op needs to be performed on every core in the system.
  59  * This may change depending on the @type of cache operation, as well as the set
  60  * of online CPUs, so preemption should be disabled by the caller to prevent CPU
  61  * hotplug from changing the result.
  62  *
  63  * Returns:     1 if the cache operation @type should be done on every core in
  64  *              the system.
  65  *              0 if the cache operation @type is globalized and only needs to
  66  *              be performed on a simple CPU.
  67  */
  68 static inline bool r4k_op_needs_ipi(unsigned int type)
  69 {
  70         /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
  71         if (mips_cm_present())
  72                 return false;
  73
  74         /*
  75          * Hardware doesn't globalize the required cache ops, so SMP calls may
  76          * be needed, but only if there are foreign CPUs (non-siblings with
  77          * separate caches).
  78          */
  79         /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
  80 #ifdef CONFIG_SMP
  81         return !cpumask_empty(&cpu_foreign_map[0]);
  82 #else
  83         return false;
  84 #endif
  85 }
  86
  87 /*
  88  * Special Variant of smp_call_function for use by cache functions:
  89  *
  90  *  o No return value
  91  *  o collapses to normal function call on UP kernels
  92  *  o collapses to normal function call on systems with a single shared
  93  *    primary cache.
  94  *  o doesn't disable interrupts on the local CPU
  95  */
  96 static inline void r4k_on_each_cpu(unsigned int type,
  97                                    void (*func)(void *info), void *info)
  98 {
  99         preempt_disable();
 100         if (r4k_op_needs_ipi(type))
 101                 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
 102                                        func, info, 1);
 103         func(info);
 104         preempt_enable();
 105 }
 106
 107 /*
 108  * Must die.
 109  */
 110 static unsigned long icache_size __read_mostly;
 111 static unsigned long dcache_size __read_mostly;
 112 static unsigned long vcache_size __read_mostly;
 113 static unsigned long scache_size __read_mostly;
 114
 115 /*
 116  * Dummy cache handling routines for machines without boardcaches
 117  */
 118 static void cache_noop(void) {}
 119
 120 static struct bcache_ops no_sc_ops = {
 121         .bc_enable = (void *)cache_noop,
 122         .bc_disable = (void *)cache_noop,
 123         .bc_wback_inv = (void *)cache_noop,
 124         .bc_inv = (void *)cache_noop
 125 };
 126
 127 struct bcache_ops *bcops = &no_sc_ops;
 128
 129 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
 130 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 131
 132 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
 133 do {                                                                    \
 134         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
 135                 *(volatile unsigned long *)CKSEG1;                      \
 136         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
 137                 __asm__ __volatile__("nop;nop;nop;nop");                \
 138 } while (0)
 139
 140 static void (*r4k_blast_dcache_page)(unsigned long addr);
 141
 142 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 143 {
 144         R4600_HIT_CACHEOP_WAR_IMPL;
 145         blast_dcache32_page(addr);
 146 }
 147
 148 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 149 {
 150         blast_dcache64_page(addr);
 151 }
 152
 153 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
 154 {
 155         blast_dcache128_page(addr);
 156 }
 157
 158 static void r4k_blast_dcache_page_setup(void)
 159 {
 160         unsigned long  dc_lsize = cpu_dcache_line_size();
 161
 162         switch (dc_lsize) {
 163         case 0:
 164                 r4k_blast_dcache_page = (void *)cache_noop;
 165                 break;
 166         case 16:
 167                 r4k_blast_dcache_page = blast_dcache16_page;
 168                 break;
 169         case 32:
 170                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 171                 break;
 172         case 64:
 173                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 174                 break;
 175         case 128:
 176                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
 177                 break;
 178         default:
 179                 break;
 180         }
 181 }
 182
 183 #ifndef CONFIG_EVA
 184 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
 185 #else
 186
 187 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
 188
 189 static void r4k_blast_dcache_user_page_setup(void)
 190 {
 191         unsigned long  dc_lsize = cpu_dcache_line_size();
 192
 193         if (dc_lsize == 0)
 194                 r4k_blast_dcache_user_page = (void *)cache_noop;
 195         else if (dc_lsize == 16)
 196                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
 197         else if (dc_lsize == 32)
 198                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
 199         else if (dc_lsize == 64)
 200                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
 201 }
 202
 203 #endif
 204
 205 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 206
 207 static void r4k_blast_dcache_page_indexed_setup(void)
 208 {
 209         unsigned long dc_lsize = cpu_dcache_line_size();
 210
 211         if (dc_lsize == 0)
 212                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 213         else if (dc_lsize == 16)
 214                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 215         else if (dc_lsize == 32)
 216                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 217         else if (dc_lsize == 64)
 218                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 219         else if (dc_lsize == 128)
 220                 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
 221 }
 222
 223 void (* r4k_blast_dcache)(void);
 224 EXPORT_SYMBOL(r4k_blast_dcache);
 225
 226 static void r4k_blast_dcache_setup(void)
 227 {
 228         unsigned long dc_lsize = cpu_dcache_line_size();
 229
 230         if (dc_lsize == 0)
 231                 r4k_blast_dcache = (void *)cache_noop;
 232         else if (dc_lsize == 16)
 233                 r4k_blast_dcache = blast_dcache16;
 234         else if (dc_lsize == 32)
 235                 r4k_blast_dcache = blast_dcache32;
 236         else if (dc_lsize == 64)
 237                 r4k_blast_dcache = blast_dcache64;
 238         else if (dc_lsize == 128)
 239                 r4k_blast_dcache = blast_dcache128;
 240 }
 241
 242 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 243 #define JUMP_TO_ALIGN(order) \
 244         __asm__ __volatile__( \
 245                 "b\t1f\n\t" \
 246                 ".align\t" #order "\n\t" \
 247                 "1:\n\t" \
 248                 )
 249 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 250 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 251
 252 static inline void blast_r4600_v1_icache32(void)
 253 {
 254         unsigned long flags;
 255
 256         local_irq_save(flags);
 257         blast_icache32();
 258         local_irq_restore(flags);
 259 }
 260
 261 static inline void tx49_blast_icache32(void)
 262 {
 263         unsigned long start = INDEX_BASE;
 264         unsigned long end = start + current_cpu_data.icache.waysize;
 265         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 266         unsigned long ws_end = current_cpu_data.icache.ways <<
 267                                current_cpu_data.icache.waybit;
 268         unsigned long ws, addr;
 269
 270         CACHE32_UNROLL32_ALIGN2;
 271         /* I'm in even chunk.  blast odd chunks */
 272         for (ws = 0; ws < ws_end; ws += ws_inc)
 273                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 274                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 275         CACHE32_UNROLL32_ALIGN;
 276         /* I'm in odd chunk.  blast even chunks */
 277         for (ws = 0; ws < ws_end; ws += ws_inc)
 278                 for (addr = start; addr < end; addr += 0x400 * 2)
 279                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 280 }
 281
 282 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 283 {
 284         unsigned long flags;
 285
 286         local_irq_save(flags);
 287         blast_icache32_page_indexed(page);
 288         local_irq_restore(flags);
 289 }
 290
 291 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 292 {
 293         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 294         unsigned long start = INDEX_BASE + (page & indexmask);
 295         unsigned long end = start + PAGE_SIZE;
 296         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 297         unsigned long ws_end = current_cpu_data.icache.ways <<
 298                                current_cpu_data.icache.waybit;
 299         unsigned long ws, addr;
 300
 301         CACHE32_UNROLL32_ALIGN2;
 302         /* I'm in even chunk.  blast odd chunks */
 303         for (ws = 0; ws < ws_end; ws += ws_inc)
 304                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 305                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 306         CACHE32_UNROLL32_ALIGN;
 307         /* I'm in odd chunk.  blast even chunks */
 308         for (ws = 0; ws < ws_end; ws += ws_inc)
 309                 for (addr = start; addr < end; addr += 0x400 * 2)
 310                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 311 }
 312
 313 static void (* r4k_blast_icache_page)(unsigned long addr);
 314
 315 static void r4k_blast_icache_page_setup(void)
 316 {
 317         unsigned long ic_lsize = cpu_icache_line_size();
 318
 319         if (ic_lsize == 0)
 320                 r4k_blast_icache_page = (void *)cache_noop;
 321         else if (ic_lsize == 16)
 322                 r4k_blast_icache_page = blast_icache16_page;
 323         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
 324                 r4k_blast_icache_page = loongson2_blast_icache32_page;
 325         else if (ic_lsize == 32)
 326                 r4k_blast_icache_page = blast_icache32_page;
 327         else if (ic_lsize == 64)
 328                 r4k_blast_icache_page = blast_icache64_page;
 329         else if (ic_lsize == 128)
 330                 r4k_blast_icache_page = blast_icache128_page;
 331 }
 332
 333 #ifndef CONFIG_EVA
 334 #define r4k_blast_icache_user_page  r4k_blast_icache_page
 335 #else
 336
 337 static void (*r4k_blast_icache_user_page)(unsigned long addr);
 338
 339 static void r4k_blast_icache_user_page_setup(void)
 340 {
 341         unsigned long ic_lsize = cpu_icache_line_size();
 342
 343         if (ic_lsize == 0)
 344                 r4k_blast_icache_user_page = (void *)cache_noop;
 345         else if (ic_lsize == 16)
 346                 r4k_blast_icache_user_page = blast_icache16_user_page;
 347         else if (ic_lsize == 32)
 348                 r4k_blast_icache_user_page = blast_icache32_user_page;
 349         else if (ic_lsize == 64)
 350                 r4k_blast_icache_user_page = blast_icache64_user_page;
 351 }
 352
 353 #endif
 354
 355 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 356
 357 static void r4k_blast_icache_page_indexed_setup(void)
 358 {
 359         unsigned long ic_lsize = cpu_icache_line_size();
 360
 361         if (ic_lsize == 0)
 362                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 363         else if (ic_lsize == 16)
 364                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 365         else if (ic_lsize == 32) {
 366                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 367                         r4k_blast_icache_page_indexed =
 368                                 blast_icache32_r4600_v1_page_indexed;
 369                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 370                         r4k_blast_icache_page_indexed =
 371                                 tx49_blast_icache32_page_indexed;
 372                 else if (current_cpu_type() == CPU_LOONGSON2)
 373                         r4k_blast_icache_page_indexed =
 374                                 loongson2_blast_icache32_page_indexed;
 375                 else
 376                         r4k_blast_icache_page_indexed =
 377                                 blast_icache32_page_indexed;
 378         } else if (ic_lsize == 64)
 379                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 380 }
 381
 382 void (* r4k_blast_icache)(void);
 383 EXPORT_SYMBOL(r4k_blast_icache);
 384
 385 static void r4k_blast_icache_setup(void)
 386 {
 387         unsigned long ic_lsize = cpu_icache_line_size();
 388
 389         if (ic_lsize == 0)
 390                 r4k_blast_icache = (void *)cache_noop;
 391         else if (ic_lsize == 16)
 392                 r4k_blast_icache = blast_icache16;
 393         else if (ic_lsize == 32) {
 394                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 395                         r4k_blast_icache = blast_r4600_v1_icache32;
 396                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 397                         r4k_blast_icache = tx49_blast_icache32;
 398                 else if (current_cpu_type() == CPU_LOONGSON2)
 399                         r4k_blast_icache = loongson2_blast_icache32;
 400                 else
 401                         r4k_blast_icache = blast_icache32;
 402         } else if (ic_lsize == 64)
 403                 r4k_blast_icache = blast_icache64;
 404         else if (ic_lsize == 128)
 405                 r4k_blast_icache = blast_icache128;
 406 }
 407
 408 static void (* r4k_blast_scache_page)(unsigned long addr);
 409
 410 static void r4k_blast_scache_page_setup(void)
 411 {
 412         unsigned long sc_lsize = cpu_scache_line_size();
 413
 414         if (scache_size == 0)
 415                 r4k_blast_scache_page = (void *)cache_noop;
 416         else if (sc_lsize == 16)
 417                 r4k_blast_scache_page = blast_scache16_page;
 418         else if (sc_lsize == 32)
 419                 r4k_blast_scache_page = blast_scache32_page;
 420         else if (sc_lsize == 64)
 421                 r4k_blast_scache_page = blast_scache64_page;
 422         else if (sc_lsize == 128)
 423                 r4k_blast_scache_page = blast_scache128_page;
 424 }
 425
 426 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 427
 428 static void r4k_blast_scache_page_indexed_setup(void)
 429 {
 430         unsigned long sc_lsize = cpu_scache_line_size();
 431
 432         if (scache_size == 0)
 433                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 434         else if (sc_lsize == 16)
 435                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 436         else if (sc_lsize == 32)
 437                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 438         else if (sc_lsize == 64)
 439                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 440         else if (sc_lsize == 128)
 441                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 442 }
 443
 444 static void (* r4k_blast_scache)(void);
 445
 446 static void r4k_blast_scache_setup(void)
 447 {
 448         unsigned long sc_lsize = cpu_scache_line_size();
 449
 450         if (scache_size == 0)
 451                 r4k_blast_scache = (void *)cache_noop;
 452         else if (sc_lsize == 16)
 453                 r4k_blast_scache = blast_scache16;
 454         else if (sc_lsize == 32)
 455                 r4k_blast_scache = blast_scache32;
 456         else if (sc_lsize == 64)
 457                 r4k_blast_scache = blast_scache64;
 458         else if (sc_lsize == 128)
 459                 r4k_blast_scache = blast_scache128;
 460 }
 461
 462 static inline void local_r4k___flush_cache_all(void * args)
 463 {
 464         switch (current_cpu_type()) {
 465         case CPU_LOONGSON2:
 466         case CPU_LOONGSON3:
 467         case CPU_R4000SC:
 468         case CPU_R4000MC:
 469         case CPU_R4400SC:
 470         case CPU_R4400MC:
 471         case CPU_R10000:
 472         case CPU_R12000:
 473         case CPU_R14000:
 474         case CPU_R16000:
 475                 /*
 476                  * These caches are inclusive caches, that is, if something
 477                  * is not cached in the S-cache, we know it also won't be
 478                  * in one of the primary caches.
 479                  */
 480                 r4k_blast_scache();
 481                 break;
 482
 483         case CPU_BMIPS5000:
 484                 r4k_blast_scache();
 485                 __sync();
 486                 break;
 487
 488         default:
 489                 r4k_blast_dcache();
 490                 r4k_blast_icache();
 491                 break;
 492         }
 493 }
 494
 495 static void r4k___flush_cache_all(void)
 496 {
 497         r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
 498 }
 499
 500 /**
 501  * has_valid_asid() - Determine if an mm already has an ASID.
 502  * @mm:         Memory map.
 503  * @type:       R4K_HIT or R4K_INDEX, type of cache op.
 504  *
 505  * Determines whether @mm already has an ASID on any of the CPUs which cache ops
 506  * of type @type within an r4k_on_each_cpu() call will affect. If
 507  * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
 508  * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
 509  * will need to be checked.
 510  *
 511  * Must be called in non-preemptive context.
 512  *
 513  * Returns:     1 if the CPUs affected by @type cache ops have an ASID for @mm.
 514  *              0 otherwise.
 515  */
 516 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
 517 {
 518         unsigned int i;
 519         const cpumask_t *mask = cpu_present_mask;
 520
 521         /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
 522 #ifdef CONFIG_SMP
 523         /*
 524          * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
 525          * each foreign core, so we only need to worry about siblings.
 526          * Otherwise we need to worry about all present CPUs.
 527          */
 528         if (r4k_op_needs_ipi(type))
 529                 mask = &cpu_sibling_map[smp_processor_id()];
 530 #endif
 531         for_each_cpu(i, mask)
 532                 if (cpu_context(i, mm))
 533                         return 1;
 534         return 0;
 535 }
 536
 537 static void r4k__flush_cache_vmap(void)
 538 {
 539         r4k_blast_dcache();
 540 }
 541
 542 static void r4k__flush_cache_vunmap(void)
 543 {
 544         r4k_blast_dcache();
 545 }
 546
 547 /*
 548  * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
 549  * whole caches when vma is executable.
 550  */
 551 static inline void local_r4k_flush_cache_range(void * args)
 552 {
 553         struct vm_area_struct *vma = args;
 554         int exec = vma->vm_flags & VM_EXEC;
 555
 556         if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
 557                 return;
 558
 559         /*
 560          * If dcache can alias, we must blast it since mapping is changing.
 561          * If executable, we must ensure any dirty lines are written back far
 562          * enough to be visible to icache.
 563          */
 564         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 565                 r4k_blast_dcache();
 566         /* If executable, blast stale lines from icache */
 567         if (exec)
 568                 r4k_blast_icache();
 569 }
 570
 571 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 572         unsigned long start, unsigned long end)
 573 {
 574         int exec = vma->vm_flags & VM_EXEC;
 575
 576         if (cpu_has_dc_aliases || exec)
 577                 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
 578 }
 579
 580 static inline void local_r4k_flush_cache_mm(void * args)
 581 {
 582         struct mm_struct *mm = args;
 583
 584         if (!has_valid_asid(mm, R4K_INDEX))
 585                 return;
 586
 587         /*
 588          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 589          * only flush the primary caches but R1x000 behave sane ...
 590          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 591          * caches, so we can bail out early.
 592          */
 593         if (current_cpu_type() == CPU_R4000SC ||
 594             current_cpu_type() == CPU_R4000MC ||
 595             current_cpu_type() == CPU_R4400SC ||
 596             current_cpu_type() == CPU_R4400MC) {
 597                 r4k_blast_scache();
 598                 return;
 599         }
 600
 601         r4k_blast_dcache();
 602 }
 603
 604 static void r4k_flush_cache_mm(struct mm_struct *mm)
 605 {
 606         if (!cpu_has_dc_aliases)
 607                 return;
 608
 609         r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
 610 }
 611
 612 struct flush_cache_page_args {
 613         struct vm_area_struct *vma;
 614         unsigned long addr;
 615         unsigned long pfn;
 616 };
 617
 618 static inline void local_r4k_flush_cache_page(void *args)
 619 {
 620         struct flush_cache_page_args *fcp_args = args;
 621         struct vm_area_struct *vma = fcp_args->vma;
 622         unsigned long addr = fcp_args->addr;
 623         struct page *page = pfn_to_page(fcp_args->pfn);
 624         int exec = vma->vm_flags & VM_EXEC;
 625         struct mm_struct *mm = vma->vm_mm;
 626         int map_coherent = 0;
 627         pgd_t *pgdp;
 628         pud_t *pudp;
 629         pmd_t *pmdp;
 630         pte_t *ptep;
 631         void *vaddr;
 632
 633         /*
 634          * If owns no valid ASID yet, cannot possibly have gotten
 635          * this page into the cache.
 636          */
 637         if (!has_valid_asid(mm, R4K_HIT))
 638                 return;
 639
 640         addr &= PAGE_MASK;
 641         pgdp = pgd_offset(mm, addr);
 642         pudp = pud_offset(pgdp, addr);
 643         pmdp = pmd_offset(pudp, addr);
 644         ptep = pte_offset(pmdp, addr);
 645
 646         /*
 647          * If the page isn't marked valid, the page cannot possibly be
 648          * in the cache.
 649          */
 650         if (!(pte_present(*ptep)))
 651                 return;
 652
 653         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 654                 vaddr = NULL;
 655         else {
 656                 /*
 657                  * Use kmap_coherent or kmap_atomic to do flushes for
 658                  * another ASID than the current one.
 659                  */
 660                 map_coherent = (cpu_has_dc_aliases &&
 661                                 page_mapcount(page) &&
 662                                 !Page_dcache_dirty(page));
 663                 if (map_coherent)
 664                         vaddr = kmap_coherent(page, addr);
 665                 else
 666                         vaddr = kmap_atomic(page);
 667                 addr = (unsigned long)vaddr;
 668         }
 669
 670         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 671                 vaddr ? r4k_blast_dcache_page(addr) :
 672                         r4k_blast_dcache_user_page(addr);
 673                 if (exec && !cpu_icache_snoops_remote_store)
 674                         r4k_blast_scache_page(addr);
 675         }
 676         if (exec) {
 677                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 678                         int cpu = smp_processor_id();
 679
 680                         if (cpu_context(cpu, mm) != 0)
 681                                 drop_mmu_context(mm, cpu);
 682                 } else
 683                         vaddr ? r4k_blast_icache_page(addr) :
 684                                 r4k_blast_icache_user_page(addr);
 685         }
 686
 687         if (vaddr) {
 688                 if (map_coherent)
 689                         kunmap_coherent();
 690                 else
 691                         kunmap_atomic(vaddr);
 692         }
 693 }
 694
 695 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 696         unsigned long addr, unsigned long pfn)
 697 {
 698         struct flush_cache_page_args args;
 699
 700         args.vma = vma;
 701         args.addr = addr;
 702         args.pfn = pfn;
 703
 704         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
 705 }
 706
 707 static inline void local_r4k_flush_data_cache_page(void * addr)
 708 {
 709         r4k_blast_dcache_page((unsigned long) addr);
 710 }
 711
 712 static void r4k_flush_data_cache_page(unsigned long addr)
 713 {
 714         if (in_atomic())
 715                 local_r4k_flush_data_cache_page((void *)addr);
 716         else
 717                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
 718                                 (void *) addr);
 719 }
 720
 721 struct flush_icache_range_args {
 722         unsigned long start;
 723         unsigned long end;
 724 };
 725
 726 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 727 {
 728         if (!cpu_has_ic_fills_f_dc) {
 729                 if (end - start >= dcache_size) {
 730                         r4k_blast_dcache();
 731                 } else {
 732                         R4600_HIT_CACHEOP_WAR_IMPL;
 733                         protected_blast_dcache_range(start, end);
 734                 }
 735         }
 736
 737         if (end - start > icache_size)
 738                 r4k_blast_icache();
 739         else {
 740                 switch (boot_cpu_type()) {
 741                 case CPU_LOONGSON2:
 742                         protected_loongson2_blast_icache_range(start, end);
 743                         break;
 744
 745                 default:
 746                         protected_blast_icache_range(start, end);
 747                         break;
 748                 }
 749         }
 750 #ifdef CONFIG_EVA
 751         /*
 752          * Due to all possible segment mappings, there might cache aliases
 753          * caused by the bootloader being in non-EVA mode, and the CPU switching
 754          * to EVA during early kernel init. It's best to flush the scache
 755          * to avoid having secondary cores fetching stale data and lead to
 756          * kernel crashes.
 757          */
 758         bc_wback_inv(start, (end - start));
 759         __sync();
 760 #endif
 761 }
 762
 763 static inline void local_r4k_flush_icache_range_ipi(void *args)
 764 {
 765         struct flush_icache_range_args *fir_args = args;
 766         unsigned long start = fir_args->start;
 767         unsigned long end = fir_args->end;
 768
 769         local_r4k_flush_icache_range(start, end);
 770 }
 771
 772 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 773 {
 774         struct flush_icache_range_args args;
 775
 776         args.start = start;
 777         args.end = end;
 778
 779         r4k_on_each_cpu(R4K_HIT | R4K_INDEX, local_r4k_flush_icache_range_ipi,
 780                         &args);
 781         instruction_hazard();
 782 }
 783
 784 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 785
 786 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 787 {
 788         /* Catch bad driver code */
 789         BUG_ON(size == 0);
 790
 791         preempt_disable();
 792         if (cpu_has_inclusive_pcaches) {
 793                 if (size >= scache_size)
 794                         r4k_blast_scache();
 795                 else
 796                         blast_scache_range(addr, addr + size);
 797                 preempt_enable();
 798                 __sync();
 799                 return;
 800         }
 801
 802         /*
 803          * Either no secondary cache or the available caches don't have the
 804          * subset property so we have to flush the primary caches
 805          * explicitly
 806          */
 807         if (size >= dcache_size) {
 808                 r4k_blast_dcache();
 809         } else {
 810                 R4600_HIT_CACHEOP_WAR_IMPL;
 811                 blast_dcache_range(addr, addr + size);
 812         }
 813         preempt_enable();
 814
 815         bc_wback_inv(addr, size);
 816         __sync();
 817 }
 818
 819 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 820 {
 821         /* Catch bad driver code */
 822         BUG_ON(size == 0);
 823
 824         preempt_disable();
 825         if (cpu_has_inclusive_pcaches) {
 826                 if (size >= scache_size)
 827                         r4k_blast_scache();
 828                 else {
 829                         /*
 830                          * There is no clearly documented alignment requirement
 831                          * for the cache instruction on MIPS processors and
 832                          * some processors, among them the RM5200 and RM7000
 833                          * QED processors will throw an address error for cache
 834                          * hit ops with insufficient alignment.  Solved by
 835                          * aligning the address to cache line size.
 836                          */
 837                         blast_inv_scache_range(addr, addr + size);
 838                 }
 839                 preempt_enable();
 840                 __sync();
 841                 return;
 842         }
 843
 844         if (size >= dcache_size) {
 845                 r4k_blast_dcache();
 846         } else {
 847                 R4600_HIT_CACHEOP_WAR_IMPL;
 848                 blast_inv_dcache_range(addr, addr + size);
 849         }
 850         preempt_enable();
 851
 852         bc_inv(addr, size);
 853         __sync();
 854 }
 855 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 856
 857 struct flush_cache_sigtramp_args {
 858         struct mm_struct *mm;
 859         struct page *page;
 860         unsigned long addr;
 861 };
 862
 863 /*
 864  * While we're protected against bad userland addresses we don't care
 865  * very much about what happens in that case.  Usually a segmentation
 866  * fault will dump the process later on anyway ...
 867  */
 868 static void local_r4k_flush_cache_sigtramp(void *args)
 869 {
 870         struct flush_cache_sigtramp_args *fcs_args = args;
 871         unsigned long addr = fcs_args->addr;
 872         struct page *page = fcs_args->page;
 873         struct mm_struct *mm = fcs_args->mm;
 874         int map_coherent = 0;
 875         void *vaddr;
 876
 877         unsigned long ic_lsize = cpu_icache_line_size();
 878         unsigned long dc_lsize = cpu_dcache_line_size();
 879         unsigned long sc_lsize = cpu_scache_line_size();
 880
 881         /*
 882          * If owns no valid ASID yet, cannot possibly have gotten
 883          * this page into the cache.
 884          */
 885         if (!has_valid_asid(mm, R4K_HIT))
 886                 return;
 887
 888         if (mm == current->active_mm) {
 889                 vaddr = NULL;
 890         } else {
 891                 /*
 892                  * Use kmap_coherent or kmap_atomic to do flushes for
 893                  * another ASID than the current one.
 894                  */
 895                 map_coherent = (cpu_has_dc_aliases &&
 896                                 page_mapcount(page) &&
 897                                 !Page_dcache_dirty(page));
 898                 if (map_coherent)
 899                         vaddr = kmap_coherent(page, addr);
 900                 else
 901                         vaddr = kmap_atomic(page);
 902                 addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
 903         }
 904
 905         R4600_HIT_CACHEOP_WAR_IMPL;
 906         if (!cpu_has_ic_fills_f_dc) {
 907                 if (dc_lsize)
 908                         vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
 909                               : protected_writeback_dcache_line(
 910                                                         addr & ~(dc_lsize - 1));
 911                 if (!cpu_icache_snoops_remote_store && scache_size)
 912                         vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
 913                               : protected_writeback_scache_line(
 914                                                         addr & ~(sc_lsize - 1));
 915         }
 916         if (ic_lsize)
 917                 vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
 918                       : protected_flush_icache_line(addr & ~(ic_lsize - 1));
 919
 920         if (vaddr) {
 921                 if (map_coherent)
 922                         kunmap_coherent();
 923                 else
 924                         kunmap_atomic(vaddr);
 925         }
 926
 927         if (MIPS4K_ICACHE_REFILL_WAR) {
 928                 __asm__ __volatile__ (
 929                         ".set push\n\t"
 930                         ".set noat\n\t"
 931                         ".set "MIPS_ISA_LEVEL"\n\t"
 932 #ifdef CONFIG_32BIT
 933                         "la     $at,1f\n\t"
 934 #endif
 935 #ifdef CONFIG_64BIT
 936                         "dla    $at,1f\n\t"
 937 #endif
 938                         "cache  %0,($at)\n\t"
 939                         "nop; nop; nop\n"
 940                         "1:\n\t"
 941                         ".set pop"
 942                         :
 943                         : "i" (Hit_Invalidate_I));
 944         }
 945         if (MIPS_CACHE_SYNC_WAR)
 946                 __asm__ __volatile__ ("sync");
 947 }
 948
 949 static void r4k_flush_cache_sigtramp(unsigned long addr)
 950 {
 951         struct flush_cache_sigtramp_args args;
 952         int npages;
 953
 954         down_read(&current->mm->mmap_sem);
 955
 956         npages = get_user_pages_fast(addr, 1, 0, &args.page);
 957         if (npages < 1)
 958                 goto out;
 959
 960         args.mm = current->mm;
 961         args.addr = addr;
 962
 963         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
 964
 965         put_page(args.page);
 966 out:
 967         up_read(&current->mm->mmap_sem);
 968 }
 969
 970 static void r4k_flush_icache_all(void)
 971 {
 972         if (cpu_has_vtag_icache)
 973                 r4k_blast_icache();
 974 }
 975
 976 struct flush_kernel_vmap_range_args {
 977         unsigned long   vaddr;
 978         int             size;
 979 };
 980
 981 static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
 982 {
 983         /*
 984          * Aliases only affect the primary caches so don't bother with
 985          * S-caches or T-caches.
 986          */
 987         r4k_blast_dcache();
 988 }
 989
 990 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 991 {
 992         struct flush_kernel_vmap_range_args *vmra = args;
 993         unsigned long vaddr = vmra->vaddr;
 994         int size = vmra->size;
 995
 996         /*
 997          * Aliases only affect the primary caches so don't bother with
 998          * S-caches or T-caches.
 999          */
1000         R4600_HIT_CACHEOP_WAR_IMPL;
1001         blast_dcache_range(vaddr, vaddr + size);
1002 }
1003
1004 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1005 {
1006         struct flush_kernel_vmap_range_args args;
1007
1008         args.vaddr = (unsigned long) vaddr;
1009         args.size = size;
1010
1011         if (size >= dcache_size)
1012                 r4k_on_each_cpu(R4K_INDEX,
1013                                 local_r4k_flush_kernel_vmap_range_index, NULL);
1014         else
1015                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1016                                 &args);
1017 }
1018
1019 static inline void rm7k_erratum31(void)
1020 {
1021         const unsigned long ic_lsize = 32;
1022         unsigned long addr;
1023
1024         /* RM7000 erratum #31. The icache is screwed at startup. */
1025         write_c0_taglo(0);
1026         write_c0_taghi(0);
1027
1028         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1029                 __asm__ __volatile__ (
1030                         ".set push\n\t"
1031                         ".set noreorder\n\t"
1032                         ".set mips3\n\t"
1033                         "cache\t%1, 0(%0)\n\t"
1034                         "cache\t%1, 0x1000(%0)\n\t"
1035                         "cache\t%1, 0x2000(%0)\n\t"
1036                         "cache\t%1, 0x3000(%0)\n\t"
1037                         "cache\t%2, 0(%0)\n\t"
1038                         "cache\t%2, 0x1000(%0)\n\t"
1039                         "cache\t%2, 0x2000(%0)\n\t"
1040                         "cache\t%2, 0x3000(%0)\n\t"
1041                         "cache\t%1, 0(%0)\n\t"
1042                         "cache\t%1, 0x1000(%0)\n\t"
1043                         "cache\t%1, 0x2000(%0)\n\t"
1044                         "cache\t%1, 0x3000(%0)\n\t"
1045                         ".set pop\n"
1046                         :
1047                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
1048         }
1049 }
1050
1051 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
1052 {
1053         unsigned int imp = c->processor_id & PRID_IMP_MASK;
1054         unsigned int rev = c->processor_id & PRID_REV_MASK;
1055         int present = 0;
1056
1057         /*
1058          * Early versions of the 74K do not update the cache tags on a
1059          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
1060          * aliases.  In this case it is better to treat the cache as always
1061          * having aliases.  Also disable the synonym tag update feature
1062          * where available.  In this case no opportunistic tag update will
1063          * happen where a load causes a virtual address miss but a physical
1064          * address hit during a D-cache look-up.
1065          */
1066         switch (imp) {
1067         case PRID_IMP_74K:
1068                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1069                         present = 1;
1070                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1071                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1072                 break;
1073         case PRID_IMP_1074K:
1074                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1075                         present = 1;
1076                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1077                 }
1078                 break;
1079         default:
1080                 BUG();
1081         }
1082
1083         return present;
1084 }
1085
1086 static void b5k_instruction_hazard(void)
1087 {
1088         __sync();
1089         __sync();
1090         __asm__ __volatile__(
1091         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1092         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1093         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1094         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1095         : : : "memory");
1096 }
1097
1098 static char *way_string[] = { NULL, "direct mapped", "2-way",
1099         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1100         "9-way", "10-way", "11-way", "12-way",
1101         "13-way", "14-way", "15-way", "16-way",
1102 };
1103
1104 static void probe_pcache(void)
1105 {
1106         struct cpuinfo_mips *c = &current_cpu_data;
1107         unsigned int config = read_c0_config();
1108         unsigned int prid = read_c0_prid();
1109         int has_74k_erratum = 0;
1110         unsigned long config1;
1111         unsigned int lsize;
1112
1113         switch (current_cpu_type()) {
1114         case CPU_R4600:                 /* QED style two way caches? */
1115         case CPU_R4700:
1116         case CPU_R5000:
1117         case CPU_NEVADA:
1118                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1119                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1120                 c->icache.ways = 2;
1121                 c->icache.waybit = __ffs(icache_size/2);
1122
1123                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1124                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1125                 c->dcache.ways = 2;
1126                 c->dcache.waybit= __ffs(dcache_size/2);
1127
1128                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1129                 break;
1130
1131         case CPU_R5432:
1132         case CPU_R5500:
1133                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1134                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1135                 c->icache.ways = 2;
1136                 c->icache.waybit= 0;
1137
1138                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1139                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1140                 c->dcache.ways = 2;
1141                 c->dcache.waybit = 0;
1142
1143                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1144                 break;
1145
1146         case CPU_TX49XX:
1147                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1148                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1149                 c->icache.ways = 4;
1150                 c->icache.waybit= 0;
1151
1152                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1153                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1154                 c->dcache.ways = 4;
1155                 c->dcache.waybit = 0;
1156
1157                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1158                 c->options |= MIPS_CPU_PREFETCH;
1159                 break;
1160
1161         case CPU_R4000PC:
1162         case CPU_R4000SC:
1163         case CPU_R4000MC:
1164         case CPU_R4400PC:
1165         case CPU_R4400SC:
1166         case CPU_R4400MC:
1167         case CPU_R4300:
1168                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1169                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1170                 c->icache.ways = 1;
1171                 c->icache.waybit = 0;   /* doesn't matter */
1172
1173                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1174                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1175                 c->dcache.ways = 1;
1176                 c->dcache.waybit = 0;   /* does not matter */
1177
1178                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1179                 break;
1180
1181         case CPU_R10000:
1182         case CPU_R12000:
1183         case CPU_R14000:
1184         case CPU_R16000:
1185                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1186                 c->icache.linesz = 64;
1187                 c->icache.ways = 2;
1188                 c->icache.waybit = 0;
1189
1190                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1191                 c->dcache.linesz = 32;
1192                 c->dcache.ways = 2;
1193                 c->dcache.waybit = 0;
1194
1195                 c->options |= MIPS_CPU_PREFETCH;
1196                 break;
1197
1198         case CPU_VR4133:
1199                 write_c0_config(config & ~VR41_CONF_P4K);
1200         case CPU_VR4131:
1201                 /* Workaround for cache instruction bug of VR4131 */
1202                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1203                     c->processor_id == 0x0c82U) {
1204                         config |= 0x00400000U;
1205                         if (c->processor_id == 0x0c80U)
1206                                 config |= VR41_CONF_BP;
1207                         write_c0_config(config);
1208                 } else
1209                         c->options |= MIPS_CPU_CACHE_CDEX_P;
1210
1211                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1212                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1213                 c->icache.ways = 2;
1214                 c->icache.waybit = __ffs(icache_size/2);
1215
1216                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1217                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1218                 c->dcache.ways = 2;
1219                 c->dcache.waybit = __ffs(dcache_size/2);
1220                 break;
1221
1222         case CPU_VR41XX:
1223         case CPU_VR4111:
1224         case CPU_VR4121:
1225         case CPU_VR4122:
1226         case CPU_VR4181:
1227         case CPU_VR4181A:
1228                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1229                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1230                 c->icache.ways = 1;
1231                 c->icache.waybit = 0;   /* doesn't matter */
1232
1233                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1234                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1235                 c->dcache.ways = 1;
1236                 c->dcache.waybit = 0;   /* does not matter */
1237
1238                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1239                 break;
1240
1241         case CPU_RM7000:
1242                 rm7k_erratum31();
1243
1244                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1245                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1246                 c->icache.ways = 4;
1247                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1248
1249                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1250                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1251                 c->dcache.ways = 4;
1252                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1253
1254                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1255                 c->options |= MIPS_CPU_PREFETCH;
1256                 break;
1257
1258         case CPU_LOONGSON2:
1259                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1260                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1261                 if (prid & 0x3)
1262                         c->icache.ways = 4;
1263                 else
1264                         c->icache.ways = 2;
1265                 c->icache.waybit = 0;
1266
1267                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1268                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1269                 if (prid & 0x3)
1270                         c->dcache.ways = 4;
1271                 else
1272                         c->dcache.ways = 2;
1273                 c->dcache.waybit = 0;
1274                 break;
1275
1276         case CPU_LOONGSON3:
1277                 config1 = read_c0_config1();
1278                 lsize = (config1 >> 19) & 7;
1279                 if (lsize)
1280                         c->icache.linesz = 2 << lsize;
1281                 else
1282                         c->icache.linesz = 0;
1283                 c->icache.sets = 64 << ((config1 >> 22) & 7);
1284                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1285                 icache_size = c->icache.sets *
1286                                           c->icache.ways *
1287                                           c->icache.linesz;
1288                 c->icache.waybit = 0;
1289
1290                 lsize = (config1 >> 10) & 7;
1291                 if (lsize)
1292                         c->dcache.linesz = 2 << lsize;
1293                 else
1294                         c->dcache.linesz = 0;
1295                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1296                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1297                 dcache_size = c->dcache.sets *
1298                                           c->dcache.ways *
1299                                           c->dcache.linesz;
1300                 c->dcache.waybit = 0;
1301                 if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
1302                         c->options |= MIPS_CPU_PREFETCH;
1303                 break;
1304
1305         case CPU_CAVIUM_OCTEON3:
1306                 /* For now lie about the number of ways. */
1307                 c->icache.linesz = 128;
1308                 c->icache.sets = 16;
1309                 c->icache.ways = 8;
1310                 c->icache.flags |= MIPS_CACHE_VTAG;
1311                 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1312
1313                 c->dcache.linesz = 128;
1314                 c->dcache.ways = 8;
1315                 c->dcache.sets = 8;
1316                 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1317                 c->options |= MIPS_CPU_PREFETCH;
1318                 break;
1319
1320         default:
1321                 if (!(config & MIPS_CONF_M))
1322                         panic("Don't know how to probe P-caches on this cpu.");
1323
1324                 /*
1325                  * So we seem to be a MIPS32 or MIPS64 CPU
1326                  * So let's probe the I-cache ...
1327                  */
1328                 config1 = read_c0_config1();
1329
1330                 lsize = (config1 >> 19) & 7;
1331
1332                 /* IL == 7 is reserved */
1333                 if (lsize == 7)
1334                         panic("Invalid icache line size");
1335
1336                 c->icache.linesz = lsize ? 2 << lsize : 0;
1337
1338                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1339                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1340
1341                 icache_size = c->icache.sets *
1342                               c->icache.ways *
1343                               c->icache.linesz;
1344                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1345
1346                 if (config & 0x8)               /* VI bit */
1347                         c->icache.flags |= MIPS_CACHE_VTAG;
1348
1349                 /*
1350                  * Now probe the MIPS32 / MIPS64 data cache.
1351                  */
1352                 c->dcache.flags = 0;
1353
1354                 lsize = (config1 >> 10) & 7;
1355
1356                 /* DL == 7 is reserved */
1357                 if (lsize == 7)
1358                         panic("Invalid dcache line size");
1359
1360                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1361
1362                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1363                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1364
1365                 dcache_size = c->dcache.sets *
1366                               c->dcache.ways *
1367                               c->dcache.linesz;
1368                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1369
1370                 c->options |= MIPS_CPU_PREFETCH;
1371                 break;
1372         }
1373
1374         /*
1375          * Processor configuration sanity check for the R4000SC erratum
1376          * #5.  With page sizes larger than 32kB there is no possibility
1377          * to get a VCE exception anymore so we don't care about this
1378          * misconfiguration.  The case is rather theoretical anyway;
1379          * presumably no vendor is shipping his hardware in the "bad"
1380          * configuration.
1381          */
1382         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1383             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1384             !(config & CONF_SC) && c->icache.linesz != 16 &&
1385             PAGE_SIZE <= 0x8000)
1386                 panic("Improper R4000SC processor configuration detected");
1387
1388         /* compute a couple of other cache variables */
1389         c->icache.waysize = icache_size / c->icache.ways;
1390         c->dcache.waysize = dcache_size / c->dcache.ways;
1391
1392         c->icache.sets = c->icache.linesz ?
1393                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1394         c->dcache.sets = c->dcache.linesz ?
1395                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1396
1397         /*
1398          * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
1399          * virtually indexed so normally would suffer from aliases.  So
1400          * normally they'd suffer from aliases but magic in the hardware deals
1401          * with that for us so we don't need to take care ourselves.
1402          */
1403         switch (current_cpu_type()) {
1404         case CPU_20KC:
1405         case CPU_25KF:
1406         case CPU_SB1:
1407         case CPU_SB1A:
1408         case CPU_XLR:
1409                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1410                 break;
1411
1412         case CPU_R10000:
1413         case CPU_R12000:
1414         case CPU_R14000:
1415         case CPU_R16000:
1416                 break;
1417
1418         case CPU_74K:
1419         case CPU_1074K:
1420                 has_74k_erratum = alias_74k_erratum(c);
1421                 /* Fall through. */
1422         case CPU_M14KC:
1423         case CPU_M14KEC:
1424         case CPU_24K:
1425         case CPU_34K:
1426         case CPU_1004K:
1427         case CPU_INTERAPTIV:
1428         case CPU_P5600:
1429         case CPU_PROAPTIV:
1430         case CPU_M5150:
1431         case CPU_QEMU_GENERIC:
1432         case CPU_I6400:
1433         case CPU_P6600:
1434         case CPU_M6250:
1435                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1436                     (c->icache.waysize > PAGE_SIZE))
1437                         c->icache.flags |= MIPS_CACHE_ALIASES;
1438                 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1439                         /*
1440                          * Effectively physically indexed dcache,
1441                          * thus no virtual aliases.
1442                         */
1443                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1444                         break;
1445                 }
1446         default:
1447                 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1448                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1449         }
1450
1451         switch (current_cpu_type()) {
1452         case CPU_20KC:
1453                 /*
1454                  * Some older 20Kc chips doesn't have the 'VI' bit in
1455                  * the config register.
1456                  */
1457                 c->icache.flags |= MIPS_CACHE_VTAG;
1458                 break;
1459
1460         case CPU_ALCHEMY:
1461         case CPU_I6400:
1462                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1463                 break;
1464
1465         case CPU_BMIPS5000:
1466                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1467                 /* Cache aliases are handled in hardware; allow HIGHMEM */
1468                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1469                 break;
1470
1471         case CPU_LOONGSON2:
1472                 /*
1473                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1474                  * one op will act on all 4 ways
1475                  */
1476                 c->icache.ways = 1;
1477         }
1478
1479         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1480                icache_size >> 10,
1481                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1482                way_string[c->icache.ways], c->icache.linesz);
1483
1484         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1485                dcache_size >> 10, way_string[c->dcache.ways],
1486                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1487                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1488                         "cache aliases" : "no aliases",
1489                c->dcache.linesz);
1490 }
1491
1492 static void probe_vcache(void)
1493 {
1494         struct cpuinfo_mips *c = &current_cpu_data;
1495         unsigned int config2, lsize;
1496
1497         if (current_cpu_type() != CPU_LOONGSON3)
1498                 return;
1499
1500         config2 = read_c0_config2();
1501         if ((lsize = ((config2 >> 20) & 15)))
1502                 c->vcache.linesz = 2 << lsize;
1503         else
1504                 c->vcache.linesz = lsize;
1505
1506         c->vcache.sets = 64 << ((config2 >> 24) & 15);
1507         c->vcache.ways = 1 + ((config2 >> 16) & 15);
1508
1509         vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1510
1511         c->vcache.waybit = 0;
1512
1513         pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1514                 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1515 }
1516
1517 /*
1518  * If you even _breathe_ on this function, look at the gcc output and make sure
1519  * it does not pop things on and off the stack for the cache sizing loop that
1520  * executes in KSEG1 space or else you will crash and burn badly.  You have
1521  * been warned.
1522  */
1523 static int probe_scache(void)
1524 {
1525         unsigned long flags, addr, begin, end, pow2;
1526         unsigned int config = read_c0_config();
1527         struct cpuinfo_mips *c = &current_cpu_data;
1528
1529         if (config & CONF_SC)
1530                 return 0;
1531
1532         begin = (unsigned long) &_stext;
1533         begin &= ~((4 * 1024 * 1024) - 1);
1534         end = begin + (4 * 1024 * 1024);
1535
1536         /*
1537          * This is such a bitch, you'd think they would make it easy to do
1538          * this.  Away you daemons of stupidity!
1539          */
1540         local_irq_save(flags);
1541
1542         /* Fill each size-multiple cache line with a valid tag. */
1543         pow2 = (64 * 1024);
1544         for (addr = begin; addr < end; addr = (begin + pow2)) {
1545                 unsigned long *p = (unsigned long *) addr;
1546                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1547                 pow2 <<= 1;
1548         }
1549
1550         /* Load first line with zero (therefore invalid) tag. */
1551         write_c0_taglo(0);
1552         write_c0_taghi(0);
1553         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1554         cache_op(Index_Store_Tag_I, begin);
1555         cache_op(Index_Store_Tag_D, begin);
1556         cache_op(Index_Store_Tag_SD, begin);
1557
1558         /* Now search for the wrap around point. */
1559         pow2 = (128 * 1024);
1560         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1561                 cache_op(Index_Load_Tag_SD, addr);
1562                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1563                 if (!read_c0_taglo())
1564                         break;
1565                 pow2 <<= 1;
1566         }
1567         local_irq_restore(flags);
1568         addr -= begin;
1569
1570         scache_size = addr;
1571         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1572         c->scache.ways = 1;
1573         c->scache.waybit = 0;           /* does not matter */
1574
1575         return 1;
1576 }
1577
1578 static void __init loongson2_sc_init(void)
1579 {
1580         struct cpuinfo_mips *c = &current_cpu_data;
1581
1582         scache_size = 512*1024;
1583         c->scache.linesz = 32;
1584         c->scache.ways = 4;
1585         c->scache.waybit = 0;
1586         c->scache.waysize = scache_size / (c->scache.ways);
1587         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1588         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1589                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1590
1591         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1592 }
1593
1594 static void __init loongson3_sc_init(void)
1595 {
1596         struct cpuinfo_mips *c = &current_cpu_data;
1597         unsigned int config2, lsize;
1598
1599         config2 = read_c0_config2();
1600         lsize = (config2 >> 4) & 15;
1601         if (lsize)
1602                 c->scache.linesz = 2 << lsize;
1603         else
1604                 c->scache.linesz = 0;
1605         c->scache.sets = 64 << ((config2 >> 8) & 15);
1606         c->scache.ways = 1 + (config2 & 15);
1607
1608         scache_size = c->scache.sets *
1609                                   c->scache.ways *
1610                                   c->scache.linesz;
1611         /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1612         scache_size *= 4;
1613         c->scache.waybit = 0;
1614         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1615                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1616         if (scache_size)
1617                 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1618         return;
1619 }
1620
1621 extern int r5k_sc_init(void);
1622 extern int rm7k_sc_init(void);
1623 extern int mips_sc_init(void);
1624
1625 static void setup_scache(void)
1626 {
1627         struct cpuinfo_mips *c = &current_cpu_data;
1628         unsigned int config = read_c0_config();
1629         int sc_present = 0;
1630
1631         /*
1632          * Do the probing thing on R4000SC and R4400SC processors.  Other
1633          * processors don't have a S-cache that would be relevant to the
1634          * Linux memory management.
1635          */
1636         switch (current_cpu_type()) {
1637         case CPU_R4000SC:
1638         case CPU_R4000MC:
1639         case CPU_R4400SC:
1640         case CPU_R4400MC:
1641                 sc_present = run_uncached(probe_scache);
1642                 if (sc_present)
1643                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1644                 break;
1645
1646         case CPU_R10000:
1647         case CPU_R12000:
1648         case CPU_R14000:
1649         case CPU_R16000:
1650                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1651                 c->scache.linesz = 64 << ((config >> 13) & 1);
1652                 c->scache.ways = 2;
1653                 c->scache.waybit= 0;
1654                 sc_present = 1;
1655                 break;
1656
1657         case CPU_R5000:
1658         case CPU_NEVADA:
1659 #ifdef CONFIG_R5000_CPU_SCACHE
1660                 r5k_sc_init();
1661 #endif
1662                 return;
1663
1664         case CPU_RM7000:
1665 #ifdef CONFIG_RM7000_CPU_SCACHE
1666                 rm7k_sc_init();
1667 #endif
1668                 return;
1669
1670         case CPU_LOONGSON2:
1671                 loongson2_sc_init();
1672                 return;
1673
1674         case CPU_LOONGSON3:
1675                 loongson3_sc_init();
1676                 return;
1677
1678         case CPU_CAVIUM_OCTEON3:
1679         case CPU_XLP:
1680                 /* don't need to worry about L2, fully coherent */
1681                 return;
1682
1683         default:
1684                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1685                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1686                                     MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1687 #ifdef CONFIG_MIPS_CPU_SCACHE
1688                         if (mips_sc_init ()) {
1689                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1690                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1691                                        scache_size >> 10,
1692                                        way_string[c->scache.ways], c->scache.linesz);
1693                         }
1694 #else
1695                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1696                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1697 #endif
1698                         return;
1699                 }
1700                 sc_present = 0;
1701         }
1702
1703         if (!sc_present)
1704                 return;
1705
1706         /* compute a couple of other cache variables */
1707         c->scache.waysize = scache_size / c->scache.ways;
1708
1709         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1710
1711         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1712                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1713
1714         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1715 }
1716
1717 void au1x00_fixup_config_od(void)
1718 {
1719         /*
1720          * c0_config.od (bit 19) was write only (and read as 0)
1721          * on the early revisions of Alchemy SOCs.  It disables the bus
1722          * transaction overlapping and needs to be set to fix various errata.
1723          */
1724         switch (read_c0_prid()) {
1725         case 0x00030100: /* Au1000 DA */
1726         case 0x00030201: /* Au1000 HA */
1727         case 0x00030202: /* Au1000 HB */
1728         case 0x01030200: /* Au1500 AB */
1729         /*
1730          * Au1100 errata actually keeps silence about this bit, so we set it
1731          * just in case for those revisions that require it to be set according
1732          * to the (now gone) cpu table.
1733          */
1734         case 0x02030200: /* Au1100 AB */
1735         case 0x02030201: /* Au1100 BA */
1736         case 0x02030202: /* Au1100 BC */
1737                 set_c0_config(1 << 19);
1738                 break;
1739         }
1740 }
1741
1742 /* CP0 hazard avoidance. */
1743 #define NXP_BARRIER()                                                   \
1744          __asm__ __volatile__(                                          \
1745         ".set noreorder\n\t"                                            \
1746         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1747         ".set reorder\n\t")
1748
1749 static void nxp_pr4450_fixup_config(void)
1750 {
1751         unsigned long config0;
1752
1753         config0 = read_c0_config();
1754
1755         /* clear all three cache coherency fields */
1756         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1757         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1758                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1759                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1760         write_c0_config(config0);
1761         NXP_BARRIER();
1762 }
1763
1764 static int cca = -1;
1765
1766 static int __init cca_setup(char *str)
1767 {
1768         get_option(&str, &cca);
1769
1770         return 0;
1771 }
1772
1773 early_param("cca", cca_setup);
1774
1775 static void coherency_setup(void)
1776 {
1777         if (cca < 0 || cca > 7)
1778                 cca = read_c0_config() & CONF_CM_CMASK;
1779         _page_cachable_default = cca << _CACHE_SHIFT;
1780
1781         pr_debug("Using cache attribute %d\n", cca);
1782         change_c0_config(CONF_CM_CMASK, cca);
1783
1784         /*
1785          * c0_status.cu=0 specifies that updates by the sc instruction use
1786          * the coherency mode specified by the TLB; 1 means cachable
1787          * coherent update on write will be used.  Not all processors have
1788          * this bit and; some wire it to zero, others like Toshiba had the
1789          * silly idea of putting something else there ...
1790          */
1791         switch (current_cpu_type()) {
1792         case CPU_R4000PC:
1793         case CPU_R4000SC:
1794         case CPU_R4000MC:
1795         case CPU_R4400PC:
1796         case CPU_R4400SC:
1797         case CPU_R4400MC:
1798                 clear_c0_config(CONF_CU);
1799                 break;
1800         /*
1801          * We need to catch the early Alchemy SOCs with
1802          * the write-only co_config.od bit and set it back to one on:
1803          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1804          */
1805         case CPU_ALCHEMY:
1806                 au1x00_fixup_config_od();
1807                 break;
1808
1809         case PRID_IMP_PR4450:
1810                 nxp_pr4450_fixup_config();
1811                 break;
1812         }
1813 }
1814
1815 static void r4k_cache_error_setup(void)
1816 {
1817         extern char __weak except_vec2_generic;
1818         extern char __weak except_vec2_sb1;
1819
1820         switch (current_cpu_type()) {
1821         case CPU_SB1:
1822         case CPU_SB1A:
1823                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1824                 break;
1825
1826         default:
1827                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1828                 break;
1829         }
1830 }
1831
1832 void r4k_cache_init(void)
1833 {
1834         extern void build_clear_page(void);
1835         extern void build_copy_page(void);
1836         struct cpuinfo_mips *c = &current_cpu_data;
1837
1838         probe_pcache();
1839         probe_vcache();
1840         setup_scache();
1841
1842         r4k_blast_dcache_page_setup();
1843         r4k_blast_dcache_page_indexed_setup();
1844         r4k_blast_dcache_setup();
1845         r4k_blast_icache_page_setup();
1846         r4k_blast_icache_page_indexed_setup();
1847         r4k_blast_icache_setup();
1848         r4k_blast_scache_page_setup();
1849         r4k_blast_scache_page_indexed_setup();
1850         r4k_blast_scache_setup();
1851 #ifdef CONFIG_EVA
1852         r4k_blast_dcache_user_page_setup();
1853         r4k_blast_icache_user_page_setup();
1854 #endif
1855
1856         /*
1857          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1858          * This code supports virtually indexed processors and will be
1859          * unnecessarily inefficient on physically indexed processors.
1860          */
1861         if (c->dcache.linesz && cpu_has_dc_aliases)
1862                 shm_align_mask = max_t( unsigned long,
1863                                         c->dcache.sets * c->dcache.linesz - 1,
1864                                         PAGE_SIZE - 1);
1865         else
1866                 shm_align_mask = PAGE_SIZE-1;
1867
1868         __flush_cache_vmap      = r4k__flush_cache_vmap;
1869         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1870
1871         flush_cache_all         = cache_noop;
1872         __flush_cache_all       = r4k___flush_cache_all;
1873         flush_cache_mm          = r4k_flush_cache_mm;
1874         flush_cache_page        = r4k_flush_cache_page;
1875         flush_cache_range       = r4k_flush_cache_range;
1876
1877         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1878
1879         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1880         flush_icache_all        = r4k_flush_icache_all;
1881         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1882         flush_data_cache_page   = r4k_flush_data_cache_page;
1883         flush_icache_range      = r4k_flush_icache_range;
1884         local_flush_icache_range        = local_r4k_flush_icache_range;
1885
1886 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1887         if (coherentio) {
1888                 _dma_cache_wback_inv    = (void *)cache_noop;
1889                 _dma_cache_wback        = (void *)cache_noop;
1890                 _dma_cache_inv          = (void *)cache_noop;
1891         } else {
1892                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1893                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1894                 _dma_cache_inv          = r4k_dma_cache_inv;
1895         }
1896 #endif
1897
1898         build_clear_page();
1899         build_copy_page();
1900
1901         /*
1902          * We want to run CMP kernels on core with and without coherent
1903          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1904          * or not to flush caches.
1905          */
1906         local_r4k___flush_cache_all(NULL);
1907
1908         coherency_setup();
1909         board_cache_error_setup = r4k_cache_error_setup;
1910
1911         /*
1912          * Per-CPU overrides
1913          */
1914         switch (current_cpu_type()) {
1915         case CPU_BMIPS4350:
1916         case CPU_BMIPS4380:
1917                 /* No IPI is needed because all CPUs share the same D$ */
1918                 flush_data_cache_page = r4k_blast_dcache_page;
1919                 break;
1920         case CPU_BMIPS5000:
1921                 /* We lose our superpowers if L2 is disabled */
1922                 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1923                         break;
1924
1925                 /* I$ fills from D$ just by emptying the write buffers */
1926                 flush_cache_page = (void *)b5k_instruction_hazard;
1927                 flush_cache_range = (void *)b5k_instruction_hazard;
1928                 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1929                 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1930                 flush_data_cache_page = (void *)b5k_instruction_hazard;
1931                 flush_icache_range = (void *)b5k_instruction_hazard;
1932                 local_flush_icache_range = (void *)b5k_instruction_hazard;
1933
1934
1935                 /* Optimization: an L2 flush implicitly flushes the L1 */
1936                 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1937                 break;
1938         case CPU_LOONGSON3:
1939                 /* Loongson-3 maintains cache coherency by hardware */
1940                 __flush_cache_all       = cache_noop;
1941                 __flush_cache_vmap      = cache_noop;
1942                 __flush_cache_vunmap    = cache_noop;
1943                 __flush_kernel_vmap_range = (void *)cache_noop;
1944                 flush_cache_mm          = (void *)cache_noop;
1945                 flush_cache_page        = (void *)cache_noop;
1946                 flush_cache_range       = (void *)cache_noop;
1947                 flush_cache_sigtramp    = (void *)cache_noop;
1948                 flush_icache_all        = (void *)cache_noop;
1949                 flush_data_cache_page   = (void *)cache_noop;
1950                 local_flush_data_cache_page     = (void *)cache_noop;
1951                 break;
1952         }
1953 }
1954
1955 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1956                                void *v)
1957 {
1958         switch (cmd) {
1959         case CPU_PM_ENTER_FAILED:
1960         case CPU_PM_EXIT:
1961                 coherency_setup();
1962                 break;
1963         }
1964
1965         return NOTIFY_OK;
1966 }
1967
1968 static struct notifier_block r4k_cache_pm_notifier_block = {
1969         .notifier_call = r4k_cache_pm_notifier,
1970 };
1971
1972 int __init r4k_cache_init_pm(void)
1973 {
1974         return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1975 }
1976 arch_initcall(r4k_cache_init_pm);