arch/mips/kernel/idle.c

   1 /*
   2  * MIPS idle loop and WAIT instruction support.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/export.h>
  15 #include <linux/init.h>
  16 #include <linux/irqflags.h>
  17 #include <linux/printk.h>
  18 #include <linux/sched.h>
  19 #include <asm/cpu.h>
  20 #include <asm/cpu-info.h>
  21 #include <asm/mipsregs.h>
  22
  23 /*
  24  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  25  * the implementation of the "wait" feature differs between CPU families. This
  26  * points to the function that implements CPU specific wait.
  27  * The wait instruction stops the pipeline and reduces the power consumption of
  28  * the CPU very much.
  29  */
  30 void (*cpu_wait)(void);
  31 EXPORT_SYMBOL(cpu_wait);
  32
  33 static void r3081_wait(void)
  34 {
  35         unsigned long cfg = read_c0_conf();
  36         write_c0_conf(cfg | R30XX_CONF_HALT);
  37 }
  38
  39 static void r39xx_wait(void)
  40 {
  41         local_irq_disable();
  42         if (!need_resched())
  43                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  44         local_irq_enable();
  45 }
  46
  47 extern void r4k_wait(void);
  48
  49 /*
  50  * This variant is preferable as it allows testing need_resched and going to
  51  * sleep depending on the outcome atomically.  Unfortunately the "It is
  52  * implementation-dependent whether the pipeline restarts when a non-enabled
  53  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  54  * using this version a gamble.
  55  */
  56 void r4k_wait_irqoff(void)
  57 {
  58         local_irq_disable();
  59         if (!need_resched())
  60                 __asm__("       .set    push            \n"
  61                         "       .set    mips3           \n"
  62                         "       wait                    \n"
  63                         "       .set    pop             \n");
  64         local_irq_enable();
  65         __asm__("       .globl __pastwait       \n"
  66                 "__pastwait:                    \n");
  67 }
  68
  69 /*
  70  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  71  * have any pending stores when the WAIT instruction is executed.
  72  */
  73 static void rm7k_wait_irqoff(void)
  74 {
  75         local_irq_disable();
  76         if (!need_resched())
  77                 __asm__(
  78                 "       .set    push                                    \n"
  79                 "       .set    mips3                                   \n"
  80                 "       .set    noat                                    \n"
  81                 "       mfc0    $1, $12                                 \n"
  82                 "       sync                                            \n"
  83                 "       mtc0    $1, $12         # stalls until W stage  \n"
  84                 "       wait                                            \n"
  85                 "       mtc0    $1, $12         # stalls until W stage  \n"
  86                 "       .set    pop                                     \n");
  87         local_irq_enable();
  88 }
  89
  90 /*
  91  * The Au1xxx wait is available only if using 32khz counter or
  92  * external timer source, but specifically not CP0 Counter.
  93  * alchemy/common/time.c may override cpu_wait!
  94  */
  95 static void au1k_wait(void)
  96 {
  97         __asm__("       .set    mips3                   \n"
  98                 "       cache   0x14, 0(%0)             \n"
  99                 "       cache   0x14, 32(%0)            \n"
 100                 "       sync                            \n"
 101                 "       nop                             \n"
 102                 "       wait                            \n"
 103                 "       nop                             \n"
 104                 "       nop                             \n"
 105                 "       nop                             \n"
 106                 "       nop                             \n"
 107                 "       .set    mips0                   \n"
 108                 : : "r" (au1k_wait));
 109 }
 110
 111 static int __initdata nowait;
 112
 113 static int __init wait_disable(char *s)
 114 {
 115         nowait = 1;
 116
 117         return 1;
 118 }
 119
 120 __setup("nowait", wait_disable);
 121
 122 void __init check_wait(void)
 123 {
 124         struct cpuinfo_mips *c = &current_cpu_data;
 125
 126         if (nowait) {
 127                 printk("Wait instruction disabled.\n");
 128                 return;
 129         }
 130
 131         switch (c->cputype) {
 132         case CPU_R3081:
 133         case CPU_R3081E:
 134                 cpu_wait = r3081_wait;
 135                 break;
 136         case CPU_TX3927:
 137                 cpu_wait = r39xx_wait;
 138                 break;
 139         case CPU_R4200:
 140 /*      case CPU_R4300: */
 141         case CPU_R4600:
 142         case CPU_R4640:
 143         case CPU_R4650:
 144         case CPU_R4700:
 145         case CPU_R5000:
 146         case CPU_R5500:
 147         case CPU_NEVADA:
 148         case CPU_4KC:
 149         case CPU_4KEC:
 150         case CPU_4KSC:
 151         case CPU_5KC:
 152         case CPU_25KF:
 153         case CPU_PR4450:
 154         case CPU_BMIPS3300:
 155         case CPU_BMIPS4350:
 156         case CPU_BMIPS4380:
 157         case CPU_BMIPS5000:
 158         case CPU_CAVIUM_OCTEON:
 159         case CPU_CAVIUM_OCTEON_PLUS:
 160         case CPU_CAVIUM_OCTEON2:
 161         case CPU_JZRISC:
 162         case CPU_LOONGSON1:
 163         case CPU_XLR:
 164         case CPU_XLP:
 165                 cpu_wait = r4k_wait;
 166                 break;
 167
 168         case CPU_RM7000:
 169                 cpu_wait = rm7k_wait_irqoff;
 170                 break;
 171
 172         case CPU_M14KC:
 173         case CPU_M14KEC:
 174         case CPU_24K:
 175         case CPU_34K:
 176         case CPU_1004K:
 177                 cpu_wait = r4k_wait;
 178                 if (read_c0_config7() & MIPS_CONF7_WII)
 179                         cpu_wait = r4k_wait_irqoff;
 180                 break;
 181
 182         case CPU_74K:
 183                 cpu_wait = r4k_wait;
 184                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 185                         cpu_wait = r4k_wait_irqoff;
 186                 break;
 187
 188         case CPU_TX49XX:
 189                 cpu_wait = r4k_wait_irqoff;
 190                 break;
 191         case CPU_ALCHEMY:
 192                 cpu_wait = au1k_wait;
 193                 break;
 194         case CPU_20KC:
 195                 /*
 196                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 197                  * WAIT on Rev2.0 and Rev3.0 has E16.
 198                  * Rev3.1 WAIT is nop, why bother
 199                  */
 200                 if ((c->processor_id & 0xff) <= 0x64)
 201                         break;
 202
 203                 /*
 204                  * Another rev is incremeting c0_count at a reduced clock
 205                  * rate while in WAIT mode.  So we basically have the choice
 206                  * between using the cp0 timer as clocksource or avoiding
 207                  * the WAIT instruction.  Until more details are known,
 208                  * disable the use of WAIT for 20Kc entirely.
 209                    cpu_wait = r4k_wait;
 210                  */
 211                 break;
 212         case CPU_RM9000:
 213                 if ((c->processor_id & 0x00ff) >= 0x40)
 214                         cpu_wait = r4k_wait;
 215                 break;
 216         default:
 217                 break;
 218         }
 219 }
 220
 221 void arch_cpu_idle(void)
 222 {
 223 #ifdef CONFIG_MIPS_MT_SMTC
 224         extern void smtc_idle_loop_hook(void);
 225
 226         smtc_idle_loop_hook();
 227 #endif
 228         if (cpu_wait)
 229                 (*cpu_wait)();
 230         else
 231                 local_irq_enable();
 232 }