2 * GT641xx clockevent routines.
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/clockchips.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock.h>
25 #include <asm/gt64120.h>
30 static DEFINE_SPINLOCK(gt641xx_timer_lock);
31 static unsigned int gt641xx_base_clock;
33 void gt641xx_set_base_clock(unsigned int clock)
35 gt641xx_base_clock = clock;
38 int gt641xx_timer0_state(void)
40 if (GT_READ(GT_TC0_OFS))
43 GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
44 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
49 static int gt641xx_timer0_set_next_event(unsigned long delta,
50 struct clock_event_device *evt)
55 spin_lock_irqsave(>641xx_timer_lock, flags);
57 ctrl = GT_READ(GT_TC_CONTROL_OFS);
58 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
59 ctrl |= GT_TC_CONTROL_ENTC0_MSK;
61 GT_WRITE(GT_TC0_OFS, delta);
62 GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
64 spin_unlock_irqrestore(>641xx_timer_lock, flags);
69 static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
70 struct clock_event_device *evt)
75 spin_lock_irqsave(>641xx_timer_lock, flags);
77 ctrl = GT_READ(GT_TC_CONTROL_OFS);
78 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
81 case CLOCK_EVT_MODE_PERIODIC:
82 ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
84 case CLOCK_EVT_MODE_ONESHOT:
85 ctrl |= GT_TC_CONTROL_ENTC0_MSK;
91 GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
93 spin_unlock_irqrestore(>641xx_timer_lock, flags);
96 static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
100 static struct clock_event_device gt641xx_timer0_clockevent = {
101 .name = "gt641xx-timer0",
102 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
103 .cpumask = CPU_MASK_CPU0,
104 .irq = GT641XX_TIMER0_IRQ,
105 .set_next_event = gt641xx_timer0_set_next_event,
106 .set_mode = gt641xx_timer0_set_mode,
107 .event_handler = gt641xx_timer0_event_handler,
110 static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
112 struct clock_event_device *cd = >641xx_timer0_clockevent;
114 cd->event_handler(cd);
119 static struct irqaction gt641xx_timer0_irqaction = {
120 .handler = gt641xx_timer0_interrupt,
121 .flags = IRQF_DISABLED | IRQF_PERCPU,
122 .name = "gt641xx_timer0",
125 static int __init gt641xx_timer0_clockevent_init(void)
127 struct clock_event_device *cd;
129 if (!gt641xx_base_clock)
132 GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
134 cd = >641xx_timer0_clockevent;
135 cd->rating = 200 + gt641xx_base_clock / 10000000;
136 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
137 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
138 clockevent_set_clock(cd, gt641xx_base_clock);
140 clockevents_register_device(>641xx_timer0_clockevent);
142 return setup_irq(GT641XX_TIMER0_IRQ, >641xx_timer0_irqaction);
144 arch_initcall(gt641xx_timer0_clockevent_init);