1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2008 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_NPEI_DEFS_H__
29 #define __CVMX_NPEI_DEFS_H__
31 #define CVMX_NPEI_BAR1_INDEXX(offset) \
32 (0x0000000000000000ull + (((offset) & 31) * 16))
33 #define CVMX_NPEI_BIST_STATUS \
34 (0x0000000000000580ull)
35 #define CVMX_NPEI_BIST_STATUS2 \
36 (0x0000000000000680ull)
37 #define CVMX_NPEI_CTL_PORT0 \
38 (0x0000000000000250ull)
39 #define CVMX_NPEI_CTL_PORT1 \
40 (0x0000000000000260ull)
41 #define CVMX_NPEI_CTL_STATUS \
42 (0x0000000000000570ull)
43 #define CVMX_NPEI_CTL_STATUS2 \
44 (0x0000000000003C00ull)
45 #define CVMX_NPEI_DATA_OUT_CNT \
46 (0x00000000000005F0ull)
47 #define CVMX_NPEI_DBG_DATA \
48 (0x0000000000000510ull)
49 #define CVMX_NPEI_DBG_SELECT \
50 (0x0000000000000500ull)
51 #define CVMX_NPEI_DMA0_INT_LEVEL \
52 (0x00000000000005C0ull)
53 #define CVMX_NPEI_DMA1_INT_LEVEL \
54 (0x00000000000005D0ull)
55 #define CVMX_NPEI_DMAX_COUNTS(offset) \
56 (0x0000000000000450ull + (((offset) & 7) * 16))
57 #define CVMX_NPEI_DMAX_DBELL(offset) \
58 (0x00000000000003B0ull + (((offset) & 7) * 16))
59 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
60 (0x0000000000000400ull + (((offset) & 7) * 16))
61 #define CVMX_NPEI_DMAX_NADDR(offset) \
62 (0x00000000000004A0ull + (((offset) & 7) * 16))
63 #define CVMX_NPEI_DMA_CNTS \
64 (0x00000000000005E0ull)
65 #define CVMX_NPEI_DMA_CONTROL \
66 (0x00000000000003A0ull)
67 #define CVMX_NPEI_INT_A_ENB \
68 (0x0000000000000560ull)
69 #define CVMX_NPEI_INT_A_ENB2 \
70 (0x0000000000003CE0ull)
71 #define CVMX_NPEI_INT_A_SUM \
72 (0x0000000000000550ull)
73 #define CVMX_NPEI_INT_ENB \
74 (0x0000000000000540ull)
75 #define CVMX_NPEI_INT_ENB2 \
76 (0x0000000000003CD0ull)
77 #define CVMX_NPEI_INT_INFO \
78 (0x0000000000000590ull)
79 #define CVMX_NPEI_INT_SUM \
80 (0x0000000000000530ull)
81 #define CVMX_NPEI_INT_SUM2 \
82 (0x0000000000003CC0ull)
83 #define CVMX_NPEI_LAST_WIN_RDATA0 \
84 (0x0000000000000600ull)
85 #define CVMX_NPEI_LAST_WIN_RDATA1 \
86 (0x0000000000000610ull)
87 #define CVMX_NPEI_MEM_ACCESS_CTL \
88 (0x00000000000004F0ull)
89 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
90 (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
91 #define CVMX_NPEI_MSI_ENB0 \
92 (0x0000000000003C50ull)
93 #define CVMX_NPEI_MSI_ENB1 \
94 (0x0000000000003C60ull)
95 #define CVMX_NPEI_MSI_ENB2 \
96 (0x0000000000003C70ull)
97 #define CVMX_NPEI_MSI_ENB3 \
98 (0x0000000000003C80ull)
99 #define CVMX_NPEI_MSI_RCV0 \
100 (0x0000000000003C10ull)
101 #define CVMX_NPEI_MSI_RCV1 \
102 (0x0000000000003C20ull)
103 #define CVMX_NPEI_MSI_RCV2 \
104 (0x0000000000003C30ull)
105 #define CVMX_NPEI_MSI_RCV3 \
106 (0x0000000000003C40ull)
107 #define CVMX_NPEI_MSI_RD_MAP \
108 (0x0000000000003CA0ull)
109 #define CVMX_NPEI_MSI_W1C_ENB0 \
110 (0x0000000000003CF0ull)
111 #define CVMX_NPEI_MSI_W1C_ENB1 \
112 (0x0000000000003D00ull)
113 #define CVMX_NPEI_MSI_W1C_ENB2 \
114 (0x0000000000003D10ull)
115 #define CVMX_NPEI_MSI_W1C_ENB3 \
116 (0x0000000000003D20ull)
117 #define CVMX_NPEI_MSI_W1S_ENB0 \
118 (0x0000000000003D30ull)
119 #define CVMX_NPEI_MSI_W1S_ENB1 \
120 (0x0000000000003D40ull)
121 #define CVMX_NPEI_MSI_W1S_ENB2 \
122 (0x0000000000003D50ull)
123 #define CVMX_NPEI_MSI_W1S_ENB3 \
124 (0x0000000000003D60ull)
125 #define CVMX_NPEI_MSI_WR_MAP \
126 (0x0000000000003C90ull)
127 #define CVMX_NPEI_PCIE_CREDIT_CNT \
128 (0x0000000000003D70ull)
129 #define CVMX_NPEI_PCIE_MSI_RCV \
130 (0x0000000000003CB0ull)
131 #define CVMX_NPEI_PCIE_MSI_RCV_B1 \
132 (0x0000000000000650ull)
133 #define CVMX_NPEI_PCIE_MSI_RCV_B2 \
134 (0x0000000000000660ull)
135 #define CVMX_NPEI_PCIE_MSI_RCV_B3 \
136 (0x0000000000000670ull)
137 #define CVMX_NPEI_PKTX_CNTS(offset) \
138 (0x0000000000002400ull + (((offset) & 31) * 16))
139 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
140 (0x0000000000002800ull + (((offset) & 31) * 16))
141 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
142 (0x0000000000002C00ull + (((offset) & 31) * 16))
143 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
144 (0x0000000000003000ull + (((offset) & 31) * 16))
145 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
146 (0x0000000000003400ull + (((offset) & 31) * 16))
147 #define CVMX_NPEI_PKTX_IN_BP(offset) \
148 (0x0000000000003800ull + (((offset) & 31) * 16))
149 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
150 (0x0000000000001400ull + (((offset) & 31) * 16))
151 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
152 (0x0000000000001800ull + (((offset) & 31) * 16))
153 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
154 (0x0000000000001C00ull + (((offset) & 31) * 16))
155 #define CVMX_NPEI_PKT_CNT_INT \
156 (0x0000000000001110ull)
157 #define CVMX_NPEI_PKT_CNT_INT_ENB \
158 (0x0000000000001130ull)
159 #define CVMX_NPEI_PKT_DATA_OUT_ES \
160 (0x00000000000010B0ull)
161 #define CVMX_NPEI_PKT_DATA_OUT_NS \
162 (0x00000000000010A0ull)
163 #define CVMX_NPEI_PKT_DATA_OUT_ROR \
164 (0x0000000000001090ull)
165 #define CVMX_NPEI_PKT_DPADDR \
166 (0x0000000000001080ull)
167 #define CVMX_NPEI_PKT_INPUT_CONTROL \
168 (0x0000000000001150ull)
169 #define CVMX_NPEI_PKT_INSTR_ENB \
170 (0x0000000000001000ull)
171 #define CVMX_NPEI_PKT_INSTR_RD_SIZE \
172 (0x0000000000001190ull)
173 #define CVMX_NPEI_PKT_INSTR_SIZE \
174 (0x0000000000001020ull)
175 #define CVMX_NPEI_PKT_INT_LEVELS \
176 (0x0000000000001100ull)
177 #define CVMX_NPEI_PKT_IN_BP \
178 (0x00000000000006B0ull)
179 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
180 (0x0000000000002000ull + (((offset) & 31) * 16))
181 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
182 (0x00000000000006A0ull)
183 #define CVMX_NPEI_PKT_IN_PCIE_PORT \
184 (0x00000000000011A0ull)
185 #define CVMX_NPEI_PKT_IPTR \
186 (0x0000000000001070ull)
187 #define CVMX_NPEI_PKT_OUTPUT_WMARK \
188 (0x0000000000001160ull)
189 #define CVMX_NPEI_PKT_OUT_BMODE \
190 (0x00000000000010D0ull)
191 #define CVMX_NPEI_PKT_OUT_ENB \
192 (0x0000000000001010ull)
193 #define CVMX_NPEI_PKT_PCIE_PORT \
194 (0x00000000000010E0ull)
195 #define CVMX_NPEI_PKT_PORT_IN_RST \
196 (0x0000000000000690ull)
197 #define CVMX_NPEI_PKT_SLIST_ES \
198 (0x0000000000001050ull)
199 #define CVMX_NPEI_PKT_SLIST_ID_SIZE \
200 (0x0000000000001180ull)
201 #define CVMX_NPEI_PKT_SLIST_NS \
202 (0x0000000000001040ull)
203 #define CVMX_NPEI_PKT_SLIST_ROR \
204 (0x0000000000001030ull)
205 #define CVMX_NPEI_PKT_TIME_INT \
206 (0x0000000000001120ull)
207 #define CVMX_NPEI_PKT_TIME_INT_ENB \
208 (0x0000000000001140ull)
209 #define CVMX_NPEI_RSL_INT_BLOCKS \
210 (0x0000000000000520ull)
211 #define CVMX_NPEI_SCRATCH_1 \
212 (0x0000000000000270ull)
213 #define CVMX_NPEI_STATE1 \
214 (0x0000000000000620ull)
215 #define CVMX_NPEI_STATE2 \
216 (0x0000000000000630ull)
217 #define CVMX_NPEI_STATE3 \
218 (0x0000000000000640ull)
219 #define CVMX_NPEI_WINDOW_CTL \
220 (0x0000000000000380ull)
221 #define CVMX_NPEI_WIN_RD_ADDR \
222 (0x0000000000000210ull)
223 #define CVMX_NPEI_WIN_RD_DATA \
224 (0x0000000000000240ull)
225 #define CVMX_NPEI_WIN_WR_ADDR \
226 (0x0000000000000200ull)
227 #define CVMX_NPEI_WIN_WR_DATA \
228 (0x0000000000000220ull)
229 #define CVMX_NPEI_WIN_WR_MASK \
230 (0x0000000000000230ull)
232 union cvmx_npei_bar1_indexx {
234 struct cvmx_npei_bar1_indexx_s {
235 uint32_t reserved_18_31:14;
236 uint32_t addr_idx:14;
241 struct cvmx_npei_bar1_indexx_s cn52xx;
242 struct cvmx_npei_bar1_indexx_s cn52xxp1;
243 struct cvmx_npei_bar1_indexx_s cn56xx;
244 struct cvmx_npei_bar1_indexx_s cn56xxp1;
247 union cvmx_npei_bist_status {
249 struct cvmx_npei_bist_status_s {
253 uint64_t reserved_60_60:1;
261 uint64_t reserved_50_52:3;
264 uint64_t reserved_36_47:12;
269 uint64_t reserved_31_31:1;
298 uint64_t reserved_2_2:1;
302 struct cvmx_npei_bist_status_cn52xx {
306 uint64_t reserved_60_60:1;
317 uint64_t reserved_48_49:2;
326 uint64_t reserved_36_39:4;
364 struct cvmx_npei_bist_status_cn52xxp1 {
365 uint64_t reserved_46_63:18;
413 struct cvmx_npei_bist_status_cn56xx {
415 uint64_t reserved_60_62:3;
426 uint64_t reserved_48_49:2;
435 uint64_t reserved_36_39:4;
473 struct cvmx_npei_bist_status_cn56xxp1 {
474 uint64_t reserved_58_63:6;
536 union cvmx_npei_bist_status2 {
538 struct cvmx_npei_bist_status2_s {
539 uint64_t reserved_5_63:59;
546 struct cvmx_npei_bist_status2_s cn52xx;
547 struct cvmx_npei_bist_status2_s cn56xx;
550 union cvmx_npei_ctl_port0 {
552 struct cvmx_npei_ctl_port0_s {
553 uint64_t reserved_21_63:43;
554 uint64_t waitl_com:1;
564 uint64_t reserved_6_6:1;
571 struct cvmx_npei_ctl_port0_s cn52xx;
572 struct cvmx_npei_ctl_port0_s cn52xxp1;
573 struct cvmx_npei_ctl_port0_s cn56xx;
574 struct cvmx_npei_ctl_port0_s cn56xxp1;
577 union cvmx_npei_ctl_port1 {
579 struct cvmx_npei_ctl_port1_s {
580 uint64_t reserved_21_63:43;
581 uint64_t waitl_com:1;
591 uint64_t reserved_6_6:1;
598 struct cvmx_npei_ctl_port1_s cn52xx;
599 struct cvmx_npei_ctl_port1_s cn52xxp1;
600 struct cvmx_npei_ctl_port1_s cn56xx;
601 struct cvmx_npei_ctl_port1_s cn56xxp1;
604 union cvmx_npei_ctl_status {
606 struct cvmx_npei_ctl_status_s {
607 uint64_t reserved_44_63:20;
610 uint64_t cfg_rtry:16;
615 uint64_t host_mode:1;
618 struct cvmx_npei_ctl_status_s cn52xx;
619 struct cvmx_npei_ctl_status_cn52xxp1 {
620 uint64_t reserved_44_63:20;
623 uint64_t cfg_rtry:16;
624 uint64_t reserved_15_15:1;
627 uint64_t reserved_9_12:4;
628 uint64_t host_mode:1;
631 struct cvmx_npei_ctl_status_s cn56xx;
632 struct cvmx_npei_ctl_status_cn56xxp1 {
633 uint64_t reserved_16_63:48;
638 uint64_t host_mode:1;
643 union cvmx_npei_ctl_status2 {
645 struct cvmx_npei_ctl_status2_s {
646 uint64_t reserved_16_63:48;
658 struct cvmx_npei_ctl_status2_s cn52xx;
659 struct cvmx_npei_ctl_status2_s cn52xxp1;
660 struct cvmx_npei_ctl_status2_s cn56xx;
661 struct cvmx_npei_ctl_status2_s cn56xxp1;
664 union cvmx_npei_data_out_cnt {
666 struct cvmx_npei_data_out_cnt_s {
667 uint64_t reserved_44_63:20;
673 struct cvmx_npei_data_out_cnt_s cn52xx;
674 struct cvmx_npei_data_out_cnt_s cn52xxp1;
675 struct cvmx_npei_data_out_cnt_s cn56xx;
676 struct cvmx_npei_data_out_cnt_s cn56xxp1;
679 union cvmx_npei_dbg_data {
681 struct cvmx_npei_dbg_data_s {
682 uint64_t reserved_28_63:36;
683 uint64_t qlm0_rev_lanes:1;
684 uint64_t reserved_25_26:2;
690 struct cvmx_npei_dbg_data_cn52xx {
691 uint64_t reserved_29_63:35;
692 uint64_t qlm0_link_width:1;
693 uint64_t qlm0_rev_lanes:1;
694 uint64_t qlm1_mode:2;
700 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
701 struct cvmx_npei_dbg_data_cn56xx {
702 uint64_t reserved_29_63:35;
703 uint64_t qlm2_rev_lanes:1;
704 uint64_t qlm0_rev_lanes:1;
711 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
714 union cvmx_npei_dbg_select {
716 struct cvmx_npei_dbg_select_s {
717 uint64_t reserved_16_63:48;
720 struct cvmx_npei_dbg_select_s cn52xx;
721 struct cvmx_npei_dbg_select_s cn52xxp1;
722 struct cvmx_npei_dbg_select_s cn56xx;
723 struct cvmx_npei_dbg_select_s cn56xxp1;
726 union cvmx_npei_dmax_counts {
728 struct cvmx_npei_dmax_counts_s {
729 uint64_t reserved_39_63:25;
733 struct cvmx_npei_dmax_counts_s cn52xx;
734 struct cvmx_npei_dmax_counts_s cn52xxp1;
735 struct cvmx_npei_dmax_counts_s cn56xx;
736 struct cvmx_npei_dmax_counts_s cn56xxp1;
739 union cvmx_npei_dmax_dbell {
741 struct cvmx_npei_dmax_dbell_s {
742 uint32_t reserved_16_31:16;
745 struct cvmx_npei_dmax_dbell_s cn52xx;
746 struct cvmx_npei_dmax_dbell_s cn52xxp1;
747 struct cvmx_npei_dmax_dbell_s cn56xx;
748 struct cvmx_npei_dmax_dbell_s cn56xxp1;
751 union cvmx_npei_dmax_ibuff_saddr {
753 struct cvmx_npei_dmax_ibuff_saddr_s {
754 uint64_t reserved_37_63:27;
757 uint64_t reserved_0_6:7;
759 struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
760 uint64_t reserved_36_63:28;
762 uint64_t reserved_0_6:7;
764 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
765 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
766 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
769 union cvmx_npei_dmax_naddr {
771 struct cvmx_npei_dmax_naddr_s {
772 uint64_t reserved_36_63:28;
775 struct cvmx_npei_dmax_naddr_s cn52xx;
776 struct cvmx_npei_dmax_naddr_s cn52xxp1;
777 struct cvmx_npei_dmax_naddr_s cn56xx;
778 struct cvmx_npei_dmax_naddr_s cn56xxp1;
781 union cvmx_npei_dma0_int_level {
783 struct cvmx_npei_dma0_int_level_s {
787 struct cvmx_npei_dma0_int_level_s cn52xx;
788 struct cvmx_npei_dma0_int_level_s cn52xxp1;
789 struct cvmx_npei_dma0_int_level_s cn56xx;
790 struct cvmx_npei_dma0_int_level_s cn56xxp1;
793 union cvmx_npei_dma1_int_level {
795 struct cvmx_npei_dma1_int_level_s {
799 struct cvmx_npei_dma1_int_level_s cn52xx;
800 struct cvmx_npei_dma1_int_level_s cn52xxp1;
801 struct cvmx_npei_dma1_int_level_s cn56xx;
802 struct cvmx_npei_dma1_int_level_s cn56xxp1;
805 union cvmx_npei_dma_cnts {
807 struct cvmx_npei_dma_cnts_s {
811 struct cvmx_npei_dma_cnts_s cn52xx;
812 struct cvmx_npei_dma_cnts_s cn52xxp1;
813 struct cvmx_npei_dma_cnts_s cn56xx;
814 struct cvmx_npei_dma_cnts_s cn56xxp1;
817 union cvmx_npei_dma_control {
819 struct cvmx_npei_dma_control_s {
820 uint64_t reserved_39_63:25;
837 struct cvmx_npei_dma_control_s cn52xx;
838 struct cvmx_npei_dma_control_cn52xxp1 {
839 uint64_t reserved_38_63:26;
855 struct cvmx_npei_dma_control_s cn56xx;
856 struct cvmx_npei_dma_control_s cn56xxp1;
859 union cvmx_npei_int_a_enb {
861 struct cvmx_npei_int_a_enb_s {
862 uint64_t reserved_10_63:54;
874 struct cvmx_npei_int_a_enb_cn52xx {
875 uint64_t reserved_8_63:56;
885 struct cvmx_npei_int_a_enb_cn52xxp1 {
886 uint64_t reserved_2_63:62;
890 struct cvmx_npei_int_a_enb_s cn56xx;
893 union cvmx_npei_int_a_enb2 {
895 struct cvmx_npei_int_a_enb2_s {
896 uint64_t reserved_10_63:54;
908 struct cvmx_npei_int_a_enb2_cn52xx {
909 uint64_t reserved_8_63:56;
916 uint64_t reserved_0_1:2;
918 struct cvmx_npei_int_a_enb2_cn52xxp1 {
919 uint64_t reserved_2_63:62;
923 struct cvmx_npei_int_a_enb2_s cn56xx;
926 union cvmx_npei_int_a_sum {
928 struct cvmx_npei_int_a_sum_s {
929 uint64_t reserved_10_63:54;
941 struct cvmx_npei_int_a_sum_cn52xx {
942 uint64_t reserved_8_63:56;
952 struct cvmx_npei_int_a_sum_cn52xxp1 {
953 uint64_t reserved_2_63:62;
957 struct cvmx_npei_int_a_sum_s cn56xx;
960 union cvmx_npei_int_enb {
962 struct cvmx_npei_int_enb_s {
964 uint64_t reserved_62_62:1;
1001 uint64_t c0_hpint:1;
1028 struct cvmx_npei_int_enb_s cn52xx;
1029 struct cvmx_npei_int_enb_cn52xxp1 {
1030 uint64_t mio_inta:1;
1031 uint64_t reserved_62_62:1;
1037 uint64_t c1_up_wf:1;
1038 uint64_t c0_up_wf:1;
1039 uint64_t c1_un_wf:1;
1040 uint64_t c0_un_wf:1;
1041 uint64_t c1_un_bx:1;
1042 uint64_t c1_un_wi:1;
1043 uint64_t c1_un_b2:1;
1044 uint64_t c1_un_b1:1;
1045 uint64_t c1_un_b0:1;
1046 uint64_t c1_up_bx:1;
1047 uint64_t c1_up_wi:1;
1048 uint64_t c1_up_b2:1;
1049 uint64_t c1_up_b1:1;
1050 uint64_t c1_up_b0:1;
1051 uint64_t c0_un_bx:1;
1052 uint64_t c0_un_wi:1;
1053 uint64_t c0_un_b2:1;
1054 uint64_t c0_un_b1:1;
1055 uint64_t c0_un_b0:1;
1056 uint64_t c0_up_bx:1;
1057 uint64_t c0_up_wi:1;
1058 uint64_t c0_up_b2:1;
1059 uint64_t c0_up_b1:1;
1060 uint64_t c0_up_b0:1;
1061 uint64_t c1_hpint:1;
1068 uint64_t c0_hpint:1;
1085 uint64_t reserved_8_8:1;
1095 struct cvmx_npei_int_enb_s cn56xx;
1096 struct cvmx_npei_int_enb_cn56xxp1 {
1097 uint64_t mio_inta:1;
1098 uint64_t reserved_61_62:2;
1103 uint64_t c1_up_wf:1;
1104 uint64_t c0_up_wf:1;
1105 uint64_t c1_un_wf:1;
1106 uint64_t c0_un_wf:1;
1107 uint64_t c1_un_bx:1;
1108 uint64_t c1_un_wi:1;
1109 uint64_t c1_un_b2:1;
1110 uint64_t c1_un_b1:1;
1111 uint64_t c1_un_b0:1;
1112 uint64_t c1_up_bx:1;
1113 uint64_t c1_up_wi:1;
1114 uint64_t c1_up_b2:1;
1115 uint64_t c1_up_b1:1;
1116 uint64_t c1_up_b0:1;
1117 uint64_t c0_un_bx:1;
1118 uint64_t c0_un_wi:1;
1119 uint64_t c0_un_b2:1;
1120 uint64_t c0_un_b1:1;
1121 uint64_t c0_un_b0:1;
1122 uint64_t c0_up_bx:1;
1123 uint64_t c0_up_wi:1;
1124 uint64_t c0_up_b2:1;
1125 uint64_t c0_up_b1:1;
1126 uint64_t c0_up_b0:1;
1127 uint64_t c1_hpint:1;
1130 uint64_t reserved_29_29:1;
1132 uint64_t reserved_27_27:1;
1134 uint64_t c0_hpint:1;
1137 uint64_t reserved_22_22:1;
1139 uint64_t reserved_20_20:1;
1163 union cvmx_npei_int_enb2 {
1165 struct cvmx_npei_int_enb2_s {
1166 uint64_t reserved_62_63:2;
1172 uint64_t c1_up_wf:1;
1173 uint64_t c0_up_wf:1;
1174 uint64_t c1_un_wf:1;
1175 uint64_t c0_un_wf:1;
1176 uint64_t c1_un_bx:1;
1177 uint64_t c1_un_wi:1;
1178 uint64_t c1_un_b2:1;
1179 uint64_t c1_un_b1:1;
1180 uint64_t c1_un_b0:1;
1181 uint64_t c1_up_bx:1;
1182 uint64_t c1_up_wi:1;
1183 uint64_t c1_up_b2:1;
1184 uint64_t c1_up_b1:1;
1185 uint64_t c1_up_b0:1;
1186 uint64_t c0_un_bx:1;
1187 uint64_t c0_un_wi:1;
1188 uint64_t c0_un_b2:1;
1189 uint64_t c0_un_b1:1;
1190 uint64_t c0_un_b0:1;
1191 uint64_t c0_up_bx:1;
1192 uint64_t c0_up_wi:1;
1193 uint64_t c0_up_b2:1;
1194 uint64_t c0_up_b1:1;
1195 uint64_t c0_up_b0:1;
1196 uint64_t c1_hpint:1;
1203 uint64_t c0_hpint:1;
1230 struct cvmx_npei_int_enb2_s cn52xx;
1231 struct cvmx_npei_int_enb2_cn52xxp1 {
1232 uint64_t reserved_62_63:2;
1238 uint64_t c1_up_wf:1;
1239 uint64_t c0_up_wf:1;
1240 uint64_t c1_un_wf:1;
1241 uint64_t c0_un_wf:1;
1242 uint64_t c1_un_bx:1;
1243 uint64_t c1_un_wi:1;
1244 uint64_t c1_un_b2:1;
1245 uint64_t c1_un_b1:1;
1246 uint64_t c1_un_b0:1;
1247 uint64_t c1_up_bx:1;
1248 uint64_t c1_up_wi:1;
1249 uint64_t c1_up_b2:1;
1250 uint64_t c1_up_b1:1;
1251 uint64_t c1_up_b0:1;
1252 uint64_t c0_un_bx:1;
1253 uint64_t c0_un_wi:1;
1254 uint64_t c0_un_b2:1;
1255 uint64_t c0_un_b1:1;
1256 uint64_t c0_un_b0:1;
1257 uint64_t c0_up_bx:1;
1258 uint64_t c0_up_wi:1;
1259 uint64_t c0_up_b2:1;
1260 uint64_t c0_up_b1:1;
1261 uint64_t c0_up_b0:1;
1262 uint64_t c1_hpint:1;
1269 uint64_t c0_hpint:1;
1286 uint64_t reserved_8_8:1;
1296 struct cvmx_npei_int_enb2_s cn56xx;
1297 struct cvmx_npei_int_enb2_cn56xxp1 {
1298 uint64_t reserved_61_63:3;
1303 uint64_t c1_up_wf:1;
1304 uint64_t c0_up_wf:1;
1305 uint64_t c1_un_wf:1;
1306 uint64_t c0_un_wf:1;
1307 uint64_t c1_un_bx:1;
1308 uint64_t c1_un_wi:1;
1309 uint64_t c1_un_b2:1;
1310 uint64_t c1_un_b1:1;
1311 uint64_t c1_un_b0:1;
1312 uint64_t c1_up_bx:1;
1313 uint64_t c1_up_wi:1;
1314 uint64_t c1_up_b2:1;
1315 uint64_t c1_up_b1:1;
1316 uint64_t c1_up_b0:1;
1317 uint64_t c0_un_bx:1;
1318 uint64_t c0_un_wi:1;
1319 uint64_t c0_un_b2:1;
1320 uint64_t c0_un_b1:1;
1321 uint64_t c0_un_b0:1;
1322 uint64_t c0_up_bx:1;
1323 uint64_t c0_up_wi:1;
1324 uint64_t c0_up_b2:1;
1325 uint64_t c0_up_b1:1;
1326 uint64_t c0_up_b0:1;
1327 uint64_t c1_hpint:1;
1330 uint64_t reserved_29_29:1;
1332 uint64_t reserved_27_27:1;
1334 uint64_t c0_hpint:1;
1337 uint64_t reserved_22_22:1;
1339 uint64_t reserved_20_20:1;
1363 union cvmx_npei_int_info {
1365 struct cvmx_npei_int_info_s {
1366 uint64_t reserved_12_63:52;
1370 struct cvmx_npei_int_info_s cn52xx;
1371 struct cvmx_npei_int_info_s cn56xx;
1372 struct cvmx_npei_int_info_s cn56xxp1;
1375 union cvmx_npei_int_sum {
1377 struct cvmx_npei_int_sum_s {
1378 uint64_t mio_inta:1;
1379 uint64_t reserved_62_62:1;
1385 uint64_t c1_up_wf:1;
1386 uint64_t c0_up_wf:1;
1387 uint64_t c1_un_wf:1;
1388 uint64_t c0_un_wf:1;
1389 uint64_t c1_un_bx:1;
1390 uint64_t c1_un_wi:1;
1391 uint64_t c1_un_b2:1;
1392 uint64_t c1_un_b1:1;
1393 uint64_t c1_un_b0:1;
1394 uint64_t c1_up_bx:1;
1395 uint64_t c1_up_wi:1;
1396 uint64_t c1_up_b2:1;
1397 uint64_t c1_up_b1:1;
1398 uint64_t c1_up_b0:1;
1399 uint64_t c0_un_bx:1;
1400 uint64_t c0_un_wi:1;
1401 uint64_t c0_un_b2:1;
1402 uint64_t c0_un_b1:1;
1403 uint64_t c0_un_b0:1;
1404 uint64_t c0_up_bx:1;
1405 uint64_t c0_up_wi:1;
1406 uint64_t c0_up_b2:1;
1407 uint64_t c0_up_b1:1;
1408 uint64_t c0_up_b0:1;
1409 uint64_t c1_hpint:1;
1416 uint64_t c0_hpint:1;
1443 struct cvmx_npei_int_sum_s cn52xx;
1444 struct cvmx_npei_int_sum_cn52xxp1 {
1445 uint64_t mio_inta:1;
1446 uint64_t reserved_62_62:1;
1452 uint64_t c1_up_wf:1;
1453 uint64_t c0_up_wf:1;
1454 uint64_t c1_un_wf:1;
1455 uint64_t c0_un_wf:1;
1456 uint64_t c1_un_bx:1;
1457 uint64_t c1_un_wi:1;
1458 uint64_t c1_un_b2:1;
1459 uint64_t c1_un_b1:1;
1460 uint64_t c1_un_b0:1;
1461 uint64_t c1_up_bx:1;
1462 uint64_t c1_up_wi:1;
1463 uint64_t c1_up_b2:1;
1464 uint64_t c1_up_b1:1;
1465 uint64_t c1_up_b0:1;
1466 uint64_t c0_un_bx:1;
1467 uint64_t c0_un_wi:1;
1468 uint64_t c0_un_b2:1;
1469 uint64_t c0_un_b1:1;
1470 uint64_t c0_un_b0:1;
1471 uint64_t c0_up_bx:1;
1472 uint64_t c0_up_wi:1;
1473 uint64_t c0_up_b2:1;
1474 uint64_t c0_up_b1:1;
1475 uint64_t c0_up_b0:1;
1476 uint64_t c1_hpint:1;
1483 uint64_t c0_hpint:1;
1490 uint64_t reserved_15_18:4;
1497 uint64_t reserved_8_8:1;
1507 struct cvmx_npei_int_sum_s cn56xx;
1508 struct cvmx_npei_int_sum_cn56xxp1 {
1509 uint64_t mio_inta:1;
1510 uint64_t reserved_61_62:2;
1515 uint64_t c1_up_wf:1;
1516 uint64_t c0_up_wf:1;
1517 uint64_t c1_un_wf:1;
1518 uint64_t c0_un_wf:1;
1519 uint64_t c1_un_bx:1;
1520 uint64_t c1_un_wi:1;
1521 uint64_t c1_un_b2:1;
1522 uint64_t c1_un_b1:1;
1523 uint64_t c1_un_b0:1;
1524 uint64_t c1_up_bx:1;
1525 uint64_t c1_up_wi:1;
1526 uint64_t c1_up_b2:1;
1527 uint64_t c1_up_b1:1;
1528 uint64_t c1_up_b0:1;
1529 uint64_t c0_un_bx:1;
1530 uint64_t c0_un_wi:1;
1531 uint64_t c0_un_b2:1;
1532 uint64_t c0_un_b1:1;
1533 uint64_t c0_un_b0:1;
1534 uint64_t c0_up_bx:1;
1535 uint64_t c0_up_wi:1;
1536 uint64_t c0_up_b2:1;
1537 uint64_t c0_up_b1:1;
1538 uint64_t c0_up_b0:1;
1539 uint64_t c1_hpint:1;
1542 uint64_t reserved_29_29:1;
1544 uint64_t reserved_27_27:1;
1546 uint64_t c0_hpint:1;
1549 uint64_t reserved_22_22:1;
1551 uint64_t reserved_20_20:1;
1575 union cvmx_npei_int_sum2 {
1577 struct cvmx_npei_int_sum2_s {
1578 uint64_t mio_inta:1;
1579 uint64_t reserved_62_62:1;
1585 uint64_t c1_up_wf:1;
1586 uint64_t c0_up_wf:1;
1587 uint64_t c1_un_wf:1;
1588 uint64_t c0_un_wf:1;
1589 uint64_t c1_un_bx:1;
1590 uint64_t c1_un_wi:1;
1591 uint64_t c1_un_b2:1;
1592 uint64_t c1_un_b1:1;
1593 uint64_t c1_un_b0:1;
1594 uint64_t c1_up_bx:1;
1595 uint64_t c1_up_wi:1;
1596 uint64_t c1_up_b2:1;
1597 uint64_t c1_up_b1:1;
1598 uint64_t c1_up_b0:1;
1599 uint64_t c0_un_bx:1;
1600 uint64_t c0_un_wi:1;
1601 uint64_t c0_un_b2:1;
1602 uint64_t c0_un_b1:1;
1603 uint64_t c0_un_b0:1;
1604 uint64_t c0_up_bx:1;
1605 uint64_t c0_up_wi:1;
1606 uint64_t c0_up_b2:1;
1607 uint64_t c0_up_b1:1;
1608 uint64_t c0_up_b0:1;
1609 uint64_t c1_hpint:1;
1616 uint64_t c0_hpint:1;
1623 uint64_t reserved_15_18:4;
1630 uint64_t reserved_8_8:1;
1640 struct cvmx_npei_int_sum2_s cn52xx;
1641 struct cvmx_npei_int_sum2_s cn52xxp1;
1642 struct cvmx_npei_int_sum2_s cn56xx;
1645 union cvmx_npei_last_win_rdata0 {
1647 struct cvmx_npei_last_win_rdata0_s {
1650 struct cvmx_npei_last_win_rdata0_s cn52xx;
1651 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
1652 struct cvmx_npei_last_win_rdata0_s cn56xx;
1653 struct cvmx_npei_last_win_rdata0_s cn56xxp1;
1656 union cvmx_npei_last_win_rdata1 {
1658 struct cvmx_npei_last_win_rdata1_s {
1661 struct cvmx_npei_last_win_rdata1_s cn52xx;
1662 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
1663 struct cvmx_npei_last_win_rdata1_s cn56xx;
1664 struct cvmx_npei_last_win_rdata1_s cn56xxp1;
1667 union cvmx_npei_mem_access_ctl {
1669 struct cvmx_npei_mem_access_ctl_s {
1670 uint64_t reserved_14_63:50;
1671 uint64_t max_word:4;
1674 struct cvmx_npei_mem_access_ctl_s cn52xx;
1675 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
1676 struct cvmx_npei_mem_access_ctl_s cn56xx;
1677 struct cvmx_npei_mem_access_ctl_s cn56xxp1;
1680 union cvmx_npei_mem_access_subidx {
1682 struct cvmx_npei_mem_access_subidx_s {
1683 uint64_t reserved_42_63:22;
1695 struct cvmx_npei_mem_access_subidx_s cn52xx;
1696 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
1697 struct cvmx_npei_mem_access_subidx_s cn56xx;
1698 struct cvmx_npei_mem_access_subidx_s cn56xxp1;
1701 union cvmx_npei_msi_enb0 {
1703 struct cvmx_npei_msi_enb0_s {
1706 struct cvmx_npei_msi_enb0_s cn52xx;
1707 struct cvmx_npei_msi_enb0_s cn52xxp1;
1708 struct cvmx_npei_msi_enb0_s cn56xx;
1709 struct cvmx_npei_msi_enb0_s cn56xxp1;
1712 union cvmx_npei_msi_enb1 {
1714 struct cvmx_npei_msi_enb1_s {
1717 struct cvmx_npei_msi_enb1_s cn52xx;
1718 struct cvmx_npei_msi_enb1_s cn52xxp1;
1719 struct cvmx_npei_msi_enb1_s cn56xx;
1720 struct cvmx_npei_msi_enb1_s cn56xxp1;
1723 union cvmx_npei_msi_enb2 {
1725 struct cvmx_npei_msi_enb2_s {
1728 struct cvmx_npei_msi_enb2_s cn52xx;
1729 struct cvmx_npei_msi_enb2_s cn52xxp1;
1730 struct cvmx_npei_msi_enb2_s cn56xx;
1731 struct cvmx_npei_msi_enb2_s cn56xxp1;
1734 union cvmx_npei_msi_enb3 {
1736 struct cvmx_npei_msi_enb3_s {
1739 struct cvmx_npei_msi_enb3_s cn52xx;
1740 struct cvmx_npei_msi_enb3_s cn52xxp1;
1741 struct cvmx_npei_msi_enb3_s cn56xx;
1742 struct cvmx_npei_msi_enb3_s cn56xxp1;
1745 union cvmx_npei_msi_rcv0 {
1747 struct cvmx_npei_msi_rcv0_s {
1750 struct cvmx_npei_msi_rcv0_s cn52xx;
1751 struct cvmx_npei_msi_rcv0_s cn52xxp1;
1752 struct cvmx_npei_msi_rcv0_s cn56xx;
1753 struct cvmx_npei_msi_rcv0_s cn56xxp1;
1756 union cvmx_npei_msi_rcv1 {
1758 struct cvmx_npei_msi_rcv1_s {
1761 struct cvmx_npei_msi_rcv1_s cn52xx;
1762 struct cvmx_npei_msi_rcv1_s cn52xxp1;
1763 struct cvmx_npei_msi_rcv1_s cn56xx;
1764 struct cvmx_npei_msi_rcv1_s cn56xxp1;
1767 union cvmx_npei_msi_rcv2 {
1769 struct cvmx_npei_msi_rcv2_s {
1772 struct cvmx_npei_msi_rcv2_s cn52xx;
1773 struct cvmx_npei_msi_rcv2_s cn52xxp1;
1774 struct cvmx_npei_msi_rcv2_s cn56xx;
1775 struct cvmx_npei_msi_rcv2_s cn56xxp1;
1778 union cvmx_npei_msi_rcv3 {
1780 struct cvmx_npei_msi_rcv3_s {
1783 struct cvmx_npei_msi_rcv3_s cn52xx;
1784 struct cvmx_npei_msi_rcv3_s cn52xxp1;
1785 struct cvmx_npei_msi_rcv3_s cn56xx;
1786 struct cvmx_npei_msi_rcv3_s cn56xxp1;
1789 union cvmx_npei_msi_rd_map {
1791 struct cvmx_npei_msi_rd_map_s {
1792 uint64_t reserved_16_63:48;
1796 struct cvmx_npei_msi_rd_map_s cn52xx;
1797 struct cvmx_npei_msi_rd_map_s cn52xxp1;
1798 struct cvmx_npei_msi_rd_map_s cn56xx;
1799 struct cvmx_npei_msi_rd_map_s cn56xxp1;
1802 union cvmx_npei_msi_w1c_enb0 {
1804 struct cvmx_npei_msi_w1c_enb0_s {
1807 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1808 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
1811 union cvmx_npei_msi_w1c_enb1 {
1813 struct cvmx_npei_msi_w1c_enb1_s {
1816 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1817 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
1820 union cvmx_npei_msi_w1c_enb2 {
1822 struct cvmx_npei_msi_w1c_enb2_s {
1825 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1826 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
1829 union cvmx_npei_msi_w1c_enb3 {
1831 struct cvmx_npei_msi_w1c_enb3_s {
1834 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1835 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
1838 union cvmx_npei_msi_w1s_enb0 {
1840 struct cvmx_npei_msi_w1s_enb0_s {
1843 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1844 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
1847 union cvmx_npei_msi_w1s_enb1 {
1849 struct cvmx_npei_msi_w1s_enb1_s {
1852 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1853 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
1856 union cvmx_npei_msi_w1s_enb2 {
1858 struct cvmx_npei_msi_w1s_enb2_s {
1861 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1862 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
1865 union cvmx_npei_msi_w1s_enb3 {
1867 struct cvmx_npei_msi_w1s_enb3_s {
1870 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1871 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
1874 union cvmx_npei_msi_wr_map {
1876 struct cvmx_npei_msi_wr_map_s {
1877 uint64_t reserved_16_63:48;
1881 struct cvmx_npei_msi_wr_map_s cn52xx;
1882 struct cvmx_npei_msi_wr_map_s cn52xxp1;
1883 struct cvmx_npei_msi_wr_map_s cn56xx;
1884 struct cvmx_npei_msi_wr_map_s cn56xxp1;
1887 union cvmx_npei_pcie_credit_cnt {
1889 struct cvmx_npei_pcie_credit_cnt_s {
1890 uint64_t reserved_48_63:16;
1898 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1899 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
1902 union cvmx_npei_pcie_msi_rcv {
1904 struct cvmx_npei_pcie_msi_rcv_s {
1905 uint64_t reserved_8_63:56;
1908 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1909 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
1910 struct cvmx_npei_pcie_msi_rcv_s cn56xx;
1911 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
1914 union cvmx_npei_pcie_msi_rcv_b1 {
1916 struct cvmx_npei_pcie_msi_rcv_b1_s {
1917 uint64_t reserved_16_63:48;
1919 uint64_t reserved_0_7:8;
1921 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1922 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
1923 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
1924 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
1927 union cvmx_npei_pcie_msi_rcv_b2 {
1929 struct cvmx_npei_pcie_msi_rcv_b2_s {
1930 uint64_t reserved_24_63:40;
1932 uint64_t reserved_0_15:16;
1934 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1935 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
1936 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
1937 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
1940 union cvmx_npei_pcie_msi_rcv_b3 {
1942 struct cvmx_npei_pcie_msi_rcv_b3_s {
1943 uint64_t reserved_32_63:32;
1945 uint64_t reserved_0_23:24;
1947 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1948 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
1949 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
1950 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
1953 union cvmx_npei_pktx_cnts {
1955 struct cvmx_npei_pktx_cnts_s {
1956 uint64_t reserved_54_63:10;
1960 struct cvmx_npei_pktx_cnts_s cn52xx;
1961 struct cvmx_npei_pktx_cnts_s cn56xx;
1962 struct cvmx_npei_pktx_cnts_s cn56xxp1;
1965 union cvmx_npei_pktx_in_bp {
1967 struct cvmx_npei_pktx_in_bp_s {
1971 struct cvmx_npei_pktx_in_bp_s cn52xx;
1972 struct cvmx_npei_pktx_in_bp_s cn56xx;
1973 struct cvmx_npei_pktx_in_bp_s cn56xxp1;
1976 union cvmx_npei_pktx_instr_baddr {
1978 struct cvmx_npei_pktx_instr_baddr_s {
1980 uint64_t reserved_0_2:3;
1982 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1983 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
1984 struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
1987 union cvmx_npei_pktx_instr_baoff_dbell {
1989 struct cvmx_npei_pktx_instr_baoff_dbell_s {
1993 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1994 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
1995 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
1998 union cvmx_npei_pktx_instr_fifo_rsize {
2000 struct cvmx_npei_pktx_instr_fifo_rsize_s {
2007 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2008 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2009 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2012 union cvmx_npei_pktx_instr_header {
2014 struct cvmx_npei_pktx_instr_header_s {
2015 uint64_t reserved_44_63:20;
2018 uint64_t rparmode:2;
2020 uint64_t rskp_len:7;
2022 uint64_t use_ihdr:1;
2024 uint64_t par_mode:2;
2029 struct cvmx_npei_pktx_instr_header_s cn52xx;
2030 struct cvmx_npei_pktx_instr_header_s cn56xx;
2031 struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2034 union cvmx_npei_pktx_slist_baddr {
2036 struct cvmx_npei_pktx_slist_baddr_s {
2038 uint64_t reserved_0_3:4;
2040 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2041 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2042 struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2045 union cvmx_npei_pktx_slist_baoff_dbell {
2047 struct cvmx_npei_pktx_slist_baoff_dbell_s {
2051 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2052 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2053 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2056 union cvmx_npei_pktx_slist_fifo_rsize {
2058 struct cvmx_npei_pktx_slist_fifo_rsize_s {
2059 uint64_t reserved_32_63:32;
2062 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2063 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2064 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2067 union cvmx_npei_pkt_cnt_int {
2069 struct cvmx_npei_pkt_cnt_int_s {
2070 uint64_t reserved_32_63:32;
2073 struct cvmx_npei_pkt_cnt_int_s cn52xx;
2074 struct cvmx_npei_pkt_cnt_int_s cn56xx;
2075 struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2078 union cvmx_npei_pkt_cnt_int_enb {
2080 struct cvmx_npei_pkt_cnt_int_enb_s {
2081 uint64_t reserved_32_63:32;
2084 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2085 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2086 struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2089 union cvmx_npei_pkt_data_out_es {
2091 struct cvmx_npei_pkt_data_out_es_s {
2094 struct cvmx_npei_pkt_data_out_es_s cn52xx;
2095 struct cvmx_npei_pkt_data_out_es_s cn56xx;
2096 struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2099 union cvmx_npei_pkt_data_out_ns {
2101 struct cvmx_npei_pkt_data_out_ns_s {
2102 uint64_t reserved_32_63:32;
2105 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2106 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2107 struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2110 union cvmx_npei_pkt_data_out_ror {
2112 struct cvmx_npei_pkt_data_out_ror_s {
2113 uint64_t reserved_32_63:32;
2116 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2117 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2118 struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2121 union cvmx_npei_pkt_dpaddr {
2123 struct cvmx_npei_pkt_dpaddr_s {
2124 uint64_t reserved_32_63:32;
2127 struct cvmx_npei_pkt_dpaddr_s cn52xx;
2128 struct cvmx_npei_pkt_dpaddr_s cn56xx;
2129 struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2132 union cvmx_npei_pkt_in_bp {
2134 struct cvmx_npei_pkt_in_bp_s {
2135 uint64_t reserved_32_63:32;
2138 struct cvmx_npei_pkt_in_bp_s cn56xx;
2141 union cvmx_npei_pkt_in_donex_cnts {
2143 struct cvmx_npei_pkt_in_donex_cnts_s {
2144 uint64_t reserved_32_63:32;
2147 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2148 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2149 struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2152 union cvmx_npei_pkt_in_instr_counts {
2154 struct cvmx_npei_pkt_in_instr_counts_s {
2158 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2159 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
2162 union cvmx_npei_pkt_in_pcie_port {
2164 struct cvmx_npei_pkt_in_pcie_port_s {
2167 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2168 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
2171 union cvmx_npei_pkt_input_control {
2173 struct cvmx_npei_pkt_input_control_s {
2174 uint64_t reserved_23_63:41;
2176 uint64_t pbp_dhi:13;
2185 struct cvmx_npei_pkt_input_control_s cn52xx;
2186 struct cvmx_npei_pkt_input_control_s cn56xx;
2187 struct cvmx_npei_pkt_input_control_s cn56xxp1;
2190 union cvmx_npei_pkt_instr_enb {
2192 struct cvmx_npei_pkt_instr_enb_s {
2193 uint64_t reserved_32_63:32;
2196 struct cvmx_npei_pkt_instr_enb_s cn52xx;
2197 struct cvmx_npei_pkt_instr_enb_s cn56xx;
2198 struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2201 union cvmx_npei_pkt_instr_rd_size {
2203 struct cvmx_npei_pkt_instr_rd_size_s {
2206 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2207 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
2210 union cvmx_npei_pkt_instr_size {
2212 struct cvmx_npei_pkt_instr_size_s {
2213 uint64_t reserved_32_63:32;
2216 struct cvmx_npei_pkt_instr_size_s cn52xx;
2217 struct cvmx_npei_pkt_instr_size_s cn56xx;
2218 struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2221 union cvmx_npei_pkt_int_levels {
2223 struct cvmx_npei_pkt_int_levels_s {
2224 uint64_t reserved_54_63:10;
2228 struct cvmx_npei_pkt_int_levels_s cn52xx;
2229 struct cvmx_npei_pkt_int_levels_s cn56xx;
2230 struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2233 union cvmx_npei_pkt_iptr {
2235 struct cvmx_npei_pkt_iptr_s {
2236 uint64_t reserved_32_63:32;
2239 struct cvmx_npei_pkt_iptr_s cn52xx;
2240 struct cvmx_npei_pkt_iptr_s cn56xx;
2241 struct cvmx_npei_pkt_iptr_s cn56xxp1;
2244 union cvmx_npei_pkt_out_bmode {
2246 struct cvmx_npei_pkt_out_bmode_s {
2247 uint64_t reserved_32_63:32;
2250 struct cvmx_npei_pkt_out_bmode_s cn52xx;
2251 struct cvmx_npei_pkt_out_bmode_s cn56xx;
2252 struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2255 union cvmx_npei_pkt_out_enb {
2257 struct cvmx_npei_pkt_out_enb_s {
2258 uint64_t reserved_32_63:32;
2261 struct cvmx_npei_pkt_out_enb_s cn52xx;
2262 struct cvmx_npei_pkt_out_enb_s cn56xx;
2263 struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2266 union cvmx_npei_pkt_output_wmark {
2268 struct cvmx_npei_pkt_output_wmark_s {
2269 uint64_t reserved_32_63:32;
2272 struct cvmx_npei_pkt_output_wmark_s cn52xx;
2273 struct cvmx_npei_pkt_output_wmark_s cn56xx;
2276 union cvmx_npei_pkt_pcie_port {
2278 struct cvmx_npei_pkt_pcie_port_s {
2281 struct cvmx_npei_pkt_pcie_port_s cn52xx;
2282 struct cvmx_npei_pkt_pcie_port_s cn56xx;
2283 struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2286 union cvmx_npei_pkt_port_in_rst {
2288 struct cvmx_npei_pkt_port_in_rst_s {
2290 uint64_t out_rst:32;
2292 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2293 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
2296 union cvmx_npei_pkt_slist_es {
2298 struct cvmx_npei_pkt_slist_es_s {
2301 struct cvmx_npei_pkt_slist_es_s cn52xx;
2302 struct cvmx_npei_pkt_slist_es_s cn56xx;
2303 struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2306 union cvmx_npei_pkt_slist_id_size {
2308 struct cvmx_npei_pkt_slist_id_size_s {
2309 uint64_t reserved_23_63:41;
2313 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2314 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2315 struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2318 union cvmx_npei_pkt_slist_ns {
2320 struct cvmx_npei_pkt_slist_ns_s {
2321 uint64_t reserved_32_63:32;
2324 struct cvmx_npei_pkt_slist_ns_s cn52xx;
2325 struct cvmx_npei_pkt_slist_ns_s cn56xx;
2326 struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2329 union cvmx_npei_pkt_slist_ror {
2331 struct cvmx_npei_pkt_slist_ror_s {
2332 uint64_t reserved_32_63:32;
2335 struct cvmx_npei_pkt_slist_ror_s cn52xx;
2336 struct cvmx_npei_pkt_slist_ror_s cn56xx;
2337 struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2340 union cvmx_npei_pkt_time_int {
2342 struct cvmx_npei_pkt_time_int_s {
2343 uint64_t reserved_32_63:32;
2346 struct cvmx_npei_pkt_time_int_s cn52xx;
2347 struct cvmx_npei_pkt_time_int_s cn56xx;
2348 struct cvmx_npei_pkt_time_int_s cn56xxp1;
2351 union cvmx_npei_pkt_time_int_enb {
2353 struct cvmx_npei_pkt_time_int_enb_s {
2354 uint64_t reserved_32_63:32;
2357 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2358 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2359 struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2362 union cvmx_npei_rsl_int_blocks {
2364 struct cvmx_npei_rsl_int_blocks_s {
2365 uint64_t reserved_31_63:33;
2369 uint64_t reserved_24_27:4;
2372 uint64_t reserved_21_21:1;
2374 uint64_t reserved_18_19:2;
2384 uint64_t reserved_8_8:1;
2386 uint64_t reserved_6_6:1;
2394 struct cvmx_npei_rsl_int_blocks_s cn52xx;
2395 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2396 struct cvmx_npei_rsl_int_blocks_cn56xx {
2397 uint64_t reserved_31_63:33;
2401 uint64_t reserved_24_27:4;
2404 uint64_t reserved_21_21:1;
2406 uint64_t reserved_18_19:2;
2409 uint64_t reserved_15_15:1;
2416 uint64_t reserved_8_8:1;
2418 uint64_t reserved_6_6:1;
2426 struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2429 union cvmx_npei_scratch_1 {
2431 struct cvmx_npei_scratch_1_s {
2434 struct cvmx_npei_scratch_1_s cn52xx;
2435 struct cvmx_npei_scratch_1_s cn52xxp1;
2436 struct cvmx_npei_scratch_1_s cn56xx;
2437 struct cvmx_npei_scratch_1_s cn56xxp1;
2440 union cvmx_npei_state1 {
2442 struct cvmx_npei_state1_s {
2448 struct cvmx_npei_state1_s cn52xx;
2449 struct cvmx_npei_state1_s cn52xxp1;
2450 struct cvmx_npei_state1_s cn56xx;
2451 struct cvmx_npei_state1_s cn56xxp1;
2454 union cvmx_npei_state2 {
2456 struct cvmx_npei_state2_s {
2457 uint64_t reserved_48_63:16;
2465 struct cvmx_npei_state2_s cn52xx;
2466 struct cvmx_npei_state2_s cn52xxp1;
2467 struct cvmx_npei_state2_s cn56xx;
2468 struct cvmx_npei_state2_s cn56xxp1;
2471 union cvmx_npei_state3 {
2473 struct cvmx_npei_state3_s {
2474 uint64_t reserved_56_63:8;
2480 struct cvmx_npei_state3_s cn52xx;
2481 struct cvmx_npei_state3_s cn52xxp1;
2482 struct cvmx_npei_state3_s cn56xx;
2483 struct cvmx_npei_state3_s cn56xxp1;
2486 union cvmx_npei_win_rd_addr {
2488 struct cvmx_npei_win_rd_addr_s {
2489 uint64_t reserved_51_63:13;
2492 uint64_t rd_addr:48;
2494 struct cvmx_npei_win_rd_addr_s cn52xx;
2495 struct cvmx_npei_win_rd_addr_s cn52xxp1;
2496 struct cvmx_npei_win_rd_addr_s cn56xx;
2497 struct cvmx_npei_win_rd_addr_s cn56xxp1;
2500 union cvmx_npei_win_rd_data {
2502 struct cvmx_npei_win_rd_data_s {
2503 uint64_t rd_data:64;
2505 struct cvmx_npei_win_rd_data_s cn52xx;
2506 struct cvmx_npei_win_rd_data_s cn52xxp1;
2507 struct cvmx_npei_win_rd_data_s cn56xx;
2508 struct cvmx_npei_win_rd_data_s cn56xxp1;
2511 union cvmx_npei_win_wr_addr {
2513 struct cvmx_npei_win_wr_addr_s {
2514 uint64_t reserved_49_63:15;
2516 uint64_t wr_addr:46;
2517 uint64_t reserved_0_1:2;
2519 struct cvmx_npei_win_wr_addr_s cn52xx;
2520 struct cvmx_npei_win_wr_addr_s cn52xxp1;
2521 struct cvmx_npei_win_wr_addr_s cn56xx;
2522 struct cvmx_npei_win_wr_addr_s cn56xxp1;
2525 union cvmx_npei_win_wr_data {
2527 struct cvmx_npei_win_wr_data_s {
2528 uint64_t wr_data:64;
2530 struct cvmx_npei_win_wr_data_s cn52xx;
2531 struct cvmx_npei_win_wr_data_s cn52xxp1;
2532 struct cvmx_npei_win_wr_data_s cn56xx;
2533 struct cvmx_npei_win_wr_data_s cn56xxp1;
2536 union cvmx_npei_win_wr_mask {
2538 struct cvmx_npei_win_wr_mask_s {
2539 uint64_t reserved_8_63:56;
2542 struct cvmx_npei_win_wr_mask_s cn52xx;
2543 struct cvmx_npei_win_wr_mask_s cn52xxp1;
2544 struct cvmx_npei_win_wr_mask_s cn56xx;
2545 struct cvmx_npei_win_wr_mask_s cn56xxp1;
2548 union cvmx_npei_window_ctl {
2550 struct cvmx_npei_window_ctl_s {
2551 uint64_t reserved_32_63:32;
2554 struct cvmx_npei_window_ctl_s cn52xx;
2555 struct cvmx_npei_window_ctl_s cn52xxp1;
2556 struct cvmx_npei_window_ctl_s cn56xx;
2557 struct cvmx_npei_window_ctl_s cn56xxp1;