arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #define _U64CAST_
  38 #else
  39 #define _ULCAST_ (unsigned long)
  40 #define _U64CAST_ (u64)
  41 #endif
  42
  43 /*
  44  * Coprocessor 0 register names
  45  */
  46 #define CP0_INDEX $0
  47 #define CP0_RANDOM $1
  48 #define CP0_ENTRYLO0 $2
  49 #define CP0_ENTRYLO1 $3
  50 #define CP0_CONF $3
  51 #define CP0_GLOBALNUMBER $3, 1
  52 #define CP0_CONTEXT $4
  53 #define CP0_PAGEMASK $5
  54 #define CP0_SEGCTL0 $5, 2
  55 #define CP0_SEGCTL1 $5, 3
  56 #define CP0_SEGCTL2 $5, 4
  57 #define CP0_WIRED $6
  58 #define CP0_INFO $7
  59 #define CP0_HWRENA $7
  60 #define CP0_BADVADDR $8
  61 #define CP0_BADINSTR $8, 1
  62 #define CP0_COUNT $9
  63 #define CP0_ENTRYHI $10
  64 #define CP0_GUESTCTL1 $10, 4
  65 #define CP0_GUESTCTL2 $10, 5
  66 #define CP0_GUESTCTL3 $10, 6
  67 #define CP0_COMPARE $11
  68 #define CP0_GUESTCTL0EXT $11, 4
  69 #define CP0_STATUS $12
  70 #define CP0_GUESTCTL0 $12, 6
  71 #define CP0_GTOFFSET $12, 7
  72 #define CP0_CAUSE $13
  73 #define CP0_EPC $14
  74 #define CP0_PRID $15
  75 #define CP0_EBASE $15, 1
  76 #define CP0_CMGCRBASE $15, 3
  77 #define CP0_CONFIG $16
  78 #define CP0_CONFIG3 $16, 3
  79 #define CP0_CONFIG5 $16, 5
  80 #define CP0_LLADDR $17
  81 #define CP0_WATCHLO $18
  82 #define CP0_WATCHHI $19
  83 #define CP0_XCONTEXT $20
  84 #define CP0_FRAMEMASK $21
  85 #define CP0_DIAGNOSTIC $22
  86 #define CP0_DEBUG $23
  87 #define CP0_DEPC $24
  88 #define CP0_PERFORMANCE $25
  89 #define CP0_ECC $26
  90 #define CP0_CACHEERR $27
  91 #define CP0_TAGLO $28
  92 #define CP0_TAGHI $29
  93 #define CP0_ERROREPC $30
  94 #define CP0_DESAVE $31
  95
  96 /*
  97  * R4640/R4650 cp0 register names.  These registers are listed
  98  * here only for completeness; without MMU these CPUs are not useable
  99  * by Linux.  A future ELKS port might take make Linux run on them
 100  * though ...
 101  */
 102 #define CP0_IBASE $0
 103 #define CP0_IBOUND $1
 104 #define CP0_DBASE $2
 105 #define CP0_DBOUND $3
 106 #define CP0_CALG $17
 107 #define CP0_IWATCH $18
 108 #define CP0_DWATCH $19
 109
 110 /*
 111  * Coprocessor 0 Set 1 register names
 112  */
 113 #define CP0_S1_DERRADDR0  $26
 114 #define CP0_S1_DERRADDR1  $27
 115 #define CP0_S1_INTCONTROL $20
 116
 117 /*
 118  * Coprocessor 0 Set 2 register names
 119  */
 120 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 121
 122 /*
 123  * Coprocessor 0 Set 3 register names
 124  */
 125 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 126
 127 /*
 128  *  TX39 Series
 129  */
 130 #define CP0_TX39_CACHE  $7
 131
 132
 133 /* Generic EntryLo bit definitions */
 134 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 135 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 136 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 137 #define ENTRYLO_C_SHIFT         3
 138 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 139
 140 /* R3000 EntryLo bit definitions */
 141 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 142 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 143 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 144 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 145
 146 /* MIPS32/64 EntryLo bit definitions */
 147 #define MIPS_ENTRYLO_PFN_SHIFT  6
 148 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 149 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 150
 151 /*
 152  * MIPSr6+ GlobalNumber register definitions
 153  */
 154 #define MIPS_GLOBALNUMBER_VP_SHF        0
 155 #define MIPS_GLOBALNUMBER_VP            (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
 156 #define MIPS_GLOBALNUMBER_CORE_SHF      8
 157 #define MIPS_GLOBALNUMBER_CORE          (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
 158 #define MIPS_GLOBALNUMBER_CLUSTER_SHF   16
 159 #define MIPS_GLOBALNUMBER_CLUSTER       (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
 160
 161 /*
 162  * Values for PageMask register
 163  */
 164 #ifdef CONFIG_CPU_VR41XX
 165
 166 /* Why doesn't stupidity hurt ... */
 167
 168 #define PM_1K           0x00000000
 169 #define PM_4K           0x00001800
 170 #define PM_16K          0x00007800
 171 #define PM_64K          0x0001f800
 172 #define PM_256K         0x0007f800
 173
 174 #else
 175
 176 #define PM_4K           0x00000000
 177 #define PM_8K           0x00002000
 178 #define PM_16K          0x00006000
 179 #define PM_32K          0x0000e000
 180 #define PM_64K          0x0001e000
 181 #define PM_128K         0x0003e000
 182 #define PM_256K         0x0007e000
 183 #define PM_512K         0x000fe000
 184 #define PM_1M           0x001fe000
 185 #define PM_2M           0x003fe000
 186 #define PM_4M           0x007fe000
 187 #define PM_8M           0x00ffe000
 188 #define PM_16M          0x01ffe000
 189 #define PM_32M          0x03ffe000
 190 #define PM_64M          0x07ffe000
 191 #define PM_256M         0x1fffe000
 192 #define PM_1G           0x7fffe000
 193
 194 #endif
 195
 196 /*
 197  * Default page size for a given kernel configuration
 198  */
 199 #ifdef CONFIG_PAGE_SIZE_4KB
 200 #define PM_DEFAULT_MASK PM_4K
 201 #elif defined(CONFIG_PAGE_SIZE_8KB)
 202 #define PM_DEFAULT_MASK PM_8K
 203 #elif defined(CONFIG_PAGE_SIZE_16KB)
 204 #define PM_DEFAULT_MASK PM_16K
 205 #elif defined(CONFIG_PAGE_SIZE_32KB)
 206 #define PM_DEFAULT_MASK PM_32K
 207 #elif defined(CONFIG_PAGE_SIZE_64KB)
 208 #define PM_DEFAULT_MASK PM_64K
 209 #else
 210 #error Bad page size configuration!
 211 #endif
 212
 213 /*
 214  * Default huge tlb size for a given kernel configuration
 215  */
 216 #ifdef CONFIG_PAGE_SIZE_4KB
 217 #define PM_HUGE_MASK    PM_1M
 218 #elif defined(CONFIG_PAGE_SIZE_8KB)
 219 #define PM_HUGE_MASK    PM_4M
 220 #elif defined(CONFIG_PAGE_SIZE_16KB)
 221 #define PM_HUGE_MASK    PM_16M
 222 #elif defined(CONFIG_PAGE_SIZE_32KB)
 223 #define PM_HUGE_MASK    PM_64M
 224 #elif defined(CONFIG_PAGE_SIZE_64KB)
 225 #define PM_HUGE_MASK    PM_256M
 226 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 227 #error Bad page size configuration for hugetlbfs!
 228 #endif
 229
 230 /*
 231  * Wired register bits
 232  */
 233 #define MIPSR6_WIRED_LIMIT_SHIFT 16
 234 #define MIPSR6_WIRED_LIMIT      (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
 235 #define MIPSR6_WIRED_WIRED_SHIFT 0
 236 #define MIPSR6_WIRED_WIRED      (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
 237
 238 /*
 239  * Values used for computation of new tlb entries
 240  */
 241 #define PL_4K           12
 242 #define PL_16K          14
 243 #define PL_64K          16
 244 #define PL_256K         18
 245 #define PL_1M           20
 246 #define PL_4M           22
 247 #define PL_16M          24
 248 #define PL_64M          26
 249 #define PL_256M         28
 250
 251 /*
 252  * PageGrain bits
 253  */
 254 #define PG_RIE          (_ULCAST_(1) <<  31)
 255 #define PG_XIE          (_ULCAST_(1) <<  30)
 256 #define PG_ELPA         (_ULCAST_(1) <<  29)
 257 #define PG_ESP          (_ULCAST_(1) <<  28)
 258 #define PG_IEC          (_ULCAST_(1) <<  27)
 259
 260 /* MIPS32/64 EntryHI bit definitions */
 261 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 262 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 263 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 264
 265 /*
 266  * R4x00 interrupt enable / cause bits
 267  */
 268 #define IE_SW0          (_ULCAST_(1) <<  8)
 269 #define IE_SW1          (_ULCAST_(1) <<  9)
 270 #define IE_IRQ0         (_ULCAST_(1) << 10)
 271 #define IE_IRQ1         (_ULCAST_(1) << 11)
 272 #define IE_IRQ2         (_ULCAST_(1) << 12)
 273 #define IE_IRQ3         (_ULCAST_(1) << 13)
 274 #define IE_IRQ4         (_ULCAST_(1) << 14)
 275 #define IE_IRQ5         (_ULCAST_(1) << 15)
 276
 277 /*
 278  * R4x00 interrupt cause bits
 279  */
 280 #define C_SW0           (_ULCAST_(1) <<  8)
 281 #define C_SW1           (_ULCAST_(1) <<  9)
 282 #define C_IRQ0          (_ULCAST_(1) << 10)
 283 #define C_IRQ1          (_ULCAST_(1) << 11)
 284 #define C_IRQ2          (_ULCAST_(1) << 12)
 285 #define C_IRQ3          (_ULCAST_(1) << 13)
 286 #define C_IRQ4          (_ULCAST_(1) << 14)
 287 #define C_IRQ5          (_ULCAST_(1) << 15)
 288
 289 /*
 290  * Bitfields in the R4xx0 cp0 status register
 291  */
 292 #define ST0_IE                  0x00000001
 293 #define ST0_EXL                 0x00000002
 294 #define ST0_ERL                 0x00000004
 295 #define ST0_KSU                 0x00000018
 296 #  define KSU_USER              0x00000010
 297 #  define KSU_SUPERVISOR        0x00000008
 298 #  define KSU_KERNEL            0x00000000
 299 #define ST0_UX                  0x00000020
 300 #define ST0_SX                  0x00000040
 301 #define ST0_KX                  0x00000080
 302 #define ST0_DE                  0x00010000
 303 #define ST0_CE                  0x00020000
 304
 305 /*
 306  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 307  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 308  * processors.
 309  */
 310 #define ST0_CO                  0x08000000
 311
 312 /*
 313  * Bitfields in the R[23]000 cp0 status register.
 314  */
 315 #define ST0_IEC                 0x00000001
 316 #define ST0_KUC                 0x00000002
 317 #define ST0_IEP                 0x00000004
 318 #define ST0_KUP                 0x00000008
 319 #define ST0_IEO                 0x00000010
 320 #define ST0_KUO                 0x00000020
 321 /* bits 6 & 7 are reserved on R[23]000 */
 322 #define ST0_ISC                 0x00010000
 323 #define ST0_SWC                 0x00020000
 324 #define ST0_CM                  0x00080000
 325
 326 /*
 327  * Bits specific to the R4640/R4650
 328  */
 329 #define ST0_UM                  (_ULCAST_(1) <<  4)
 330 #define ST0_IL                  (_ULCAST_(1) << 23)
 331 #define ST0_DL                  (_ULCAST_(1) << 24)
 332
 333 /*
 334  * Enable the MIPS MDMX and DSP ASEs
 335  */
 336 #define ST0_MX                  0x01000000
 337
 338 /*
 339  * Status register bits available in all MIPS CPUs.
 340  */
 341 #define ST0_IM                  0x0000ff00
 342 #define  STATUSB_IP0            8
 343 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 344 #define  STATUSB_IP1            9
 345 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 346 #define  STATUSB_IP2            10
 347 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 348 #define  STATUSB_IP3            11
 349 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 350 #define  STATUSB_IP4            12
 351 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 352 #define  STATUSB_IP5            13
 353 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 354 #define  STATUSB_IP6            14
 355 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 356 #define  STATUSB_IP7            15
 357 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 358 #define  STATUSB_IP8            0
 359 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 360 #define  STATUSB_IP9            1
 361 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 362 #define  STATUSB_IP10           2
 363 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 364 #define  STATUSB_IP11           3
 365 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 366 #define  STATUSB_IP12           4
 367 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 368 #define  STATUSB_IP13           5
 369 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 370 #define  STATUSB_IP14           6
 371 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 372 #define  STATUSB_IP15           7
 373 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 374 #define ST0_CH                  0x00040000
 375 #define ST0_NMI                 0x00080000
 376 #define ST0_SR                  0x00100000
 377 #define ST0_TS                  0x00200000
 378 #define ST0_BEV                 0x00400000
 379 #define ST0_RE                  0x02000000
 380 #define ST0_FR                  0x04000000
 381 #define ST0_CU                  0xf0000000
 382 #define ST0_CU0                 0x10000000
 383 #define ST0_CU1                 0x20000000
 384 #define ST0_CU2                 0x40000000
 385 #define ST0_CU3                 0x80000000
 386 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 387
 388 /*
 389  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 390  */
 391 #define INTCTLB_IPFDC           23
 392 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 393 #define INTCTLB_IPPCI           26
 394 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 395 #define INTCTLB_IPTI            29
 396 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 397
 398 /*
 399  * Bitfields and bit numbers in the coprocessor 0 cause register.
 400  *
 401  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 402  */
 403 #define CAUSEB_EXCCODE          2
 404 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 405 #define CAUSEB_IP               8
 406 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 407 #define  CAUSEB_IP0             8
 408 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 409 #define  CAUSEB_IP1             9
 410 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 411 #define  CAUSEB_IP2             10
 412 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 413 #define  CAUSEB_IP3             11
 414 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 415 #define  CAUSEB_IP4             12
 416 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 417 #define  CAUSEB_IP5             13
 418 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 419 #define  CAUSEB_IP6             14
 420 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 421 #define  CAUSEB_IP7             15
 422 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 423 #define CAUSEB_FDCI             21
 424 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 425 #define CAUSEB_WP               22
 426 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 427 #define CAUSEB_IV               23
 428 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 429 #define CAUSEB_PCI              26
 430 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 431 #define CAUSEB_DC               27
 432 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 433 #define CAUSEB_CE               28
 434 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 435 #define CAUSEB_TI               30
 436 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 437 #define CAUSEB_BD               31
 438 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 439
 440 /*
 441  * Cause.ExcCode trap codes.
 442  */
 443 #define EXCCODE_INT             0       /* Interrupt pending */
 444 #define EXCCODE_MOD             1       /* TLB modified fault */
 445 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 446 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 447 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 448 #define EXCCODE_ADES            5       /* Address error on a store */
 449 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 450 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 451 #define EXCCODE_SYS             8       /* System call */
 452 #define EXCCODE_BP              9       /* Breakpoint */
 453 #define EXCCODE_RI              10      /* Reserved instruction exception */
 454 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 455 #define EXCCODE_OV              12      /* Arithmetic overflow */
 456 #define EXCCODE_TR              13      /* Trap instruction */
 457 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 458 #define EXCCODE_FPE             15      /* Floating point exception */
 459 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 460 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 461 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 462 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 463 #define EXCCODE_WATCH           23      /* Watch address reference */
 464 #define EXCCODE_MCHECK          24      /* Machine check */
 465 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 466 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 467 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 468
 469 /* Implementation specific trap codes used by MIPS cores */
 470 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 471
 472 /*
 473  * Bits in the coprocessor 0 config register.
 474  */
 475 /* Generic bits.  */
 476 #define CONF_CM_CACHABLE_NO_WA          0
 477 #define CONF_CM_CACHABLE_WA             1
 478 #define CONF_CM_UNCACHED                2
 479 #define CONF_CM_CACHABLE_NONCOHERENT    3
 480 #define CONF_CM_CACHABLE_CE             4
 481 #define CONF_CM_CACHABLE_COW            5
 482 #define CONF_CM_CACHABLE_CUW            6
 483 #define CONF_CM_CACHABLE_ACCELERATED    7
 484 #define CONF_CM_CMASK                   7
 485 #define CONF_BE                 (_ULCAST_(1) << 15)
 486
 487 /* Bits common to various processors.  */
 488 #define CONF_CU                 (_ULCAST_(1) <<  3)
 489 #define CONF_DB                 (_ULCAST_(1) <<  4)
 490 #define CONF_IB                 (_ULCAST_(1) <<  5)
 491 #define CONF_DC                 (_ULCAST_(7) <<  6)
 492 #define CONF_IC                 (_ULCAST_(7) <<  9)
 493 #define CONF_EB                 (_ULCAST_(1) << 13)
 494 #define CONF_EM                 (_ULCAST_(1) << 14)
 495 #define CONF_SM                 (_ULCAST_(1) << 16)
 496 #define CONF_SC                 (_ULCAST_(1) << 17)
 497 #define CONF_EW                 (_ULCAST_(3) << 18)
 498 #define CONF_EP                 (_ULCAST_(15)<< 24)
 499 #define CONF_EC                 (_ULCAST_(7) << 28)
 500 #define CONF_CM                 (_ULCAST_(1) << 31)
 501
 502 /* Bits specific to the R4xx0.  */
 503 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 504 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 505 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 506
 507 /* Bits specific to the R5000.  */
 508 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 509 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 510
 511 /* Bits specific to the RM7000.  */
 512 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 513 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 514 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 515 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 516 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 517 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 518
 519 /* Bits specific to the R10000.  */
 520 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 521 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 522 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 523 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 524 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 525 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 526 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 527 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 528 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 529 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 530 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 531
 532 /* Bits specific to the VR41xx.  */
 533 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 534 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 535 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 536 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 537 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 538
 539 /* Bits specific to the R30xx.  */
 540 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 541 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 542 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 543 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 544 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 545 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 546 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 547 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 548 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 549
 550 /* Bits specific to the TX49.  */
 551 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 552 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 553 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 554 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 555
 556 /* Bits specific to the MIPS32/64 PRA.  */
 557 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 558 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 559 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 560 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 561 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 562 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 563 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 564
 565 /*
 566  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 567  */
 568 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 569 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 570 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 571 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 572 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 573 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 574 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 575 #define MIPS_CONF1_DA_SHF       7
 576 #define MIPS_CONF1_DA_SZ        3
 577 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 578 #define MIPS_CONF1_DL_SHF       10
 579 #define MIPS_CONF1_DL_SZ        3
 580 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 581 #define MIPS_CONF1_DS_SHF       13
 582 #define MIPS_CONF1_DS_SZ        3
 583 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 584 #define MIPS_CONF1_IA_SHF       16
 585 #define MIPS_CONF1_IA_SZ        3
 586 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 587 #define MIPS_CONF1_IL_SHF       19
 588 #define MIPS_CONF1_IL_SZ        3
 589 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 590 #define MIPS_CONF1_IS_SHF       22
 591 #define MIPS_CONF1_IS_SZ        3
 592 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 593 #define MIPS_CONF1_TLBS_SHIFT   (25)
 594 #define MIPS_CONF1_TLBS_SIZE    (6)
 595 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 596
 597 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 598 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 599 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 600 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 601 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 602 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 603 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 604 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 605
 606 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 607 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 608 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 609 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 610 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 611 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 612 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 613 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 614 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 615 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 616 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 617 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 618 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 619 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 620 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 621 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 622 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 623 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 624 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 625 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 626 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 627 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 628 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 629 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 630 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 631 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 632 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 633
 634 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 635 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 636 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 637 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 638 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 639 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 640 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 641 /* bits 10:8 in FTLB-only configurations */
 642 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 643 /* bits 12:8 in VTLB-FTLB only configurations */
 644 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 645 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 646 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 647 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 648 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 649 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 650 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 651 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 652 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 653 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 654 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 655 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 656
 657 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 658 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 659 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 660 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 661 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 662 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 663 #define MIPS_CONF5_SBRI         (_ULCAST_(1) << 6)
 664 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 665 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 666 #define MIPS_CONF5_CA2          (_ULCAST_(1) << 14)
 667 #define MIPS_CONF5_CRCP         (_ULCAST_(1) << 18)
 668 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 669 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 670 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 671 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 672
 673 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 674 /* proAptiv FTLB on/off bit */
 675 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 676 /* Loongson-3 FTLB on/off bit */
 677 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 678 /* FTLB probability bits */
 679 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 680
 681 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 682
 683 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 684 /* ExternalSync */
 685 #define MIPS_CONF7_ES           (_ULCAST_(1) << 8)
 686
 687 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 688 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 689
 690 /* Config7 Bits specific to MIPS Technologies. */
 691
 692 /* Performance counters implemented Per TC */
 693 #define MTI_CONF7_PTC           (_ULCAST_(1) << 19)
 694
 695 /* WatchLo* register definitions */
 696 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 697
 698 /* WatchHi* register definitions */
 699 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 700 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 701 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 702 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 703 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 704 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 705 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 706 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 707 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 708 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 709 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 710 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 711 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 712
 713 /* PerfCnt control register definitions */
 714 #define MIPS_PERFCTRL_EXL       (_ULCAST_(1) << 0)
 715 #define MIPS_PERFCTRL_K         (_ULCAST_(1) << 1)
 716 #define MIPS_PERFCTRL_S         (_ULCAST_(1) << 2)
 717 #define MIPS_PERFCTRL_U         (_ULCAST_(1) << 3)
 718 #define MIPS_PERFCTRL_IE        (_ULCAST_(1) << 4)
 719 #define MIPS_PERFCTRL_EVENT_S   5
 720 #define MIPS_PERFCTRL_EVENT     (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 721 #define MIPS_PERFCTRL_PCTD      (_ULCAST_(1) << 15)
 722 #define MIPS_PERFCTRL_EC        (_ULCAST_(0x3) << 23)
 723 #define MIPS_PERFCTRL_EC_R      (_ULCAST_(0) << 23)
 724 #define MIPS_PERFCTRL_EC_RI     (_ULCAST_(1) << 23)
 725 #define MIPS_PERFCTRL_EC_G      (_ULCAST_(2) << 23)
 726 #define MIPS_PERFCTRL_EC_GRI    (_ULCAST_(3) << 23)
 727 #define MIPS_PERFCTRL_W         (_ULCAST_(1) << 30)
 728 #define MIPS_PERFCTRL_M         (_ULCAST_(1) << 31)
 729
 730 /* PerfCnt control register MT extensions used by MIPS cores */
 731 #define MIPS_PERFCTRL_VPEID_S   16
 732 #define MIPS_PERFCTRL_VPEID     (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 733 #define MIPS_PERFCTRL_TCID_S    22
 734 #define MIPS_PERFCTRL_TCID      (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 735 #define MIPS_PERFCTRL_MT_EN     (_ULCAST_(0x3) << 20)
 736 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
 737 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
 738 #define MIPS_PERFCTRL_MT_EN_TC  (_ULCAST_(2) << 20)
 739
 740 /* PerfCnt control register MT extensions used by BMIPS5000 */
 741 #define BRCM_PERFCTRL_TC        (_ULCAST_(1) << 30)
 742
 743 /* PerfCnt control register MT extensions used by Netlogic XLR */
 744 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
 745
 746 /* MAAR bit definitions */
 747 #define MIPS_MAAR_VH            (_U64CAST_(1) << 63)
 748 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 749 #define MIPS_MAAR_ADDR_SHIFT    12
 750 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 751 #define MIPS_MAAR_VL            (_ULCAST_(1) << 0)
 752
 753 /* MAARI bit definitions */
 754 #define MIPS_MAARI_INDEX        (_ULCAST_(0x3f) << 0)
 755
 756 /* EBase bit definitions */
 757 #define MIPS_EBASE_CPUNUM_SHIFT 0
 758 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 759 #define MIPS_EBASE_WG_SHIFT     11
 760 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 761 #define MIPS_EBASE_BASE_SHIFT   12
 762 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 763
 764 /* CMGCRBase bit definitions */
 765 #define MIPS_CMGCRB_BASE        11
 766 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 767
 768 /* LLAddr bit definitions */
 769 #define MIPS_LLADDR_LLB_SHIFT   0
 770 #define MIPS_LLADDR_LLB         (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
 771
 772 /*
 773  * Bits in the MIPS32 Memory Segmentation registers.
 774  */
 775 #define MIPS_SEGCFG_PA_SHIFT    9
 776 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 777 #define MIPS_SEGCFG_AM_SHIFT    4
 778 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 779 #define MIPS_SEGCFG_EU_SHIFT    3
 780 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 781 #define MIPS_SEGCFG_C_SHIFT     0
 782 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 783
 784 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 785 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 786 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 787 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 788 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 789 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 790 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 791
 792 #define MIPS_PWFIELD_GDI_SHIFT  24
 793 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 794 #define MIPS_PWFIELD_UDI_SHIFT  18
 795 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 796 #define MIPS_PWFIELD_MDI_SHIFT  12
 797 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 798 #define MIPS_PWFIELD_PTI_SHIFT  6
 799 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 800 #define MIPS_PWFIELD_PTEI_SHIFT 0
 801 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 802
 803 #define MIPS_PWSIZE_PS_SHIFT    30
 804 #define MIPS_PWSIZE_PS_MASK     0x40000000
 805 #define MIPS_PWSIZE_GDW_SHIFT   24
 806 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 807 #define MIPS_PWSIZE_UDW_SHIFT   18
 808 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 809 #define MIPS_PWSIZE_MDW_SHIFT   12
 810 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 811 #define MIPS_PWSIZE_PTW_SHIFT   6
 812 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 813 #define MIPS_PWSIZE_PTEW_SHIFT  0
 814 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 815
 816 #define MIPS_PWCTL_PWEN_SHIFT   31
 817 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 818 #define MIPS_PWCTL_XK_SHIFT     28
 819 #define MIPS_PWCTL_XK_MASK      0x10000000
 820 #define MIPS_PWCTL_XS_SHIFT     27
 821 #define MIPS_PWCTL_XS_MASK      0x08000000
 822 #define MIPS_PWCTL_XU_SHIFT     26
 823 #define MIPS_PWCTL_XU_MASK      0x04000000
 824 #define MIPS_PWCTL_DPH_SHIFT    7
 825 #define MIPS_PWCTL_DPH_MASK     0x00000080
 826 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 827 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 828 #define MIPS_PWCTL_PSN_SHIFT    0
 829 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 830
 831 /* GuestCtl0 fields */
 832 #define MIPS_GCTL0_GM_SHIFT     31
 833 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 834 #define MIPS_GCTL0_RI_SHIFT     30
 835 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 836 #define MIPS_GCTL0_MC_SHIFT     29
 837 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 838 #define MIPS_GCTL0_CP0_SHIFT    28
 839 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 840 #define MIPS_GCTL0_AT_SHIFT     26
 841 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 842 #define MIPS_GCTL0_GT_SHIFT     25
 843 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 844 #define MIPS_GCTL0_CG_SHIFT     24
 845 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 846 #define MIPS_GCTL0_CF_SHIFT     23
 847 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 848 #define MIPS_GCTL0_G1_SHIFT     22
 849 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 850 #define MIPS_GCTL0_G0E_SHIFT    19
 851 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 852 #define MIPS_GCTL0_PT_SHIFT     18
 853 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 854 #define MIPS_GCTL0_RAD_SHIFT    9
 855 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 856 #define MIPS_GCTL0_DRG_SHIFT    8
 857 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 858 #define MIPS_GCTL0_G2_SHIFT     7
 859 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 860 #define MIPS_GCTL0_GEXC_SHIFT   2
 861 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 862 #define MIPS_GCTL0_SFC2_SHIFT   1
 863 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 864 #define MIPS_GCTL0_SFC1_SHIFT   0
 865 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 866
 867 /* GuestCtl0.AT Guest address translation control */
 868 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 869 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 870
 871 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 872 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 873 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 874 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 875 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 876 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 877 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 878 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 879
 880 /* GuestCtl0Ext fields */
 881 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 882 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 883 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 884 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 885 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 886 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 887 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 888 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 889 #define MIPS_GCTL0EXT_OG_SHIFT  2
 890 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 891 #define MIPS_GCTL0EXT_BG_SHIFT  1
 892 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 893 #define MIPS_GCTL0EXT_MG_SHIFT  0
 894 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 895
 896 /* GuestCtl0Ext.RPW Root page walk configuration */
 897 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 898 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 899 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 900
 901 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 902 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 903 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 904
 905 /* GuestCtl1 fields */
 906 #define MIPS_GCTL1_ID_SHIFT     0
 907 #define MIPS_GCTL1_ID_WIDTH     8
 908 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 909 #define MIPS_GCTL1_RID_SHIFT    16
 910 #define MIPS_GCTL1_RID_WIDTH    8
 911 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 912 #define MIPS_GCTL1_EID_SHIFT    24
 913 #define MIPS_GCTL1_EID_WIDTH    8
 914 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 915
 916 /* GuestID reserved for root context */
 917 #define MIPS_GCTL1_ROOT_GUESTID 0
 918
 919 /* CDMMBase register bit definitions */
 920 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 921 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 922 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 923 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 924 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 925 #define MIPS_CDMMBASE_ADDR_START 15
 926
 927 /* RDHWR register numbers */
 928 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 929 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 930 #define MIPS_HWR_CC             2       /* Cycle counter */
 931 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 932 #define MIPS_HWR_ULR            29      /* UserLocal */
 933 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 934 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 935
 936 /* Bits in HWREna register */
 937 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 938 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 939 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 940 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 941 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 942 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 943 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 944
 945 /*
 946  * Bitfields in the TX39 family CP0 Configuration Register 3
 947  */
 948 #define TX39_CONF_ICS_SHIFT     19
 949 #define TX39_CONF_ICS_MASK      0x00380000
 950 #define TX39_CONF_ICS_1KB       0x00000000
 951 #define TX39_CONF_ICS_2KB       0x00080000
 952 #define TX39_CONF_ICS_4KB       0x00100000
 953 #define TX39_CONF_ICS_8KB       0x00180000
 954 #define TX39_CONF_ICS_16KB      0x00200000
 955
 956 #define TX39_CONF_DCS_SHIFT     16
 957 #define TX39_CONF_DCS_MASK      0x00070000
 958 #define TX39_CONF_DCS_1KB       0x00000000
 959 #define TX39_CONF_DCS_2KB       0x00010000
 960 #define TX39_CONF_DCS_4KB       0x00020000
 961 #define TX39_CONF_DCS_8KB       0x00030000
 962 #define TX39_CONF_DCS_16KB      0x00040000
 963
 964 #define TX39_CONF_CWFON         0x00004000
 965 #define TX39_CONF_WBON          0x00002000
 966 #define TX39_CONF_RF_SHIFT      10
 967 #define TX39_CONF_RF_MASK       0x00000c00
 968 #define TX39_CONF_DOZE          0x00000200
 969 #define TX39_CONF_HALT          0x00000100
 970 #define TX39_CONF_LOCK          0x00000080
 971 #define TX39_CONF_ICE           0x00000020
 972 #define TX39_CONF_DCE           0x00000010
 973 #define TX39_CONF_IRSIZE_SHIFT  2
 974 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 975 #define TX39_CONF_DRSIZE_SHIFT  0
 976 #define TX39_CONF_DRSIZE_MASK   0x00000003
 977
 978 /*
 979  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 980  */
 981 /* Disable Branch Target Address Cache */
 982 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 983 /* Enable Branch Prediction Global History */
 984 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 985 /* Disable Branch Return Cache */
 986 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 987
 988 /* Flush ITLB */
 989 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 990 /* Flush DTLB */
 991 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 992 /* Flush VTLB */
 993 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 994 /* Flush FTLB */
 995 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 996
 997 /* CvmCtl register field definitions */
 998 #define CVMCTL_IPPCI_SHIFT      7
 999 #define CVMCTL_IPPCI            (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1000 #define CVMCTL_IPTI_SHIFT       4
1001 #define CVMCTL_IPTI             (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1002
1003 /* CvmMemCtl2 register field definitions */
1004 #define CVMMEMCTL2_INHIBITTS    (_U64CAST_(1) << 17)
1005
1006 /* CvmVMConfig register field definitions */
1007 #define CVMVMCONF_DGHT          (_U64CAST_(1) << 60)
1008 #define CVMVMCONF_MMUSIZEM1_S   12
1009 #define CVMVMCONF_MMUSIZEM1     (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1010 #define CVMVMCONF_RMMUSIZEM1_S  0
1011 #define CVMVMCONF_RMMUSIZEM1    (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1012
1013 /*
1014  * Coprocessor 1 (FPU) register names
1015  */
1016 #define CP1_REVISION    $0
1017 #define CP1_UFR         $1
1018 #define CP1_UNFR        $4
1019 #define CP1_FCCR        $25
1020 #define CP1_FEXR        $26
1021 #define CP1_FENR        $28
1022 #define CP1_STATUS      $31
1023
1024
1025 /*
1026  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1027  */
1028 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
1029 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
1030 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
1031 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
1032 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
1033 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
1034 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
1035 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
1036 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
1037 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
1038
1039 /*
1040  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1041  */
1042 #define MIPS_FCCR_CONDX_S       0
1043 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1044 #define MIPS_FCCR_COND0_S       0
1045 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1046 #define MIPS_FCCR_COND1_S       1
1047 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1048 #define MIPS_FCCR_COND2_S       2
1049 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1050 #define MIPS_FCCR_COND3_S       3
1051 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1052 #define MIPS_FCCR_COND4_S       4
1053 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1054 #define MIPS_FCCR_COND5_S       5
1055 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1056 #define MIPS_FCCR_COND6_S       6
1057 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1058 #define MIPS_FCCR_COND7_S       7
1059 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1060
1061 /*
1062  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1063  */
1064 #define MIPS_FENR_FS_S          2
1065 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
1066
1067 /*
1068  * FPU Status Register Values
1069  */
1070 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
1071 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
1072
1073 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
1074 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
1075
1076 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
1077 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
1078 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
1079 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
1080 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
1081 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
1082 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
1083 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
1084 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
1085 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
1086 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
1087 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1088 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1089 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1090 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1091 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1092
1093 /*
1094  * Bits 22:20 of the FPU Status Register will be read as 0,
1095  * and should be written as zero.
1096  */
1097 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1098
1099 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1100 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1101
1102 /*
1103  * X the exception cause indicator
1104  * E the exception enable
1105  * S the sticky/flag bit
1106 */
1107 #define FPU_CSR_ALL_X   0x0003f000
1108 #define FPU_CSR_UNI_X   0x00020000
1109 #define FPU_CSR_INV_X   0x00010000
1110 #define FPU_CSR_DIV_X   0x00008000
1111 #define FPU_CSR_OVF_X   0x00004000
1112 #define FPU_CSR_UDF_X   0x00002000
1113 #define FPU_CSR_INE_X   0x00001000
1114
1115 #define FPU_CSR_ALL_E   0x00000f80
1116 #define FPU_CSR_INV_E   0x00000800
1117 #define FPU_CSR_DIV_E   0x00000400
1118 #define FPU_CSR_OVF_E   0x00000200
1119 #define FPU_CSR_UDF_E   0x00000100
1120 #define FPU_CSR_INE_E   0x00000080
1121
1122 #define FPU_CSR_ALL_S   0x0000007c
1123 #define FPU_CSR_INV_S   0x00000040
1124 #define FPU_CSR_DIV_S   0x00000020
1125 #define FPU_CSR_OVF_S   0x00000010
1126 #define FPU_CSR_UDF_S   0x00000008
1127 #define FPU_CSR_INE_S   0x00000004
1128
1129 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1130 #define FPU_CSR_RM      0x00000003
1131 #define FPU_CSR_RN      0x0     /* nearest */
1132 #define FPU_CSR_RZ      0x1     /* towards zero */
1133 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1134 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1135
1136
1137 #ifndef __ASSEMBLY__
1138
1139 /*
1140  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1141  */
1142 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1143     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1144 #define get_isa16_mode(x)               ((x) & 0x1)
1145 #define msk_isa16_mode(x)               ((x) & ~0x1)
1146 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1147 #else
1148 #define get_isa16_mode(x)               0
1149 #define msk_isa16_mode(x)               (x)
1150 #define set_isa16_mode(x)               do { } while(0)
1151 #endif
1152
1153 /*
1154  * microMIPS instructions can be 16-bit or 32-bit in length. This
1155  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1156  */
1157 static inline int mm_insn_16bit(u16 insn)
1158 {
1159         u16 opcode = (insn >> 10) & 0x7;
1160
1161         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1162 }
1163
1164 /*
1165  * Helper macros for generating raw instruction encodings in inline asm.
1166  */
1167 #ifdef CONFIG_CPU_MICROMIPS
1168 #define _ASM_INSN16_IF_MM(_enc)                 \
1169         ".insn\n\t"                             \
1170         ".hword (" #_enc ")\n\t"
1171 #define _ASM_INSN32_IF_MM(_enc)                 \
1172         ".insn\n\t"                             \
1173         ".hword ((" #_enc ") >> 16)\n\t"        \
1174         ".hword ((" #_enc ") & 0xffff)\n\t"
1175 #else
1176 #define _ASM_INSN_IF_MIPS(_enc)                 \
1177         ".insn\n\t"                             \
1178         ".word (" #_enc ")\n\t"
1179 #endif
1180
1181 #ifndef _ASM_INSN16_IF_MM
1182 #define _ASM_INSN16_IF_MM(_enc)
1183 #endif
1184 #ifndef _ASM_INSN32_IF_MM
1185 #define _ASM_INSN32_IF_MM(_enc)
1186 #endif
1187 #ifndef _ASM_INSN_IF_MIPS
1188 #define _ASM_INSN_IF_MIPS(_enc)
1189 #endif
1190
1191 /*
1192  * parse_r var, r - Helper assembler macro for parsing register names.
1193  *
1194  * This converts the register name in $n form provided in \r to the
1195  * corresponding register number, which is assigned to the variable \var. It is
1196  * needed to allow explicit encoding of instructions in inline assembly where
1197  * registers are chosen by the compiler in $n form, allowing us to avoid using
1198  * fixed register numbers.
1199  *
1200  * It also allows newer instructions (not implemented by the assembler) to be
1201  * transparently implemented using assembler macros, instead of needing separate
1202  * cases depending on toolchain support.
1203  *
1204  * Simple usage example:
1205  * __asm__ __volatile__("parse_r __rt, %0\n\t"
1206  *                      ".insn\n\t"
1207  *                      "# di    %0\n\t"
1208  *                      ".word   (0x41606000 | (__rt << 16))"
1209  *                      : "=r" (status);
1210  */
1211
1212 /* Match an individual register number and assign to \var */
1213 #define _IFC_REG(n)                             \
1214         ".ifc   \\r, $" #n "\n\t"               \
1215         "\\var  = " #n "\n\t"                   \
1216         ".endif\n\t"
1217
1218 __asm__(".macro parse_r var r\n\t"
1219         "\\var  = -1\n\t"
1220         _IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
1221         _IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
1222         _IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
1223         _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1224         _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1225         _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1226         _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1227         _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1228         ".iflt  \\var\n\t"
1229         ".error \"Unable to parse register name \\r\"\n\t"
1230         ".endif\n\t"
1231         ".endm");
1232
1233 #undef _IFC_REG
1234
1235 /*
1236  * C macros for generating assembler macros for common instruction formats.
1237  *
1238  * The names of the operands can be chosen by the caller, and the encoding of
1239  * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1240  * the ENC encodings.
1241  */
1242
1243 /* Instructions with no operands */
1244 #define _ASM_MACRO_0(OP, ENC)                                           \
1245         __asm__(".macro " #OP "\n\t"                                    \
1246                 ENC                                                     \
1247                 ".endm")
1248
1249 /* Instructions with 2 register operands */
1250 #define _ASM_MACRO_2R(OP, R1, R2, ENC)                                  \
1251         __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t"                   \
1252                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1253                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1254                 ENC                                                     \
1255                 ".endm")
1256
1257 /* Instructions with 3 register operands */
1258 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)                              \
1259         __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t"          \
1260                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1261                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1262                 "parse_r __" #R3 ", \\" #R3 "\n\t"                      \
1263                 ENC                                                     \
1264                 ".endm")
1265
1266 /* Instructions with 2 register operands and 1 optional select operand */
1267 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)                         \
1268         __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"    \
1269                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1270                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1271                 ENC                                                     \
1272                 ".endm")
1273
1274 /*
1275  * TLB Invalidate Flush
1276  */
1277 static inline void tlbinvf(void)
1278 {
1279         __asm__ __volatile__(
1280                 ".set push\n\t"
1281                 ".set noreorder\n\t"
1282                 "# tlbinvf\n\t"
1283                 _ASM_INSN_IF_MIPS(0x42000004)
1284                 _ASM_INSN32_IF_MM(0x0000537c)
1285                 ".set pop");
1286 }
1287
1288
1289 /*
1290  * Functions to access the R10000 performance counters.  These are basically
1291  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1292  * performance counter number encoded into bits 1 ... 5 of the instruction.
1293  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1294  * disassembler these will look like an access to sel 0 or 1.
1295  */
1296 #define read_r10k_perf_cntr(counter)                            \
1297 ({                                                              \
1298         unsigned int __res;                                     \
1299         __asm__ __volatile__(                                   \
1300         "mfpc\t%0, %1"                                          \
1301         : "=r" (__res)                                          \
1302         : "i" (counter));                                       \
1303                                                                 \
1304         __res;                                                  \
1305 })
1306
1307 #define write_r10k_perf_cntr(counter,val)                       \
1308 do {                                                            \
1309         __asm__ __volatile__(                                   \
1310         "mtpc\t%0, %1"                                          \
1311         :                                                       \
1312         : "r" (val), "i" (counter));                            \
1313 } while (0)
1314
1315 #define read_r10k_perf_event(counter)                           \
1316 ({                                                              \
1317         unsigned int __res;                                     \
1318         __asm__ __volatile__(                                   \
1319         "mfps\t%0, %1"                                          \
1320         : "=r" (__res)                                          \
1321         : "i" (counter));                                       \
1322                                                                 \
1323         __res;                                                  \
1324 })
1325
1326 #define write_r10k_perf_cntl(counter,val)                       \
1327 do {                                                            \
1328         __asm__ __volatile__(                                   \
1329         "mtps\t%0, %1"                                          \
1330         :                                                       \
1331         : "r" (val), "i" (counter));                            \
1332 } while (0)
1333
1334
1335 /*
1336  * Macros to access the system control coprocessor
1337  */
1338
1339 #define ___read_32bit_c0_register(source, sel, vol)                     \
1340 ({ unsigned int __res;                                                  \
1341         if (sel == 0)                                                   \
1342                 __asm__ vol(                                            \
1343                         "mfc0\t%0, " #source "\n\t"                     \
1344                         : "=r" (__res));                                \
1345         else                                                            \
1346                 __asm__ vol(                                            \
1347                         ".set\tmips32\n\t"                              \
1348                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1349                         ".set\tmips0\n\t"                               \
1350                         : "=r" (__res));                                \
1351         __res;                                                          \
1352 })
1353
1354 #define ___read_64bit_c0_register(source, sel, vol)                     \
1355 ({ unsigned long long __res;                                            \
1356         if (sizeof(unsigned long) == 4)                                 \
1357                 __res = __read_64bit_c0_split(source, sel, vol);        \
1358         else if (sel == 0)                                              \
1359                 __asm__ vol(                                            \
1360                         ".set\tmips3\n\t"                               \
1361                         "dmfc0\t%0, " #source "\n\t"                    \
1362                         ".set\tmips0"                                   \
1363                         : "=r" (__res));                                \
1364         else                                                            \
1365                 __asm__ vol(                                            \
1366                         ".set\tmips64\n\t"                              \
1367                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1368                         ".set\tmips0"                                   \
1369                         : "=r" (__res));                                \
1370         __res;                                                          \
1371 })
1372
1373 #define __read_32bit_c0_register(source, sel)                           \
1374         ___read_32bit_c0_register(source, sel, __volatile__)
1375
1376 #define __read_const_32bit_c0_register(source, sel)                     \
1377         ___read_32bit_c0_register(source, sel,)
1378
1379 #define __read_64bit_c0_register(source, sel)                           \
1380         ___read_64bit_c0_register(source, sel, __volatile__)
1381
1382 #define __read_const_64bit_c0_register(source, sel)                     \
1383         ___read_64bit_c0_register(source, sel,)
1384
1385 #define __write_32bit_c0_register(register, sel, value)                 \
1386 do {                                                                    \
1387         if (sel == 0)                                                   \
1388                 __asm__ __volatile__(                                   \
1389                         "mtc0\t%z0, " #register "\n\t"                  \
1390                         : : "Jr" ((unsigned int)(value)));              \
1391         else                                                            \
1392                 __asm__ __volatile__(                                   \
1393                         ".set\tmips32\n\t"                              \
1394                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1395                         ".set\tmips0"                                   \
1396                         : : "Jr" ((unsigned int)(value)));              \
1397 } while (0)
1398
1399 #define __write_64bit_c0_register(register, sel, value)                 \
1400 do {                                                                    \
1401         if (sizeof(unsigned long) == 4)                                 \
1402                 __write_64bit_c0_split(register, sel, value);           \
1403         else if (sel == 0)                                              \
1404                 __asm__ __volatile__(                                   \
1405                         ".set\tmips3\n\t"                               \
1406                         "dmtc0\t%z0, " #register "\n\t"                 \
1407                         ".set\tmips0"                                   \
1408                         : : "Jr" (value));                              \
1409         else                                                            \
1410                 __asm__ __volatile__(                                   \
1411                         ".set\tmips64\n\t"                              \
1412                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1413                         ".set\tmips0"                                   \
1414                         : : "Jr" (value));                              \
1415 } while (0)
1416
1417 #define __read_ulong_c0_register(reg, sel)                              \
1418         ((sizeof(unsigned long) == 4) ?                                 \
1419         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1420         (unsigned long) __read_64bit_c0_register(reg, sel))
1421
1422 #define __read_const_ulong_c0_register(reg, sel)                        \
1423         ((sizeof(unsigned long) == 4) ?                                 \
1424         (unsigned long) __read_const_32bit_c0_register(reg, sel) :      \
1425         (unsigned long) __read_const_64bit_c0_register(reg, sel))
1426
1427 #define __write_ulong_c0_register(reg, sel, val)                        \
1428 do {                                                                    \
1429         if (sizeof(unsigned long) == 4)                                 \
1430                 __write_32bit_c0_register(reg, sel, val);               \
1431         else                                                            \
1432                 __write_64bit_c0_register(reg, sel, val);               \
1433 } while (0)
1434
1435 /*
1436  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1437  */
1438 #define __read_32bit_c0_ctrl_register(source)                           \
1439 ({ unsigned int __res;                                                  \
1440         __asm__ __volatile__(                                           \
1441                 "cfc0\t%0, " #source "\n\t"                             \
1442                 : "=r" (__res));                                        \
1443         __res;                                                          \
1444 })
1445
1446 #define __write_32bit_c0_ctrl_register(register, value)                 \
1447 do {                                                                    \
1448         __asm__ __volatile__(                                           \
1449                 "ctc0\t%z0, " #register "\n\t"                          \
1450                 : : "Jr" ((unsigned int)(value)));                      \
1451 } while (0)
1452
1453 /*
1454  * These versions are only needed for systems with more than 38 bits of
1455  * physical address space running the 32-bit kernel.  That's none atm :-)
1456  */
1457 #define __read_64bit_c0_split(source, sel, vol)                         \
1458 ({                                                                      \
1459         unsigned long long __val;                                       \
1460         unsigned long __flags;                                          \
1461                                                                         \
1462         local_irq_save(__flags);                                        \
1463         if (sel == 0)                                                   \
1464                 __asm__ vol(                                            \
1465                         ".set\tmips64\n\t"                              \
1466                         "dmfc0\t%L0, " #source "\n\t"                   \
1467                         "dsra\t%M0, %L0, 32\n\t"                        \
1468                         "sll\t%L0, %L0, 0\n\t"                          \
1469                         ".set\tmips0"                                   \
1470                         : "=r" (__val));                                \
1471         else                                                            \
1472                 __asm__ vol(                                            \
1473                         ".set\tmips64\n\t"                              \
1474                         "dmfc0\t%L0, " #source ", " #sel "\n\t"         \
1475                         "dsra\t%M0, %L0, 32\n\t"                        \
1476                         "sll\t%L0, %L0, 0\n\t"                          \
1477                         ".set\tmips0"                                   \
1478                         : "=r" (__val));                                \
1479         local_irq_restore(__flags);                                     \
1480                                                                         \
1481         __val;                                                          \
1482 })
1483
1484 #define __write_64bit_c0_split(source, sel, val)                        \
1485 do {                                                                    \
1486         unsigned long long __tmp;                                       \
1487         unsigned long __flags;                                          \
1488                                                                         \
1489         local_irq_save(__flags);                                        \
1490         if (sel == 0)                                                   \
1491                 __asm__ __volatile__(                                   \
1492                         ".set\tmips64\n\t"                              \
1493                         "dsll\t%L0, %L1, 32\n\t"                        \
1494                         "dsrl\t%L0, %L0, 32\n\t"                        \
1495                         "dsll\t%M0, %M1, 32\n\t"                        \
1496                         "or\t%L0, %L0, %M0\n\t"                         \
1497                         "dmtc0\t%L0, " #source "\n\t"                   \
1498                         ".set\tmips0"                                   \
1499                         : "=&r,r" (__tmp)                               \
1500                         : "r,0" (val));                                 \
1501         else                                                            \
1502                 __asm__ __volatile__(                                   \
1503                         ".set\tmips64\n\t"                              \
1504                         "dsll\t%L0, %L1, 32\n\t"                        \
1505                         "dsrl\t%L0, %L0, 32\n\t"                        \
1506                         "dsll\t%M0, %M1, 32\n\t"                        \
1507                         "or\t%L0, %L0, %M0\n\t"                         \
1508                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1509                         ".set\tmips0"                                   \
1510                         : "=&r,r" (__tmp)                               \
1511                         : "r,0" (val));                                 \
1512         local_irq_restore(__flags);                                     \
1513 } while (0)
1514
1515 #ifndef TOOLCHAIN_SUPPORTS_XPA
1516 _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1517         _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1518         _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1519 _ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1520         _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1521         _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1522 #define _ASM_SET_XPA ""
1523 #else   /* !TOOLCHAIN_SUPPORTS_XPA */
1524 #define _ASM_SET_XPA ".set\txpa\n\t"
1525 #endif
1526
1527 #define __readx_32bit_c0_register(source, sel)                          \
1528 ({                                                                      \
1529         unsigned int __res;                                             \
1530                                                                         \
1531         __asm__ __volatile__(                                           \
1532         "       .set    push                                    \n"     \
1533         "       .set    mips32r2                                \n"     \
1534         _ASM_SET_XPA                                                    \
1535         "       mfhc0   %0, " #source ", %1                     \n"     \
1536         "       .set    pop                                     \n"     \
1537         : "=r" (__res)                                                  \
1538         : "i" (sel));                                                   \
1539         __res;                                                          \
1540 })
1541
1542 #define __writex_32bit_c0_register(register, sel, value)                \
1543 do {                                                                    \
1544         __asm__ __volatile__(                                           \
1545         "       .set    push                                    \n"     \
1546         "       .set    mips32r2                                \n"     \
1547         _ASM_SET_XPA                                                    \
1548         "       mthc0   %z0, " #register ", %1                  \n"     \
1549         "       .set    pop                                     \n"     \
1550         :                                                               \
1551         : "Jr" (value), "i" (sel));                                     \
1552 } while (0)
1553
1554 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1555 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1556
1557 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1558 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1559
1560 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1561 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1562
1563 #define readx_c0_entrylo0()     __readx_32bit_c0_register($2, 0)
1564 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1565
1566 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1567 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1568
1569 #define readx_c0_entrylo1()     __readx_32bit_c0_register($3, 0)
1570 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1571
1572 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1573 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1574
1575 #define read_c0_globalnumber()  __read_32bit_c0_register($3, 1)
1576
1577 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1578 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1579
1580 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1581 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1582
1583 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1584 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1585
1586 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1587 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1588
1589 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1590 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1591
1592 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1593 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1594
1595 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1596 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1597
1598 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1599
1600 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1601 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1602
1603 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1604 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1605
1606 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1607 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1608
1609 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1610 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1611
1612 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1613 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1614
1615 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1616 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1617
1618 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1619 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1620
1621 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1622 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1623
1624 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1625 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1626
1627 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1628 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1629
1630 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1631 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1632
1633 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1634 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1635
1636 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1637 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1638
1639 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1640 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1641
1642 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1643
1644 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1645
1646 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1647 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1648
1649 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1650 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1651
1652 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1653 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1654
1655 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1656 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1657
1658 #define read_c0_prid()          __read_const_32bit_c0_register($15, 0)
1659
1660 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1661
1662 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1663 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1664 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1665 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1666 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1667 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1668 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1669 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1670 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1671 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1672 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1673 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1674 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1675 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1676 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1677 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1678
1679 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1680 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1681 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1682 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1683 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1684 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1685
1686 /*
1687  * The WatchLo register.  There may be up to 8 of them.
1688  */
1689 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1690 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1691 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1692 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1693 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1694 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1695 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1696 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1697 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1698 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1699 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1700 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1701 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1702 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1703 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1704 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1705
1706 /*
1707  * The WatchHi register.  There may be up to 8 of them.
1708  */
1709 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1710 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1711 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1712 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1713 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1714 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1715 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1716 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1717
1718 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1719 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1720 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1721 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1722 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1723 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1724 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1725 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1726
1727 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1728 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1729
1730 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1731 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1732
1733 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1734 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1735
1736 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1737 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1738
1739 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1740 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1741 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1742
1743 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1744 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1745
1746 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1747 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1748
1749 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1750 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1751
1752 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1753 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1754
1755 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1756 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1757
1758 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1759 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1760
1761 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1762 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1763
1764 /*
1765  * MIPS32 / MIPS64 performance counters
1766  */
1767 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1768 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1769 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1770 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1771 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1772 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1773 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1774 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1775 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1776 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1777 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1778 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1779 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1780 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1781 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1782 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1783 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1784 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1785 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1786 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1787 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1788 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1789 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1790 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1791
1792 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1793 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1794
1795 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1796 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1797
1798 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1799
1800 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1801 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1802
1803 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1804 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1805
1806 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1807 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1808
1809 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1810 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1811
1812 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1813 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1814
1815 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1816 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1817
1818 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1819 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1820
1821 /* MIPSR2 */
1822 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1823 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1824
1825 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1826 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1827
1828 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1829 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1830
1831 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1832 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1833
1834 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1835 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1836
1837 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1838 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1839
1840 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1841 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1842
1843 /* MIPSR3 */
1844 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1845 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1846
1847 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1848 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1849
1850 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1851 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1852
1853 /* Hardware Page Table Walker */
1854 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1855 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1856
1857 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1858 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1859
1860 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1861 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1862
1863 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1864 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1865
1866 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1867 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1868
1869 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1870 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1871
1872 /* Cavium OCTEON (cnMIPS) */
1873 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1874 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1875
1876 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1877 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1878
1879 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1880 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1881
1882 #define read_c0_cvmmemctl2()    __read_64bit_c0_register($16, 6)
1883 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1884
1885 #define read_c0_cvmvmconfig()   __read_64bit_c0_register($16, 7)
1886 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1887
1888 /*
1889  * The cacheerr registers are not standardized.  On OCTEON, they are
1890  * 64 bits wide.
1891  */
1892 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1893 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1894
1895 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1896 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1897
1898 /* BMIPS3300 */
1899 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1900 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1901
1902 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1903 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1904
1905 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1906 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1907
1908 /* BMIPS43xx */
1909 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1910 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1911
1912 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1913 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1914
1915 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1916 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1917
1918 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1919 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1920
1921 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1922 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1923
1924 /* BMIPS5000 */
1925 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1926 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1927
1928 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1929 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1930
1931 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1932 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1933
1934 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1935 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1936
1937 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1938 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1939
1940 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1941 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1942
1943 /*
1944  * Macros to access the guest system control coprocessor
1945  */
1946
1947 #ifndef TOOLCHAIN_SUPPORTS_VIRT
1948 _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1949         _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1950         _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1951 _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1952         _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1953         _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1954 _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1955         _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1956         _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1957 _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1958         _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1959         _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1960 _ASM_MACRO_0(tlbgp,    _ASM_INSN_IF_MIPS(0x42000010)
1961                        _ASM_INSN32_IF_MM(0x0000017c));
1962 _ASM_MACRO_0(tlbgr,    _ASM_INSN_IF_MIPS(0x42000009)
1963                        _ASM_INSN32_IF_MM(0x0000117c));
1964 _ASM_MACRO_0(tlbgwi,   _ASM_INSN_IF_MIPS(0x4200000a)
1965                        _ASM_INSN32_IF_MM(0x0000217c));
1966 _ASM_MACRO_0(tlbgwr,   _ASM_INSN_IF_MIPS(0x4200000e)
1967                        _ASM_INSN32_IF_MM(0x0000317c));
1968 _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
1969                        _ASM_INSN32_IF_MM(0x0000517c));
1970 #define _ASM_SET_VIRT ""
1971 #else   /* !TOOLCHAIN_SUPPORTS_VIRT */
1972 #define _ASM_SET_VIRT ".set\tvirt\n\t"
1973 #endif
1974
1975 #define __read_32bit_gc0_register(source, sel)                          \
1976 ({ int __res;                                                           \
1977         __asm__ __volatile__(                                           \
1978                 ".set\tpush\n\t"                                        \
1979                 ".set\tmips32r2\n\t"                                    \
1980                 _ASM_SET_VIRT                                           \
1981                 "mfgc0\t%0, " #source ", %1\n\t"                        \
1982                 ".set\tpop"                                             \
1983                 : "=r" (__res)                                          \
1984                 : "i" (sel));                                           \
1985         __res;                                                          \
1986 })
1987
1988 #define __read_64bit_gc0_register(source, sel)                          \
1989 ({ unsigned long long __res;                                            \
1990         __asm__ __volatile__(                                           \
1991                 ".set\tpush\n\t"                                        \
1992                 ".set\tmips64r2\n\t"                                    \
1993                 _ASM_SET_VIRT                                           \
1994                 "dmfgc0\t%0, " #source ", %1\n\t"                       \
1995                 ".set\tpop"                                             \
1996                 : "=r" (__res)                                          \
1997                 : "i" (sel));                                           \
1998         __res;                                                          \
1999 })
2000
2001 #define __write_32bit_gc0_register(register, sel, value)                \
2002 do {                                                                    \
2003         __asm__ __volatile__(                                           \
2004                 ".set\tpush\n\t"                                        \
2005                 ".set\tmips32r2\n\t"                                    \
2006                 _ASM_SET_VIRT                                           \
2007                 "mtgc0\t%z0, " #register ", %1\n\t"                     \
2008                 ".set\tpop"                                             \
2009                 : : "Jr" ((unsigned int)(value)),                       \
2010                     "i" (sel));                                         \
2011 } while (0)
2012
2013 #define __write_64bit_gc0_register(register, sel, value)                \
2014 do {                                                                    \
2015         __asm__ __volatile__(                                           \
2016                 ".set\tpush\n\t"                                        \
2017                 ".set\tmips64r2\n\t"                                    \
2018                 _ASM_SET_VIRT                                           \
2019                 "dmtgc0\t%z0, " #register ", %1\n\t"                    \
2020                 ".set\tpop"                                             \
2021                 : : "Jr" (value),                                       \
2022                     "i" (sel));                                         \
2023 } while (0)
2024
2025 #define __read_ulong_gc0_register(reg, sel)                             \
2026         ((sizeof(unsigned long) == 4) ?                                 \
2027         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
2028         (unsigned long) __read_64bit_gc0_register(reg, sel))
2029
2030 #define __write_ulong_gc0_register(reg, sel, val)                       \
2031 do {                                                                    \
2032         if (sizeof(unsigned long) == 4)                                 \
2033                 __write_32bit_gc0_register(reg, sel, val);              \
2034         else                                                            \
2035                 __write_64bit_gc0_register(reg, sel, val);              \
2036 } while (0)
2037
2038 #define read_gc0_index()                __read_32bit_gc0_register($0, 0)
2039 #define write_gc0_index(val)            __write_32bit_gc0_register($0, 0, val)
2040
2041 #define read_gc0_entrylo0()             __read_ulong_gc0_register($2, 0)
2042 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register($2, 0, val)
2043
2044 #define read_gc0_entrylo1()             __read_ulong_gc0_register($3, 0)
2045 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register($3, 0, val)
2046
2047 #define read_gc0_context()              __read_ulong_gc0_register($4, 0)
2048 #define write_gc0_context(val)          __write_ulong_gc0_register($4, 0, val)
2049
2050 #define read_gc0_contextconfig()        __read_32bit_gc0_register($4, 1)
2051 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register($4, 1, val)
2052
2053 #define read_gc0_userlocal()            __read_ulong_gc0_register($4, 2)
2054 #define write_gc0_userlocal(val)        __write_ulong_gc0_register($4, 2, val)
2055
2056 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register($4, 3)
2057 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register($4, 3, val)
2058
2059 #define read_gc0_pagemask()             __read_32bit_gc0_register($5, 0)
2060 #define write_gc0_pagemask(val)         __write_32bit_gc0_register($5, 0, val)
2061
2062 #define read_gc0_pagegrain()            __read_32bit_gc0_register($5, 1)
2063 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register($5, 1, val)
2064
2065 #define read_gc0_segctl0()              __read_ulong_gc0_register($5, 2)
2066 #define write_gc0_segctl0(val)          __write_ulong_gc0_register($5, 2, val)
2067
2068 #define read_gc0_segctl1()              __read_ulong_gc0_register($5, 3)
2069 #define write_gc0_segctl1(val)          __write_ulong_gc0_register($5, 3, val)
2070
2071 #define read_gc0_segctl2()              __read_ulong_gc0_register($5, 4)
2072 #define write_gc0_segctl2(val)          __write_ulong_gc0_register($5, 4, val)
2073
2074 #define read_gc0_pwbase()               __read_ulong_gc0_register($5, 5)
2075 #define write_gc0_pwbase(val)           __write_ulong_gc0_register($5, 5, val)
2076
2077 #define read_gc0_pwfield()              __read_ulong_gc0_register($5, 6)
2078 #define write_gc0_pwfield(val)          __write_ulong_gc0_register($5, 6, val)
2079
2080 #define read_gc0_pwsize()               __read_ulong_gc0_register($5, 7)
2081 #define write_gc0_pwsize(val)           __write_ulong_gc0_register($5, 7, val)
2082
2083 #define read_gc0_wired()                __read_32bit_gc0_register($6, 0)
2084 #define write_gc0_wired(val)            __write_32bit_gc0_register($6, 0, val)
2085
2086 #define read_gc0_pwctl()                __read_32bit_gc0_register($6, 6)
2087 #define write_gc0_pwctl(val)            __write_32bit_gc0_register($6, 6, val)
2088
2089 #define read_gc0_hwrena()               __read_32bit_gc0_register($7, 0)
2090 #define write_gc0_hwrena(val)           __write_32bit_gc0_register($7, 0, val)
2091
2092 #define read_gc0_badvaddr()             __read_ulong_gc0_register($8, 0)
2093 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register($8, 0, val)
2094
2095 #define read_gc0_badinstr()             __read_32bit_gc0_register($8, 1)
2096 #define write_gc0_badinstr(val)         __write_32bit_gc0_register($8, 1, val)
2097
2098 #define read_gc0_badinstrp()            __read_32bit_gc0_register($8, 2)
2099 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register($8, 2, val)
2100
2101 #define read_gc0_count()                __read_32bit_gc0_register($9, 0)
2102
2103 #define read_gc0_entryhi()              __read_ulong_gc0_register($10, 0)
2104 #define write_gc0_entryhi(val)          __write_ulong_gc0_register($10, 0, val)
2105
2106 #define read_gc0_compare()              __read_32bit_gc0_register($11, 0)
2107 #define write_gc0_compare(val)          __write_32bit_gc0_register($11, 0, val)
2108
2109 #define read_gc0_status()               __read_32bit_gc0_register($12, 0)
2110 #define write_gc0_status(val)           __write_32bit_gc0_register($12, 0, val)
2111
2112 #define read_gc0_intctl()               __read_32bit_gc0_register($12, 1)
2113 #define write_gc0_intctl(val)           __write_32bit_gc0_register($12, 1, val)
2114
2115 #define read_gc0_cause()                __read_32bit_gc0_register($13, 0)
2116 #define write_gc0_cause(val)            __write_32bit_gc0_register($13, 0, val)
2117
2118 #define read_gc0_epc()                  __read_ulong_gc0_register($14, 0)
2119 #define write_gc0_epc(val)              __write_ulong_gc0_register($14, 0, val)
2120
2121 #define read_gc0_prid()                 __read_32bit_gc0_register($15, 0)
2122
2123 #define read_gc0_ebase()                __read_32bit_gc0_register($15, 1)
2124 #define write_gc0_ebase(val)            __write_32bit_gc0_register($15, 1, val)
2125
2126 #define read_gc0_ebase_64()             __read_64bit_gc0_register($15, 1)
2127 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register($15, 1, val)
2128
2129 #define read_gc0_config()               __read_32bit_gc0_register($16, 0)
2130 #define read_gc0_config1()              __read_32bit_gc0_register($16, 1)
2131 #define read_gc0_config2()              __read_32bit_gc0_register($16, 2)
2132 #define read_gc0_config3()              __read_32bit_gc0_register($16, 3)
2133 #define read_gc0_config4()              __read_32bit_gc0_register($16, 4)
2134 #define read_gc0_config5()              __read_32bit_gc0_register($16, 5)
2135 #define read_gc0_config6()              __read_32bit_gc0_register($16, 6)
2136 #define read_gc0_config7()              __read_32bit_gc0_register($16, 7)
2137 #define write_gc0_config(val)           __write_32bit_gc0_register($16, 0, val)
2138 #define write_gc0_config1(val)          __write_32bit_gc0_register($16, 1, val)
2139 #define write_gc0_config2(val)          __write_32bit_gc0_register($16, 2, val)
2140 #define write_gc0_config3(val)          __write_32bit_gc0_register($16, 3, val)
2141 #define write_gc0_config4(val)          __write_32bit_gc0_register($16, 4, val)
2142 #define write_gc0_config5(val)          __write_32bit_gc0_register($16, 5, val)
2143 #define write_gc0_config6(val)          __write_32bit_gc0_register($16, 6, val)
2144 #define write_gc0_config7(val)          __write_32bit_gc0_register($16, 7, val)
2145
2146 #define read_gc0_lladdr()               __read_ulong_gc0_register($17, 0)
2147 #define write_gc0_lladdr(val)           __write_ulong_gc0_register($17, 0, val)
2148
2149 #define read_gc0_watchlo0()             __read_ulong_gc0_register($18, 0)
2150 #define read_gc0_watchlo1()             __read_ulong_gc0_register($18, 1)
2151 #define read_gc0_watchlo2()             __read_ulong_gc0_register($18, 2)
2152 #define read_gc0_watchlo3()             __read_ulong_gc0_register($18, 3)
2153 #define read_gc0_watchlo4()             __read_ulong_gc0_register($18, 4)
2154 #define read_gc0_watchlo5()             __read_ulong_gc0_register($18, 5)
2155 #define read_gc0_watchlo6()             __read_ulong_gc0_register($18, 6)
2156 #define read_gc0_watchlo7()             __read_ulong_gc0_register($18, 7)
2157 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register($18, 0, val)
2158 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register($18, 1, val)
2159 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register($18, 2, val)
2160 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register($18, 3, val)
2161 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register($18, 4, val)
2162 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register($18, 5, val)
2163 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register($18, 6, val)
2164 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register($18, 7, val)
2165
2166 #define read_gc0_watchhi0()             __read_32bit_gc0_register($19, 0)
2167 #define read_gc0_watchhi1()             __read_32bit_gc0_register($19, 1)
2168 #define read_gc0_watchhi2()             __read_32bit_gc0_register($19, 2)
2169 #define read_gc0_watchhi3()             __read_32bit_gc0_register($19, 3)
2170 #define read_gc0_watchhi4()             __read_32bit_gc0_register($19, 4)
2171 #define read_gc0_watchhi5()             __read_32bit_gc0_register($19, 5)
2172 #define read_gc0_watchhi6()             __read_32bit_gc0_register($19, 6)
2173 #define read_gc0_watchhi7()             __read_32bit_gc0_register($19, 7)
2174 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register($19, 0, val)
2175 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register($19, 1, val)
2176 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register($19, 2, val)
2177 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register($19, 3, val)
2178 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register($19, 4, val)
2179 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register($19, 5, val)
2180 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register($19, 6, val)
2181 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register($19, 7, val)
2182
2183 #define read_gc0_xcontext()             __read_ulong_gc0_register($20, 0)
2184 #define write_gc0_xcontext(val)         __write_ulong_gc0_register($20, 0, val)
2185
2186 #define read_gc0_perfctrl0()            __read_32bit_gc0_register($25, 0)
2187 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register($25, 0, val)
2188 #define read_gc0_perfcntr0()            __read_32bit_gc0_register($25, 1)
2189 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register($25, 1, val)
2190 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register($25, 1)
2191 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register($25, 1, val)
2192 #define read_gc0_perfctrl1()            __read_32bit_gc0_register($25, 2)
2193 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register($25, 2, val)
2194 #define read_gc0_perfcntr1()            __read_32bit_gc0_register($25, 3)
2195 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register($25, 3, val)
2196 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register($25, 3)
2197 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register($25, 3, val)
2198 #define read_gc0_perfctrl2()            __read_32bit_gc0_register($25, 4)
2199 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register($25, 4, val)
2200 #define read_gc0_perfcntr2()            __read_32bit_gc0_register($25, 5)
2201 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register($25, 5, val)
2202 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register($25, 5)
2203 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register($25, 5, val)
2204 #define read_gc0_perfctrl3()            __read_32bit_gc0_register($25, 6)
2205 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register($25, 6, val)
2206 #define read_gc0_perfcntr3()            __read_32bit_gc0_register($25, 7)
2207 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register($25, 7, val)
2208 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register($25, 7)
2209 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register($25, 7, val)
2210
2211 #define read_gc0_errorepc()             __read_ulong_gc0_register($30, 0)
2212 #define write_gc0_errorepc(val)         __write_ulong_gc0_register($30, 0, val)
2213
2214 #define read_gc0_kscratch1()            __read_ulong_gc0_register($31, 2)
2215 #define read_gc0_kscratch2()            __read_ulong_gc0_register($31, 3)
2216 #define read_gc0_kscratch3()            __read_ulong_gc0_register($31, 4)
2217 #define read_gc0_kscratch4()            __read_ulong_gc0_register($31, 5)
2218 #define read_gc0_kscratch5()            __read_ulong_gc0_register($31, 6)
2219 #define read_gc0_kscratch6()            __read_ulong_gc0_register($31, 7)
2220 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register($31, 2, val)
2221 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register($31, 3, val)
2222 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register($31, 4, val)
2223 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register($31, 5, val)
2224 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register($31, 6, val)
2225 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register($31, 7, val)
2226
2227 /* Cavium OCTEON (cnMIPS) */
2228 #define read_gc0_cvmcount()             __read_ulong_gc0_register($9, 6)
2229 #define write_gc0_cvmcount(val)         __write_ulong_gc0_register($9, 6, val)
2230
2231 #define read_gc0_cvmctl()               __read_64bit_gc0_register($9, 7)
2232 #define write_gc0_cvmctl(val)           __write_64bit_gc0_register($9, 7, val)
2233
2234 #define read_gc0_cvmmemctl()            __read_64bit_gc0_register($11, 7)
2235 #define write_gc0_cvmmemctl(val)        __write_64bit_gc0_register($11, 7, val)
2236
2237 #define read_gc0_cvmmemctl2()           __read_64bit_gc0_register($16, 6)
2238 #define write_gc0_cvmmemctl2(val)       __write_64bit_gc0_register($16, 6, val)
2239
2240 /*
2241  * Macros to access the floating point coprocessor control registers
2242  */
2243 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2244 ({                                                                      \
2245         unsigned int __res;                                             \
2246                                                                         \
2247         __asm__ __volatile__(                                           \
2248         "       .set    push                                    \n"     \
2249         "       .set    reorder                                 \n"     \
2250         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2251         "       # like Octeon.                                  \n"     \
2252         "       .set    mips1                                   \n"     \
2253         "       "STR(gas_hardfloat)"                            \n"     \
2254         "       cfc1    %0,"STR(source)"                        \n"     \
2255         "       .set    pop                                     \n"     \
2256         : "=r" (__res));                                                \
2257         __res;                                                          \
2258 })
2259
2260 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2261 do {                                                                    \
2262         __asm__ __volatile__(                                           \
2263         "       .set    push                                    \n"     \
2264         "       .set    reorder                                 \n"     \
2265         "       "STR(gas_hardfloat)"                            \n"     \
2266         "       ctc1    %0,"STR(dest)"                          \n"     \
2267         "       .set    pop                                     \n"     \
2268         : : "r" (val));                                                 \
2269 } while (0)
2270
2271 #ifdef GAS_HAS_SET_HARDFLOAT
2272 #define read_32bit_cp1_register(source)                                 \
2273         _read_32bit_cp1_register(source, .set hardfloat)
2274 #define write_32bit_cp1_register(dest, val)                             \
2275         _write_32bit_cp1_register(dest, val, .set hardfloat)
2276 #else
2277 #define read_32bit_cp1_register(source)                                 \
2278         _read_32bit_cp1_register(source, )
2279 #define write_32bit_cp1_register(dest, val)                             \
2280         _write_32bit_cp1_register(dest, val, )
2281 #endif
2282
2283 #ifdef HAVE_AS_DSP
2284 #define rddsp(mask)                                                     \
2285 ({                                                                      \
2286         unsigned int __dspctl;                                          \
2287                                                                         \
2288         __asm__ __volatile__(                                           \
2289         "       .set push                                       \n"     \
2290         "       .set dsp                                        \n"     \
2291         "       rddsp   %0, %x1                                 \n"     \
2292         "       .set pop                                        \n"     \
2293         : "=r" (__dspctl)                                               \
2294         : "i" (mask));                                                  \
2295         __dspctl;                                                       \
2296 })
2297
2298 #define wrdsp(val, mask)                                                \
2299 do {                                                                    \
2300         __asm__ __volatile__(                                           \
2301         "       .set push                                       \n"     \
2302         "       .set dsp                                        \n"     \
2303         "       wrdsp   %0, %x1                                 \n"     \
2304         "       .set pop                                        \n"     \
2305         :                                                               \
2306         : "r" (val), "i" (mask));                                       \
2307 } while (0)
2308
2309 #define mflo0()                                                         \
2310 ({                                                                      \
2311         long mflo0;                                                     \
2312         __asm__(                                                        \
2313         "       .set push                                       \n"     \
2314         "       .set dsp                                        \n"     \
2315         "       mflo %0, $ac0                                   \n"     \
2316         "       .set pop                                        \n"     \
2317         : "=r" (mflo0));                                                \
2318         mflo0;                                                          \
2319 })
2320
2321 #define mflo1()                                                         \
2322 ({                                                                      \
2323         long mflo1;                                                     \
2324         __asm__(                                                        \
2325         "       .set push                                       \n"     \
2326         "       .set dsp                                        \n"     \
2327         "       mflo %0, $ac1                                   \n"     \
2328         "       .set pop                                        \n"     \
2329         : "=r" (mflo1));                                                \
2330         mflo1;                                                          \
2331 })
2332
2333 #define mflo2()                                                         \
2334 ({                                                                      \
2335         long mflo2;                                                     \
2336         __asm__(                                                        \
2337         "       .set push                                       \n"     \
2338         "       .set dsp                                        \n"     \
2339         "       mflo %0, $ac2                                   \n"     \
2340         "       .set pop                                        \n"     \
2341         : "=r" (mflo2));                                                \
2342         mflo2;                                                          \
2343 })
2344
2345 #define mflo3()                                                         \
2346 ({                                                                      \
2347         long mflo3;                                                     \
2348         __asm__(                                                        \
2349         "       .set push                                       \n"     \
2350         "       .set dsp                                        \n"     \
2351         "       mflo %0, $ac3                                   \n"     \
2352         "       .set pop                                        \n"     \
2353         : "=r" (mflo3));                                                \
2354         mflo3;                                                          \
2355 })
2356
2357 #define mfhi0()                                                         \
2358 ({                                                                      \
2359         long mfhi0;                                                     \
2360         __asm__(                                                        \
2361         "       .set push                                       \n"     \
2362         "       .set dsp                                        \n"     \
2363         "       mfhi %0, $ac0                                   \n"     \
2364         "       .set pop                                        \n"     \
2365         : "=r" (mfhi0));                                                \
2366         mfhi0;                                                          \
2367 })
2368
2369 #define mfhi1()                                                         \
2370 ({                                                                      \
2371         long mfhi1;                                                     \
2372         __asm__(                                                        \
2373         "       .set push                                       \n"     \
2374         "       .set dsp                                        \n"     \
2375         "       mfhi %0, $ac1                                   \n"     \
2376         "       .set pop                                        \n"     \
2377         : "=r" (mfhi1));                                                \
2378         mfhi1;                                                          \
2379 })
2380
2381 #define mfhi2()                                                         \
2382 ({                                                                      \
2383         long mfhi2;                                                     \
2384         __asm__(                                                        \
2385         "       .set push                                       \n"     \
2386         "       .set dsp                                        \n"     \
2387         "       mfhi %0, $ac2                                   \n"     \
2388         "       .set pop                                        \n"     \
2389         : "=r" (mfhi2));                                                \
2390         mfhi2;                                                          \
2391 })
2392
2393 #define mfhi3()                                                         \
2394 ({                                                                      \
2395         long mfhi3;                                                     \
2396         __asm__(                                                        \
2397         "       .set push                                       \n"     \
2398         "       .set dsp                                        \n"     \
2399         "       mfhi %0, $ac3                                   \n"     \
2400         "       .set pop                                        \n"     \
2401         : "=r" (mfhi3));                                                \
2402         mfhi3;                                                          \
2403 })
2404
2405
2406 #define mtlo0(x)                                                        \
2407 ({                                                                      \
2408         __asm__(                                                        \
2409         "       .set push                                       \n"     \
2410         "       .set dsp                                        \n"     \
2411         "       mtlo %0, $ac0                                   \n"     \
2412         "       .set pop                                        \n"     \
2413         :                                                               \
2414         : "r" (x));                                                     \
2415 })
2416
2417 #define mtlo1(x)                                                        \
2418 ({                                                                      \
2419         __asm__(                                                        \
2420         "       .set push                                       \n"     \
2421         "       .set dsp                                        \n"     \
2422         "       mtlo %0, $ac1                                   \n"     \
2423         "       .set pop                                        \n"     \
2424         :                                                               \
2425         : "r" (x));                                                     \
2426 })
2427
2428 #define mtlo2(x)                                                        \
2429 ({                                                                      \
2430         __asm__(                                                        \
2431         "       .set push                                       \n"     \
2432         "       .set dsp                                        \n"     \
2433         "       mtlo %0, $ac2                                   \n"     \
2434         "       .set pop                                        \n"     \
2435         :                                                               \
2436         : "r" (x));                                                     \
2437 })
2438
2439 #define mtlo3(x)                                                        \
2440 ({                                                                      \
2441         __asm__(                                                        \
2442         "       .set push                                       \n"     \
2443         "       .set dsp                                        \n"     \
2444         "       mtlo %0, $ac3                                   \n"     \
2445         "       .set pop                                        \n"     \
2446         :                                                               \
2447         : "r" (x));                                                     \
2448 })
2449
2450 #define mthi0(x)                                                        \
2451 ({                                                                      \
2452         __asm__(                                                        \
2453         "       .set push                                       \n"     \
2454         "       .set dsp                                        \n"     \
2455         "       mthi %0, $ac0                                   \n"     \
2456         "       .set pop                                        \n"     \
2457         :                                                               \
2458         : "r" (x));                                                     \
2459 })
2460
2461 #define mthi1(x)                                                        \
2462 ({                                                                      \
2463         __asm__(                                                        \
2464         "       .set push                                       \n"     \
2465         "       .set dsp                                        \n"     \
2466         "       mthi %0, $ac1                                   \n"     \
2467         "       .set pop                                        \n"     \
2468         :                                                               \
2469         : "r" (x));                                                     \
2470 })
2471
2472 #define mthi2(x)                                                        \
2473 ({                                                                      \
2474         __asm__(                                                        \
2475         "       .set push                                       \n"     \
2476         "       .set dsp                                        \n"     \
2477         "       mthi %0, $ac2                                   \n"     \
2478         "       .set pop                                        \n"     \
2479         :                                                               \
2480         : "r" (x));                                                     \
2481 })
2482
2483 #define mthi3(x)                                                        \
2484 ({                                                                      \
2485         __asm__(                                                        \
2486         "       .set push                                       \n"     \
2487         "       .set dsp                                        \n"     \
2488         "       mthi %0, $ac3                                   \n"     \
2489         "       .set pop                                        \n"     \
2490         :                                                               \
2491         : "r" (x));                                                     \
2492 })
2493
2494 #else
2495
2496 #define rddsp(mask)                                                     \
2497 ({                                                                      \
2498         unsigned int __res;                                             \
2499                                                                         \
2500         __asm__ __volatile__(                                           \
2501         "       .set    push                                    \n"     \
2502         "       .set    noat                                    \n"     \
2503         "       # rddsp $1, %x1                                 \n"     \
2504         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2505         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2506         "       move    %0, $1                                  \n"     \
2507         "       .set    pop                                     \n"     \
2508         : "=r" (__res)                                                  \
2509         : "i" (mask));                                                  \
2510         __res;                                                          \
2511 })
2512
2513 #define wrdsp(val, mask)                                                \
2514 do {                                                                    \
2515         __asm__ __volatile__(                                           \
2516         "       .set    push                                    \n"     \
2517         "       .set    noat                                    \n"     \
2518         "       move    $1, %0                                  \n"     \
2519         "       # wrdsp $1, %x1                                 \n"     \
2520         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2521         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2522         "       .set    pop                                     \n"     \
2523         :                                                               \
2524         : "r" (val), "i" (mask));                                       \
2525 } while (0)
2526
2527 #define _dsp_mfxxx(ins)                                                 \
2528 ({                                                                      \
2529         unsigned long __treg;                                           \
2530                                                                         \
2531         __asm__ __volatile__(                                           \
2532         "       .set    push                                    \n"     \
2533         "       .set    noat                                    \n"     \
2534         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2535         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2536         "       move    %0, $1                                  \n"     \
2537         "       .set    pop                                     \n"     \
2538         : "=r" (__treg)                                                 \
2539         : "i" (ins));                                                   \
2540         __treg;                                                         \
2541 })
2542
2543 #define _dsp_mtxxx(val, ins)                                            \
2544 do {                                                                    \
2545         __asm__ __volatile__(                                           \
2546         "       .set    push                                    \n"     \
2547         "       .set    noat                                    \n"     \
2548         "       move    $1, %0                                  \n"     \
2549         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2550         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2551         "       .set    pop                                     \n"     \
2552         :                                                               \
2553         : "r" (val), "i" (ins));                                        \
2554 } while (0)
2555
2556 #ifdef CONFIG_CPU_MICROMIPS
2557
2558 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2559 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2560
2561 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2562 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2563
2564 #else  /* !CONFIG_CPU_MICROMIPS */
2565
2566 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2567 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2568
2569 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2570 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2571
2572 #endif /* CONFIG_CPU_MICROMIPS */
2573
2574 #define mflo0() _dsp_mflo(0)
2575 #define mflo1() _dsp_mflo(1)
2576 #define mflo2() _dsp_mflo(2)
2577 #define mflo3() _dsp_mflo(3)
2578
2579 #define mfhi0() _dsp_mfhi(0)
2580 #define mfhi1() _dsp_mfhi(1)
2581 #define mfhi2() _dsp_mfhi(2)
2582 #define mfhi3() _dsp_mfhi(3)
2583
2584 #define mtlo0(x) _dsp_mtlo(x, 0)
2585 #define mtlo1(x) _dsp_mtlo(x, 1)
2586 #define mtlo2(x) _dsp_mtlo(x, 2)
2587 #define mtlo3(x) _dsp_mtlo(x, 3)
2588
2589 #define mthi0(x) _dsp_mthi(x, 0)
2590 #define mthi1(x) _dsp_mthi(x, 1)
2591 #define mthi2(x) _dsp_mthi(x, 2)
2592 #define mthi3(x) _dsp_mthi(x, 3)
2593
2594 #endif
2595
2596 /*
2597  * TLB operations.
2598  *
2599  * It is responsibility of the caller to take care of any TLB hazards.
2600  */
2601 static inline void tlb_probe(void)
2602 {
2603         __asm__ __volatile__(
2604                 ".set noreorder\n\t"
2605                 "tlbp\n\t"
2606                 ".set reorder");
2607 }
2608
2609 static inline void tlb_read(void)
2610 {
2611 #if MIPS34K_MISSED_ITLB_WAR
2612         int res = 0;
2613
2614         __asm__ __volatile__(
2615         "       .set    push                                    \n"
2616         "       .set    noreorder                               \n"
2617         "       .set    noat                                    \n"
2618         "       .set    mips32r2                                \n"
2619         "       .word   0x41610001              # dvpe $1       \n"
2620         "       move    %0, $1                                  \n"
2621         "       ehb                                             \n"
2622         "       .set    pop                                     \n"
2623         : "=r" (res));
2624
2625         instruction_hazard();
2626 #endif
2627
2628         __asm__ __volatile__(
2629                 ".set noreorder\n\t"
2630                 "tlbr\n\t"
2631                 ".set reorder");
2632
2633 #if MIPS34K_MISSED_ITLB_WAR
2634         if ((res & _ULCAST_(1)))
2635                 __asm__ __volatile__(
2636                 "       .set    push                            \n"
2637                 "       .set    noreorder                       \n"
2638                 "       .set    noat                            \n"
2639                 "       .set    mips32r2                        \n"
2640                 "       .word   0x41600021      # evpe          \n"
2641                 "       ehb                                     \n"
2642                 "       .set    pop                             \n");
2643 #endif
2644 }
2645
2646 static inline void tlb_write_indexed(void)
2647 {
2648         __asm__ __volatile__(
2649                 ".set noreorder\n\t"
2650                 "tlbwi\n\t"
2651                 ".set reorder");
2652 }
2653
2654 static inline void tlb_write_random(void)
2655 {
2656         __asm__ __volatile__(
2657                 ".set noreorder\n\t"
2658                 "tlbwr\n\t"
2659                 ".set reorder");
2660 }
2661
2662 /*
2663  * Guest TLB operations.
2664  *
2665  * It is responsibility of the caller to take care of any TLB hazards.
2666  */
2667 static inline void guest_tlb_probe(void)
2668 {
2669         __asm__ __volatile__(
2670                 ".set push\n\t"
2671                 ".set noreorder\n\t"
2672                 _ASM_SET_VIRT
2673                 "tlbgp\n\t"
2674                 ".set pop");
2675 }
2676
2677 static inline void guest_tlb_read(void)
2678 {
2679         __asm__ __volatile__(
2680                 ".set push\n\t"
2681                 ".set noreorder\n\t"
2682                 _ASM_SET_VIRT
2683                 "tlbgr\n\t"
2684                 ".set pop");
2685 }
2686
2687 static inline void guest_tlb_write_indexed(void)
2688 {
2689         __asm__ __volatile__(
2690                 ".set push\n\t"
2691                 ".set noreorder\n\t"
2692                 _ASM_SET_VIRT
2693                 "tlbgwi\n\t"
2694                 ".set pop");
2695 }
2696
2697 static inline void guest_tlb_write_random(void)
2698 {
2699         __asm__ __volatile__(
2700                 ".set push\n\t"
2701                 ".set noreorder\n\t"
2702                 _ASM_SET_VIRT
2703                 "tlbgwr\n\t"
2704                 ".set pop");
2705 }
2706
2707 /*
2708  * Guest TLB Invalidate Flush
2709  */
2710 static inline void guest_tlbinvf(void)
2711 {
2712         __asm__ __volatile__(
2713                 ".set push\n\t"
2714                 ".set noreorder\n\t"
2715                 _ASM_SET_VIRT
2716                 "tlbginvf\n\t"
2717                 ".set pop");
2718 }
2719
2720 /*
2721  * Manipulate bits in a register.
2722  */
2723 #define __BUILD_SET_COMMON(name)                                \
2724 static inline unsigned int                                      \
2725 set_##name(unsigned int set)                                    \
2726 {                                                               \
2727         unsigned int res, new;                                  \
2728                                                                 \
2729         res = read_##name();                                    \
2730         new = res | set;                                        \
2731         write_##name(new);                                      \
2732                                                                 \
2733         return res;                                             \
2734 }                                                               \
2735                                                                 \
2736 static inline unsigned int                                      \
2737 clear_##name(unsigned int clear)                                \
2738 {                                                               \
2739         unsigned int res, new;                                  \
2740                                                                 \
2741         res = read_##name();                                    \
2742         new = res & ~clear;                                     \
2743         write_##name(new);                                      \
2744                                                                 \
2745         return res;                                             \
2746 }                                                               \
2747                                                                 \
2748 static inline unsigned int                                      \
2749 change_##name(unsigned int change, unsigned int val)            \
2750 {                                                               \
2751         unsigned int res, new;                                  \
2752                                                                 \
2753         res = read_##name();                                    \
2754         new = res & ~change;                                    \
2755         new |= (val & change);                                  \
2756         write_##name(new);                                      \
2757                                                                 \
2758         return res;                                             \
2759 }
2760
2761 /*
2762  * Manipulate bits in a c0 register.
2763  */
2764 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2765
2766 __BUILD_SET_C0(status)
2767 __BUILD_SET_C0(cause)
2768 __BUILD_SET_C0(config)
2769 __BUILD_SET_C0(config5)
2770 __BUILD_SET_C0(config7)
2771 __BUILD_SET_C0(intcontrol)
2772 __BUILD_SET_C0(intctl)
2773 __BUILD_SET_C0(srsmap)
2774 __BUILD_SET_C0(pagegrain)
2775 __BUILD_SET_C0(guestctl0)
2776 __BUILD_SET_C0(guestctl0ext)
2777 __BUILD_SET_C0(guestctl1)
2778 __BUILD_SET_C0(guestctl2)
2779 __BUILD_SET_C0(guestctl3)
2780 __BUILD_SET_C0(brcm_config_0)
2781 __BUILD_SET_C0(brcm_bus_pll)
2782 __BUILD_SET_C0(brcm_reset)
2783 __BUILD_SET_C0(brcm_cmt_intr)
2784 __BUILD_SET_C0(brcm_cmt_ctrl)
2785 __BUILD_SET_C0(brcm_config)
2786 __BUILD_SET_C0(brcm_mode)
2787
2788 /*
2789  * Manipulate bits in a guest c0 register.
2790  */
2791 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2792
2793 __BUILD_SET_GC0(wired)
2794 __BUILD_SET_GC0(status)
2795 __BUILD_SET_GC0(cause)
2796 __BUILD_SET_GC0(ebase)
2797 __BUILD_SET_GC0(config1)
2798
2799 /*
2800  * Return low 10 bits of ebase.
2801  * Note that under KVM (MIPSVZ) this returns vcpu id.
2802  */
2803 static inline unsigned int get_ebase_cpunum(void)
2804 {
2805         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2806 }
2807
2808 #endif /* !__ASSEMBLY__ */
2809
2810 #endif /* _ASM_MIPSREGS_H */