arch/mips/include/asm/io.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  10  *      Author: Maciej W. Rozycki <macro@mips.com>
  11  */
  12 #ifndef _ASM_IO_H
  13 #define _ASM_IO_H
  14
  15 #define ARCH_HAS_IOREMAP_WC
  16
  17 #include <linux/compiler.h>
  18 #include <linux/kernel.h>
  19 #include <linux/types.h>
  20 #include <linux/irqflags.h>
  21
  22 #include <asm/addrspace.h>
  23 #include <asm/barrier.h>
  24 #include <asm/bug.h>
  25 #include <asm/byteorder.h>
  26 #include <asm/cpu.h>
  27 #include <asm/cpu-features.h>
  28 #include <asm-generic/iomap.h>
  29 #include <asm/page.h>
  30 #include <asm/pgtable-bits.h>
  31 #include <asm/processor.h>
  32 #include <asm/string.h>
  33
  34 #include <ioremap.h>
  35 #include <mangle-port.h>
  36
  37 /*
  38  * Raw operations are never swapped in software.  OTOH values that raw
  39  * operations are working on may or may not have been swapped by the bus
  40  * hardware.  An example use would be for flash memory that's used for
  41  * execute in place.
  42  */
  43 # define __raw_ioswabb(a, x)    (x)
  44 # define __raw_ioswabw(a, x)    (x)
  45 # define __raw_ioswabl(a, x)    (x)
  46 # define __raw_ioswabq(a, x)    (x)
  47 # define ____raw_ioswabq(a, x)  (x)
  48
  49 # define __relaxed_ioswabb ioswabb
  50 # define __relaxed_ioswabw ioswabw
  51 # define __relaxed_ioswabl ioswabl
  52 # define __relaxed_ioswabq ioswabq
  53
  54 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
  55
  56 #define IO_SPACE_LIMIT 0xffff
  57
  58 /*
  59  * On MIPS I/O ports are memory mapped, so we access them using normal
  60  * load/store instructions. mips_io_port_base is the virtual address to
  61  * which all ports are being mapped.  For sake of efficiency some code
  62  * assumes that this is an address that can be loaded with a single lui
  63  * instruction, so the lower 16 bits must be zero.  Should be true on
  64  * on any sane architecture; generic code does not use this assumption.
  65  */
  66 extern const unsigned long mips_io_port_base;
  67
  68 /*
  69  * Gcc will generate code to load the value of mips_io_port_base after each
  70  * function call which may be fairly wasteful in some cases.  So we don't
  71  * play quite by the book.  We tell gcc mips_io_port_base is a long variable
  72  * which solves the code generation issue.  Now we need to violate the
  73  * aliasing rules a little to make initialization possible and finally we
  74  * will need the barrier() to fight side effects of the aliasing chat.
  75  * This trickery will eventually collapse under gcc's optimizer.  Oh well.
  76  */
  77 static inline void set_io_port_base(unsigned long base)
  78 {
  79         * (unsigned long *) &mips_io_port_base = base;
  80         barrier();
  81 }
  82
  83 /*
  84  * Provide the necessary definitions for generic iomap. We make use of
  85  * mips_io_port_base for iomap(), but we don't reserve any low addresses for
  86  * use with I/O ports.
  87  */
  88
  89 #define HAVE_ARCH_PIO_SIZE
  90 #define PIO_OFFSET      mips_io_port_base
  91 #define PIO_MASK        IO_SPACE_LIMIT
  92 #define PIO_RESERVED    0x0UL
  93
  94 /*
  95  * Enforce in-order execution of data I/O.  In the MIPS architecture
  96  * these are equivalent to corresponding platform-specific memory
  97  * barriers defined in <asm/barrier.h>.  API pinched from PowerPC,
  98  * with sync additionally defined.
  99  */
 100 #define iobarrier_rw() mb()
 101 #define iobarrier_r() rmb()
 102 #define iobarrier_w() wmb()
 103 #define iobarrier_sync() iob()
 104
 105 /* Some callers use this older API instead.  */
 106 #define mmiowb() iobarrier_w()
 107
 108 /*
 109  *     virt_to_phys    -       map virtual addresses to physical
 110  *     @address: address to remap
 111  *
 112  *     The returned physical address is the physical (CPU) mapping for
 113  *     the memory address given. It is only valid to use this function on
 114  *     addresses directly mapped or allocated via kmalloc.
 115  *
 116  *     This function does not give bus mappings for DMA transfers. In
 117  *     almost all conceivable cases a device driver should not be using
 118  *     this function
 119  */
 120 static inline unsigned long virt_to_phys(volatile const void *address)
 121 {
 122         return __pa(address);
 123 }
 124
 125 /*
 126  *     phys_to_virt    -       map physical address to virtual
 127  *     @address: address to remap
 128  *
 129  *     The returned virtual address is a current CPU mapping for
 130  *     the memory address given. It is only valid to use this function on
 131  *     addresses that have a kernel mapping
 132  *
 133  *     This function does not handle bus mappings for DMA transfers. In
 134  *     almost all conceivable cases a device driver should not be using
 135  *     this function
 136  */
 137 static inline void * phys_to_virt(unsigned long address)
 138 {
 139         return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
 140 }
 141
 142 /*
 143  * ISA I/O bus memory addresses are 1:1 with the physical address.
 144  */
 145 static inline unsigned long isa_virt_to_bus(volatile void *address)
 146 {
 147         return virt_to_phys(address);
 148 }
 149
 150 static inline void *isa_bus_to_virt(unsigned long address)
 151 {
 152         return phys_to_virt(address);
 153 }
 154
 155 #define isa_page_to_bus page_to_phys
 156
 157 /*
 158  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 159  * are forbidden in portable PCI drivers.
 160  *
 161  * Allow them for x86 for legacy drivers, though.
 162  */
 163 #define virt_to_bus virt_to_phys
 164 #define bus_to_virt phys_to_virt
 165
 166 /*
 167  * Change "struct page" to physical address.
 168  */
 169 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 170
 171 extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
 172 extern void __iounmap(const volatile void __iomem *addr);
 173
 174 static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
 175         unsigned long flags)
 176 {
 177         void __iomem *addr = plat_ioremap(offset, size, flags);
 178
 179         if (addr)
 180                 return addr;
 181
 182 #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
 183
 184         if (cpu_has_64bit_addresses) {
 185                 u64 base = UNCAC_BASE;
 186
 187                 /*
 188                  * R10000 supports a 2 bit uncached attribute therefore
 189                  * UNCAC_BASE may not equal IO_BASE.
 190                  */
 191                 if (flags == _CACHE_UNCACHED)
 192                         base = (u64) IO_BASE;
 193                 return (void __iomem *) (unsigned long) (base + offset);
 194         } else if (__builtin_constant_p(offset) &&
 195                    __builtin_constant_p(size) && __builtin_constant_p(flags)) {
 196                 phys_addr_t phys_addr, last_addr;
 197
 198                 phys_addr = fixup_bigphys_addr(offset, size);
 199
 200                 /* Don't allow wraparound or zero size. */
 201                 last_addr = phys_addr + size - 1;
 202                 if (!size || last_addr < phys_addr)
 203                         return NULL;
 204
 205                 /*
 206                  * Map uncached objects in the low 512MB of address
 207                  * space using KSEG1.
 208                  */
 209                 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
 210                     flags == _CACHE_UNCACHED)
 211                         return (void __iomem *)
 212                                 (unsigned long)CKSEG1ADDR(phys_addr);
 213         }
 214
 215         return __ioremap(offset, size, flags);
 216
 217 #undef __IS_LOW512
 218 }
 219
 220 /*
 221  * ioremap     -   map bus memory into CPU space
 222  * @offset:    bus address of the memory
 223  * @size:      size of the resource to map
 224  *
 225  * ioremap performs a platform specific sequence of operations to
 226  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 227  * writew/writel functions and the other mmio helpers. The returned
 228  * address is not guaranteed to be usable directly as a virtual
 229  * address.
 230  */
 231 #define ioremap(offset, size)                                           \
 232         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 233
 234 /*
 235  * ioremap_nocache     -   map bus memory into CPU space
 236  * @offset:    bus address of the memory
 237  * @size:      size of the resource to map
 238  *
 239  * ioremap_nocache performs a platform specific sequence of operations to
 240  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 241  * writew/writel functions and the other mmio helpers. The returned
 242  * address is not guaranteed to be usable directly as a virtual
 243  * address.
 244  *
 245  * This version of ioremap ensures that the memory is marked uncachable
 246  * on the CPU as well as honouring existing caching rules from things like
 247  * the PCI bus. Note that there are other caches and buffers on many
 248  * busses. In particular driver authors should read up on PCI writes
 249  *
 250  * It's useful if some control registers are in such an area and
 251  * write combining or read caching is not desirable:
 252  */
 253 #define ioremap_nocache(offset, size)                                   \
 254         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 255 #define ioremap_uc ioremap_nocache
 256
 257 /*
 258  * ioremap_cachable -   map bus memory into CPU space
 259  * @offset:         bus address of the memory
 260  * @size:           size of the resource to map
 261  *
 262  * ioremap_nocache performs a platform specific sequence of operations to
 263  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 264  * writew/writel functions and the other mmio helpers. The returned
 265  * address is not guaranteed to be usable directly as a virtual
 266  * address.
 267  *
 268  * This version of ioremap ensures that the memory is marked cachable by
 269  * the CPU.  Also enables full write-combining.  Useful for some
 270  * memory-like regions on I/O busses.
 271  */
 272 #define ioremap_cachable(offset, size)                                  \
 273         __ioremap_mode((offset), (size), _page_cachable_default)
 274 #define ioremap_cache ioremap_cachable
 275
 276 /*
 277  * ioremap_wc     -   map bus memory into CPU space
 278  * @offset:    bus address of the memory
 279  * @size:      size of the resource to map
 280  *
 281  * ioremap_wc performs a platform specific sequence of operations to
 282  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 283  * writew/writel functions and the other mmio helpers. The returned
 284  * address is not guaranteed to be usable directly as a virtual
 285  * address.
 286  *
 287  * This version of ioremap ensures that the memory is marked uncachable
 288  * but accelerated by means of write-combining feature. It is specifically
 289  * useful for PCIe prefetchable windows, which may vastly improve a
 290  * communications performance. If it was determined on boot stage, what
 291  * CPU CCA doesn't support UCA, the method shall fall-back to the
 292  * _CACHE_UNCACHED option (see cpu_probe() method).
 293  */
 294 #define ioremap_wc(offset, size)                                        \
 295         __ioremap_mode((offset), (size), boot_cpu_data.writecombine)
 296
 297 static inline void iounmap(const volatile void __iomem *addr)
 298 {
 299         if (plat_iounmap(addr))
 300                 return;
 301
 302 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
 303
 304         if (cpu_has_64bit_addresses ||
 305             (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
 306                 return;
 307
 308         __iounmap(addr);
 309
 310 #undef __IS_KSEG1
 311 }
 312
 313 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
 314 #define war_io_reorder_wmb()            wmb()
 315 #else
 316 #define war_io_reorder_wmb()            barrier()
 317 #endif
 318
 319 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq)     \
 320                                                                         \
 321 static inline void pfx##write##bwlq(type val,                           \
 322                                     volatile void __iomem *mem)         \
 323 {                                                                       \
 324         volatile type *__mem;                                           \
 325         type __val;                                                     \
 326                                                                         \
 327         if (barrier)                                                    \
 328                 iobarrier_rw();                                         \
 329         else                                                            \
 330                 war_io_reorder_wmb();                                   \
 331                                                                         \
 332         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 333                                                                         \
 334         __val = pfx##ioswab##bwlq(__mem, val);                          \
 335                                                                         \
 336         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 337                 *__mem = __val;                                         \
 338         else if (cpu_has_64bits) {                                      \
 339                 unsigned long __flags;                                  \
 340                 type __tmp;                                             \
 341                                                                         \
 342                 if (irq)                                                \
 343                         local_irq_save(__flags);                        \
 344                 __asm__ __volatile__(                                   \
 345                         ".set   arch=r4000"     "\t\t# __writeq""\n\t"  \
 346                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
 347                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
 348                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
 349                         "or     %L0, %L0, %M0"                  "\n\t"  \
 350                         "sd     %L0, %2"                        "\n\t"  \
 351                         ".set   mips0"                          "\n"    \
 352                         : "=r" (__tmp)                                  \
 353                         : "0" (__val), "m" (*__mem));                   \
 354                 if (irq)                                                \
 355                         local_irq_restore(__flags);                     \
 356         } else                                                          \
 357                 BUG();                                                  \
 358 }                                                                       \
 359                                                                         \
 360 static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
 361 {                                                                       \
 362         volatile type *__mem;                                           \
 363         type __val;                                                     \
 364                                                                         \
 365         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 366                                                                         \
 367         if (barrier)                                                    \
 368                 iobarrier_rw();                                         \
 369                                                                         \
 370         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 371                 __val = *__mem;                                         \
 372         else if (cpu_has_64bits) {                                      \
 373                 unsigned long __flags;                                  \
 374                                                                         \
 375                 if (irq)                                                \
 376                         local_irq_save(__flags);                        \
 377                 __asm__ __volatile__(                                   \
 378                         ".set   arch=r4000"     "\t\t# __readq" "\n\t"  \
 379                         "ld     %L0, %1"                        "\n\t"  \
 380                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
 381                         "sll    %L0, %L0, 0"                    "\n\t"  \
 382                         ".set   mips0"                          "\n"    \
 383                         : "=r" (__val)                                  \
 384                         : "m" (*__mem));                                \
 385                 if (irq)                                                \
 386                         local_irq_restore(__flags);                     \
 387         } else {                                                        \
 388                 __val = 0;                                              \
 389                 BUG();                                                  \
 390         }                                                               \
 391                                                                         \
 392         /* prevent prefetching of coherent DMA data prematurely */      \
 393         if (!relax)                                                     \
 394                 rmb();                                                  \
 395         return pfx##ioswab##bwlq(__mem, __val);                         \
 396 }
 397
 398 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p)       \
 399                                                                         \
 400 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 401 {                                                                       \
 402         volatile type *__addr;                                          \
 403         type __val;                                                     \
 404                                                                         \
 405         if (barrier)                                                    \
 406                 iobarrier_rw();                                         \
 407         else                                                            \
 408                 war_io_reorder_wmb();                                   \
 409                                                                         \
 410         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 411                                                                         \
 412         __val = pfx##ioswab##bwlq(__addr, val);                         \
 413                                                                         \
 414         /* Really, we want this to be atomic */                         \
 415         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 416                                                                         \
 417         *__addr = __val;                                                \
 418 }                                                                       \
 419                                                                         \
 420 static inline type pfx##in##bwlq##p(unsigned long port)                 \
 421 {                                                                       \
 422         volatile type *__addr;                                          \
 423         type __val;                                                     \
 424                                                                         \
 425         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 426                                                                         \
 427         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 428                                                                         \
 429         if (barrier)                                                    \
 430                 iobarrier_rw();                                         \
 431                                                                         \
 432         __val = *__addr;                                                \
 433                                                                         \
 434         /* prevent prefetching of coherent DMA data prematurely */      \
 435         if (!relax)                                                     \
 436                 rmb();                                                  \
 437         return pfx##ioswab##bwlq(__addr, __val);                        \
 438 }
 439
 440 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax)                      \
 441                                                                         \
 442 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
 443
 444 #define BUILDIO_MEM(bwlq, type)                                         \
 445                                                                         \
 446 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0)                               \
 447 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1)                           \
 448 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0)                               \
 449 __BUILD_MEMORY_PFX(, bwlq, type, 0)
 450
 451 BUILDIO_MEM(b, u8)
 452 BUILDIO_MEM(w, u16)
 453 BUILDIO_MEM(l, u32)
 454 BUILDIO_MEM(q, u64)
 455
 456 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 457         __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,)                   \
 458         __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
 459
 460 #define BUILDIO_IOPORT(bwlq, type)                                      \
 461         __BUILD_IOPORT_PFX(, bwlq, type)                                \
 462         __BUILD_IOPORT_PFX(__mem_, bwlq, type)
 463
 464 BUILDIO_IOPORT(b, u8)
 465 BUILDIO_IOPORT(w, u16)
 466 BUILDIO_IOPORT(l, u32)
 467 #ifdef CONFIG_64BIT
 468 BUILDIO_IOPORT(q, u64)
 469 #endif
 470
 471 #define __BUILDIO(bwlq, type)                                           \
 472                                                                         \
 473 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
 474
 475 __BUILDIO(q, u64)
 476
 477 #define readb_relaxed                   __relaxed_readb
 478 #define readw_relaxed                   __relaxed_readw
 479 #define readl_relaxed                   __relaxed_readl
 480 #define readq_relaxed                   __relaxed_readq
 481
 482 #define writeb_relaxed                  __relaxed_writeb
 483 #define writew_relaxed                  __relaxed_writew
 484 #define writel_relaxed                  __relaxed_writel
 485 #define writeq_relaxed                  __relaxed_writeq
 486
 487 #define readb_be(addr)                                                  \
 488         __raw_readb((__force unsigned *)(addr))
 489 #define readw_be(addr)                                                  \
 490         be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
 491 #define readl_be(addr)                                                  \
 492         be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
 493 #define readq_be(addr)                                                  \
 494         be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
 495
 496 #define writeb_be(val, addr)                                            \
 497         __raw_writeb((val), (__force unsigned *)(addr))
 498 #define writew_be(val, addr)                                            \
 499         __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
 500 #define writel_be(val, addr)                                            \
 501         __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
 502 #define writeq_be(val, addr)                                            \
 503         __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
 504
 505 /*
 506  * Some code tests for these symbols
 507  */
 508 #define readq                           readq
 509 #define writeq                          writeq
 510
 511 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
 512                                                                         \
 513 static inline void writes##bwlq(volatile void __iomem *mem,             \
 514                                 const void *addr, unsigned int count)   \
 515 {                                                                       \
 516         const volatile type *__addr = addr;                             \
 517                                                                         \
 518         while (count--) {                                               \
 519                 __mem_write##bwlq(*__addr, mem);                        \
 520                 __addr++;                                               \
 521         }                                                               \
 522 }                                                                       \
 523                                                                         \
 524 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
 525                                unsigned int count)                      \
 526 {                                                                       \
 527         volatile type *__addr = addr;                                   \
 528                                                                         \
 529         while (count--) {                                               \
 530                 *__addr = __mem_read##bwlq(mem);                        \
 531                 __addr++;                                               \
 532         }                                                               \
 533 }
 534
 535 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
 536                                                                         \
 537 static inline void outs##bwlq(unsigned long port, const void *addr,     \
 538                               unsigned int count)                       \
 539 {                                                                       \
 540         const volatile type *__addr = addr;                             \
 541                                                                         \
 542         while (count--) {                                               \
 543                 __mem_out##bwlq(*__addr, port);                         \
 544                 __addr++;                                               \
 545         }                                                               \
 546 }                                                                       \
 547                                                                         \
 548 static inline void ins##bwlq(unsigned long port, void *addr,            \
 549                              unsigned int count)                        \
 550 {                                                                       \
 551         volatile type *__addr = addr;                                   \
 552                                                                         \
 553         while (count--) {                                               \
 554                 *__addr = __mem_in##bwlq(port);                         \
 555                 __addr++;                                               \
 556         }                                                               \
 557 }
 558
 559 #define BUILDSTRING(bwlq, type)                                         \
 560                                                                         \
 561 __BUILD_MEMORY_STRING(bwlq, type)                                       \
 562 __BUILD_IOPORT_STRING(bwlq, type)
 563
 564 BUILDSTRING(b, u8)
 565 BUILDSTRING(w, u16)
 566 BUILDSTRING(l, u32)
 567 #ifdef CONFIG_64BIT
 568 BUILDSTRING(q, u64)
 569 #endif
 570
 571 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 572 {
 573         memset((void __force *) addr, val, count);
 574 }
 575 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
 576 {
 577         memcpy(dst, (void __force *) src, count);
 578 }
 579 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 580 {
 581         memcpy((void __force *) dst, src, count);
 582 }
 583
 584 /*
 585  * The caches on some architectures aren't dma-coherent and have need to
 586  * handle this in software.  There are three types of operations that
 587  * can be applied to dma buffers.
 588  *
 589  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 590  *    writing the content of the caches back to memory, if necessary.
 591  *    The function also invalidates the affected part of the caches as
 592  *    necessary before DMA transfers from outside to memory.
 593  *  - dma_cache_wback(start, size) makes caches and coherent by
 594  *    writing the content of the caches back to memory, if necessary.
 595  *    The function also invalidates the affected part of the caches as
 596  *    necessary before DMA transfers from outside to memory.
 597  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 598  *    caches.  Dirty lines of the caches may be written back or simply
 599  *    be discarded.  This operation is necessary before dma operations
 600  *    to the memory.
 601  *
 602  * This API used to be exported; it now is for arch code internal use only.
 603  */
 604 #ifdef CONFIG_DMA_NONCOHERENT
 605
 606 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 607 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 608 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 609
 610 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start, size)
 611 #define dma_cache_wback(start, size)            _dma_cache_wback(start, size)
 612 #define dma_cache_inv(start, size)              _dma_cache_inv(start, size)
 613
 614 #else /* Sane hardware */
 615
 616 #define dma_cache_wback_inv(start,size) \
 617         do { (void) (start); (void) (size); } while (0)
 618 #define dma_cache_wback(start,size)     \
 619         do { (void) (start); (void) (size); } while (0)
 620 #define dma_cache_inv(start,size)       \
 621         do { (void) (start); (void) (size); } while (0)
 622
 623 #endif /* CONFIG_DMA_NONCOHERENT */
 624
 625 /*
 626  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 627  * Avoid interrupt mucking, just adjust the address for 4-byte access.
 628  * Assume the addresses are 8-byte aligned.
 629  */
 630 #ifdef __MIPSEB__
 631 #define __CSR_32_ADJUST 4
 632 #else
 633 #define __CSR_32_ADJUST 0
 634 #endif
 635
 636 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 637 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 638
 639 /*
 640  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 641  * access
 642  */
 643 #define xlate_dev_mem_ptr(p)    __va(p)
 644
 645 /*
 646  * Convert a virtual cached pointer to an uncached pointer
 647  */
 648 #define xlate_dev_kmem_ptr(p)   p
 649
 650 void __ioread64_copy(void *to, const void __iomem *from, size_t count);
 651
 652 #endif /* _ASM_IO_H */