1 #ifndef __ARCH_M68K_ATOMIC__
2 #define __ARCH_M68K_ATOMIC__
4 #include <linux/types.h>
5 #include <linux/irqflags.h>
6 #include <asm/cmpxchg.h>
7 #include <asm/barrier.h>
10 * Atomic operations that C can't guarantee us. Useful for
11 * resource counting etc..
15 * We do not have SMP m68k systems, so we don't have to deal with that.
18 #define ATOMIC_INIT(i) { (i) }
20 #define atomic_read(v) (*(volatile int *)&(v)->counter)
21 #define atomic_set(v, i) (((v)->counter) = i)
24 * The ColdFire parts cannot do some immediate to memory operations,
25 * so for them we do not specify the "i" asm constraint.
27 #ifdef CONFIG_COLDFIRE
33 static inline void atomic_add(int i, atomic_t *v)
35 __asm__ __volatile__("addl %1,%0" : "+m" (*v) : ASM_DI (i));
38 static inline void atomic_sub(int i, atomic_t *v)
40 __asm__ __volatile__("subl %1,%0" : "+m" (*v) : ASM_DI (i));
43 static inline void atomic_inc(atomic_t *v)
45 __asm__ __volatile__("addql #1,%0" : "+m" (*v));
48 static inline void atomic_dec(atomic_t *v)
50 __asm__ __volatile__("subql #1,%0" : "+m" (*v));
53 static inline int atomic_dec_and_test(atomic_t *v)
56 __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
60 static inline int atomic_dec_and_test_lt(atomic_t *v)
70 static inline int atomic_inc_and_test(atomic_t *v)
73 __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
77 #ifdef CONFIG_RMW_INSNS
79 static inline int atomic_add_return(int i, atomic_t *v)
88 : "+m" (*v), "=&d" (t), "=&d" (tmp)
89 : "g" (i), "2" (atomic_read(v)));
93 static inline int atomic_sub_return(int i, atomic_t *v)
102 : "+m" (*v), "=&d" (t), "=&d" (tmp)
103 : "g" (i), "2" (atomic_read(v)));
107 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
108 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
110 #else /* !CONFIG_RMW_INSNS */
112 static inline int atomic_add_return(int i, atomic_t * v)
117 local_irq_save(flags);
121 local_irq_restore(flags);
126 static inline int atomic_sub_return(int i, atomic_t * v)
131 local_irq_save(flags);
135 local_irq_restore(flags);
140 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
145 local_irq_save(flags);
146 prev = atomic_read(v);
149 local_irq_restore(flags);
153 static inline int atomic_xchg(atomic_t *v, int new)
158 local_irq_save(flags);
159 prev = atomic_read(v);
161 local_irq_restore(flags);
165 #endif /* !CONFIG_RMW_INSNS */
167 #define atomic_dec_return(v) atomic_sub_return(1, (v))
168 #define atomic_inc_return(v) atomic_add_return(1, (v))
170 static inline int atomic_sub_and_test(int i, atomic_t *v)
173 __asm__ __volatile__("subl %2,%1; seq %0"
174 : "=d" (c), "+m" (*v)
179 static inline int atomic_add_negative(int i, atomic_t *v)
182 __asm__ __volatile__("addl %2,%1; smi %0"
183 : "=d" (c), "+m" (*v)
188 static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
190 __asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask)));
193 static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
195 __asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask));
198 static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
203 if (unlikely(c == (u)))
205 old = atomic_cmpxchg((v), c, c + (a));
206 if (likely(old == c))
213 #endif /* __ARCH_M68K_ATOMIC __ */