1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __ASM_CSKY_ENTRY_H
4 #define __ASM_CSKY_ENTRY_H
7 #include <abi/regdef.h>
23 .macro SAVE_ALL epc_inc
58 #ifdef CONFIG_CPU_HAS_HILO
81 #ifdef CONFIG_CPU_HAS_HILO
106 .macro SAVE_REGS_FTRACE
128 #ifdef CONFIG_CPU_HAS_HILO
139 .macro RESTORE_REGS_FTRACE
142 #ifdef CONFIG_CPU_HAS_HILO
163 .macro SAVE_SWITCH_STACK
174 #ifdef CONFIG_CPU_HAS_HILO
185 .macro RESTORE_SWITCH_STACK
186 #ifdef CONFIG_CPU_HAS_HILO
207 /* MMU registers operators. */
236 #ifdef CONFIG_PAGE_OFFSET_80000000
237 #define MSA_SET cr<30, 15>
238 #define MSA_CLR cr<31, 15>
241 #ifdef CONFIG_PAGE_OFFSET_A0000000
242 #define MSA_SET cr<31, 15>
243 #define MSA_CLR cr<30, 15>
247 /* Init psr and enable ee */
248 lrw r6, DEFAULT_PSR_VALUE
252 /* Invalid I/Dcache BTB BHT */
258 /* Invalid all TLB */
260 mtcr r6, cr<8, 15> /* Set MCIR */
262 /* Check MMU on/off */
267 /* MMU off: setup mapping tlb entry */
269 mtcr r6, cr<6, 15> /* Set MPR with 4K page size */
271 grs r6, 1f /* Get current pa by PC */
272 bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
274 mtcr r6, cr<4, 15> /* Set MEH */
279 mtcr r8, cr<2, 15> /* Set MEL0 */
282 mtcr r8, cr<3, 15> /* Set MEL1 */
285 mtcr r8, cr<8, 15> /* Set MCIR to write TLB */
290 * MMU on: use origin MSA value from bootloader
292 * cr<30/31, 15> MSA register format:
293 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
294 * BA Reserved SH WA B SO SEC C D V
296 mfcr r6, MSA_SET /* Get MSA */
301 mtcr r6, MSA_SET /* Set MSA */
304 mtcr r6, MSA_CLR /* Clr MSA */
311 jmpi 3f /* jump to va */
314 #endif /* __ASM_CSKY_ENTRY_H */