1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __bif_core_defs_h
3 #define __bif_core_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/bif/rtl/bif_core_regs.r
8 * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
9 * last modfied: Mon Apr 11 16:06:33 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
12 * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope bif_core */
88 /* Register rw_grp1_cfg, scope bif_core, type rw */
97 unsigned int wr_extend : 1;
98 unsigned int erc_en : 1;
99 unsigned int mode : 1;
100 unsigned int dummy1 : 10;
101 } reg_bif_core_rw_grp1_cfg;
102 #define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
103 #define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
105 /* Register rw_grp2_cfg, scope bif_core, type rw */
112 unsigned int ewb : 2;
114 unsigned int wr_extend : 1;
115 unsigned int erc_en : 1;
116 unsigned int mode : 1;
117 unsigned int dummy1 : 10;
118 } reg_bif_core_rw_grp2_cfg;
119 #define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
120 #define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
122 /* Register rw_grp3_cfg, scope bif_core, type rw */
129 unsigned int ewb : 2;
131 unsigned int wr_extend : 1;
132 unsigned int erc_en : 1;
133 unsigned int mode : 1;
134 unsigned int dummy1 : 2;
135 unsigned int gated_csp0 : 2;
136 unsigned int gated_csp1 : 2;
137 unsigned int gated_csp2 : 2;
138 unsigned int gated_csp3 : 2;
139 } reg_bif_core_rw_grp3_cfg;
140 #define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
141 #define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
143 /* Register rw_grp4_cfg, scope bif_core, type rw */
150 unsigned int ewb : 2;
152 unsigned int wr_extend : 1;
153 unsigned int erc_en : 1;
154 unsigned int mode : 1;
155 unsigned int dummy1 : 4;
156 unsigned int gated_csp4 : 2;
157 unsigned int gated_csp5 : 2;
158 unsigned int gated_csp6 : 2;
159 } reg_bif_core_rw_grp4_cfg;
160 #define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
161 #define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
163 /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
165 unsigned int bank_sel : 5;
167 unsigned int type : 1;
170 unsigned int wmm : 1;
171 unsigned int sh16 : 1;
172 unsigned int grp_sel : 5;
173 unsigned int dummy1 : 12;
174 } reg_bif_core_rw_sdram_cfg_grp0;
175 #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
176 #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
178 /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
180 unsigned int bank_sel : 5;
182 unsigned int type : 1;
185 unsigned int wmm : 1;
186 unsigned int sh16 : 1;
187 unsigned int dummy1 : 17;
188 } reg_bif_core_rw_sdram_cfg_grp1;
189 #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
190 #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
192 /* Register rw_sdram_timing, scope bif_core, type rw */
195 unsigned int rcd : 3;
198 unsigned int dpl : 2;
199 unsigned int pde : 1;
200 unsigned int ref : 2;
201 unsigned int cpd : 1;
202 unsigned int sdcke : 1;
203 unsigned int sdclk : 1;
204 unsigned int dummy1 : 13;
205 } reg_bif_core_rw_sdram_timing;
206 #define REG_RD_ADDR_bif_core_rw_sdram_timing 24
207 #define REG_WR_ADDR_bif_core_rw_sdram_timing 24
209 /* Register rw_sdram_cmd, scope bif_core, type rw */
211 unsigned int cmd : 3;
212 unsigned int mrs_data : 15;
213 unsigned int dummy1 : 14;
214 } reg_bif_core_rw_sdram_cmd;
215 #define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
216 #define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
218 /* Register rs_sdram_ref_stat, scope bif_core, type rs */
221 unsigned int dummy1 : 31;
222 } reg_bif_core_rs_sdram_ref_stat;
223 #define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
225 /* Register r_sdram_ref_stat, scope bif_core, type r */
228 unsigned int dummy1 : 31;
229 } reg_bif_core_r_sdram_ref_stat;
230 #define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
235 regk_bif_core_bank2 = 0x00000000,
236 regk_bif_core_bank4 = 0x00000001,
237 regk_bif_core_bit10 = 0x0000000a,
238 regk_bif_core_bit11 = 0x0000000b,
239 regk_bif_core_bit12 = 0x0000000c,
240 regk_bif_core_bit13 = 0x0000000d,
241 regk_bif_core_bit14 = 0x0000000e,
242 regk_bif_core_bit15 = 0x0000000f,
243 regk_bif_core_bit16 = 0x00000010,
244 regk_bif_core_bit17 = 0x00000011,
245 regk_bif_core_bit18 = 0x00000012,
246 regk_bif_core_bit19 = 0x00000013,
247 regk_bif_core_bit20 = 0x00000014,
248 regk_bif_core_bit21 = 0x00000015,
249 regk_bif_core_bit22 = 0x00000016,
250 regk_bif_core_bit23 = 0x00000017,
251 regk_bif_core_bit24 = 0x00000018,
252 regk_bif_core_bit25 = 0x00000019,
253 regk_bif_core_bit26 = 0x0000001a,
254 regk_bif_core_bit27 = 0x0000001b,
255 regk_bif_core_bit28 = 0x0000001c,
256 regk_bif_core_bit29 = 0x0000001d,
257 regk_bif_core_bit9 = 0x00000009,
258 regk_bif_core_bw16 = 0x00000001,
259 regk_bif_core_bw32 = 0x00000000,
260 regk_bif_core_bwe = 0x00000000,
261 regk_bif_core_cwe = 0x00000001,
262 regk_bif_core_e15us = 0x00000001,
263 regk_bif_core_e7800ns = 0x00000002,
264 regk_bif_core_grp0 = 0x00000000,
265 regk_bif_core_grp1 = 0x00000001,
266 regk_bif_core_mrs = 0x00000003,
267 regk_bif_core_no = 0x00000000,
268 regk_bif_core_none = 0x00000000,
269 regk_bif_core_nop = 0x00000000,
270 regk_bif_core_off = 0x00000000,
271 regk_bif_core_pre = 0x00000002,
272 regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
273 regk_bif_core_rd = 0x00000002,
274 regk_bif_core_ref = 0x00000001,
275 regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
276 regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
277 regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
278 regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
279 regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
280 regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
281 regk_bif_core_slf = 0x00000004,
282 regk_bif_core_wr = 0x00000001,
283 regk_bif_core_yes = 0x00000001
285 #endif /* __bif_core_defs_h */