arch/blackfin/kernel/setup.c

   1 /*
   2  * File:         arch/blackfin/kernel/setup.c
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/console.h>
  32 #include <linux/bootmem.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/cpu.h>
  35 #include <linux/module.h>
  36 #include <linux/tty.h>
  37
  38 #include <linux/ext2_fs.h>
  39 #include <linux/cramfs_fs.h>
  40 #include <linux/romfs_fs.h>
  41
  42 #include <asm/cacheflush.h>
  43 #include <asm/blackfin.h>
  44 #include <asm/cplbinit.h>
  45
  46 u16 _bfin_swrst;
  47
  48 unsigned long memory_start, memory_end, physical_mem_end;
  49 unsigned long reserved_mem_dcache_on;
  50 unsigned long reserved_mem_icache_on;
  51 EXPORT_SYMBOL(memory_start);
  52 EXPORT_SYMBOL(memory_end);
  53 EXPORT_SYMBOL(physical_mem_end);
  54 EXPORT_SYMBOL(_ramend);
  55
  56 #ifdef CONFIG_MTD_UCLINUX
  57 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
  58 unsigned long _ebss;
  59 EXPORT_SYMBOL(memory_mtd_end);
  60 EXPORT_SYMBOL(memory_mtd_start);
  61 EXPORT_SYMBOL(mtd_size);
  62 #endif
  63
  64 char command_line[COMMAND_LINE_SIZE];
  65
  66 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
  67 static void generate_cpl_tables(void);
  68 #endif
  69
  70 void __init bf53x_cache_init(void)
  71 {
  72 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
  73         generate_cpl_tables();
  74 #endif
  75
  76 #ifdef CONFIG_BLKFIN_CACHE
  77         bfin_icache_init();
  78         printk(KERN_INFO "Instruction Cache Enabled\n");
  79 #endif
  80
  81 #ifdef CONFIG_BLKFIN_DCACHE
  82         bfin_dcache_init();
  83         printk(KERN_INFO "Data Cache Enabled"
  84 # if defined CONFIG_BLKFIN_WB
  85                 " (write-back)"
  86 # elif defined CONFIG_BLKFIN_WT
  87                 " (write-through)"
  88 # endif
  89                 "\n");
  90 #endif
  91 }
  92
  93 void __init bf53x_relocate_l1_mem(void)
  94 {
  95         unsigned long l1_code_length;
  96         unsigned long l1_data_a_length;
  97         unsigned long l1_data_b_length;
  98
  99         l1_code_length = _etext_l1 - _stext_l1;
 100         if (l1_code_length > L1_CODE_LENGTH)
 101                 l1_code_length = L1_CODE_LENGTH;
 102         /* cannot complain as printk is not available as yet.
 103          * But we can continue booting and complain later!
 104          */
 105
 106         /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
 107         dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
 108
 109         l1_data_a_length = _ebss_l1 - _sdata_l1;
 110         if (l1_data_a_length > L1_DATA_A_LENGTH)
 111                 l1_data_a_length = L1_DATA_A_LENGTH;
 112
 113         /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
 114         dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
 115
 116         l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
 117         if (l1_data_b_length > L1_DATA_B_LENGTH)
 118                 l1_data_b_length = L1_DATA_B_LENGTH;
 119
 120         /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
 121         dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
 122                         l1_data_a_length, l1_data_b_length);
 123
 124 }
 125
 126 /*
 127  * Initial parsing of the command line.  Currently, we support:
 128  *  - Controlling the linux memory size: mem=xxx[KMG]
 129  *  - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
 130  *       $ -> reserved memory is dcacheable
 131  *       # -> reserved memory is icacheable
 132  */
 133 static __init void parse_cmdline_early(char *cmdline_p)
 134 {
 135         char c = ' ', *to = cmdline_p;
 136         unsigned int memsize;
 137         for (;;) {
 138                 if (c == ' ') {
 139
 140                         if (!memcmp(to, "mem=", 4)) {
 141                                 to += 4;
 142                                 memsize = memparse(to, &to);
 143                                 if (memsize)
 144                                         _ramend = memsize;
 145
 146                         } else if (!memcmp(to, "max_mem=", 8)) {
 147                                 to += 8;
 148                                 memsize = memparse(to, &to);
 149                                 if (memsize) {
 150                                         physical_mem_end = memsize;
 151                                         if (*to != ' ') {
 152                                                 if (*to == '$'
 153                                                     || *(to + 1) == '$')
 154                                                         reserved_mem_dcache_on =
 155                                                             1;
 156                                                 if (*to == '#'
 157                                                     || *(to + 1) == '#')
 158                                                         reserved_mem_icache_on =
 159                                                             1;
 160                                         }
 161                                 }
 162                         }
 163
 164                 }
 165                 c = *(to++);
 166                 if (!c)
 167                         break;
 168         }
 169 }
 170
 171 void __init setup_arch(char **cmdline_p)
 172 {
 173         int bootmap_size;
 174         unsigned long l1_length, sclk, cclk;
 175 #ifdef CONFIG_MTD_UCLINUX
 176         unsigned long mtd_phys = 0;
 177 #endif
 178
 179 #ifdef CONFIG_DUMMY_CONSOLE
 180         conswitchp = &dummy_con;
 181 #endif
 182         cclk = get_cclk();
 183         sclk = get_sclk();
 184
 185 #if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
 186         if (cclk == sclk)
 187                 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
 188 #endif
 189
 190 #if defined(ANOMALY_05000266)
 191         bfin_read_IMDMA_D0_IRQ_STATUS();
 192         bfin_read_IMDMA_D1_IRQ_STATUS();
 193 #endif
 194
 195 #ifdef DEBUG_SERIAL_EARLY_INIT
 196         bfin_console_init();    /* early console registration */
 197         /* this give a chance to get printk() working before crash. */
 198 #endif
 199
 200 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
 201         /* we need to initialize the Flashrom device here since we might
 202          * do things with flash early on in the boot
 203          */
 204         flash_probe();
 205 #endif
 206
 207 #if defined(CONFIG_CMDLINE_BOOL)
 208         memset(command_line, 0, sizeof(command_line));
 209         strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
 210         command_line[sizeof(command_line) - 1] = 0;
 211 #endif
 212
 213         /* Keep a copy of command line */
 214         *cmdline_p = &command_line[0];
 215         memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 216         boot_command_line[COMMAND_LINE_SIZE - 1] = 0;
 217
 218         /* setup memory defaults from the user config */
 219         physical_mem_end = 0;
 220         _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
 221
 222         parse_cmdline_early(&command_line[0]);
 223
 224         if (physical_mem_end == 0)
 225                 physical_mem_end = _ramend;
 226
 227         /* by now the stack is part of the init task */
 228         memory_end = _ramend - DMA_UNCACHED_REGION;
 229
 230         _ramstart = (unsigned long)__bss_stop;
 231         memory_start = PAGE_ALIGN(_ramstart);
 232
 233 #if defined(CONFIG_MTD_UCLINUX)
 234         /* generic memory mapped MTD driver */
 235         memory_mtd_end = memory_end;
 236
 237         mtd_phys = _ramstart;
 238         mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
 239
 240 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
 241         if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
 242                 mtd_size =
 243                     PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
 244 # endif
 245
 246 # if defined(CONFIG_CRAMFS)
 247         if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
 248                 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
 249 # endif
 250
 251 # if defined(CONFIG_ROMFS_FS)
 252         if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
 253             && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
 254                 mtd_size =
 255                     PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
 256 #  if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
 257         /* Due to a Hardware Anomaly we need to limit the size of usable
 258          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
 259          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
 260          */
 261 #   if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
 262         if (memory_end >= 56 * 1024 * 1024)
 263                 memory_end = 56 * 1024 * 1024;
 264 #   else
 265         if (memory_end >= 60 * 1024 * 1024)
 266                 memory_end = 60 * 1024 * 1024;
 267 #   endif                               /* CONFIG_DEBUG_HUNT_FOR_ZERO */
 268 #  endif                                /* ANOMALY_05000263 */
 269 # endif                         /* CONFIG_ROMFS_FS */
 270
 271         memory_end -= mtd_size;
 272
 273         if (mtd_size == 0) {
 274                 console_init();
 275                 panic("Don't boot kernel without rootfs attached.\n");
 276         }
 277
 278         /* Relocate MTD image to the top of memory after the uncached memory area */
 279         dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
 280
 281         memory_mtd_start = memory_end;
 282         _ebss = memory_mtd_start;       /* define _ebss for compatible */
 283 #endif                          /* CONFIG_MTD_UCLINUX */
 284
 285 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
 286         /* Due to a Hardware Anomaly we need to limit the size of usable
 287          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
 288          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
 289          */
 290 #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
 291         if (memory_end >= 56 * 1024 * 1024)
 292                 memory_end = 56 * 1024 * 1024;
 293 #else
 294         if (memory_end >= 60 * 1024 * 1024)
 295                 memory_end = 60 * 1024 * 1024;
 296 #endif                          /* CONFIG_DEBUG_HUNT_FOR_ZERO */
 297         printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
 298 #endif                          /* ANOMALY_05000263 */
 299
 300 #if !defined(CONFIG_MTD_UCLINUX)
 301         memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
 302 #endif
 303         init_mm.start_code = (unsigned long)_stext;
 304         init_mm.end_code = (unsigned long)_etext;
 305         init_mm.end_data = (unsigned long)_edata;
 306         init_mm.brk = (unsigned long)0;
 307
 308         init_leds();
 309
 310         printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
 311         printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
 312         if (bfin_revid() != bfin_compiled_revid())
 313                 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
 314                        bfin_compiled_revid(), bfin_revid());
 315         if (bfin_revid() < SUPPORTED_REVID)
 316                 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
 317                        CPU, bfin_revid());
 318         printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
 319
 320         printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
 321                cclk / 1000000,  sclk / 1000000);
 322
 323 #if defined(ANOMALY_05000273)
 324         if ((cclk >> 1) <= sclk)
 325                 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
 326 #endif
 327
 328         printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
 329         printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
 330
 331         printk(KERN_INFO "Memory map:\n"
 332                KERN_INFO "  text      = 0x%p-0x%p\n"
 333                KERN_INFO "  init      = 0x%p-0x%p\n"
 334                KERN_INFO "  data      = 0x%p-0x%p\n"
 335                KERN_INFO "  stack     = 0x%p-0x%p\n"
 336                KERN_INFO "  bss       = 0x%p-0x%p\n"
 337                KERN_INFO "  available = 0x%p-0x%p\n"
 338 #ifdef CONFIG_MTD_UCLINUX
 339                KERN_INFO "  rootfs    = 0x%p-0x%p\n"
 340 #endif
 341 #if DMA_UNCACHED_REGION > 0
 342                KERN_INFO "  DMA Zone  = 0x%p-0x%p\n"
 343 #endif
 344                , _stext, _etext,
 345                __init_begin, __init_end,
 346                _sdata, _edata,
 347                (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
 348                __bss_start, __bss_stop,
 349                (void*)_ramstart, (void*)memory_end
 350 #ifdef CONFIG_MTD_UCLINUX
 351                , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
 352 #endif
 353 #if DMA_UNCACHED_REGION > 0
 354                , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
 355 #endif
 356                );
 357
 358         /*
 359          * give all the memory to the bootmap allocator,  tell it to put the
 360          * boot mem_map at the start of memory
 361          */
 362         bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT,      /* map goes here */
 363                                          PAGE_OFFSET >> PAGE_SHIFT,
 364                                          memory_end >> PAGE_SHIFT);
 365         /*
 366          * free the usable memory,  we have to make sure we do not free
 367          * the bootmem bitmap so we then reserve it after freeing it :-)
 368          */
 369         free_bootmem(memory_start, memory_end - memory_start);
 370
 371         reserve_bootmem(memory_start, bootmap_size);
 372         /*
 373          * get kmalloc into gear
 374          */
 375         paging_init();
 376
 377         /* check the size of the l1 area */
 378         l1_length = _etext_l1 - _stext_l1;
 379         if (l1_length > L1_CODE_LENGTH)
 380                 panic("L1 memory overflow\n");
 381
 382         l1_length = _ebss_l1 - _sdata_l1;
 383         if (l1_length > L1_DATA_A_LENGTH)
 384                 panic("L1 memory overflow\n");
 385
 386 #ifdef BF561_FAMILY
 387         _bfin_swrst = bfin_read_SICA_SWRST();
 388 #else
 389         _bfin_swrst = bfin_read_SWRST();
 390 #endif
 391
 392         bf53x_cache_init();
 393
 394         printk(KERN_INFO "Hardware Trace Enabled\n");
 395         bfin_write_TBUFCTL(0x03);
 396 }
 397
 398 static int __init topology_init(void)
 399 {
 400 #if defined (CONFIG_BF561)
 401         static struct cpu cpu[2];
 402         register_cpu(&cpu[0], 0);
 403         register_cpu(&cpu[1], 1);
 404         return 0;
 405 #else
 406         static struct cpu cpu[1];
 407         return register_cpu(cpu, 0);
 408 #endif
 409 }
 410
 411 subsys_initcall(topology_init);
 412
 413 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
 414 static u16 __init lock_kernel_check(u32 start, u32 end)
 415 {
 416         if ((start <= (u32) _stext && end >= (u32) _end)
 417             || (start >= (u32) _stext && end <= (u32) _end))
 418                 return IN_KERNEL;
 419         return 0;
 420 }
 421
 422 static unsigned short __init
 423 fill_cplbtab(struct cplb_tab *table,
 424              unsigned long start, unsigned long end,
 425              unsigned long block_size, unsigned long cplb_data)
 426 {
 427         int i;
 428
 429         switch (block_size) {
 430         case SIZE_4M:
 431                 i = 3;
 432                 break;
 433         case SIZE_1M:
 434                 i = 2;
 435                 break;
 436         case SIZE_4K:
 437                 i = 1;
 438                 break;
 439         case SIZE_1K:
 440         default:
 441                 i = 0;
 442                 break;
 443         }
 444
 445         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 446
 447         while ((start < end) && (table->pos < table->size)) {
 448
 449                 table->tab[table->pos++] = start;
 450
 451                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
 452                         table->tab[table->pos++] =
 453                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 454                 else
 455                         table->tab[table->pos++] = cplb_data;
 456
 457                 start += block_size;
 458         }
 459         return 0;
 460 }
 461
 462 static unsigned short __init
 463 close_cplbtab(struct cplb_tab *table)
 464 {
 465
 466         while (table->pos < table->size) {
 467
 468                 table->tab[table->pos++] = 0;
 469                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
 470         }
 471         return 0;
 472 }
 473
 474 /* helper function */
 475 static void __fill_code_cplbtab(struct cplb_tab *t, int i,
 476                                 u32 a_start, u32 a_end)
 477 {
 478         if (cplb_data[i].psize) {
 479                 fill_cplbtab(t,
 480                                 cplb_data[i].start,
 481                                 cplb_data[i].end,
 482                                 cplb_data[i].psize,
 483                                 cplb_data[i].i_conf);
 484         } else {
 485 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
 486                 if (i == SDRAM_KERN) {
 487                         fill_cplbtab(t,
 488                                         cplb_data[i].start,
 489                                         cplb_data[i].end,
 490                                         SIZE_4M,
 491                                         cplb_data[i].i_conf);
 492                 } else {
 493 #endif
 494                         fill_cplbtab(t,
 495                                         cplb_data[i].start,
 496                                         a_start,
 497                                         SIZE_1M,
 498                                         cplb_data[i].i_conf);
 499                         fill_cplbtab(t,
 500                                         a_start,
 501                                         a_end,
 502                                         SIZE_4M,
 503                                         cplb_data[i].i_conf);
 504                         fill_cplbtab(t, a_end,
 505                                         cplb_data[i].end,
 506                                         SIZE_1M,
 507                                         cplb_data[i].i_conf);
 508                 }
 509         }
 510 }
 511
 512 static void __fill_data_cplbtab(struct cplb_tab *t, int i,
 513                                 u32 a_start, u32 a_end)
 514 {
 515         if (cplb_data[i].psize) {
 516                 fill_cplbtab(t,
 517                                 cplb_data[i].start,
 518                                 cplb_data[i].end,
 519                                 cplb_data[i].psize,
 520                                 cplb_data[i].d_conf);
 521         } else {
 522                 fill_cplbtab(t,
 523                                 cplb_data[i].start,
 524                                 a_start, SIZE_1M,
 525                                 cplb_data[i].d_conf);
 526                 fill_cplbtab(t, a_start,
 527                                 a_end, SIZE_4M,
 528                                 cplb_data[i].d_conf);
 529                 fill_cplbtab(t, a_end,
 530                                 cplb_data[i].end,
 531                                 SIZE_1M,
 532                                 cplb_data[i].d_conf);
 533         }
 534 }
 535 static void __init generate_cpl_tables(void)
 536 {
 537
 538         u16 i, j, process;
 539         u32 a_start, a_end, as, ae, as_1m;
 540
 541         struct cplb_tab *t_i = NULL;
 542         struct cplb_tab *t_d = NULL;
 543         struct s_cplb cplb;
 544
 545         cplb.init_i.size = MAX_CPLBS;
 546         cplb.init_d.size = MAX_CPLBS;
 547         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 548         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 549
 550         cplb.init_i.pos = 0;
 551         cplb.init_d.pos = 0;
 552         cplb.switch_i.pos = 0;
 553         cplb.switch_d.pos = 0;
 554
 555         cplb.init_i.tab = icplb_table;
 556         cplb.init_d.tab = dcplb_table;
 557         cplb.switch_i.tab = ipdt_table;
 558         cplb.switch_d.tab = dpdt_table;
 559
 560         cplb_data[SDRAM_KERN].end = memory_end;
 561
 562 #ifdef CONFIG_MTD_UCLINUX
 563         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 564         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 565         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 566 # if defined(CONFIG_ROMFS_FS)
 567         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 568
 569         /*
 570          * The ROMFS_FS size is often not multiple of 1MB.
 571          * This can cause multiple CPLB sets covering the same memory area.
 572          * This will then cause multiple CPLB hit exceptions.
 573          * Workaround: We ensure a contiguous memory area by extending the kernel
 574          * memory section over the mtd section.
 575          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 576          * So there is no difference between kernel and mtd memory setup.
 577          */
 578
 579         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 580         cplb_data[SDRAM_RAM_MTD].valid = 0;
 581
 582 # endif
 583 #else
 584         cplb_data[SDRAM_RAM_MTD].valid = 0;
 585 #endif
 586
 587         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 588         cplb_data[SDRAM_DMAZ].end = _ramend;
 589
 590         cplb_data[RES_MEM].start = _ramend;
 591         cplb_data[RES_MEM].end = physical_mem_end;
 592
 593         if (reserved_mem_dcache_on)
 594                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 595         else
 596                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 597
 598         if (reserved_mem_icache_on)
 599                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 600         else
 601                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 602
 603         for (i = ZERO_P; i <= L2_MEM; i++) {
 604                 if (!cplb_data[i].valid)
 605                         continue;
 606
 607                 as_1m = cplb_data[i].start % SIZE_1M;
 608
 609                 /*
 610                  * We need to make sure all sections are properly 1M aligned
 611                  * However between Kernel Memory and the Kernel mtd section,
 612                  * depending on the rootfs size, there can be overlapping
 613                  * memory areas.
 614                  */
 615
 616                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 617 #ifdef CONFIG_MTD_UCLINUX
 618                         if (i == SDRAM_RAM_MTD) {
 619                                 if ((cplb_data[SDRAM_KERN].end + 1) >
 620                                                 cplb_data[SDRAM_RAM_MTD].start)
 621                                         cplb_data[SDRAM_RAM_MTD].start =
 622                                                 (cplb_data[i].start &
 623                                                  (-2*SIZE_1M)) + SIZE_1M;
 624                                 else
 625                                         cplb_data[SDRAM_RAM_MTD].start =
 626                                                 (cplb_data[i].start &
 627                                                  (-2*SIZE_1M));
 628                         } else
 629 #endif
 630                                 printk(KERN_WARNING
 631                                         "Unaligned Start of %s at 0x%X\n",
 632                                         cplb_data[i].name, cplb_data[i].start);
 633                 }
 634
 635                 as = cplb_data[i].start % SIZE_4M;
 636                 ae = cplb_data[i].end % SIZE_4M;
 637
 638                 if (as)
 639                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 640                 else
 641                         a_start = cplb_data[i].start;
 642
 643                 a_end = cplb_data[i].end - ae;
 644
 645                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 646
 647                         switch (j) {
 648                         case INITIAL_T:
 649                                 if (cplb_data[i].attr & INITIAL_T) {
 650                                         t_i = &cplb.init_i;
 651                                         t_d = &cplb.init_d;
 652                                         process = 1;
 653                                 } else
 654                                         process = 0;
 655                                 break;
 656                         case SWITCH_T:
 657                                 if (cplb_data[i].attr & SWITCH_T) {
 658                                         t_i = &cplb.switch_i;
 659                                         t_d = &cplb.switch_d;
 660                                         process = 1;
 661                                 } else
 662                                         process = 0;
 663                                 break;
 664                         default:
 665                                         process = 0;
 666                                 break;
 667                         }
 668
 669                         if (!process)
 670                                 continue;
 671                         if (cplb_data[i].attr & I_CPLB)
 672                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 673
 674                         if (cplb_data[i].attr & D_CPLB)
 675                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 676                 }
 677         }
 678
 679 /* close tables */
 680
 681         close_cplbtab(&cplb.init_i);
 682         close_cplbtab(&cplb.init_d);
 683
 684         cplb.init_i.tab[cplb.init_i.pos] = -1;
 685         cplb.init_d.tab[cplb.init_d.pos] = -1;
 686         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 687         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 688
 689 }
 690
 691 #endif
 692
 693 static u_long get_vco(void)
 694 {
 695         u_long msel;
 696         u_long vco;
 697
 698         msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
 699         if (0 == msel)
 700                 msel = 64;
 701
 702         vco = CONFIG_CLKIN_HZ;
 703         vco >>= (1 & bfin_read_PLL_CTL());      /* DF bit */
 704         vco = msel * vco;
 705         return vco;
 706 }
 707
 708 /*Get the Core clock*/
 709 u_long get_cclk(void)
 710 {
 711         u_long csel, ssel;
 712         if (bfin_read_PLL_STAT() & 0x1)
 713                 return CONFIG_CLKIN_HZ;
 714
 715         ssel = bfin_read_PLL_DIV();
 716         csel = ((ssel >> 4) & 0x03);
 717         ssel &= 0xf;
 718         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
 719                 return get_vco() / ssel;
 720         return get_vco() >> csel;
 721 }
 722
 723 EXPORT_SYMBOL(get_cclk);
 724
 725 /* Get the System clock */
 726 u_long get_sclk(void)
 727 {
 728         u_long ssel;
 729
 730         if (bfin_read_PLL_STAT() & 0x1)
 731                 return CONFIG_CLKIN_HZ;
 732
 733         ssel = (bfin_read_PLL_DIV() & 0xf);
 734         if (0 == ssel) {
 735                 printk(KERN_WARNING "Invalid System Clock\n");
 736                 ssel = 1;
 737         }
 738
 739         return get_vco() / ssel;
 740 }
 741
 742 EXPORT_SYMBOL(get_sclk);
 743
 744 /*
 745  *      Get CPU information for use by the procfs.
 746  */
 747 static int show_cpuinfo(struct seq_file *m, void *v)
 748 {
 749         char *cpu, *mmu, *fpu, *name;
 750         uint32_t revid;
 751
 752         u_long cclk = 0, sclk = 0;
 753         u_int dcache_size = 0, dsup_banks = 0;
 754
 755         cpu = CPU;
 756         mmu = "none";
 757         fpu = "none";
 758         revid = bfin_revid();
 759         name = bfin_board_name;
 760
 761         cclk = get_cclk();
 762         sclk = get_sclk();
 763
 764         seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
 765                    "MMU:\t\t%s\n"
 766                    "FPU:\t\t%s\n"
 767                    "Core Clock:\t%9lu Hz\n"
 768                    "System Clock:\t%9lu Hz\n"
 769                    "BogoMips:\t%lu.%02lu\n"
 770                    "Calibration:\t%lu loops\n",
 771                    cpu, revid, mmu, fpu,
 772                    cclk,
 773                    sclk,
 774                    (loops_per_jiffy * HZ) / 500000,
 775                    ((loops_per_jiffy * HZ) / 5000) % 100,
 776                    (loops_per_jiffy * HZ));
 777         seq_printf(m, "Board Name:\t%s\n", name);
 778         seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
 779         seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
 780         if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
 781                 seq_printf(m, "I-CACHE:\tON\n");
 782         else
 783                 seq_printf(m, "I-CACHE:\tOFF\n");
 784         if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
 785                 seq_printf(m, "D-CACHE:\tON"
 786 #if defined CONFIG_BLKFIN_WB
 787                            " (write-back)"
 788 #elif defined CONFIG_BLKFIN_WT
 789                            " (write-through)"
 790 #endif
 791                            "\n");
 792         else
 793                 seq_printf(m, "D-CACHE:\tOFF\n");
 794
 795
 796         switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
 797                 case ACACHE_BSRAM:
 798                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
 799                         dcache_size = 16;
 800                         dsup_banks = 1;
 801                         break;
 802                 case ACACHE_BCACHE:
 803                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
 804                         dcache_size = 32;
 805                         dsup_banks = 2;
 806                         break;
 807                 case ASRAM_BSRAM:
 808                         seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
 809                         dcache_size = 0;
 810                         dsup_banks = 0;
 811                         break;
 812                 default:
 813                 break;
 814         }
 815
 816
 817         seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
 818         seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
 819         seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
 820                    BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
 821         seq_printf(m,
 822                    "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
 823                    dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
 824                    BLKFIN_DLINES);
 825 #ifdef CONFIG_BLKFIN_CACHE_LOCK
 826         switch (read_iloc()) {
 827         case WAY0_L:
 828                 seq_printf(m, "Way0 Locked-Down\n");
 829                 break;
 830         case WAY1_L:
 831                 seq_printf(m, "Way1 Locked-Down\n");
 832                 break;
 833         case WAY01_L:
 834                 seq_printf(m, "Way0,Way1 Locked-Down\n");
 835                 break;
 836         case WAY2_L:
 837                 seq_printf(m, "Way2 Locked-Down\n");
 838                 break;
 839         case WAY02_L:
 840                 seq_printf(m, "Way0,Way2 Locked-Down\n");
 841                 break;
 842         case WAY12_L:
 843                 seq_printf(m, "Way1,Way2 Locked-Down\n");
 844                 break;
 845         case WAY012_L:
 846                 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
 847                 break;
 848         case WAY3_L:
 849                 seq_printf(m, "Way3 Locked-Down\n");
 850                 break;
 851         case WAY03_L:
 852                 seq_printf(m, "Way0,Way3 Locked-Down\n");
 853                 break;
 854         case WAY13_L:
 855                 seq_printf(m, "Way1,Way3 Locked-Down\n");
 856                 break;
 857         case WAY013_L:
 858                 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
 859                 break;
 860         case WAY32_L:
 861                 seq_printf(m, "Way3,Way2 Locked-Down\n");
 862                 break;
 863         case WAY320_L:
 864                 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
 865                 break;
 866         case WAY321_L:
 867                 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
 868                 break;
 869         case WAYALL_L:
 870                 seq_printf(m, "All Ways are locked\n");
 871                 break;
 872         default:
 873                 seq_printf(m, "No Ways are locked\n");
 874         }
 875 #endif
 876         return 0;
 877 }
 878
 879 static void *c_start(struct seq_file *m, loff_t *pos)
 880 {
 881         return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
 882 }
 883
 884 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 885 {
 886         ++*pos;
 887         return c_start(m, pos);
 888 }
 889
 890 static void c_stop(struct seq_file *m, void *v)
 891 {
 892 }
 893
 894 struct seq_operations cpuinfo_op = {
 895         .start = c_start,
 896         .next = c_next,
 897         .stop = c_stop,
 898         .show = show_cpuinfo,
 899 };
 900
 901 void __init cmdline_init(char *r0)
 902 {
 903         if (r0)
 904                 strncpy(command_line, r0, COMMAND_LINE_SIZE);
 905 }