arch/arm64/kvm/hyp/switch.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/arm-smccc.h>
   8 #include <linux/kvm_host.h>
   9 #include <linux/types.h>
  10 #include <linux/jump_label.h>
  11 #include <uapi/linux/psci.h>
  12
  13 #include <kvm/arm_psci.h>
  14
  15 #include <asm/arch_gicv3.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/kprobes.h>
  18 #include <asm/kvm_asm.h>
  19 #include <asm/kvm_emulate.h>
  20 #include <asm/kvm_host.h>
  21 #include <asm/kvm_hyp.h>
  22 #include <asm/kvm_mmu.h>
  23 #include <asm/fpsimd.h>
  24 #include <asm/debug-monitors.h>
  25 #include <asm/processor.h>
  26 #include <asm/thread_info.h>
  27
  28 /* Check whether the FP regs were dirtied while in the host-side run loop: */
  29 static bool __hyp_text update_fp_enabled(struct kvm_vcpu *vcpu)
  30 {
  31         if (vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
  32                 vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
  33                                       KVM_ARM64_FP_HOST);
  34
  35         return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
  36 }
  37
  38 /* Save the 32-bit only FPSIMD system register state */
  39 static void __hyp_text __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
  40 {
  41         if (!vcpu_el1_is_32bit(vcpu))
  42                 return;
  43
  44         vcpu->arch.ctxt.sys_regs[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
  45 }
  46
  47 static void __hyp_text __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
  48 {
  49         /*
  50          * We are about to set CPTR_EL2.TFP to trap all floating point
  51          * register accesses to EL2, however, the ARM ARM clearly states that
  52          * traps are only taken to EL2 if the operation would not otherwise
  53          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  54          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  55          * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
  56          * it will cause an exception.
  57          */
  58         if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
  59                 write_sysreg(1 << 30, fpexc32_el2);
  60                 isb();
  61         }
  62 }
  63
  64 static void __hyp_text __activate_traps_common(struct kvm_vcpu *vcpu)
  65 {
  66         /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
  67         write_sysreg(1 << 15, hstr_el2);
  68
  69         /*
  70          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
  71          * PMSELR_EL0 to make sure it never contains the cycle
  72          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
  73          * EL1 instead of being trapped to EL2.
  74          */
  75         write_sysreg(0, pmselr_el0);
  76         write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
  77         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
  78 }
  79
  80 static void __hyp_text __deactivate_traps_common(void)
  81 {
  82         write_sysreg(0, hstr_el2);
  83         write_sysreg(0, pmuserenr_el0);
  84 }
  85
  86 static void activate_traps_vhe(struct kvm_vcpu *vcpu)
  87 {
  88         u64 val;
  89
  90         val = read_sysreg(cpacr_el1);
  91         val |= CPACR_EL1_TTA;
  92         val &= ~CPACR_EL1_ZEN;
  93         if (update_fp_enabled(vcpu)) {
  94                 if (vcpu_has_sve(vcpu))
  95                         val |= CPACR_EL1_ZEN;
  96         } else {
  97                 val &= ~CPACR_EL1_FPEN;
  98                 __activate_traps_fpsimd32(vcpu);
  99         }
 100
 101         write_sysreg(val, cpacr_el1);
 102
 103         write_sysreg(kvm_get_hyp_vector(), vbar_el1);
 104 }
 105 NOKPROBE_SYMBOL(activate_traps_vhe);
 106
 107 static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
 108 {
 109         u64 val;
 110
 111         __activate_traps_common(vcpu);
 112
 113         val = CPTR_EL2_DEFAULT;
 114         val |= CPTR_EL2_TTA | CPTR_EL2_TZ;
 115         if (!update_fp_enabled(vcpu)) {
 116                 val |= CPTR_EL2_TFP;
 117                 __activate_traps_fpsimd32(vcpu);
 118         }
 119
 120         write_sysreg(val, cptr_el2);
 121 }
 122
 123 static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
 124 {
 125         u64 hcr = vcpu->arch.hcr_el2;
 126
 127         write_sysreg(hcr, hcr_el2);
 128
 129         if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
 130                 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
 131
 132         if (has_vhe())
 133                 activate_traps_vhe(vcpu);
 134         else
 135                 __activate_traps_nvhe(vcpu);
 136 }
 137
 138 static void deactivate_traps_vhe(void)
 139 {
 140         extern char vectors[];  /* kernel exception vectors */
 141         write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
 142
 143         /*
 144          * ARM erratum 1165522 requires the actual execution of the above
 145          * before we can switch to the EL2/EL0 translation regime used by
 146          * the host.
 147          */
 148         asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));
 149
 150         write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
 151         write_sysreg(vectors, vbar_el1);
 152 }
 153 NOKPROBE_SYMBOL(deactivate_traps_vhe);
 154
 155 static void __hyp_text __deactivate_traps_nvhe(void)
 156 {
 157         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 158
 159         __deactivate_traps_common();
 160
 161         mdcr_el2 &= MDCR_EL2_HPMN_MASK;
 162         mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
 163
 164         write_sysreg(mdcr_el2, mdcr_el2);
 165         write_sysreg(HCR_HOST_NVHE_FLAGS, hcr_el2);
 166         write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
 167 }
 168
 169 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
 170 {
 171         /*
 172          * If we pended a virtual abort, preserve it until it gets
 173          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 174          * the crucial bit is "On taking a vSError interrupt,
 175          * HCR_EL2.VSE is cleared to 0."
 176          */
 177         if (vcpu->arch.hcr_el2 & HCR_VSE)
 178                 vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
 179
 180         if (has_vhe())
 181                 deactivate_traps_vhe();
 182         else
 183                 __deactivate_traps_nvhe();
 184 }
 185
 186 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
 187 {
 188         __activate_traps_common(vcpu);
 189 }
 190
 191 void deactivate_traps_vhe_put(void)
 192 {
 193         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 194
 195         mdcr_el2 &= MDCR_EL2_HPMN_MASK |
 196                     MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
 197                     MDCR_EL2_TPMS;
 198
 199         write_sysreg(mdcr_el2, mdcr_el2);
 200
 201         __deactivate_traps_common();
 202 }
 203
 204 static void __hyp_text __activate_vm(struct kvm *kvm)
 205 {
 206         __load_guest_stage2(kvm);
 207 }
 208
 209 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
 210 {
 211         write_sysreg(0, vttbr_el2);
 212 }
 213
 214 /* Save VGICv3 state on non-VHE systems */
 215 static void __hyp_text __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
 216 {
 217         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 218                 __vgic_v3_save_state(vcpu);
 219                 __vgic_v3_deactivate_traps(vcpu);
 220         }
 221 }
 222
 223 /* Restore VGICv3 state on non_VEH systems */
 224 static void __hyp_text __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
 225 {
 226         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 227                 __vgic_v3_activate_traps(vcpu);
 228                 __vgic_v3_restore_state(vcpu);
 229         }
 230 }
 231
 232 static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
 233 {
 234         u64 par, tmp;
 235
 236         /*
 237          * Resolve the IPA the hard way using the guest VA.
 238          *
 239          * Stage-1 translation already validated the memory access
 240          * rights. As such, we can use the EL1 translation regime, and
 241          * don't have to distinguish between EL0 and EL1 access.
 242          *
 243          * We do need to save/restore PAR_EL1 though, as we haven't
 244          * saved the guest context yet, and we may return early...
 245          */
 246         par = read_sysreg(par_el1);
 247         asm volatile("at s1e1r, %0" : : "r" (far));
 248         isb();
 249
 250         tmp = read_sysreg(par_el1);
 251         write_sysreg(par, par_el1);
 252
 253         if (unlikely(tmp & SYS_PAR_EL1_F))
 254                 return false; /* Translation failed, back to guest */
 255
 256         /* Convert PAR to HPFAR format */
 257         *hpfar = PAR_TO_HPFAR(tmp);
 258         return true;
 259 }
 260
 261 static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
 262 {
 263         u8 ec;
 264         u64 esr;
 265         u64 hpfar, far;
 266
 267         esr = vcpu->arch.fault.esr_el2;
 268         ec = ESR_ELx_EC(esr);
 269
 270         if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
 271                 return true;
 272
 273         far = read_sysreg_el2(SYS_FAR);
 274
 275         /*
 276          * The HPFAR can be invalid if the stage 2 fault did not
 277          * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
 278          * bit is clear) and one of the two following cases are true:
 279          *   1. The fault was due to a permission fault
 280          *   2. The processor carries errata 834220
 281          *
 282          * Therefore, for all non S1PTW faults where we either have a
 283          * permission fault or the errata workaround is enabled, we
 284          * resolve the IPA using the AT instruction.
 285          */
 286         if (!(esr & ESR_ELx_S1PTW) &&
 287             (cpus_have_const_cap(ARM64_WORKAROUND_834220) ||
 288              (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
 289                 if (!__translate_far_to_hpfar(far, &hpfar))
 290                         return false;
 291         } else {
 292                 hpfar = read_sysreg(hpfar_el2);
 293         }
 294
 295         vcpu->arch.fault.far_el2 = far;
 296         vcpu->arch.fault.hpfar_el2 = hpfar;
 297         return true;
 298 }
 299
 300 /* Check for an FPSIMD/SVE trap and handle as appropriate */
 301 static bool __hyp_text __hyp_handle_fpsimd(struct kvm_vcpu *vcpu)
 302 {
 303         bool vhe, sve_guest, sve_host;
 304         u8 hsr_ec;
 305
 306         if (!system_supports_fpsimd())
 307                 return false;
 308
 309         if (system_supports_sve()) {
 310                 sve_guest = vcpu_has_sve(vcpu);
 311                 sve_host = vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE;
 312                 vhe = true;
 313         } else {
 314                 sve_guest = false;
 315                 sve_host = false;
 316                 vhe = has_vhe();
 317         }
 318
 319         hsr_ec = kvm_vcpu_trap_get_class(vcpu);
 320         if (hsr_ec != ESR_ELx_EC_FP_ASIMD &&
 321             hsr_ec != ESR_ELx_EC_SVE)
 322                 return false;
 323
 324         /* Don't handle SVE traps for non-SVE vcpus here: */
 325         if (!sve_guest)
 326                 if (hsr_ec != ESR_ELx_EC_FP_ASIMD)
 327                         return false;
 328
 329         /* Valid trap.  Switch the context: */
 330
 331         if (vhe) {
 332                 u64 reg = read_sysreg(cpacr_el1) | CPACR_EL1_FPEN;
 333
 334                 if (sve_guest)
 335                         reg |= CPACR_EL1_ZEN;
 336
 337                 write_sysreg(reg, cpacr_el1);
 338         } else {
 339                 write_sysreg(read_sysreg(cptr_el2) & ~(u64)CPTR_EL2_TFP,
 340                              cptr_el2);
 341         }
 342
 343         isb();
 344
 345         if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
 346                 /*
 347                  * In the SVE case, VHE is assumed: it is enforced by
 348                  * Kconfig and kvm_arch_init().
 349                  */
 350                 if (sve_host) {
 351                         struct thread_struct *thread = container_of(
 352                                 vcpu->arch.host_fpsimd_state,
 353                                 struct thread_struct, uw.fpsimd_state);
 354
 355                         sve_save_state(sve_pffr(thread),
 356                                        &vcpu->arch.host_fpsimd_state->fpsr);
 357                 } else {
 358                         __fpsimd_save_state(vcpu->arch.host_fpsimd_state);
 359                 }
 360
 361                 vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
 362         }
 363
 364         if (sve_guest) {
 365                 sve_load_state(vcpu_sve_pffr(vcpu),
 366                                &vcpu->arch.ctxt.gp_regs.fp_regs.fpsr,
 367                                sve_vq_from_vl(vcpu->arch.sve_max_vl) - 1);
 368                 write_sysreg_s(vcpu->arch.ctxt.sys_regs[ZCR_EL1], SYS_ZCR_EL12);
 369         } else {
 370                 __fpsimd_restore_state(&vcpu->arch.ctxt.gp_regs.fp_regs);
 371         }
 372
 373         /* Skip restoring fpexc32 for AArch64 guests */
 374         if (!(read_sysreg(hcr_el2) & HCR_RW))
 375                 write_sysreg(vcpu->arch.ctxt.sys_regs[FPEXC32_EL2],
 376                              fpexc32_el2);
 377
 378         vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
 379
 380         return true;
 381 }
 382
 383 /*
 384  * Return true when we were able to fixup the guest exit and should return to
 385  * the guest, false when we should restore the host state and return to the
 386  * main run loop.
 387  */
 388 static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 389 {
 390         if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
 391                 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
 392
 393         /*
 394          * We're using the raw exception code in order to only process
 395          * the trap if no SError is pending. We will come back to the
 396          * same PC once the SError has been injected, and replay the
 397          * trapping instruction.
 398          */
 399         if (*exit_code != ARM_EXCEPTION_TRAP)
 400                 goto exit;
 401
 402         /*
 403          * We trap the first access to the FP/SIMD to save the host context
 404          * and restore the guest context lazily.
 405          * If FP/SIMD is not implemented, handle the trap and inject an
 406          * undefined instruction exception to the guest.
 407          * Similarly for trapped SVE accesses.
 408          */
 409         if (__hyp_handle_fpsimd(vcpu))
 410                 return true;
 411
 412         if (!__populate_fault_info(vcpu))
 413                 return true;
 414
 415         if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 416                 bool valid;
 417
 418                 valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
 419                         kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
 420                         kvm_vcpu_dabt_isvalid(vcpu) &&
 421                         !kvm_vcpu_dabt_isextabt(vcpu) &&
 422                         !kvm_vcpu_dabt_iss1tw(vcpu);
 423
 424                 if (valid) {
 425                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 426
 427                         if (ret == 1)
 428                                 return true;
 429
 430                         /* Promote an illegal access to an SError.*/
 431                         if (ret == -1)
 432                                 *exit_code = ARM_EXCEPTION_EL1_SERROR;
 433
 434                         goto exit;
 435                 }
 436         }
 437
 438         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 439             (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
 440              kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
 441                 int ret = __vgic_v3_perform_cpuif_access(vcpu);
 442
 443                 if (ret == 1)
 444                         return true;
 445         }
 446
 447 exit:
 448         /* Return to the host kernel and handle the exit */
 449         return false;
 450 }
 451
 452 static inline bool __hyp_text __needs_ssbd_off(struct kvm_vcpu *vcpu)
 453 {
 454         if (!cpus_have_const_cap(ARM64_SSBD))
 455                 return false;
 456
 457         return !(vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG);
 458 }
 459
 460 static void __hyp_text __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
 461 {
 462 #ifdef CONFIG_ARM64_SSBD
 463         /*
 464          * The host runs with the workaround always present. If the
 465          * guest wants it disabled, so be it...
 466          */
 467         if (__needs_ssbd_off(vcpu) &&
 468             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 469                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
 470 #endif
 471 }
 472
 473 static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
 474 {
 475 #ifdef CONFIG_ARM64_SSBD
 476         /*
 477          * If the guest has disabled the workaround, bring it back on.
 478          */
 479         if (__needs_ssbd_off(vcpu) &&
 480             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 481                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
 482 #endif
 483 }
 484
 485 /**
 486  * Disable host events, enable guest events
 487  */
 488 static bool __hyp_text __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
 489 {
 490         struct kvm_host_data *host;
 491         struct kvm_pmu_events *pmu;
 492
 493         host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
 494         pmu = &host->pmu_events;
 495
 496         if (pmu->events_host)
 497                 write_sysreg(pmu->events_host, pmcntenclr_el0);
 498
 499         if (pmu->events_guest)
 500                 write_sysreg(pmu->events_guest, pmcntenset_el0);
 501
 502         return (pmu->events_host || pmu->events_guest);
 503 }
 504
 505 /**
 506  * Disable guest events, enable host events
 507  */
 508 static void __hyp_text __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
 509 {
 510         struct kvm_host_data *host;
 511         struct kvm_pmu_events *pmu;
 512
 513         host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
 514         pmu = &host->pmu_events;
 515
 516         if (pmu->events_guest)
 517                 write_sysreg(pmu->events_guest, pmcntenclr_el0);
 518
 519         if (pmu->events_host)
 520                 write_sysreg(pmu->events_host, pmcntenset_el0);
 521 }
 522
 523 /* Switch to the guest for VHE systems running in EL2 */
 524 int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
 525 {
 526         struct kvm_cpu_context *host_ctxt;
 527         struct kvm_cpu_context *guest_ctxt;
 528         u64 exit_code;
 529
 530         host_ctxt = vcpu->arch.host_cpu_context;
 531         host_ctxt->__hyp_running_vcpu = vcpu;
 532         guest_ctxt = &vcpu->arch.ctxt;
 533
 534         sysreg_save_host_state_vhe(host_ctxt);
 535
 536         /*
 537          * ARM erratum 1165522 requires us to configure both stage 1 and
 538          * stage 2 translation for the guest context before we clear
 539          * HCR_EL2.TGE.
 540          *
 541          * We have already configured the guest's stage 1 translation in
 542          * kvm_vcpu_load_sysregs above.  We must now call __activate_vm
 543          * before __activate_traps, because __activate_vm configures
 544          * stage 2 translation, and __activate_traps clear HCR_EL2.TGE
 545          * (among other things).
 546          */
 547         __activate_vm(vcpu->kvm);
 548         __activate_traps(vcpu);
 549
 550         sysreg_restore_guest_state_vhe(guest_ctxt);
 551         __debug_switch_to_guest(vcpu);
 552
 553         __set_guest_arch_workaround_state(vcpu);
 554
 555         do {
 556                 /* Jump in the fire! */
 557                 exit_code = __guest_enter(vcpu, host_ctxt);
 558
 559                 /* And we're baaack! */
 560         } while (fixup_guest_exit(vcpu, &exit_code));
 561
 562         __set_host_arch_workaround_state(vcpu);
 563
 564         sysreg_save_guest_state_vhe(guest_ctxt);
 565
 566         __deactivate_traps(vcpu);
 567
 568         sysreg_restore_host_state_vhe(host_ctxt);
 569
 570         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 571                 __fpsimd_save_fpexc32(vcpu);
 572
 573         __debug_switch_to_host(vcpu);
 574
 575         return exit_code;
 576 }
 577 NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);
 578
 579 /* Switch to the guest for legacy non-VHE systems */
 580 int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
 581 {
 582         struct kvm_cpu_context *host_ctxt;
 583         struct kvm_cpu_context *guest_ctxt;
 584         bool pmu_switch_needed;
 585         u64 exit_code;
 586
 587         /*
 588          * Having IRQs masked via PMR when entering the guest means the GIC
 589          * will not signal the CPU of interrupts of lower priority, and the
 590          * only way to get out will be via guest exceptions.
 591          * Naturally, we want to avoid this.
 592          */
 593         if (system_uses_irq_prio_masking()) {
 594                 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
 595                 dsb(sy);
 596         }
 597
 598         vcpu = kern_hyp_va(vcpu);
 599
 600         host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
 601         host_ctxt->__hyp_running_vcpu = vcpu;
 602         guest_ctxt = &vcpu->arch.ctxt;
 603
 604         pmu_switch_needed = __pmu_switch_to_guest(host_ctxt);
 605
 606         __sysreg_save_state_nvhe(host_ctxt);
 607
 608         __activate_vm(kern_hyp_va(vcpu->kvm));
 609         __activate_traps(vcpu);
 610
 611         __hyp_vgic_restore_state(vcpu);
 612         __timer_enable_traps(vcpu);
 613
 614         /*
 615          * We must restore the 32-bit state before the sysregs, thanks
 616          * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
 617          */
 618         __sysreg32_restore_state(vcpu);
 619         __sysreg_restore_state_nvhe(guest_ctxt);
 620         __debug_switch_to_guest(vcpu);
 621
 622         __set_guest_arch_workaround_state(vcpu);
 623
 624         do {
 625                 /* Jump in the fire! */
 626                 exit_code = __guest_enter(vcpu, host_ctxt);
 627
 628                 /* And we're baaack! */
 629         } while (fixup_guest_exit(vcpu, &exit_code));
 630
 631         __set_host_arch_workaround_state(vcpu);
 632
 633         __sysreg_save_state_nvhe(guest_ctxt);
 634         __sysreg32_save_state(vcpu);
 635         __timer_disable_traps(vcpu);
 636         __hyp_vgic_save_state(vcpu);
 637
 638         __deactivate_traps(vcpu);
 639         __deactivate_vm(vcpu);
 640
 641         __sysreg_restore_state_nvhe(host_ctxt);
 642
 643         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 644                 __fpsimd_save_fpexc32(vcpu);
 645
 646         /*
 647          * This must come after restoring the host sysregs, since a non-VHE
 648          * system may enable SPE here and make use of the TTBRs.
 649          */
 650         __debug_switch_to_host(vcpu);
 651
 652         if (pmu_switch_needed)
 653                 __pmu_switch_to_host(host_ctxt);
 654
 655         /* Returning to host will clear PSR.I, remask PMR if needed */
 656         if (system_uses_irq_prio_masking())
 657                 gic_write_pmr(GIC_PRIO_IRQOFF);
 658
 659         return exit_code;
 660 }
 661
 662 static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
 663
 664 static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
 665                                              struct kvm_cpu_context *__host_ctxt)
 666 {
 667         struct kvm_vcpu *vcpu;
 668         unsigned long str_va;
 669
 670         vcpu = __host_ctxt->__hyp_running_vcpu;
 671
 672         if (read_sysreg(vttbr_el2)) {
 673                 __timer_disable_traps(vcpu);
 674                 __deactivate_traps(vcpu);
 675                 __deactivate_vm(vcpu);
 676                 __sysreg_restore_state_nvhe(__host_ctxt);
 677         }
 678
 679         /*
 680          * Force the panic string to be loaded from the literal pool,
 681          * making sure it is a kernel address and not a PC-relative
 682          * reference.
 683          */
 684         asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va));
 685
 686         __hyp_do_panic(str_va,
 687                        spsr, elr,
 688                        read_sysreg(esr_el2), read_sysreg_el2(SYS_FAR),
 689                        read_sysreg(hpfar_el2), par, vcpu);
 690 }
 691
 692 static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
 693                                  struct kvm_cpu_context *host_ctxt)
 694 {
 695         struct kvm_vcpu *vcpu;
 696         vcpu = host_ctxt->__hyp_running_vcpu;
 697
 698         __deactivate_traps(vcpu);
 699         sysreg_restore_host_state_vhe(host_ctxt);
 700
 701         panic(__hyp_panic_string,
 702               spsr,  elr,
 703               read_sysreg_el2(SYS_ESR),   read_sysreg_el2(SYS_FAR),
 704               read_sysreg(hpfar_el2), par, vcpu);
 705 }
 706 NOKPROBE_SYMBOL(__hyp_call_panic_vhe);
 707
 708 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
 709 {
 710         u64 spsr = read_sysreg_el2(SYS_SPSR);
 711         u64 elr = read_sysreg_el2(SYS_ELR);
 712         u64 par = read_sysreg(par_el1);
 713
 714         if (!has_vhe())
 715                 __hyp_call_panic_nvhe(spsr, elr, par, host_ctxt);
 716         else
 717                 __hyp_call_panic_vhe(spsr, elr, par, host_ctxt);
 718
 719         unreachable();
 720 }