arch/arm64/kvm/emulate-nested.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 - Linaro and Columbia University
   4  * Author: Jintack Lim <jintack.lim@linaro.org>
   5  */
   6
   7 #include <linux/kvm.h>
   8 #include <linux/kvm_host.h>
   9
  10 #include <asm/kvm_emulate.h>
  11 #include <asm/kvm_nested.h>
  12
  13 #include "hyp/include/hyp/adjust_pc.h"
  14
  15 #include "trace.h"
  16
  17 enum trap_behaviour {
  18         BEHAVE_HANDLE_LOCALLY   = 0,
  19         BEHAVE_FORWARD_READ     = BIT(0),
  20         BEHAVE_FORWARD_WRITE    = BIT(1),
  21         BEHAVE_FORWARD_ANY      = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE,
  22 };
  23
  24 struct trap_bits {
  25         const enum vcpu_sysreg          index;
  26         const enum trap_behaviour       behaviour;
  27         const u64                       value;
  28         const u64                       mask;
  29 };
  30
  31 /* Coarse Grained Trap definitions */
  32 enum cgt_group_id {
  33         /* Indicates no coarse trap control */
  34         __RESERVED__,
  35
  36         /*
  37          * The first batch of IDs denote coarse trapping that are used
  38          * on their own instead of being part of a combination of
  39          * trap controls.
  40          */
  41         CGT_HCR_TID1,
  42         CGT_HCR_TID2,
  43         CGT_HCR_TID3,
  44         CGT_HCR_IMO,
  45         CGT_HCR_FMO,
  46         CGT_HCR_TIDCP,
  47         CGT_HCR_TACR,
  48         CGT_HCR_TSW,
  49         CGT_HCR_TPC,
  50         CGT_HCR_TPU,
  51         CGT_HCR_TTLB,
  52         CGT_HCR_TVM,
  53         CGT_HCR_TDZ,
  54         CGT_HCR_TRVM,
  55         CGT_HCR_TLOR,
  56         CGT_HCR_TERR,
  57         CGT_HCR_APK,
  58         CGT_HCR_NV,
  59         CGT_HCR_NV_nNV2,
  60         CGT_HCR_NV1_nNV2,
  61         CGT_HCR_AT,
  62         CGT_HCR_nFIEN,
  63         CGT_HCR_TID4,
  64         CGT_HCR_TICAB,
  65         CGT_HCR_TOCU,
  66         CGT_HCR_ENSCXT,
  67         CGT_HCR_TTLBIS,
  68         CGT_HCR_TTLBOS,
  69
  70         CGT_MDCR_TPMCR,
  71         CGT_MDCR_TPM,
  72         CGT_MDCR_TDE,
  73         CGT_MDCR_TDA,
  74         CGT_MDCR_TDOSA,
  75         CGT_MDCR_TDRA,
  76         CGT_MDCR_E2PB,
  77         CGT_MDCR_TPMS,
  78         CGT_MDCR_TTRF,
  79         CGT_MDCR_E2TB,
  80         CGT_MDCR_TDCC,
  81
  82         /*
  83          * Anything after this point is a combination of coarse trap
  84          * controls, which must all be evaluated to decide what to do.
  85          */
  86         __MULTIPLE_CONTROL_BITS__,
  87         CGT_HCR_IMO_FMO = __MULTIPLE_CONTROL_BITS__,
  88         CGT_HCR_TID2_TID4,
  89         CGT_HCR_TTLB_TTLBIS,
  90         CGT_HCR_TTLB_TTLBOS,
  91         CGT_HCR_TVM_TRVM,
  92         CGT_HCR_TPU_TICAB,
  93         CGT_HCR_TPU_TOCU,
  94         CGT_HCR_NV1_nNV2_ENSCXT,
  95         CGT_MDCR_TPM_TPMCR,
  96         CGT_MDCR_TDE_TDA,
  97         CGT_MDCR_TDE_TDOSA,
  98         CGT_MDCR_TDE_TDRA,
  99         CGT_MDCR_TDCC_TDE_TDA,
 100
 101         /*
 102          * Anything after this point requires a callback evaluating a
 103          * complex trap condition. Ugly stuff.
 104          */
 105         __COMPLEX_CONDITIONS__,
 106         CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__,
 107         CGT_CNTHCTL_EL1PTEN,
 108
 109         /* Must be last */
 110         __NR_CGT_GROUP_IDS__
 111 };
 112
 113 static const struct trap_bits coarse_trap_bits[] = {
 114         [CGT_HCR_TID1] = {
 115                 .index          = HCR_EL2,
 116                 .value          = HCR_TID1,
 117                 .mask           = HCR_TID1,
 118                 .behaviour      = BEHAVE_FORWARD_READ,
 119         },
 120         [CGT_HCR_TID2] = {
 121                 .index          = HCR_EL2,
 122                 .value          = HCR_TID2,
 123                 .mask           = HCR_TID2,
 124                 .behaviour      = BEHAVE_FORWARD_ANY,
 125         },
 126         [CGT_HCR_TID3] = {
 127                 .index          = HCR_EL2,
 128                 .value          = HCR_TID3,
 129                 .mask           = HCR_TID3,
 130                 .behaviour      = BEHAVE_FORWARD_READ,
 131         },
 132         [CGT_HCR_IMO] = {
 133                 .index          = HCR_EL2,
 134                 .value          = HCR_IMO,
 135                 .mask           = HCR_IMO,
 136                 .behaviour      = BEHAVE_FORWARD_WRITE,
 137         },
 138         [CGT_HCR_FMO] = {
 139                 .index          = HCR_EL2,
 140                 .value          = HCR_FMO,
 141                 .mask           = HCR_FMO,
 142                 .behaviour      = BEHAVE_FORWARD_WRITE,
 143         },
 144         [CGT_HCR_TIDCP] = {
 145                 .index          = HCR_EL2,
 146                 .value          = HCR_TIDCP,
 147                 .mask           = HCR_TIDCP,
 148                 .behaviour      = BEHAVE_FORWARD_ANY,
 149         },
 150         [CGT_HCR_TACR] = {
 151                 .index          = HCR_EL2,
 152                 .value          = HCR_TACR,
 153                 .mask           = HCR_TACR,
 154                 .behaviour      = BEHAVE_FORWARD_ANY,
 155         },
 156         [CGT_HCR_TSW] = {
 157                 .index          = HCR_EL2,
 158                 .value          = HCR_TSW,
 159                 .mask           = HCR_TSW,
 160                 .behaviour      = BEHAVE_FORWARD_ANY,
 161         },
 162         [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */
 163                 .index          = HCR_EL2,
 164                 .value          = HCR_TPC,
 165                 .mask           = HCR_TPC,
 166                 .behaviour      = BEHAVE_FORWARD_ANY,
 167         },
 168         [CGT_HCR_TPU] = {
 169                 .index          = HCR_EL2,
 170                 .value          = HCR_TPU,
 171                 .mask           = HCR_TPU,
 172                 .behaviour      = BEHAVE_FORWARD_ANY,
 173         },
 174         [CGT_HCR_TTLB] = {
 175                 .index          = HCR_EL2,
 176                 .value          = HCR_TTLB,
 177                 .mask           = HCR_TTLB,
 178                 .behaviour      = BEHAVE_FORWARD_ANY,
 179         },
 180         [CGT_HCR_TVM] = {
 181                 .index          = HCR_EL2,
 182                 .value          = HCR_TVM,
 183                 .mask           = HCR_TVM,
 184                 .behaviour      = BEHAVE_FORWARD_WRITE,
 185         },
 186         [CGT_HCR_TDZ] = {
 187                 .index          = HCR_EL2,
 188                 .value          = HCR_TDZ,
 189                 .mask           = HCR_TDZ,
 190                 .behaviour      = BEHAVE_FORWARD_ANY,
 191         },
 192         [CGT_HCR_TRVM] = {
 193                 .index          = HCR_EL2,
 194                 .value          = HCR_TRVM,
 195                 .mask           = HCR_TRVM,
 196                 .behaviour      = BEHAVE_FORWARD_READ,
 197         },
 198         [CGT_HCR_TLOR] = {
 199                 .index          = HCR_EL2,
 200                 .value          = HCR_TLOR,
 201                 .mask           = HCR_TLOR,
 202                 .behaviour      = BEHAVE_FORWARD_ANY,
 203         },
 204         [CGT_HCR_TERR] = {
 205                 .index          = HCR_EL2,
 206                 .value          = HCR_TERR,
 207                 .mask           = HCR_TERR,
 208                 .behaviour      = BEHAVE_FORWARD_ANY,
 209         },
 210         [CGT_HCR_APK] = {
 211                 .index          = HCR_EL2,
 212                 .value          = 0,
 213                 .mask           = HCR_APK,
 214                 .behaviour      = BEHAVE_FORWARD_ANY,
 215         },
 216         [CGT_HCR_NV] = {
 217                 .index          = HCR_EL2,
 218                 .value          = HCR_NV,
 219                 .mask           = HCR_NV,
 220                 .behaviour      = BEHAVE_FORWARD_ANY,
 221         },
 222         [CGT_HCR_NV_nNV2] = {
 223                 .index          = HCR_EL2,
 224                 .value          = HCR_NV,
 225                 .mask           = HCR_NV | HCR_NV2,
 226                 .behaviour      = BEHAVE_FORWARD_ANY,
 227         },
 228         [CGT_HCR_NV1_nNV2] = {
 229                 .index          = HCR_EL2,
 230                 .value          = HCR_NV | HCR_NV1,
 231                 .mask           = HCR_NV | HCR_NV1 | HCR_NV2,
 232                 .behaviour      = BEHAVE_FORWARD_ANY,
 233         },
 234         [CGT_HCR_AT] = {
 235                 .index          = HCR_EL2,
 236                 .value          = HCR_AT,
 237                 .mask           = HCR_AT,
 238                 .behaviour      = BEHAVE_FORWARD_ANY,
 239         },
 240         [CGT_HCR_nFIEN] = {
 241                 .index          = HCR_EL2,
 242                 .value          = 0,
 243                 .mask           = HCR_FIEN,
 244                 .behaviour      = BEHAVE_FORWARD_ANY,
 245         },
 246         [CGT_HCR_TID4] = {
 247                 .index          = HCR_EL2,
 248                 .value          = HCR_TID4,
 249                 .mask           = HCR_TID4,
 250                 .behaviour      = BEHAVE_FORWARD_ANY,
 251         },
 252         [CGT_HCR_TICAB] = {
 253                 .index          = HCR_EL2,
 254                 .value          = HCR_TICAB,
 255                 .mask           = HCR_TICAB,
 256                 .behaviour      = BEHAVE_FORWARD_ANY,
 257         },
 258         [CGT_HCR_TOCU] = {
 259                 .index          = HCR_EL2,
 260                 .value          = HCR_TOCU,
 261                 .mask           = HCR_TOCU,
 262                 .behaviour      = BEHAVE_FORWARD_ANY,
 263         },
 264         [CGT_HCR_ENSCXT] = {
 265                 .index          = HCR_EL2,
 266                 .value          = 0,
 267                 .mask           = HCR_ENSCXT,
 268                 .behaviour      = BEHAVE_FORWARD_ANY,
 269         },
 270         [CGT_HCR_TTLBIS] = {
 271                 .index          = HCR_EL2,
 272                 .value          = HCR_TTLBIS,
 273                 .mask           = HCR_TTLBIS,
 274                 .behaviour      = BEHAVE_FORWARD_ANY,
 275         },
 276         [CGT_HCR_TTLBOS] = {
 277                 .index          = HCR_EL2,
 278                 .value          = HCR_TTLBOS,
 279                 .mask           = HCR_TTLBOS,
 280                 .behaviour      = BEHAVE_FORWARD_ANY,
 281         },
 282         [CGT_MDCR_TPMCR] = {
 283                 .index          = MDCR_EL2,
 284                 .value          = MDCR_EL2_TPMCR,
 285                 .mask           = MDCR_EL2_TPMCR,
 286                 .behaviour      = BEHAVE_FORWARD_ANY,
 287         },
 288         [CGT_MDCR_TPM] = {
 289                 .index          = MDCR_EL2,
 290                 .value          = MDCR_EL2_TPM,
 291                 .mask           = MDCR_EL2_TPM,
 292                 .behaviour      = BEHAVE_FORWARD_ANY,
 293         },
 294         [CGT_MDCR_TDE] = {
 295                 .index          = MDCR_EL2,
 296                 .value          = MDCR_EL2_TDE,
 297                 .mask           = MDCR_EL2_TDE,
 298                 .behaviour      = BEHAVE_FORWARD_ANY,
 299         },
 300         [CGT_MDCR_TDA] = {
 301                 .index          = MDCR_EL2,
 302                 .value          = MDCR_EL2_TDA,
 303                 .mask           = MDCR_EL2_TDA,
 304                 .behaviour      = BEHAVE_FORWARD_ANY,
 305         },
 306         [CGT_MDCR_TDOSA] = {
 307                 .index          = MDCR_EL2,
 308                 .value          = MDCR_EL2_TDOSA,
 309                 .mask           = MDCR_EL2_TDOSA,
 310                 .behaviour      = BEHAVE_FORWARD_ANY,
 311         },
 312         [CGT_MDCR_TDRA] = {
 313                 .index          = MDCR_EL2,
 314                 .value          = MDCR_EL2_TDRA,
 315                 .mask           = MDCR_EL2_TDRA,
 316                 .behaviour      = BEHAVE_FORWARD_ANY,
 317         },
 318         [CGT_MDCR_E2PB] = {
 319                 .index          = MDCR_EL2,
 320                 .value          = 0,
 321                 .mask           = BIT(MDCR_EL2_E2PB_SHIFT),
 322                 .behaviour      = BEHAVE_FORWARD_ANY,
 323         },
 324         [CGT_MDCR_TPMS] = {
 325                 .index          = MDCR_EL2,
 326                 .value          = MDCR_EL2_TPMS,
 327                 .mask           = MDCR_EL2_TPMS,
 328                 .behaviour      = BEHAVE_FORWARD_ANY,
 329         },
 330         [CGT_MDCR_TTRF] = {
 331                 .index          = MDCR_EL2,
 332                 .value          = MDCR_EL2_TTRF,
 333                 .mask           = MDCR_EL2_TTRF,
 334                 .behaviour      = BEHAVE_FORWARD_ANY,
 335         },
 336         [CGT_MDCR_E2TB] = {
 337                 .index          = MDCR_EL2,
 338                 .value          = 0,
 339                 .mask           = BIT(MDCR_EL2_E2TB_SHIFT),
 340                 .behaviour      = BEHAVE_FORWARD_ANY,
 341         },
 342         [CGT_MDCR_TDCC] = {
 343                 .index          = MDCR_EL2,
 344                 .value          = MDCR_EL2_TDCC,
 345                 .mask           = MDCR_EL2_TDCC,
 346                 .behaviour      = BEHAVE_FORWARD_ANY,
 347         },
 348 };
 349
 350 #define MCB(id, ...)                                            \
 351         [id - __MULTIPLE_CONTROL_BITS__]        =               \
 352                 (const enum cgt_group_id[]){                    \
 353                 __VA_ARGS__, __RESERVED__                       \
 354                 }
 355
 356 static const enum cgt_group_id *coarse_control_combo[] = {
 357         MCB(CGT_HCR_IMO_FMO,            CGT_HCR_IMO, CGT_HCR_FMO),
 358         MCB(CGT_HCR_TID2_TID4,          CGT_HCR_TID2, CGT_HCR_TID4),
 359         MCB(CGT_HCR_TTLB_TTLBIS,        CGT_HCR_TTLB, CGT_HCR_TTLBIS),
 360         MCB(CGT_HCR_TTLB_TTLBOS,        CGT_HCR_TTLB, CGT_HCR_TTLBOS),
 361         MCB(CGT_HCR_TVM_TRVM,           CGT_HCR_TVM, CGT_HCR_TRVM),
 362         MCB(CGT_HCR_TPU_TICAB,          CGT_HCR_TPU, CGT_HCR_TICAB),
 363         MCB(CGT_HCR_TPU_TOCU,           CGT_HCR_TPU, CGT_HCR_TOCU),
 364         MCB(CGT_HCR_NV1_nNV2_ENSCXT,    CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT),
 365         MCB(CGT_MDCR_TPM_TPMCR,         CGT_MDCR_TPM, CGT_MDCR_TPMCR),
 366         MCB(CGT_MDCR_TDE_TDA,           CGT_MDCR_TDE, CGT_MDCR_TDA),
 367         MCB(CGT_MDCR_TDE_TDOSA,         CGT_MDCR_TDE, CGT_MDCR_TDOSA),
 368         MCB(CGT_MDCR_TDE_TDRA,          CGT_MDCR_TDE, CGT_MDCR_TDRA),
 369         MCB(CGT_MDCR_TDCC_TDE_TDA,      CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA),
 370 };
 371
 372 typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *);
 373
 374 /*
 375  * Warning, maximum confusion ahead.
 376  *
 377  * When E2H=0, CNTHCTL_EL2[1:0] are defined as EL1PCEN:EL1PCTEN
 378  * When E2H=1, CNTHCTL_EL2[11:10] are defined as EL1PTEN:EL1PCTEN
 379  *
 380  * Note the single letter difference? Yet, the bits have the same
 381  * function despite a different layout and a different name.
 382  *
 383  * We don't try to reconcile this mess. We just use the E2H=0 bits
 384  * to generate something that is in the E2H=1 format, and live with
 385  * it. You're welcome.
 386  */
 387 static u64 get_sanitized_cnthctl(struct kvm_vcpu *vcpu)
 388 {
 389         u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
 390
 391         if (!vcpu_el2_e2h_is_set(vcpu))
 392                 val = (val & (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN)) << 10;
 393
 394         return val & ((CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10);
 395 }
 396
 397 static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu)
 398 {
 399         if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10))
 400                 return BEHAVE_HANDLE_LOCALLY;
 401
 402         return BEHAVE_FORWARD_ANY;
 403 }
 404
 405 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu)
 406 {
 407         if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10))
 408                 return BEHAVE_HANDLE_LOCALLY;
 409
 410         return BEHAVE_FORWARD_ANY;
 411 }
 412
 413 #define CCC(id, fn)                             \
 414         [id - __COMPLEX_CONDITIONS__] = fn
 415
 416 static const complex_condition_check ccc[] = {
 417         CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten),
 418         CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten),
 419 };
 420
 421 /*
 422  * Bit assignment for the trap controls. We use a 64bit word with the
 423  * following layout for each trapped sysreg:
 424  *
 425  * [9:0]        enum cgt_group_id (10 bits)
 426  * [13:10]      enum fgt_group_id (4 bits)
 427  * [19:14]      bit number in the FGT register (6 bits)
 428  * [20]         trap polarity (1 bit)
 429  * [62:21]      Unused (42 bits)
 430  * [63]         RES0 - Must be zero, as lost on insertion in the xarray
 431  */
 432 #define TC_CGT_BITS     10
 433 #define TC_FGT_BITS     4
 434
 435 union trap_config {
 436         u64     val;
 437         struct {
 438                 unsigned long   cgt:TC_CGT_BITS; /* Coarse Grained Trap id */
 439                 unsigned long   fgt:TC_FGT_BITS; /* Fine Grained Trap id */
 440                 unsigned long   bit:6;           /* Bit number */
 441                 unsigned long   pol:1;           /* Polarity */
 442                 unsigned long   unused:42;       /* Unused, should be zero */
 443                 unsigned long   mbz:1;           /* Must Be Zero */
 444         };
 445 };
 446
 447 struct encoding_to_trap_config {
 448         const u32                       encoding;
 449         const u32                       end;
 450         const union trap_config         tc;
 451         const unsigned int              line;
 452 };
 453
 454 #define SR_RANGE_TRAP(sr_start, sr_end, trap_id)                        \
 455         {                                                               \
 456                 .encoding       = sr_start,                             \
 457                 .end            = sr_end,                               \
 458                 .tc             = {                                     \
 459                         .cgt            = trap_id,                      \
 460                 },                                                      \
 461                 .line = __LINE__,                                       \
 462         }
 463
 464 #define SR_TRAP(sr, trap_id)            SR_RANGE_TRAP(sr, sr, trap_id)
 465
 466 /*
 467  * Map encoding to trap bits for exception reported with EC=0x18.
 468  * These must only be evaluated when running a nested hypervisor, but
 469  * that the current context is not a hypervisor context. When the
 470  * trapped access matches one of the trap controls, the exception is
 471  * re-injected in the nested hypervisor.
 472  */
 473 static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
 474         SR_TRAP(SYS_REVIDR_EL1,         CGT_HCR_TID1),
 475         SR_TRAP(SYS_AIDR_EL1,           CGT_HCR_TID1),
 476         SR_TRAP(SYS_SMIDR_EL1,          CGT_HCR_TID1),
 477         SR_TRAP(SYS_CTR_EL0,            CGT_HCR_TID2),
 478         SR_TRAP(SYS_CCSIDR_EL1,         CGT_HCR_TID2_TID4),
 479         SR_TRAP(SYS_CCSIDR2_EL1,        CGT_HCR_TID2_TID4),
 480         SR_TRAP(SYS_CLIDR_EL1,          CGT_HCR_TID2_TID4),
 481         SR_TRAP(SYS_CSSELR_EL1,         CGT_HCR_TID2_TID4),
 482         SR_RANGE_TRAP(SYS_ID_PFR0_EL1,
 483                       sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3),
 484         SR_TRAP(SYS_ICC_SGI0R_EL1,      CGT_HCR_IMO_FMO),
 485         SR_TRAP(SYS_ICC_ASGI1R_EL1,     CGT_HCR_IMO_FMO),
 486         SR_TRAP(SYS_ICC_SGI1R_EL1,      CGT_HCR_IMO_FMO),
 487         SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0),
 488                       sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP),
 489         SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0),
 490                       sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP),
 491         SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0),
 492                       sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP),
 493         SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0),
 494                       sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP),
 495         SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0),
 496                       sys_reg(3, 4, 11, 15, 7), CGT_HCR_TIDCP),
 497         SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0),
 498                       sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP),
 499         SR_RANGE_TRAP(sys_reg(3, 6, 11, 0, 0),
 500                       sys_reg(3, 6, 11, 15, 7), CGT_HCR_TIDCP),
 501         SR_RANGE_TRAP(sys_reg(3, 7, 11, 0, 0),
 502                       sys_reg(3, 7, 11, 15, 7), CGT_HCR_TIDCP),
 503         SR_RANGE_TRAP(sys_reg(3, 0, 15, 0, 0),
 504                       sys_reg(3, 0, 15, 15, 7), CGT_HCR_TIDCP),
 505         SR_RANGE_TRAP(sys_reg(3, 1, 15, 0, 0),
 506                       sys_reg(3, 1, 15, 15, 7), CGT_HCR_TIDCP),
 507         SR_RANGE_TRAP(sys_reg(3, 2, 15, 0, 0),
 508                       sys_reg(3, 2, 15, 15, 7), CGT_HCR_TIDCP),
 509         SR_RANGE_TRAP(sys_reg(3, 3, 15, 0, 0),
 510                       sys_reg(3, 3, 15, 15, 7), CGT_HCR_TIDCP),
 511         SR_RANGE_TRAP(sys_reg(3, 4, 15, 0, 0),
 512                       sys_reg(3, 4, 15, 15, 7), CGT_HCR_TIDCP),
 513         SR_RANGE_TRAP(sys_reg(3, 5, 15, 0, 0),
 514                       sys_reg(3, 5, 15, 15, 7), CGT_HCR_TIDCP),
 515         SR_RANGE_TRAP(sys_reg(3, 6, 15, 0, 0),
 516                       sys_reg(3, 6, 15, 15, 7), CGT_HCR_TIDCP),
 517         SR_RANGE_TRAP(sys_reg(3, 7, 15, 0, 0),
 518                       sys_reg(3, 7, 15, 15, 7), CGT_HCR_TIDCP),
 519         SR_TRAP(SYS_ACTLR_EL1,          CGT_HCR_TACR),
 520         SR_TRAP(SYS_DC_ISW,             CGT_HCR_TSW),
 521         SR_TRAP(SYS_DC_CSW,             CGT_HCR_TSW),
 522         SR_TRAP(SYS_DC_CISW,            CGT_HCR_TSW),
 523         SR_TRAP(SYS_DC_IGSW,            CGT_HCR_TSW),
 524         SR_TRAP(SYS_DC_IGDSW,           CGT_HCR_TSW),
 525         SR_TRAP(SYS_DC_CGSW,            CGT_HCR_TSW),
 526         SR_TRAP(SYS_DC_CGDSW,           CGT_HCR_TSW),
 527         SR_TRAP(SYS_DC_CIGSW,           CGT_HCR_TSW),
 528         SR_TRAP(SYS_DC_CIGDSW,          CGT_HCR_TSW),
 529         SR_TRAP(SYS_DC_CIVAC,           CGT_HCR_TPC),
 530         SR_TRAP(SYS_DC_CVAC,            CGT_HCR_TPC),
 531         SR_TRAP(SYS_DC_CVAP,            CGT_HCR_TPC),
 532         SR_TRAP(SYS_DC_CVADP,           CGT_HCR_TPC),
 533         SR_TRAP(SYS_DC_IVAC,            CGT_HCR_TPC),
 534         SR_TRAP(SYS_DC_CIGVAC,          CGT_HCR_TPC),
 535         SR_TRAP(SYS_DC_CIGDVAC,         CGT_HCR_TPC),
 536         SR_TRAP(SYS_DC_IGVAC,           CGT_HCR_TPC),
 537         SR_TRAP(SYS_DC_IGDVAC,          CGT_HCR_TPC),
 538         SR_TRAP(SYS_DC_CGVAC,           CGT_HCR_TPC),
 539         SR_TRAP(SYS_DC_CGDVAC,          CGT_HCR_TPC),
 540         SR_TRAP(SYS_DC_CGVAP,           CGT_HCR_TPC),
 541         SR_TRAP(SYS_DC_CGDVAP,          CGT_HCR_TPC),
 542         SR_TRAP(SYS_DC_CGVADP,          CGT_HCR_TPC),
 543         SR_TRAP(SYS_DC_CGDVADP,         CGT_HCR_TPC),
 544         SR_TRAP(SYS_IC_IVAU,            CGT_HCR_TPU_TOCU),
 545         SR_TRAP(SYS_IC_IALLU,           CGT_HCR_TPU_TOCU),
 546         SR_TRAP(SYS_IC_IALLUIS,         CGT_HCR_TPU_TICAB),
 547         SR_TRAP(SYS_DC_CVAU,            CGT_HCR_TPU_TOCU),
 548         SR_TRAP(OP_TLBI_RVAE1,          CGT_HCR_TTLB),
 549         SR_TRAP(OP_TLBI_RVAAE1,         CGT_HCR_TTLB),
 550         SR_TRAP(OP_TLBI_RVALE1,         CGT_HCR_TTLB),
 551         SR_TRAP(OP_TLBI_RVAALE1,        CGT_HCR_TTLB),
 552         SR_TRAP(OP_TLBI_VMALLE1,        CGT_HCR_TTLB),
 553         SR_TRAP(OP_TLBI_VAE1,           CGT_HCR_TTLB),
 554         SR_TRAP(OP_TLBI_ASIDE1,         CGT_HCR_TTLB),
 555         SR_TRAP(OP_TLBI_VAAE1,          CGT_HCR_TTLB),
 556         SR_TRAP(OP_TLBI_VALE1,          CGT_HCR_TTLB),
 557         SR_TRAP(OP_TLBI_VAALE1,         CGT_HCR_TTLB),
 558         SR_TRAP(OP_TLBI_RVAE1NXS,       CGT_HCR_TTLB),
 559         SR_TRAP(OP_TLBI_RVAAE1NXS,      CGT_HCR_TTLB),
 560         SR_TRAP(OP_TLBI_RVALE1NXS,      CGT_HCR_TTLB),
 561         SR_TRAP(OP_TLBI_RVAALE1NXS,     CGT_HCR_TTLB),
 562         SR_TRAP(OP_TLBI_VMALLE1NXS,     CGT_HCR_TTLB),
 563         SR_TRAP(OP_TLBI_VAE1NXS,        CGT_HCR_TTLB),
 564         SR_TRAP(OP_TLBI_ASIDE1NXS,      CGT_HCR_TTLB),
 565         SR_TRAP(OP_TLBI_VAAE1NXS,       CGT_HCR_TTLB),
 566         SR_TRAP(OP_TLBI_VALE1NXS,       CGT_HCR_TTLB),
 567         SR_TRAP(OP_TLBI_VAALE1NXS,      CGT_HCR_TTLB),
 568         SR_TRAP(OP_TLBI_RVAE1IS,        CGT_HCR_TTLB_TTLBIS),
 569         SR_TRAP(OP_TLBI_RVAAE1IS,       CGT_HCR_TTLB_TTLBIS),
 570         SR_TRAP(OP_TLBI_RVALE1IS,       CGT_HCR_TTLB_TTLBIS),
 571         SR_TRAP(OP_TLBI_RVAALE1IS,      CGT_HCR_TTLB_TTLBIS),
 572         SR_TRAP(OP_TLBI_VMALLE1IS,      CGT_HCR_TTLB_TTLBIS),
 573         SR_TRAP(OP_TLBI_VAE1IS,         CGT_HCR_TTLB_TTLBIS),
 574         SR_TRAP(OP_TLBI_ASIDE1IS,       CGT_HCR_TTLB_TTLBIS),
 575         SR_TRAP(OP_TLBI_VAAE1IS,        CGT_HCR_TTLB_TTLBIS),
 576         SR_TRAP(OP_TLBI_VALE1IS,        CGT_HCR_TTLB_TTLBIS),
 577         SR_TRAP(OP_TLBI_VAALE1IS,       CGT_HCR_TTLB_TTLBIS),
 578         SR_TRAP(OP_TLBI_RVAE1ISNXS,     CGT_HCR_TTLB_TTLBIS),
 579         SR_TRAP(OP_TLBI_RVAAE1ISNXS,    CGT_HCR_TTLB_TTLBIS),
 580         SR_TRAP(OP_TLBI_RVALE1ISNXS,    CGT_HCR_TTLB_TTLBIS),
 581         SR_TRAP(OP_TLBI_RVAALE1ISNXS,   CGT_HCR_TTLB_TTLBIS),
 582         SR_TRAP(OP_TLBI_VMALLE1ISNXS,   CGT_HCR_TTLB_TTLBIS),
 583         SR_TRAP(OP_TLBI_VAE1ISNXS,      CGT_HCR_TTLB_TTLBIS),
 584         SR_TRAP(OP_TLBI_ASIDE1ISNXS,    CGT_HCR_TTLB_TTLBIS),
 585         SR_TRAP(OP_TLBI_VAAE1ISNXS,     CGT_HCR_TTLB_TTLBIS),
 586         SR_TRAP(OP_TLBI_VALE1ISNXS,     CGT_HCR_TTLB_TTLBIS),
 587         SR_TRAP(OP_TLBI_VAALE1ISNXS,    CGT_HCR_TTLB_TTLBIS),
 588         SR_TRAP(OP_TLBI_VMALLE1OS,      CGT_HCR_TTLB_TTLBOS),
 589         SR_TRAP(OP_TLBI_VAE1OS,         CGT_HCR_TTLB_TTLBOS),
 590         SR_TRAP(OP_TLBI_ASIDE1OS,       CGT_HCR_TTLB_TTLBOS),
 591         SR_TRAP(OP_TLBI_VAAE1OS,        CGT_HCR_TTLB_TTLBOS),
 592         SR_TRAP(OP_TLBI_VALE1OS,        CGT_HCR_TTLB_TTLBOS),
 593         SR_TRAP(OP_TLBI_VAALE1OS,       CGT_HCR_TTLB_TTLBOS),
 594         SR_TRAP(OP_TLBI_RVAE1OS,        CGT_HCR_TTLB_TTLBOS),
 595         SR_TRAP(OP_TLBI_RVAAE1OS,       CGT_HCR_TTLB_TTLBOS),
 596         SR_TRAP(OP_TLBI_RVALE1OS,       CGT_HCR_TTLB_TTLBOS),
 597         SR_TRAP(OP_TLBI_RVAALE1OS,      CGT_HCR_TTLB_TTLBOS),
 598         SR_TRAP(OP_TLBI_VMALLE1OSNXS,   CGT_HCR_TTLB_TTLBOS),
 599         SR_TRAP(OP_TLBI_VAE1OSNXS,      CGT_HCR_TTLB_TTLBOS),
 600         SR_TRAP(OP_TLBI_ASIDE1OSNXS,    CGT_HCR_TTLB_TTLBOS),
 601         SR_TRAP(OP_TLBI_VAAE1OSNXS,     CGT_HCR_TTLB_TTLBOS),
 602         SR_TRAP(OP_TLBI_VALE1OSNXS,     CGT_HCR_TTLB_TTLBOS),
 603         SR_TRAP(OP_TLBI_VAALE1OSNXS,    CGT_HCR_TTLB_TTLBOS),
 604         SR_TRAP(OP_TLBI_RVAE1OSNXS,     CGT_HCR_TTLB_TTLBOS),
 605         SR_TRAP(OP_TLBI_RVAAE1OSNXS,    CGT_HCR_TTLB_TTLBOS),
 606         SR_TRAP(OP_TLBI_RVALE1OSNXS,    CGT_HCR_TTLB_TTLBOS),
 607         SR_TRAP(OP_TLBI_RVAALE1OSNXS,   CGT_HCR_TTLB_TTLBOS),
 608         SR_TRAP(SYS_SCTLR_EL1,          CGT_HCR_TVM_TRVM),
 609         SR_TRAP(SYS_TTBR0_EL1,          CGT_HCR_TVM_TRVM),
 610         SR_TRAP(SYS_TTBR1_EL1,          CGT_HCR_TVM_TRVM),
 611         SR_TRAP(SYS_TCR_EL1,            CGT_HCR_TVM_TRVM),
 612         SR_TRAP(SYS_ESR_EL1,            CGT_HCR_TVM_TRVM),
 613         SR_TRAP(SYS_FAR_EL1,            CGT_HCR_TVM_TRVM),
 614         SR_TRAP(SYS_AFSR0_EL1,          CGT_HCR_TVM_TRVM),
 615         SR_TRAP(SYS_AFSR1_EL1,          CGT_HCR_TVM_TRVM),
 616         SR_TRAP(SYS_MAIR_EL1,           CGT_HCR_TVM_TRVM),
 617         SR_TRAP(SYS_AMAIR_EL1,          CGT_HCR_TVM_TRVM),
 618         SR_TRAP(SYS_CONTEXTIDR_EL1,     CGT_HCR_TVM_TRVM),
 619         SR_TRAP(SYS_DC_ZVA,             CGT_HCR_TDZ),
 620         SR_TRAP(SYS_DC_GVA,             CGT_HCR_TDZ),
 621         SR_TRAP(SYS_DC_GZVA,            CGT_HCR_TDZ),
 622         SR_TRAP(SYS_LORSA_EL1,          CGT_HCR_TLOR),
 623         SR_TRAP(SYS_LOREA_EL1,          CGT_HCR_TLOR),
 624         SR_TRAP(SYS_LORN_EL1,           CGT_HCR_TLOR),
 625         SR_TRAP(SYS_LORC_EL1,           CGT_HCR_TLOR),
 626         SR_TRAP(SYS_LORID_EL1,          CGT_HCR_TLOR),
 627         SR_TRAP(SYS_ERRIDR_EL1,         CGT_HCR_TERR),
 628         SR_TRAP(SYS_ERRSELR_EL1,        CGT_HCR_TERR),
 629         SR_TRAP(SYS_ERXADDR_EL1,        CGT_HCR_TERR),
 630         SR_TRAP(SYS_ERXCTLR_EL1,        CGT_HCR_TERR),
 631         SR_TRAP(SYS_ERXFR_EL1,          CGT_HCR_TERR),
 632         SR_TRAP(SYS_ERXMISC0_EL1,       CGT_HCR_TERR),
 633         SR_TRAP(SYS_ERXMISC1_EL1,       CGT_HCR_TERR),
 634         SR_TRAP(SYS_ERXMISC2_EL1,       CGT_HCR_TERR),
 635         SR_TRAP(SYS_ERXMISC3_EL1,       CGT_HCR_TERR),
 636         SR_TRAP(SYS_ERXSTATUS_EL1,      CGT_HCR_TERR),
 637         SR_TRAP(SYS_APIAKEYLO_EL1,      CGT_HCR_APK),
 638         SR_TRAP(SYS_APIAKEYHI_EL1,      CGT_HCR_APK),
 639         SR_TRAP(SYS_APIBKEYLO_EL1,      CGT_HCR_APK),
 640         SR_TRAP(SYS_APIBKEYHI_EL1,      CGT_HCR_APK),
 641         SR_TRAP(SYS_APDAKEYLO_EL1,      CGT_HCR_APK),
 642         SR_TRAP(SYS_APDAKEYHI_EL1,      CGT_HCR_APK),
 643         SR_TRAP(SYS_APDBKEYLO_EL1,      CGT_HCR_APK),
 644         SR_TRAP(SYS_APDBKEYHI_EL1,      CGT_HCR_APK),
 645         SR_TRAP(SYS_APGAKEYLO_EL1,      CGT_HCR_APK),
 646         SR_TRAP(SYS_APGAKEYHI_EL1,      CGT_HCR_APK),
 647         /* All _EL2 registers */
 648         SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),
 649                       sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),
 650         /* Skip the SP_EL1 encoding... */
 651         SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),
 652                       sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),
 653         SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),
 654                       sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),
 655         /* All _EL02, _EL12 registers */
 656         SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
 657                       sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
 658         SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
 659                       sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
 660         SR_TRAP(OP_AT_S1E2R,            CGT_HCR_NV),
 661         SR_TRAP(OP_AT_S1E2W,            CGT_HCR_NV),
 662         SR_TRAP(OP_AT_S12E1R,           CGT_HCR_NV),
 663         SR_TRAP(OP_AT_S12E1W,           CGT_HCR_NV),
 664         SR_TRAP(OP_AT_S12E0R,           CGT_HCR_NV),
 665         SR_TRAP(OP_AT_S12E0W,           CGT_HCR_NV),
 666         SR_TRAP(OP_TLBI_IPAS2E1,        CGT_HCR_NV),
 667         SR_TRAP(OP_TLBI_RIPAS2E1,       CGT_HCR_NV),
 668         SR_TRAP(OP_TLBI_IPAS2LE1,       CGT_HCR_NV),
 669         SR_TRAP(OP_TLBI_RIPAS2LE1,      CGT_HCR_NV),
 670         SR_TRAP(OP_TLBI_RVAE2,          CGT_HCR_NV),
 671         SR_TRAP(OP_TLBI_RVALE2,         CGT_HCR_NV),
 672         SR_TRAP(OP_TLBI_ALLE2,          CGT_HCR_NV),
 673         SR_TRAP(OP_TLBI_VAE2,           CGT_HCR_NV),
 674         SR_TRAP(OP_TLBI_ALLE1,          CGT_HCR_NV),
 675         SR_TRAP(OP_TLBI_VALE2,          CGT_HCR_NV),
 676         SR_TRAP(OP_TLBI_VMALLS12E1,     CGT_HCR_NV),
 677         SR_TRAP(OP_TLBI_IPAS2E1NXS,     CGT_HCR_NV),
 678         SR_TRAP(OP_TLBI_RIPAS2E1NXS,    CGT_HCR_NV),
 679         SR_TRAP(OP_TLBI_IPAS2LE1NXS,    CGT_HCR_NV),
 680         SR_TRAP(OP_TLBI_RIPAS2LE1NXS,   CGT_HCR_NV),
 681         SR_TRAP(OP_TLBI_RVAE2NXS,       CGT_HCR_NV),
 682         SR_TRAP(OP_TLBI_RVALE2NXS,      CGT_HCR_NV),
 683         SR_TRAP(OP_TLBI_ALLE2NXS,       CGT_HCR_NV),
 684         SR_TRAP(OP_TLBI_VAE2NXS,        CGT_HCR_NV),
 685         SR_TRAP(OP_TLBI_ALLE1NXS,       CGT_HCR_NV),
 686         SR_TRAP(OP_TLBI_VALE2NXS,       CGT_HCR_NV),
 687         SR_TRAP(OP_TLBI_VMALLS12E1NXS,  CGT_HCR_NV),
 688         SR_TRAP(OP_TLBI_IPAS2E1IS,      CGT_HCR_NV),
 689         SR_TRAP(OP_TLBI_RIPAS2E1IS,     CGT_HCR_NV),
 690         SR_TRAP(OP_TLBI_IPAS2LE1IS,     CGT_HCR_NV),
 691         SR_TRAP(OP_TLBI_RIPAS2LE1IS,    CGT_HCR_NV),
 692         SR_TRAP(OP_TLBI_RVAE2IS,        CGT_HCR_NV),
 693         SR_TRAP(OP_TLBI_RVALE2IS,       CGT_HCR_NV),
 694         SR_TRAP(OP_TLBI_ALLE2IS,        CGT_HCR_NV),
 695         SR_TRAP(OP_TLBI_VAE2IS,         CGT_HCR_NV),
 696         SR_TRAP(OP_TLBI_ALLE1IS,        CGT_HCR_NV),
 697         SR_TRAP(OP_TLBI_VALE2IS,        CGT_HCR_NV),
 698         SR_TRAP(OP_TLBI_VMALLS12E1IS,   CGT_HCR_NV),
 699         SR_TRAP(OP_TLBI_IPAS2E1ISNXS,   CGT_HCR_NV),
 700         SR_TRAP(OP_TLBI_RIPAS2E1ISNXS,  CGT_HCR_NV),
 701         SR_TRAP(OP_TLBI_IPAS2LE1ISNXS,  CGT_HCR_NV),
 702         SR_TRAP(OP_TLBI_RIPAS2LE1ISNXS, CGT_HCR_NV),
 703         SR_TRAP(OP_TLBI_RVAE2ISNXS,     CGT_HCR_NV),
 704         SR_TRAP(OP_TLBI_RVALE2ISNXS,    CGT_HCR_NV),
 705         SR_TRAP(OP_TLBI_ALLE2ISNXS,     CGT_HCR_NV),
 706         SR_TRAP(OP_TLBI_VAE2ISNXS,      CGT_HCR_NV),
 707         SR_TRAP(OP_TLBI_ALLE1ISNXS,     CGT_HCR_NV),
 708         SR_TRAP(OP_TLBI_VALE2ISNXS,     CGT_HCR_NV),
 709         SR_TRAP(OP_TLBI_VMALLS12E1ISNXS,CGT_HCR_NV),
 710         SR_TRAP(OP_TLBI_ALLE2OS,        CGT_HCR_NV),
 711         SR_TRAP(OP_TLBI_VAE2OS,         CGT_HCR_NV),
 712         SR_TRAP(OP_TLBI_ALLE1OS,        CGT_HCR_NV),
 713         SR_TRAP(OP_TLBI_VALE2OS,        CGT_HCR_NV),
 714         SR_TRAP(OP_TLBI_VMALLS12E1OS,   CGT_HCR_NV),
 715         SR_TRAP(OP_TLBI_IPAS2E1OS,      CGT_HCR_NV),
 716         SR_TRAP(OP_TLBI_RIPAS2E1OS,     CGT_HCR_NV),
 717         SR_TRAP(OP_TLBI_IPAS2LE1OS,     CGT_HCR_NV),
 718         SR_TRAP(OP_TLBI_RIPAS2LE1OS,    CGT_HCR_NV),
 719         SR_TRAP(OP_TLBI_RVAE2OS,        CGT_HCR_NV),
 720         SR_TRAP(OP_TLBI_RVALE2OS,       CGT_HCR_NV),
 721         SR_TRAP(OP_TLBI_ALLE2OSNXS,     CGT_HCR_NV),
 722         SR_TRAP(OP_TLBI_VAE2OSNXS,      CGT_HCR_NV),
 723         SR_TRAP(OP_TLBI_ALLE1OSNXS,     CGT_HCR_NV),
 724         SR_TRAP(OP_TLBI_VALE2OSNXS,     CGT_HCR_NV),
 725         SR_TRAP(OP_TLBI_VMALLS12E1OSNXS,CGT_HCR_NV),
 726         SR_TRAP(OP_TLBI_IPAS2E1OSNXS,   CGT_HCR_NV),
 727         SR_TRAP(OP_TLBI_RIPAS2E1OSNXS,  CGT_HCR_NV),
 728         SR_TRAP(OP_TLBI_IPAS2LE1OSNXS,  CGT_HCR_NV),
 729         SR_TRAP(OP_TLBI_RIPAS2LE1OSNXS, CGT_HCR_NV),
 730         SR_TRAP(OP_TLBI_RVAE2OSNXS,     CGT_HCR_NV),
 731         SR_TRAP(OP_TLBI_RVALE2OSNXS,    CGT_HCR_NV),
 732         SR_TRAP(OP_CPP_RCTX,            CGT_HCR_NV),
 733         SR_TRAP(OP_DVP_RCTX,            CGT_HCR_NV),
 734         SR_TRAP(OP_CFP_RCTX,            CGT_HCR_NV),
 735         SR_TRAP(SYS_SP_EL1,             CGT_HCR_NV_nNV2),
 736         SR_TRAP(SYS_VBAR_EL1,           CGT_HCR_NV1_nNV2),
 737         SR_TRAP(SYS_ELR_EL1,            CGT_HCR_NV1_nNV2),
 738         SR_TRAP(SYS_SPSR_EL1,           CGT_HCR_NV1_nNV2),
 739         SR_TRAP(SYS_SCXTNUM_EL1,        CGT_HCR_NV1_nNV2_ENSCXT),
 740         SR_TRAP(SYS_SCXTNUM_EL0,        CGT_HCR_ENSCXT),
 741         SR_TRAP(OP_AT_S1E1R,            CGT_HCR_AT),
 742         SR_TRAP(OP_AT_S1E1W,            CGT_HCR_AT),
 743         SR_TRAP(OP_AT_S1E0R,            CGT_HCR_AT),
 744         SR_TRAP(OP_AT_S1E0W,            CGT_HCR_AT),
 745         SR_TRAP(OP_AT_S1E1RP,           CGT_HCR_AT),
 746         SR_TRAP(OP_AT_S1E1WP,           CGT_HCR_AT),
 747         SR_TRAP(SYS_ERXPFGF_EL1,        CGT_HCR_nFIEN),
 748         SR_TRAP(SYS_ERXPFGCTL_EL1,      CGT_HCR_nFIEN),
 749         SR_TRAP(SYS_ERXPFGCDN_EL1,      CGT_HCR_nFIEN),
 750         SR_TRAP(SYS_PMCR_EL0,           CGT_MDCR_TPM_TPMCR),
 751         SR_TRAP(SYS_PMCNTENSET_EL0,     CGT_MDCR_TPM),
 752         SR_TRAP(SYS_PMCNTENCLR_EL0,     CGT_MDCR_TPM),
 753         SR_TRAP(SYS_PMOVSSET_EL0,       CGT_MDCR_TPM),
 754         SR_TRAP(SYS_PMOVSCLR_EL0,       CGT_MDCR_TPM),
 755         SR_TRAP(SYS_PMCEID0_EL0,        CGT_MDCR_TPM),
 756         SR_TRAP(SYS_PMCEID1_EL0,        CGT_MDCR_TPM),
 757         SR_TRAP(SYS_PMXEVTYPER_EL0,     CGT_MDCR_TPM),
 758         SR_TRAP(SYS_PMSWINC_EL0,        CGT_MDCR_TPM),
 759         SR_TRAP(SYS_PMSELR_EL0,         CGT_MDCR_TPM),
 760         SR_TRAP(SYS_PMXEVCNTR_EL0,      CGT_MDCR_TPM),
 761         SR_TRAP(SYS_PMCCNTR_EL0,        CGT_MDCR_TPM),
 762         SR_TRAP(SYS_PMUSERENR_EL0,      CGT_MDCR_TPM),
 763         SR_TRAP(SYS_PMINTENSET_EL1,     CGT_MDCR_TPM),
 764         SR_TRAP(SYS_PMINTENCLR_EL1,     CGT_MDCR_TPM),
 765         SR_TRAP(SYS_PMMIR_EL1,          CGT_MDCR_TPM),
 766         SR_TRAP(SYS_PMEVCNTRn_EL0(0),   CGT_MDCR_TPM),
 767         SR_TRAP(SYS_PMEVCNTRn_EL0(1),   CGT_MDCR_TPM),
 768         SR_TRAP(SYS_PMEVCNTRn_EL0(2),   CGT_MDCR_TPM),
 769         SR_TRAP(SYS_PMEVCNTRn_EL0(3),   CGT_MDCR_TPM),
 770         SR_TRAP(SYS_PMEVCNTRn_EL0(4),   CGT_MDCR_TPM),
 771         SR_TRAP(SYS_PMEVCNTRn_EL0(5),   CGT_MDCR_TPM),
 772         SR_TRAP(SYS_PMEVCNTRn_EL0(6),   CGT_MDCR_TPM),
 773         SR_TRAP(SYS_PMEVCNTRn_EL0(7),   CGT_MDCR_TPM),
 774         SR_TRAP(SYS_PMEVCNTRn_EL0(8),   CGT_MDCR_TPM),
 775         SR_TRAP(SYS_PMEVCNTRn_EL0(9),   CGT_MDCR_TPM),
 776         SR_TRAP(SYS_PMEVCNTRn_EL0(10),  CGT_MDCR_TPM),
 777         SR_TRAP(SYS_PMEVCNTRn_EL0(11),  CGT_MDCR_TPM),
 778         SR_TRAP(SYS_PMEVCNTRn_EL0(12),  CGT_MDCR_TPM),
 779         SR_TRAP(SYS_PMEVCNTRn_EL0(13),  CGT_MDCR_TPM),
 780         SR_TRAP(SYS_PMEVCNTRn_EL0(14),  CGT_MDCR_TPM),
 781         SR_TRAP(SYS_PMEVCNTRn_EL0(15),  CGT_MDCR_TPM),
 782         SR_TRAP(SYS_PMEVCNTRn_EL0(16),  CGT_MDCR_TPM),
 783         SR_TRAP(SYS_PMEVCNTRn_EL0(17),  CGT_MDCR_TPM),
 784         SR_TRAP(SYS_PMEVCNTRn_EL0(18),  CGT_MDCR_TPM),
 785         SR_TRAP(SYS_PMEVCNTRn_EL0(19),  CGT_MDCR_TPM),
 786         SR_TRAP(SYS_PMEVCNTRn_EL0(20),  CGT_MDCR_TPM),
 787         SR_TRAP(SYS_PMEVCNTRn_EL0(21),  CGT_MDCR_TPM),
 788         SR_TRAP(SYS_PMEVCNTRn_EL0(22),  CGT_MDCR_TPM),
 789         SR_TRAP(SYS_PMEVCNTRn_EL0(23),  CGT_MDCR_TPM),
 790         SR_TRAP(SYS_PMEVCNTRn_EL0(24),  CGT_MDCR_TPM),
 791         SR_TRAP(SYS_PMEVCNTRn_EL0(25),  CGT_MDCR_TPM),
 792         SR_TRAP(SYS_PMEVCNTRn_EL0(26),  CGT_MDCR_TPM),
 793         SR_TRAP(SYS_PMEVCNTRn_EL0(27),  CGT_MDCR_TPM),
 794         SR_TRAP(SYS_PMEVCNTRn_EL0(28),  CGT_MDCR_TPM),
 795         SR_TRAP(SYS_PMEVCNTRn_EL0(29),  CGT_MDCR_TPM),
 796         SR_TRAP(SYS_PMEVCNTRn_EL0(30),  CGT_MDCR_TPM),
 797         SR_TRAP(SYS_PMEVTYPERn_EL0(0),  CGT_MDCR_TPM),
 798         SR_TRAP(SYS_PMEVTYPERn_EL0(1),  CGT_MDCR_TPM),
 799         SR_TRAP(SYS_PMEVTYPERn_EL0(2),  CGT_MDCR_TPM),
 800         SR_TRAP(SYS_PMEVTYPERn_EL0(3),  CGT_MDCR_TPM),
 801         SR_TRAP(SYS_PMEVTYPERn_EL0(4),  CGT_MDCR_TPM),
 802         SR_TRAP(SYS_PMEVTYPERn_EL0(5),  CGT_MDCR_TPM),
 803         SR_TRAP(SYS_PMEVTYPERn_EL0(6),  CGT_MDCR_TPM),
 804         SR_TRAP(SYS_PMEVTYPERn_EL0(7),  CGT_MDCR_TPM),
 805         SR_TRAP(SYS_PMEVTYPERn_EL0(8),  CGT_MDCR_TPM),
 806         SR_TRAP(SYS_PMEVTYPERn_EL0(9),  CGT_MDCR_TPM),
 807         SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM),
 808         SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM),
 809         SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM),
 810         SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM),
 811         SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM),
 812         SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM),
 813         SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM),
 814         SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM),
 815         SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM),
 816         SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM),
 817         SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM),
 818         SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM),
 819         SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM),
 820         SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM),
 821         SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM),
 822         SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM),
 823         SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM),
 824         SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM),
 825         SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM),
 826         SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM),
 827         SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM),
 828         SR_TRAP(SYS_PMCCFILTR_EL0,      CGT_MDCR_TPM),
 829         SR_TRAP(SYS_MDCCSR_EL0,         CGT_MDCR_TDCC_TDE_TDA),
 830         SR_TRAP(SYS_MDCCINT_EL1,        CGT_MDCR_TDCC_TDE_TDA),
 831         SR_TRAP(SYS_OSDTRRX_EL1,        CGT_MDCR_TDCC_TDE_TDA),
 832         SR_TRAP(SYS_OSDTRTX_EL1,        CGT_MDCR_TDCC_TDE_TDA),
 833         SR_TRAP(SYS_DBGDTR_EL0,         CGT_MDCR_TDCC_TDE_TDA),
 834         /*
 835          * Also covers DBGDTRRX_EL0, which has the same encoding as
 836          * SYS_DBGDTRTX_EL0...
 837          */
 838         SR_TRAP(SYS_DBGDTRTX_EL0,       CGT_MDCR_TDCC_TDE_TDA),
 839         SR_TRAP(SYS_MDSCR_EL1,          CGT_MDCR_TDE_TDA),
 840         SR_TRAP(SYS_OSECCR_EL1,         CGT_MDCR_TDE_TDA),
 841         SR_TRAP(SYS_DBGBVRn_EL1(0),     CGT_MDCR_TDE_TDA),
 842         SR_TRAP(SYS_DBGBVRn_EL1(1),     CGT_MDCR_TDE_TDA),
 843         SR_TRAP(SYS_DBGBVRn_EL1(2),     CGT_MDCR_TDE_TDA),
 844         SR_TRAP(SYS_DBGBVRn_EL1(3),     CGT_MDCR_TDE_TDA),
 845         SR_TRAP(SYS_DBGBVRn_EL1(4),     CGT_MDCR_TDE_TDA),
 846         SR_TRAP(SYS_DBGBVRn_EL1(5),     CGT_MDCR_TDE_TDA),
 847         SR_TRAP(SYS_DBGBVRn_EL1(6),     CGT_MDCR_TDE_TDA),
 848         SR_TRAP(SYS_DBGBVRn_EL1(7),     CGT_MDCR_TDE_TDA),
 849         SR_TRAP(SYS_DBGBVRn_EL1(8),     CGT_MDCR_TDE_TDA),
 850         SR_TRAP(SYS_DBGBVRn_EL1(9),     CGT_MDCR_TDE_TDA),
 851         SR_TRAP(SYS_DBGBVRn_EL1(10),    CGT_MDCR_TDE_TDA),
 852         SR_TRAP(SYS_DBGBVRn_EL1(11),    CGT_MDCR_TDE_TDA),
 853         SR_TRAP(SYS_DBGBVRn_EL1(12),    CGT_MDCR_TDE_TDA),
 854         SR_TRAP(SYS_DBGBVRn_EL1(13),    CGT_MDCR_TDE_TDA),
 855         SR_TRAP(SYS_DBGBVRn_EL1(14),    CGT_MDCR_TDE_TDA),
 856         SR_TRAP(SYS_DBGBVRn_EL1(15),    CGT_MDCR_TDE_TDA),
 857         SR_TRAP(SYS_DBGBCRn_EL1(0),     CGT_MDCR_TDE_TDA),
 858         SR_TRAP(SYS_DBGBCRn_EL1(1),     CGT_MDCR_TDE_TDA),
 859         SR_TRAP(SYS_DBGBCRn_EL1(2),     CGT_MDCR_TDE_TDA),
 860         SR_TRAP(SYS_DBGBCRn_EL1(3),     CGT_MDCR_TDE_TDA),
 861         SR_TRAP(SYS_DBGBCRn_EL1(4),     CGT_MDCR_TDE_TDA),
 862         SR_TRAP(SYS_DBGBCRn_EL1(5),     CGT_MDCR_TDE_TDA),
 863         SR_TRAP(SYS_DBGBCRn_EL1(6),     CGT_MDCR_TDE_TDA),
 864         SR_TRAP(SYS_DBGBCRn_EL1(7),     CGT_MDCR_TDE_TDA),
 865         SR_TRAP(SYS_DBGBCRn_EL1(8),     CGT_MDCR_TDE_TDA),
 866         SR_TRAP(SYS_DBGBCRn_EL1(9),     CGT_MDCR_TDE_TDA),
 867         SR_TRAP(SYS_DBGBCRn_EL1(10),    CGT_MDCR_TDE_TDA),
 868         SR_TRAP(SYS_DBGBCRn_EL1(11),    CGT_MDCR_TDE_TDA),
 869         SR_TRAP(SYS_DBGBCRn_EL1(12),    CGT_MDCR_TDE_TDA),
 870         SR_TRAP(SYS_DBGBCRn_EL1(13),    CGT_MDCR_TDE_TDA),
 871         SR_TRAP(SYS_DBGBCRn_EL1(14),    CGT_MDCR_TDE_TDA),
 872         SR_TRAP(SYS_DBGBCRn_EL1(15),    CGT_MDCR_TDE_TDA),
 873         SR_TRAP(SYS_DBGWVRn_EL1(0),     CGT_MDCR_TDE_TDA),
 874         SR_TRAP(SYS_DBGWVRn_EL1(1),     CGT_MDCR_TDE_TDA),
 875         SR_TRAP(SYS_DBGWVRn_EL1(2),     CGT_MDCR_TDE_TDA),
 876         SR_TRAP(SYS_DBGWVRn_EL1(3),     CGT_MDCR_TDE_TDA),
 877         SR_TRAP(SYS_DBGWVRn_EL1(4),     CGT_MDCR_TDE_TDA),
 878         SR_TRAP(SYS_DBGWVRn_EL1(5),     CGT_MDCR_TDE_TDA),
 879         SR_TRAP(SYS_DBGWVRn_EL1(6),     CGT_MDCR_TDE_TDA),
 880         SR_TRAP(SYS_DBGWVRn_EL1(7),     CGT_MDCR_TDE_TDA),
 881         SR_TRAP(SYS_DBGWVRn_EL1(8),     CGT_MDCR_TDE_TDA),
 882         SR_TRAP(SYS_DBGWVRn_EL1(9),     CGT_MDCR_TDE_TDA),
 883         SR_TRAP(SYS_DBGWVRn_EL1(10),    CGT_MDCR_TDE_TDA),
 884         SR_TRAP(SYS_DBGWVRn_EL1(11),    CGT_MDCR_TDE_TDA),
 885         SR_TRAP(SYS_DBGWVRn_EL1(12),    CGT_MDCR_TDE_TDA),
 886         SR_TRAP(SYS_DBGWVRn_EL1(13),    CGT_MDCR_TDE_TDA),
 887         SR_TRAP(SYS_DBGWVRn_EL1(14),    CGT_MDCR_TDE_TDA),
 888         SR_TRAP(SYS_DBGWVRn_EL1(15),    CGT_MDCR_TDE_TDA),
 889         SR_TRAP(SYS_DBGWCRn_EL1(0),     CGT_MDCR_TDE_TDA),
 890         SR_TRAP(SYS_DBGWCRn_EL1(1),     CGT_MDCR_TDE_TDA),
 891         SR_TRAP(SYS_DBGWCRn_EL1(2),     CGT_MDCR_TDE_TDA),
 892         SR_TRAP(SYS_DBGWCRn_EL1(3),     CGT_MDCR_TDE_TDA),
 893         SR_TRAP(SYS_DBGWCRn_EL1(4),     CGT_MDCR_TDE_TDA),
 894         SR_TRAP(SYS_DBGWCRn_EL1(5),     CGT_MDCR_TDE_TDA),
 895         SR_TRAP(SYS_DBGWCRn_EL1(6),     CGT_MDCR_TDE_TDA),
 896         SR_TRAP(SYS_DBGWCRn_EL1(7),     CGT_MDCR_TDE_TDA),
 897         SR_TRAP(SYS_DBGWCRn_EL1(8),     CGT_MDCR_TDE_TDA),
 898         SR_TRAP(SYS_DBGWCRn_EL1(9),     CGT_MDCR_TDE_TDA),
 899         SR_TRAP(SYS_DBGWCRn_EL1(10),    CGT_MDCR_TDE_TDA),
 900         SR_TRAP(SYS_DBGWCRn_EL1(11),    CGT_MDCR_TDE_TDA),
 901         SR_TRAP(SYS_DBGWCRn_EL1(12),    CGT_MDCR_TDE_TDA),
 902         SR_TRAP(SYS_DBGWCRn_EL1(13),    CGT_MDCR_TDE_TDA),
 903         SR_TRAP(SYS_DBGWCRn_EL1(14),    CGT_MDCR_TDE_TDA),
 904         SR_TRAP(SYS_DBGCLAIMSET_EL1,    CGT_MDCR_TDE_TDA),
 905         SR_TRAP(SYS_DBGCLAIMCLR_EL1,    CGT_MDCR_TDE_TDA),
 906         SR_TRAP(SYS_DBGAUTHSTATUS_EL1,  CGT_MDCR_TDE_TDA),
 907         SR_TRAP(SYS_OSLAR_EL1,          CGT_MDCR_TDE_TDOSA),
 908         SR_TRAP(SYS_OSLSR_EL1,          CGT_MDCR_TDE_TDOSA),
 909         SR_TRAP(SYS_OSDLR_EL1,          CGT_MDCR_TDE_TDOSA),
 910         SR_TRAP(SYS_DBGPRCR_EL1,        CGT_MDCR_TDE_TDOSA),
 911         SR_TRAP(SYS_MDRAR_EL1,          CGT_MDCR_TDE_TDRA),
 912         SR_TRAP(SYS_PMBLIMITR_EL1,      CGT_MDCR_E2PB),
 913         SR_TRAP(SYS_PMBPTR_EL1,         CGT_MDCR_E2PB),
 914         SR_TRAP(SYS_PMBSR_EL1,          CGT_MDCR_E2PB),
 915         SR_TRAP(SYS_PMSCR_EL1,          CGT_MDCR_TPMS),
 916         SR_TRAP(SYS_PMSEVFR_EL1,        CGT_MDCR_TPMS),
 917         SR_TRAP(SYS_PMSFCR_EL1,         CGT_MDCR_TPMS),
 918         SR_TRAP(SYS_PMSICR_EL1,         CGT_MDCR_TPMS),
 919         SR_TRAP(SYS_PMSIDR_EL1,         CGT_MDCR_TPMS),
 920         SR_TRAP(SYS_PMSIRR_EL1,         CGT_MDCR_TPMS),
 921         SR_TRAP(SYS_PMSLATFR_EL1,       CGT_MDCR_TPMS),
 922         SR_TRAP(SYS_PMSNEVFR_EL1,       CGT_MDCR_TPMS),
 923         SR_TRAP(SYS_TRFCR_EL1,          CGT_MDCR_TTRF),
 924         SR_TRAP(SYS_TRBBASER_EL1,       CGT_MDCR_E2TB),
 925         SR_TRAP(SYS_TRBLIMITR_EL1,      CGT_MDCR_E2TB),
 926         SR_TRAP(SYS_TRBMAR_EL1,         CGT_MDCR_E2TB),
 927         SR_TRAP(SYS_TRBPTR_EL1,         CGT_MDCR_E2TB),
 928         SR_TRAP(SYS_TRBSR_EL1,          CGT_MDCR_E2TB),
 929         SR_TRAP(SYS_TRBTRG_EL1,         CGT_MDCR_E2TB),
 930         SR_TRAP(SYS_CNTP_TVAL_EL0,      CGT_CNTHCTL_EL1PTEN),
 931         SR_TRAP(SYS_CNTP_CVAL_EL0,      CGT_CNTHCTL_EL1PTEN),
 932         SR_TRAP(SYS_CNTP_CTL_EL0,       CGT_CNTHCTL_EL1PTEN),
 933         SR_TRAP(SYS_CNTPCT_EL0,         CGT_CNTHCTL_EL1PCTEN),
 934         SR_TRAP(SYS_CNTPCTSS_EL0,       CGT_CNTHCTL_EL1PCTEN),
 935 };
 936
 937 static DEFINE_XARRAY(sr_forward_xa);
 938
 939 enum fgt_group_id {
 940         __NO_FGT_GROUP__,
 941         HFGxTR_GROUP,
 942         HFGITR_GROUP,
 943
 944         /* Must be last */
 945         __NR_FGT_GROUP_IDS__
 946 };
 947
 948 #define SR_FGT(sr, g, b, p)                                     \
 949         {                                                       \
 950                 .encoding       = sr,                           \
 951                 .end            = sr,                           \
 952                 .tc             = {                             \
 953                         .fgt = g ## _GROUP,                     \
 954                         .bit = g ## _EL2_ ## b ## _SHIFT,       \
 955                         .pol = p,                               \
 956                 },                                              \
 957                 .line = __LINE__,                               \
 958         }
 959
 960 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
 961         /* HFGRTR_EL2, HFGWTR_EL2 */
 962         SR_FGT(SYS_TPIDR2_EL0,          HFGxTR, nTPIDR2_EL0, 0),
 963         SR_FGT(SYS_SMPRI_EL1,           HFGxTR, nSMPRI_EL1, 0),
 964         SR_FGT(SYS_ACCDATA_EL1,         HFGxTR, nACCDATA_EL1, 0),
 965         SR_FGT(SYS_ERXADDR_EL1,         HFGxTR, ERXADDR_EL1, 1),
 966         SR_FGT(SYS_ERXPFGCDN_EL1,       HFGxTR, ERXPFGCDN_EL1, 1),
 967         SR_FGT(SYS_ERXPFGCTL_EL1,       HFGxTR, ERXPFGCTL_EL1, 1),
 968         SR_FGT(SYS_ERXPFGF_EL1,         HFGxTR, ERXPFGF_EL1, 1),
 969         SR_FGT(SYS_ERXMISC0_EL1,        HFGxTR, ERXMISCn_EL1, 1),
 970         SR_FGT(SYS_ERXMISC1_EL1,        HFGxTR, ERXMISCn_EL1, 1),
 971         SR_FGT(SYS_ERXMISC2_EL1,        HFGxTR, ERXMISCn_EL1, 1),
 972         SR_FGT(SYS_ERXMISC3_EL1,        HFGxTR, ERXMISCn_EL1, 1),
 973         SR_FGT(SYS_ERXSTATUS_EL1,       HFGxTR, ERXSTATUS_EL1, 1),
 974         SR_FGT(SYS_ERXCTLR_EL1,         HFGxTR, ERXCTLR_EL1, 1),
 975         SR_FGT(SYS_ERXFR_EL1,           HFGxTR, ERXFR_EL1, 1),
 976         SR_FGT(SYS_ERRSELR_EL1,         HFGxTR, ERRSELR_EL1, 1),
 977         SR_FGT(SYS_ERRIDR_EL1,          HFGxTR, ERRIDR_EL1, 1),
 978         SR_FGT(SYS_ICC_IGRPEN0_EL1,     HFGxTR, ICC_IGRPENn_EL1, 1),
 979         SR_FGT(SYS_ICC_IGRPEN1_EL1,     HFGxTR, ICC_IGRPENn_EL1, 1),
 980         SR_FGT(SYS_VBAR_EL1,            HFGxTR, VBAR_EL1, 1),
 981         SR_FGT(SYS_TTBR1_EL1,           HFGxTR, TTBR1_EL1, 1),
 982         SR_FGT(SYS_TTBR0_EL1,           HFGxTR, TTBR0_EL1, 1),
 983         SR_FGT(SYS_TPIDR_EL0,           HFGxTR, TPIDR_EL0, 1),
 984         SR_FGT(SYS_TPIDRRO_EL0,         HFGxTR, TPIDRRO_EL0, 1),
 985         SR_FGT(SYS_TPIDR_EL1,           HFGxTR, TPIDR_EL1, 1),
 986         SR_FGT(SYS_TCR_EL1,             HFGxTR, TCR_EL1, 1),
 987         SR_FGT(SYS_SCXTNUM_EL0,         HFGxTR, SCXTNUM_EL0, 1),
 988         SR_FGT(SYS_SCXTNUM_EL1,         HFGxTR, SCXTNUM_EL1, 1),
 989         SR_FGT(SYS_SCTLR_EL1,           HFGxTR, SCTLR_EL1, 1),
 990         SR_FGT(SYS_REVIDR_EL1,          HFGxTR, REVIDR_EL1, 1),
 991         SR_FGT(SYS_PAR_EL1,             HFGxTR, PAR_EL1, 1),
 992         SR_FGT(SYS_MPIDR_EL1,           HFGxTR, MPIDR_EL1, 1),
 993         SR_FGT(SYS_MIDR_EL1,            HFGxTR, MIDR_EL1, 1),
 994         SR_FGT(SYS_MAIR_EL1,            HFGxTR, MAIR_EL1, 1),
 995         SR_FGT(SYS_LORSA_EL1,           HFGxTR, LORSA_EL1, 1),
 996         SR_FGT(SYS_LORN_EL1,            HFGxTR, LORN_EL1, 1),
 997         SR_FGT(SYS_LORID_EL1,           HFGxTR, LORID_EL1, 1),
 998         SR_FGT(SYS_LOREA_EL1,           HFGxTR, LOREA_EL1, 1),
 999         SR_FGT(SYS_LORC_EL1,            HFGxTR, LORC_EL1, 1),
1000         SR_FGT(SYS_ISR_EL1,             HFGxTR, ISR_EL1, 1),
1001         SR_FGT(SYS_FAR_EL1,             HFGxTR, FAR_EL1, 1),
1002         SR_FGT(SYS_ESR_EL1,             HFGxTR, ESR_EL1, 1),
1003         SR_FGT(SYS_DCZID_EL0,           HFGxTR, DCZID_EL0, 1),
1004         SR_FGT(SYS_CTR_EL0,             HFGxTR, CTR_EL0, 1),
1005         SR_FGT(SYS_CSSELR_EL1,          HFGxTR, CSSELR_EL1, 1),
1006         SR_FGT(SYS_CPACR_EL1,           HFGxTR, CPACR_EL1, 1),
1007         SR_FGT(SYS_CONTEXTIDR_EL1,      HFGxTR, CONTEXTIDR_EL1, 1),
1008         SR_FGT(SYS_CLIDR_EL1,           HFGxTR, CLIDR_EL1, 1),
1009         SR_FGT(SYS_CCSIDR_EL1,          HFGxTR, CCSIDR_EL1, 1),
1010         SR_FGT(SYS_APIBKEYLO_EL1,       HFGxTR, APIBKey, 1),
1011         SR_FGT(SYS_APIBKEYHI_EL1,       HFGxTR, APIBKey, 1),
1012         SR_FGT(SYS_APIAKEYLO_EL1,       HFGxTR, APIAKey, 1),
1013         SR_FGT(SYS_APIAKEYHI_EL1,       HFGxTR, APIAKey, 1),
1014         SR_FGT(SYS_APGAKEYLO_EL1,       HFGxTR, APGAKey, 1),
1015         SR_FGT(SYS_APGAKEYHI_EL1,       HFGxTR, APGAKey, 1),
1016         SR_FGT(SYS_APDBKEYLO_EL1,       HFGxTR, APDBKey, 1),
1017         SR_FGT(SYS_APDBKEYHI_EL1,       HFGxTR, APDBKey, 1),
1018         SR_FGT(SYS_APDAKEYLO_EL1,       HFGxTR, APDAKey, 1),
1019         SR_FGT(SYS_APDAKEYHI_EL1,       HFGxTR, APDAKey, 1),
1020         SR_FGT(SYS_AMAIR_EL1,           HFGxTR, AMAIR_EL1, 1),
1021         SR_FGT(SYS_AIDR_EL1,            HFGxTR, AIDR_EL1, 1),
1022         SR_FGT(SYS_AFSR1_EL1,           HFGxTR, AFSR1_EL1, 1),
1023         SR_FGT(SYS_AFSR0_EL1,           HFGxTR, AFSR0_EL1, 1),
1024         /* HFGITR_EL2 */
1025         SR_FGT(OP_BRB_IALL,             HFGITR, nBRBIALL, 0),
1026         SR_FGT(OP_BRB_INJ,              HFGITR, nBRBINJ, 0),
1027         SR_FGT(SYS_DC_CVAC,             HFGITR, DCCVAC, 1),
1028         SR_FGT(SYS_DC_CGVAC,            HFGITR, DCCVAC, 1),
1029         SR_FGT(SYS_DC_CGDVAC,           HFGITR, DCCVAC, 1),
1030         SR_FGT(OP_CPP_RCTX,             HFGITR, CPPRCTX, 1),
1031         SR_FGT(OP_DVP_RCTX,             HFGITR, DVPRCTX, 1),
1032         SR_FGT(OP_CFP_RCTX,             HFGITR, CFPRCTX, 1),
1033         SR_FGT(OP_TLBI_VAALE1,          HFGITR, TLBIVAALE1, 1),
1034         SR_FGT(OP_TLBI_VALE1,           HFGITR, TLBIVALE1, 1),
1035         SR_FGT(OP_TLBI_VAAE1,           HFGITR, TLBIVAAE1, 1),
1036         SR_FGT(OP_TLBI_ASIDE1,          HFGITR, TLBIASIDE1, 1),
1037         SR_FGT(OP_TLBI_VAE1,            HFGITR, TLBIVAE1, 1),
1038         SR_FGT(OP_TLBI_VMALLE1,         HFGITR, TLBIVMALLE1, 1),
1039         SR_FGT(OP_TLBI_RVAALE1,         HFGITR, TLBIRVAALE1, 1),
1040         SR_FGT(OP_TLBI_RVALE1,          HFGITR, TLBIRVALE1, 1),
1041         SR_FGT(OP_TLBI_RVAAE1,          HFGITR, TLBIRVAAE1, 1),
1042         SR_FGT(OP_TLBI_RVAE1,           HFGITR, TLBIRVAE1, 1),
1043         SR_FGT(OP_TLBI_RVAALE1IS,       HFGITR, TLBIRVAALE1IS, 1),
1044         SR_FGT(OP_TLBI_RVALE1IS,        HFGITR, TLBIRVALE1IS, 1),
1045         SR_FGT(OP_TLBI_RVAAE1IS,        HFGITR, TLBIRVAAE1IS, 1),
1046         SR_FGT(OP_TLBI_RVAE1IS,         HFGITR, TLBIRVAE1IS, 1),
1047         SR_FGT(OP_TLBI_VAALE1IS,        HFGITR, TLBIVAALE1IS, 1),
1048         SR_FGT(OP_TLBI_VALE1IS,         HFGITR, TLBIVALE1IS, 1),
1049         SR_FGT(OP_TLBI_VAAE1IS,         HFGITR, TLBIVAAE1IS, 1),
1050         SR_FGT(OP_TLBI_ASIDE1IS,        HFGITR, TLBIASIDE1IS, 1),
1051         SR_FGT(OP_TLBI_VAE1IS,          HFGITR, TLBIVAE1IS, 1),
1052         SR_FGT(OP_TLBI_VMALLE1IS,       HFGITR, TLBIVMALLE1IS, 1),
1053         SR_FGT(OP_TLBI_RVAALE1OS,       HFGITR, TLBIRVAALE1OS, 1),
1054         SR_FGT(OP_TLBI_RVALE1OS,        HFGITR, TLBIRVALE1OS, 1),
1055         SR_FGT(OP_TLBI_RVAAE1OS,        HFGITR, TLBIRVAAE1OS, 1),
1056         SR_FGT(OP_TLBI_RVAE1OS,         HFGITR, TLBIRVAE1OS, 1),
1057         SR_FGT(OP_TLBI_VAALE1OS,        HFGITR, TLBIVAALE1OS, 1),
1058         SR_FGT(OP_TLBI_VALE1OS,         HFGITR, TLBIVALE1OS, 1),
1059         SR_FGT(OP_TLBI_VAAE1OS,         HFGITR, TLBIVAAE1OS, 1),
1060         SR_FGT(OP_TLBI_ASIDE1OS,        HFGITR, TLBIASIDE1OS, 1),
1061         SR_FGT(OP_TLBI_VAE1OS,          HFGITR, TLBIVAE1OS, 1),
1062         SR_FGT(OP_TLBI_VMALLE1OS,       HFGITR, TLBIVMALLE1OS, 1),
1063         /* FIXME: nXS variants must be checked against HCRX_EL2.FGTnXS */
1064         SR_FGT(OP_TLBI_VAALE1NXS,       HFGITR, TLBIVAALE1, 1),
1065         SR_FGT(OP_TLBI_VALE1NXS,        HFGITR, TLBIVALE1, 1),
1066         SR_FGT(OP_TLBI_VAAE1NXS,        HFGITR, TLBIVAAE1, 1),
1067         SR_FGT(OP_TLBI_ASIDE1NXS,       HFGITR, TLBIASIDE1, 1),
1068         SR_FGT(OP_TLBI_VAE1NXS,         HFGITR, TLBIVAE1, 1),
1069         SR_FGT(OP_TLBI_VMALLE1NXS,      HFGITR, TLBIVMALLE1, 1),
1070         SR_FGT(OP_TLBI_RVAALE1NXS,      HFGITR, TLBIRVAALE1, 1),
1071         SR_FGT(OP_TLBI_RVALE1NXS,       HFGITR, TLBIRVALE1, 1),
1072         SR_FGT(OP_TLBI_RVAAE1NXS,       HFGITR, TLBIRVAAE1, 1),
1073         SR_FGT(OP_TLBI_RVAE1NXS,        HFGITR, TLBIRVAE1, 1),
1074         SR_FGT(OP_TLBI_RVAALE1ISNXS,    HFGITR, TLBIRVAALE1IS, 1),
1075         SR_FGT(OP_TLBI_RVALE1ISNXS,     HFGITR, TLBIRVALE1IS, 1),
1076         SR_FGT(OP_TLBI_RVAAE1ISNXS,     HFGITR, TLBIRVAAE1IS, 1),
1077         SR_FGT(OP_TLBI_RVAE1ISNXS,      HFGITR, TLBIRVAE1IS, 1),
1078         SR_FGT(OP_TLBI_VAALE1ISNXS,     HFGITR, TLBIVAALE1IS, 1),
1079         SR_FGT(OP_TLBI_VALE1ISNXS,      HFGITR, TLBIVALE1IS, 1),
1080         SR_FGT(OP_TLBI_VAAE1ISNXS,      HFGITR, TLBIVAAE1IS, 1),
1081         SR_FGT(OP_TLBI_ASIDE1ISNXS,     HFGITR, TLBIASIDE1IS, 1),
1082         SR_FGT(OP_TLBI_VAE1ISNXS,       HFGITR, TLBIVAE1IS, 1),
1083         SR_FGT(OP_TLBI_VMALLE1ISNXS,    HFGITR, TLBIVMALLE1IS, 1),
1084         SR_FGT(OP_TLBI_RVAALE1OSNXS,    HFGITR, TLBIRVAALE1OS, 1),
1085         SR_FGT(OP_TLBI_RVALE1OSNXS,     HFGITR, TLBIRVALE1OS, 1),
1086         SR_FGT(OP_TLBI_RVAAE1OSNXS,     HFGITR, TLBIRVAAE1OS, 1),
1087         SR_FGT(OP_TLBI_RVAE1OSNXS,      HFGITR, TLBIRVAE1OS, 1),
1088         SR_FGT(OP_TLBI_VAALE1OSNXS,     HFGITR, TLBIVAALE1OS, 1),
1089         SR_FGT(OP_TLBI_VALE1OSNXS,      HFGITR, TLBIVALE1OS, 1),
1090         SR_FGT(OP_TLBI_VAAE1OSNXS,      HFGITR, TLBIVAAE1OS, 1),
1091         SR_FGT(OP_TLBI_ASIDE1OSNXS,     HFGITR, TLBIASIDE1OS, 1),
1092         SR_FGT(OP_TLBI_VAE1OSNXS,       HFGITR, TLBIVAE1OS, 1),
1093         SR_FGT(OP_TLBI_VMALLE1OSNXS,    HFGITR, TLBIVMALLE1OS, 1),
1094         SR_FGT(OP_AT_S1E1WP,            HFGITR, ATS1E1WP, 1),
1095         SR_FGT(OP_AT_S1E1RP,            HFGITR, ATS1E1RP, 1),
1096         SR_FGT(OP_AT_S1E0W,             HFGITR, ATS1E0W, 1),
1097         SR_FGT(OP_AT_S1E0R,             HFGITR, ATS1E0R, 1),
1098         SR_FGT(OP_AT_S1E1W,             HFGITR, ATS1E1W, 1),
1099         SR_FGT(OP_AT_S1E1R,             HFGITR, ATS1E1R, 1),
1100         SR_FGT(SYS_DC_ZVA,              HFGITR, DCZVA, 1),
1101         SR_FGT(SYS_DC_GVA,              HFGITR, DCZVA, 1),
1102         SR_FGT(SYS_DC_GZVA,             HFGITR, DCZVA, 1),
1103         SR_FGT(SYS_DC_CIVAC,            HFGITR, DCCIVAC, 1),
1104         SR_FGT(SYS_DC_CIGVAC,           HFGITR, DCCIVAC, 1),
1105         SR_FGT(SYS_DC_CIGDVAC,          HFGITR, DCCIVAC, 1),
1106         SR_FGT(SYS_DC_CVADP,            HFGITR, DCCVADP, 1),
1107         SR_FGT(SYS_DC_CGVADP,           HFGITR, DCCVADP, 1),
1108         SR_FGT(SYS_DC_CGDVADP,          HFGITR, DCCVADP, 1),
1109         SR_FGT(SYS_DC_CVAP,             HFGITR, DCCVAP, 1),
1110         SR_FGT(SYS_DC_CGVAP,            HFGITR, DCCVAP, 1),
1111         SR_FGT(SYS_DC_CGDVAP,           HFGITR, DCCVAP, 1),
1112         SR_FGT(SYS_DC_CVAU,             HFGITR, DCCVAU, 1),
1113         SR_FGT(SYS_DC_CISW,             HFGITR, DCCISW, 1),
1114         SR_FGT(SYS_DC_CIGSW,            HFGITR, DCCISW, 1),
1115         SR_FGT(SYS_DC_CIGDSW,           HFGITR, DCCISW, 1),
1116         SR_FGT(SYS_DC_CSW,              HFGITR, DCCSW, 1),
1117         SR_FGT(SYS_DC_CGSW,             HFGITR, DCCSW, 1),
1118         SR_FGT(SYS_DC_CGDSW,            HFGITR, DCCSW, 1),
1119         SR_FGT(SYS_DC_ISW,              HFGITR, DCISW, 1),
1120         SR_FGT(SYS_DC_IGSW,             HFGITR, DCISW, 1),
1121         SR_FGT(SYS_DC_IGDSW,            HFGITR, DCISW, 1),
1122         SR_FGT(SYS_DC_IVAC,             HFGITR, DCIVAC, 1),
1123         SR_FGT(SYS_DC_IGVAC,            HFGITR, DCIVAC, 1),
1124         SR_FGT(SYS_DC_IGDVAC,           HFGITR, DCIVAC, 1),
1125         SR_FGT(SYS_IC_IVAU,             HFGITR, ICIVAU, 1),
1126         SR_FGT(SYS_IC_IALLU,            HFGITR, ICIALLU, 1),
1127         SR_FGT(SYS_IC_IALLUIS,          HFGITR, ICIALLUIS, 1),
1128 };
1129
1130 static union trap_config get_trap_config(u32 sysreg)
1131 {
1132         return (union trap_config) {
1133                 .val = xa_to_value(xa_load(&sr_forward_xa, sysreg)),
1134         };
1135 }
1136
1137 static __init void print_nv_trap_error(const struct encoding_to_trap_config *tc,
1138                                        const char *type, int err)
1139 {
1140         kvm_err("%s line %d encoding range "
1141                 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n",
1142                 type, tc->line,
1143                 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding),
1144                 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding),
1145                 sys_reg_Op2(tc->encoding),
1146                 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end),
1147                 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end),
1148                 sys_reg_Op2(tc->end),
1149                 err);
1150 }
1151
1152 int __init populate_nv_trap_config(void)
1153 {
1154         int ret = 0;
1155
1156         BUILD_BUG_ON(sizeof(union trap_config) != sizeof(void *));
1157         BUILD_BUG_ON(__NR_CGT_GROUP_IDS__ > BIT(TC_CGT_BITS));
1158         BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS));
1159
1160         for (int i = 0; i < ARRAY_SIZE(encoding_to_cgt); i++) {
1161                 const struct encoding_to_trap_config *cgt = &encoding_to_cgt[i];
1162                 void *prev;
1163
1164                 if (cgt->tc.val & BIT(63)) {
1165                         kvm_err("CGT[%d] has MBZ bit set\n", i);
1166                         ret = -EINVAL;
1167                 }
1168
1169                 if (cgt->encoding != cgt->end) {
1170                         prev = xa_store_range(&sr_forward_xa,
1171                                               cgt->encoding, cgt->end,
1172                                               xa_mk_value(cgt->tc.val),
1173                                               GFP_KERNEL);
1174                 } else {
1175                         prev = xa_store(&sr_forward_xa, cgt->encoding,
1176                                         xa_mk_value(cgt->tc.val), GFP_KERNEL);
1177                         if (prev && !xa_is_err(prev)) {
1178                                 ret = -EINVAL;
1179                                 print_nv_trap_error(cgt, "Duplicate CGT", ret);
1180                         }
1181                 }
1182
1183                 if (xa_is_err(prev)) {
1184                         ret = xa_err(prev);
1185                         print_nv_trap_error(cgt, "Failed CGT insertion", ret);
1186                 }
1187         }
1188
1189         kvm_info("nv: %ld coarse grained trap handlers\n",
1190                  ARRAY_SIZE(encoding_to_cgt));
1191
1192         if (!cpus_have_final_cap(ARM64_HAS_FGT))
1193                 goto check_mcb;
1194
1195         for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) {
1196                 const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i];
1197                 union trap_config tc;
1198
1199                 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) {
1200                         ret = -EINVAL;
1201                         print_nv_trap_error(fgt, "Invalid FGT", ret);
1202                 }
1203
1204                 tc = get_trap_config(fgt->encoding);
1205
1206                 if (tc.fgt) {
1207                         ret = -EINVAL;
1208                         print_nv_trap_error(fgt, "Duplicate FGT", ret);
1209                 }
1210
1211                 tc.val |= fgt->tc.val;
1212                 xa_store(&sr_forward_xa, fgt->encoding,
1213                          xa_mk_value(tc.val), GFP_KERNEL);
1214         }
1215
1216         kvm_info("nv: %ld fine grained trap handlers\n",
1217                  ARRAY_SIZE(encoding_to_fgt));
1218
1219 check_mcb:
1220         for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) {
1221                 const enum cgt_group_id *cgids;
1222
1223                 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__];
1224
1225                 for (int i = 0; cgids[i] != __RESERVED__; i++) {
1226                         if (cgids[i] >= __MULTIPLE_CONTROL_BITS__) {
1227                                 kvm_err("Recursive MCB %d/%d\n", id, cgids[i]);
1228                                 ret = -EINVAL;
1229                         }
1230                 }
1231         }
1232
1233         if (ret)
1234                 xa_destroy(&sr_forward_xa);
1235
1236         return ret;
1237 }
1238
1239 static enum trap_behaviour get_behaviour(struct kvm_vcpu *vcpu,
1240                                          const struct trap_bits *tb)
1241 {
1242         enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY;
1243         u64 val;
1244
1245         val = __vcpu_sys_reg(vcpu, tb->index);
1246         if ((val & tb->mask) == tb->value)
1247                 b |= tb->behaviour;
1248
1249         return b;
1250 }
1251
1252 static enum trap_behaviour __compute_trap_behaviour(struct kvm_vcpu *vcpu,
1253                                                     const enum cgt_group_id id,
1254                                                     enum trap_behaviour b)
1255 {
1256         switch (id) {
1257                 const enum cgt_group_id *cgids;
1258
1259         case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1:
1260                 if (likely(id != __RESERVED__))
1261                         b |= get_behaviour(vcpu, &coarse_trap_bits[id]);
1262                 break;
1263         case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1:
1264                 /* Yes, this is recursive. Don't do anything stupid. */
1265                 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__];
1266                 for (int i = 0; cgids[i] != __RESERVED__; i++)
1267                         b |= __compute_trap_behaviour(vcpu, cgids[i], b);
1268                 break;
1269         default:
1270                 if (ARRAY_SIZE(ccc))
1271                         b |= ccc[id -  __COMPLEX_CONDITIONS__](vcpu);
1272                 break;
1273         }
1274
1275         return b;
1276 }
1277
1278 static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu,
1279                                                   const union trap_config tc)
1280 {
1281         enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY;
1282
1283         return __compute_trap_behaviour(vcpu, tc.cgt, b);
1284 }
1285
1286 static bool check_fgt_bit(u64 val, const union trap_config tc)
1287 {
1288         return ((val >> tc.bit) & 1) == tc.pol;
1289 }
1290
1291 #define sanitised_sys_reg(vcpu, reg)                    \
1292         ({                                              \
1293                 u64 __val;                              \
1294                 __val = __vcpu_sys_reg(vcpu, reg);      \
1295                 __val &= ~__ ## reg ## _RES0;           \
1296                 (__val);                                \
1297         })
1298
1299 bool __check_nv_sr_forward(struct kvm_vcpu *vcpu)
1300 {
1301         union trap_config tc;
1302         enum trap_behaviour b;
1303         bool is_read;
1304         u32 sysreg;
1305         u64 esr, val;
1306
1307         if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
1308                 return false;
1309
1310         esr = kvm_vcpu_get_esr(vcpu);
1311         sysreg = esr_sys64_to_sysreg(esr);
1312         is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
1313
1314         tc = get_trap_config(sysreg);
1315
1316         /*
1317          * A value of 0 for the whole entry means that we know nothing
1318          * for this sysreg, and that it cannot be re-injected into the
1319          * nested hypervisor. In this situation, let's cut it short.
1320          *
1321          * Note that ultimately, we could also make use of the xarray
1322          * to store the index of the sysreg in the local descriptor
1323          * array, avoiding another search... Hint, hint...
1324          */
1325         if (!tc.val)
1326                 return false;
1327
1328         switch ((enum fgt_group_id)tc.fgt) {
1329         case __NO_FGT_GROUP__:
1330                 break;
1331
1332         case HFGxTR_GROUP:
1333                 if (is_read)
1334                         val = sanitised_sys_reg(vcpu, HFGRTR_EL2);
1335                 else
1336                         val = sanitised_sys_reg(vcpu, HFGWTR_EL2);
1337                 break;
1338
1339         case HFGITR_GROUP:
1340                 val = sanitised_sys_reg(vcpu, HFGITR_EL2);
1341                 break;
1342
1343         case __NR_FGT_GROUP_IDS__:
1344                 /* Something is really wrong, bail out */
1345                 WARN_ONCE(1, "__NR_FGT_GROUP_IDS__");
1346                 return false;
1347         }
1348
1349         if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(val, tc))
1350                 goto inject;
1351
1352         b = compute_trap_behaviour(vcpu, tc);
1353
1354         if (((b & BEHAVE_FORWARD_READ) && is_read) ||
1355             ((b & BEHAVE_FORWARD_WRITE) && !is_read))
1356                 goto inject;
1357
1358         return false;
1359
1360 inject:
1361         trace_kvm_forward_sysreg_trap(vcpu, sysreg, is_read);
1362
1363         kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
1364         return true;
1365 }
1366
1367 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr)
1368 {
1369         u64 mode = spsr & PSR_MODE_MASK;
1370
1371         /*
1372          * Possible causes for an Illegal Exception Return from EL2:
1373          * - trying to return to EL3
1374          * - trying to return to an illegal M value
1375          * - trying to return to a 32bit EL
1376          * - trying to return to EL1 with HCR_EL2.TGE set
1377          */
1378         if (mode == PSR_MODE_EL3t   || mode == PSR_MODE_EL3h ||
1379             mode == 0b00001         || (mode & BIT(1))       ||
1380             (spsr & PSR_MODE32_BIT) ||
1381             (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t ||
1382                                            mode == PSR_MODE_EL1h))) {
1383                 /*
1384                  * The guest is playing with our nerves. Preserve EL, SP,
1385                  * masks, flags from the existing PSTATE, and set IL.
1386                  * The HW will then generate an Illegal State Exception
1387                  * immediately after ERET.
1388                  */
1389                 spsr = *vcpu_cpsr(vcpu);
1390
1391                 spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
1392                          PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT |
1393                          PSR_MODE_MASK | PSR_MODE32_BIT);
1394                 spsr |= PSR_IL_BIT;
1395         }
1396
1397         return spsr;
1398 }
1399
1400 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
1401 {
1402         u64 spsr, elr, mode;
1403         bool direct_eret;
1404
1405         /*
1406          * Going through the whole put/load motions is a waste of time
1407          * if this is a VHE guest hypervisor returning to its own
1408          * userspace, or the hypervisor performing a local exception
1409          * return. No need to save/restore registers, no need to
1410          * switch S2 MMU. Just do the canonical ERET.
1411          */
1412         spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2);
1413         spsr = kvm_check_illegal_exception_return(vcpu, spsr);
1414
1415         mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT);
1416
1417         direct_eret  = (mode == PSR_MODE_EL0t &&
1418                         vcpu_el2_e2h_is_set(vcpu) &&
1419                         vcpu_el2_tge_is_set(vcpu));
1420         direct_eret |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t);
1421
1422         if (direct_eret) {
1423                 *vcpu_pc(vcpu) = vcpu_read_sys_reg(vcpu, ELR_EL2);
1424                 *vcpu_cpsr(vcpu) = spsr;
1425                 trace_kvm_nested_eret(vcpu, *vcpu_pc(vcpu), spsr);
1426                 return;
1427         }
1428
1429         preempt_disable();
1430         kvm_arch_vcpu_put(vcpu);
1431
1432         elr = __vcpu_sys_reg(vcpu, ELR_EL2);
1433
1434         trace_kvm_nested_eret(vcpu, elr, spsr);
1435
1436         /*
1437          * Note that the current exception level is always the virtual EL2,
1438          * since we set HCR_EL2.NV bit only when entering the virtual EL2.
1439          */
1440         *vcpu_pc(vcpu) = elr;
1441         *vcpu_cpsr(vcpu) = spsr;
1442
1443         kvm_arch_vcpu_load(vcpu, smp_processor_id());
1444         preempt_enable();
1445 }
1446
1447 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2,
1448                                      enum exception_type type)
1449 {
1450         trace_kvm_inject_nested_exception(vcpu, esr_el2, type);
1451
1452         switch (type) {
1453         case except_type_sync:
1454                 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC);
1455                 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2);
1456                 break;
1457         case except_type_irq:
1458                 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_IRQ);
1459                 break;
1460         default:
1461                 WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type);
1462         }
1463 }
1464
1465 /*
1466  * Emulate taking an exception to EL2.
1467  * See ARM ARM J8.1.2 AArch64.TakeException()
1468  */
1469 static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2,
1470                              enum exception_type type)
1471 {
1472         u64 pstate, mode;
1473         bool direct_inject;
1474
1475         if (!vcpu_has_nv(vcpu)) {
1476                 kvm_err("Unexpected call to %s for the non-nesting configuration\n",
1477                                 __func__);
1478                 return -EINVAL;
1479         }
1480
1481         /*
1482          * As for ERET, we can avoid doing too much on the injection path by
1483          * checking that we either took the exception from a VHE host
1484          * userspace or from vEL2. In these cases, there is no change in
1485          * translation regime (or anything else), so let's do as little as
1486          * possible.
1487          */
1488         pstate = *vcpu_cpsr(vcpu);
1489         mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
1490
1491         direct_inject  = (mode == PSR_MODE_EL0t &&
1492                           vcpu_el2_e2h_is_set(vcpu) &&
1493                           vcpu_el2_tge_is_set(vcpu));
1494         direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t);
1495
1496         if (direct_inject) {
1497                 kvm_inject_el2_exception(vcpu, esr_el2, type);
1498                 return 1;
1499         }
1500
1501         preempt_disable();
1502
1503         /*
1504          * We may have an exception or PC update in the EL0/EL1 context.
1505          * Commit it before entering EL2.
1506          */
1507         __kvm_adjust_pc(vcpu);
1508
1509         kvm_arch_vcpu_put(vcpu);
1510
1511         kvm_inject_el2_exception(vcpu, esr_el2, type);
1512
1513         /*
1514          * A hard requirement is that a switch between EL1 and EL2
1515          * contexts has to happen between a put/load, so that we can
1516          * pick the correct timer and interrupt configuration, among
1517          * other things.
1518          *
1519          * Make sure the exception actually took place before we load
1520          * the new context.
1521          */
1522         __kvm_adjust_pc(vcpu);
1523
1524         kvm_arch_vcpu_load(vcpu, smp_processor_id());
1525         preempt_enable();
1526
1527         return 1;
1528 }
1529
1530 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2)
1531 {
1532         return kvm_inject_nested(vcpu, esr_el2, except_type_sync);
1533 }
1534
1535 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu)
1536 {
1537         /*
1538          * Do not inject an irq if the:
1539          *  - Current exception level is EL2, and
1540          *  - virtual HCR_EL2.TGE == 0
1541          *  - virtual HCR_EL2.IMO == 0
1542          *
1543          * See Table D1-17 "Physical interrupt target and masking when EL3 is
1544          * not implemented and EL2 is implemented" in ARM DDI 0487C.a.
1545          */
1546
1547         if (vcpu_is_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) &&
1548             !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO))
1549                 return 1;
1550
1551         /* esr_el2 value doesn't matter for exits due to irqs. */
1552         return kvm_inject_nested(vcpu, 0, except_type_irq);
1553 }