1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/traps.c
5 * Copyright (C) 1995-2009 Russell King
6 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/signal.h>
11 #include <linux/personality.h>
12 #include <linux/kallsyms.h>
13 #include <linux/spinlock.h>
14 #include <linux/uaccess.h>
15 #include <linux/hardirq.h>
16 #include <linux/kdebug.h>
17 #include <linux/module.h>
18 #include <linux/kexec.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/sched/signal.h>
22 #include <linux/sched/debug.h>
23 #include <linux/sched/task_stack.h>
24 #include <linux/sizes.h>
25 #include <linux/syscalls.h>
26 #include <linux/mm_types.h>
27 #include <linux/kasan.h>
29 #include <asm/atomic.h>
31 #include <asm/cpufeature.h>
32 #include <asm/daifflags.h>
33 #include <asm/debug-monitors.h>
36 #include <asm/traps.h>
38 #include <asm/stack_pointer.h>
39 #include <asm/stacktrace.h>
40 #include <asm/exception.h>
41 #include <asm/system_misc.h>
42 #include <asm/sysreg.h>
44 static const char *handler[]= {
51 int show_unhandled_signals = 0;
53 static void dump_backtrace_entry(unsigned long where)
55 printk(" %pS\n", (void *)where);
58 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
60 unsigned long addr = instruction_pointer(regs);
61 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
67 for (i = -4; i < 1; i++) {
68 unsigned int val, bad;
70 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
73 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
75 p += sprintf(p, "bad PC value");
80 printk("%sCode: %s\n", lvl, str);
83 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
85 struct stackframe frame;
88 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
99 if (!try_get_task_stack(tsk))
102 if (tsk == current) {
103 frame.fp = (unsigned long)__builtin_frame_address(0);
104 frame.pc = (unsigned long)dump_backtrace;
107 * task blocked in __switch_to
109 frame.fp = thread_saved_fp(tsk);
110 frame.pc = thread_saved_pc(tsk);
112 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
116 printk("Call trace:\n");
118 /* skip until specified stack frame */
120 dump_backtrace_entry(frame.pc);
121 } else if (frame.fp == regs->regs[29]) {
124 * Mostly, this is the case where this function is
125 * called in panic/abort. As exception handler's
126 * stack frame does not contain the corresponding pc
127 * at which an exception has taken place, use regs->pc
130 dump_backtrace_entry(regs->pc);
132 } while (!unwind_frame(tsk, &frame));
137 void show_stack(struct task_struct *tsk, unsigned long *sp)
139 dump_backtrace(NULL, tsk);
143 #ifdef CONFIG_PREEMPT
144 #define S_PREEMPT " PREEMPT"
150 static int __die(const char *str, int err, struct pt_regs *regs)
152 static int die_counter;
155 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
156 str, err, ++die_counter);
158 /* trap and error numbers are mostly meaningless on ARM */
159 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
160 if (ret == NOTIFY_STOP)
166 dump_kernel_instr(KERN_EMERG, regs);
171 static DEFINE_RAW_SPINLOCK(die_lock);
174 * This function is protected against re-entrancy.
176 void die(const char *str, struct pt_regs *regs, int err)
181 raw_spin_lock_irqsave(&die_lock, flags);
187 ret = __die(str, err, regs);
189 if (regs && kexec_should_crash(current))
193 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
197 panic("Fatal exception in interrupt");
199 panic("Fatal exception");
201 raw_spin_unlock_irqrestore(&die_lock, flags);
203 if (ret != NOTIFY_STOP)
207 static void arm64_show_signal(int signo, const char *str)
209 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
210 DEFAULT_RATELIMIT_BURST);
211 struct task_struct *tsk = current;
212 unsigned int esr = tsk->thread.fault_code;
213 struct pt_regs *regs = task_pt_regs(tsk);
215 /* Leave if the signal won't be shown */
216 if (!show_unhandled_signals ||
217 !unhandled_signal(tsk, signo) ||
221 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
223 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
226 print_vma_addr(KERN_CONT " in ", regs->pc);
231 void arm64_force_sig_fault(int signo, int code, void __user *addr,
234 arm64_show_signal(signo, str);
235 if (signo == SIGKILL)
238 force_sig_fault(signo, code, addr);
241 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,
244 arm64_show_signal(SIGBUS, str);
245 force_sig_mceerr(code, addr, lsb);
248 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr,
251 arm64_show_signal(SIGTRAP, str);
252 force_sig_ptrace_errno_trap(errno, addr);
255 void arm64_notify_die(const char *str, struct pt_regs *regs,
256 int signo, int sicode, void __user *addr,
259 if (user_mode(regs)) {
260 WARN_ON(regs != current_pt_regs());
261 current->thread.fault_address = 0;
262 current->thread.fault_code = err;
264 arm64_force_sig_fault(signo, sicode, addr, str);
270 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
275 * If we were single stepping, we want to get the step exception after
276 * we return from the trap.
279 user_fastforward_single_step(current);
282 static LIST_HEAD(undef_hook);
283 static DEFINE_RAW_SPINLOCK(undef_lock);
285 void register_undef_hook(struct undef_hook *hook)
289 raw_spin_lock_irqsave(&undef_lock, flags);
290 list_add(&hook->node, &undef_hook);
291 raw_spin_unlock_irqrestore(&undef_lock, flags);
294 void unregister_undef_hook(struct undef_hook *hook)
298 raw_spin_lock_irqsave(&undef_lock, flags);
299 list_del(&hook->node);
300 raw_spin_unlock_irqrestore(&undef_lock, flags);
303 static int call_undef_hook(struct pt_regs *regs)
305 struct undef_hook *hook;
308 int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
309 void __user *pc = (void __user *)instruction_pointer(regs);
311 if (!user_mode(regs)) {
313 if (probe_kernel_address((__force __le32 *)pc, instr_le))
315 instr = le32_to_cpu(instr_le);
316 } else if (compat_thumb_mode(regs)) {
317 /* 16-bit Thumb instruction */
319 if (get_user(instr_le, (__le16 __user *)pc))
321 instr = le16_to_cpu(instr_le);
322 if (aarch32_insn_is_wide(instr)) {
325 if (get_user(instr_le, (__le16 __user *)(pc + 2)))
327 instr2 = le16_to_cpu(instr_le);
328 instr = (instr << 16) | instr2;
331 /* 32-bit ARM instruction */
333 if (get_user(instr_le, (__le32 __user *)pc))
335 instr = le32_to_cpu(instr_le);
338 raw_spin_lock_irqsave(&undef_lock, flags);
339 list_for_each_entry(hook, &undef_hook, node)
340 if ((instr & hook->instr_mask) == hook->instr_val &&
341 (regs->pstate & hook->pstate_mask) == hook->pstate_val)
344 raw_spin_unlock_irqrestore(&undef_lock, flags);
346 return fn ? fn(regs, instr) : 1;
349 void force_signal_inject(int signal, int code, unsigned long address)
352 struct pt_regs *regs = current_pt_regs();
354 if (WARN_ON(!user_mode(regs)))
359 desc = "undefined instruction";
362 desc = "illegal memory access";
365 desc = "unknown or unrecoverable error";
369 /* Force signals we don't understand to SIGKILL */
370 if (WARN_ON(signal != SIGKILL &&
371 siginfo_layout(signal, code) != SIL_FAULT)) {
375 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0);
379 * Set up process info to signal segmentation fault - called on access error.
381 void arm64_notify_segfault(unsigned long addr)
385 down_read(¤t->mm->mmap_sem);
386 if (find_vma(current->mm, addr) == NULL)
390 up_read(¤t->mm->mmap_sem);
392 force_signal_inject(SIGSEGV, code, addr);
395 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
397 /* check for AArch32 breakpoint instructions */
398 if (!aarch32_break_handler(regs))
401 if (call_undef_hook(regs) == 0)
404 BUG_ON(!user_mode(regs));
405 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
408 #define __user_cache_maint(insn, address, res) \
409 if (address >= user_addr_max()) { \
412 uaccess_ttbr0_enable(); \
414 "1: " insn ", %1\n" \
417 " .pushsection .fixup,\"ax\"\n" \
419 "3: mov %w0, %w2\n" \
422 _ASM_EXTABLE(1b, 3b) \
424 : "r" (address), "i" (-EFAULT)); \
425 uaccess_ttbr0_disable(); \
428 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
430 unsigned long address;
431 int rt = ESR_ELx_SYS64_ISS_RT(esr);
432 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
435 address = untagged_addr(pt_regs_read_reg(regs, rt));
438 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
439 __user_cache_maint("dc civac", address, ret);
441 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
442 __user_cache_maint("dc civac", address, ret);
444 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */
445 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
447 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */
448 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
450 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
451 __user_cache_maint("dc civac", address, ret);
453 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
454 __user_cache_maint("ic ivau", address, ret);
457 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
462 arm64_notify_segfault(address);
464 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
467 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
469 int rt = ESR_ELx_SYS64_ISS_RT(esr);
470 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
472 pt_regs_write_reg(regs, rt, val);
474 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
477 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
479 int rt = ESR_ELx_SYS64_ISS_RT(esr);
481 pt_regs_write_reg(regs, rt, arch_timer_read_counter());
482 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
485 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
487 int rt = ESR_ELx_SYS64_ISS_RT(esr);
489 pt_regs_write_reg(regs, rt, arch_timer_get_rate());
490 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
493 static void mrs_handler(unsigned int esr, struct pt_regs *regs)
497 rt = ESR_ELx_SYS64_ISS_RT(esr);
498 sysreg = esr_sys64_to_sysreg(esr);
500 if (do_emulate_mrs(regs, sysreg, rt) != 0)
501 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
504 static void wfi_handler(unsigned int esr, struct pt_regs *regs)
506 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
510 unsigned int esr_mask;
511 unsigned int esr_val;
512 void (*handler)(unsigned int esr, struct pt_regs *regs);
515 static struct sys64_hook sys64_hooks[] = {
517 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
518 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
519 .handler = user_cache_maint_handler,
522 /* Trap read access to CTR_EL0 */
523 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
524 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
525 .handler = ctr_read_handler,
528 /* Trap read access to CNTVCT_EL0 */
529 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
530 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
531 .handler = cntvct_read_handler,
534 /* Trap read access to CNTFRQ_EL0 */
535 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
536 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
537 .handler = cntfrq_read_handler,
540 /* Trap read access to CPUID registers */
541 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
542 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
543 .handler = mrs_handler,
546 /* Trap WFI instructions executed in userspace */
547 .esr_mask = ESR_ELx_WFx_MASK,
548 .esr_val = ESR_ELx_WFx_WFI_VAL,
549 .handler = wfi_handler,
556 #define PSTATE_IT_1_0_SHIFT 25
557 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT)
558 #define PSTATE_IT_7_2_SHIFT 10
559 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT)
561 static u32 compat_get_it_state(struct pt_regs *regs)
563 u32 it, pstate = regs->pstate;
565 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
566 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
571 static void compat_set_it_state(struct pt_regs *regs, u32 it)
575 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
576 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
578 regs->pstate &= ~PSR_AA32_IT_MASK;
579 regs->pstate |= pstate_it;
582 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs)
586 /* Only a T32 instruction can trap without CV being set */
587 if (!(esr & ESR_ELx_CV)) {
590 it = compat_get_it_state(regs);
596 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
599 return aarch32_opcode_cond_checks[cond](regs->pstate);
602 static void advance_itstate(struct pt_regs *regs)
607 if (!(regs->pstate & PSR_AA32_T_BIT) ||
608 !(regs->pstate & PSR_AA32_IT_MASK))
611 it = compat_get_it_state(regs);
614 * If this is the last instruction of the block, wipe the IT
615 * state. Otherwise advance it.
620 it = (it & 0xe0) | ((it << 1) & 0x1f);
622 compat_set_it_state(regs, it);
625 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs,
628 advance_itstate(regs);
629 arm64_skip_faulting_instruction(regs, sz);
632 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
634 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
636 pt_regs_write_reg(regs, reg, arch_timer_get_rate());
637 arm64_compat_skip_faulting_instruction(regs, 4);
640 static struct sys64_hook cp15_32_hooks[] = {
642 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
643 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
644 .handler = compat_cntfrq_read_handler,
649 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
651 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
652 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
653 u64 val = arch_timer_read_counter();
655 pt_regs_write_reg(regs, rt, lower_32_bits(val));
656 pt_regs_write_reg(regs, rt2, upper_32_bits(val));
657 arm64_compat_skip_faulting_instruction(regs, 4);
660 static struct sys64_hook cp15_64_hooks[] = {
662 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
663 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
664 .handler = compat_cntvct_read_handler,
669 asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs)
671 struct sys64_hook *hook, *hook_base;
673 if (!cp15_cond_valid(esr, regs)) {
675 * There is no T16 variant of a CP access, so we
676 * always advance PC by 4 bytes.
678 arm64_compat_skip_faulting_instruction(regs, 4);
682 switch (ESR_ELx_EC(esr)) {
683 case ESR_ELx_EC_CP15_32:
684 hook_base = cp15_32_hooks;
686 case ESR_ELx_EC_CP15_64:
687 hook_base = cp15_64_hooks;
694 for (hook = hook_base; hook->handler; hook++)
695 if ((hook->esr_mask & esr) == hook->esr_val) {
696 hook->handler(esr, regs);
701 * New cp15 instructions may previously have been undefined at
702 * EL0. Fall back to our usual undefined instruction handler
703 * so that we handle these consistently.
709 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
711 struct sys64_hook *hook;
713 for (hook = sys64_hooks; hook->handler; hook++)
714 if ((hook->esr_mask & esr) == hook->esr_val) {
715 hook->handler(esr, regs);
720 * New SYS instructions may previously have been undefined at EL0. Fall
721 * back to our usual undefined instruction handler so that we handle
722 * these consistently.
727 static const char *esr_class_str[] = {
728 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC",
729 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized",
730 [ESR_ELx_EC_WFx] = "WFI/WFE",
731 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC",
732 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC",
733 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC",
734 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC",
735 [ESR_ELx_EC_FP_ASIMD] = "ASIMD",
736 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS",
737 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC",
738 [ESR_ELx_EC_ILL] = "PSTATE.IL",
739 [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
740 [ESR_ELx_EC_HVC32] = "HVC (AArch32)",
741 [ESR_ELx_EC_SMC32] = "SMC (AArch32)",
742 [ESR_ELx_EC_SVC64] = "SVC (AArch64)",
743 [ESR_ELx_EC_HVC64] = "HVC (AArch64)",
744 [ESR_ELx_EC_SMC64] = "SMC (AArch64)",
745 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
746 [ESR_ELx_EC_SVE] = "SVE",
747 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
748 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
749 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
750 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment",
751 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)",
752 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)",
753 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment",
754 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)",
755 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)",
756 [ESR_ELx_EC_SERROR] = "SError",
757 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)",
758 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)",
759 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)",
760 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)",
761 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
762 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)",
763 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
764 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
765 [ESR_ELx_EC_BRK64] = "BRK (AArch64)",
768 const char *esr_get_class_string(u32 esr)
770 return esr_class_str[ESR_ELx_EC(esr)];
774 * bad_mode handles the impossible case in the exception vector. This is always
777 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
781 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
782 handler[reason], smp_processor_id(), esr,
783 esr_get_class_string(esr));
790 * bad_el0_sync handles unexpected, but potentially recoverable synchronous
791 * exceptions taken from EL0. Unlike bad_mode, this returns.
793 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
795 void __user *pc = (void __user *)instruction_pointer(regs);
797 current->thread.fault_address = 0;
798 current->thread.fault_code = esr;
800 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
801 "Bad EL0 synchronous exception");
804 #ifdef CONFIG_VMAP_STACK
806 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
809 asmlinkage void handle_bad_stack(struct pt_regs *regs)
811 unsigned long tsk_stk = (unsigned long)current->stack;
812 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
813 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
814 unsigned int esr = read_sysreg(esr_el1);
815 unsigned long far = read_sysreg(far_el1);
818 pr_emerg("Insufficient stack space to handle exception!");
820 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
821 pr_emerg("FAR: 0x%016lx\n", far);
823 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n",
824 tsk_stk, tsk_stk + THREAD_SIZE);
825 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n",
826 irq_stk, irq_stk + THREAD_SIZE);
827 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
828 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
833 * We use nmi_panic to limit the potential for recusive overflows, and
834 * to get a better stack trace.
836 nmi_panic(NULL, "kernel stack overflow");
841 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
845 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
846 smp_processor_id(), esr, esr_get_class_string(esr));
850 nmi_panic(regs, "Asynchronous SError Interrupt");
856 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
858 u32 aet = arm64_ras_serror_get_severity(esr);
861 case ESR_ELx_AET_CE: /* corrected error */
862 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */
864 * The CPU can make progress. We may take UEO again as
865 * a more severe error.
869 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */
870 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
872 * The CPU can't make progress. The exception may have
877 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */
879 /* Error has been silently propagated */
880 arm64_serror_panic(regs, esr);
884 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
886 const bool was_in_nmi = in_nmi();
891 /* non-RAS errors are not containable */
892 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
893 arm64_serror_panic(regs, esr);
899 void __pte_error(const char *file, int line, unsigned long val)
901 pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
904 void __pmd_error(const char *file, int line, unsigned long val)
906 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
909 void __pud_error(const char *file, int line, unsigned long val)
911 pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
914 void __pgd_error(const char *file, int line, unsigned long val)
916 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
919 /* GENERIC_BUG traps */
921 int is_valid_bugaddr(unsigned long addr)
924 * bug_handler() only called for BRK #BUG_BRK_IMM.
925 * So the answer is trivial -- any spurious instances with no
926 * bug table entry will be rejected by report_bug() and passed
927 * back to the debug-monitors code and handled as a fatal
928 * unexpected debug exception.
933 static int bug_handler(struct pt_regs *regs, unsigned int esr)
935 switch (report_bug(regs->pc, regs)) {
936 case BUG_TRAP_TYPE_BUG:
937 die("Oops - BUG", regs, 0);
940 case BUG_TRAP_TYPE_WARN:
944 /* unknown/unrecognised bug trap type */
945 return DBG_HOOK_ERROR;
948 /* If thread survives, skip over the BUG instruction and continue: */
949 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
950 return DBG_HOOK_HANDLED;
953 static struct break_hook bug_break_hook = {
958 #ifdef CONFIG_KASAN_SW_TAGS
960 #define KASAN_ESR_RECOVER 0x20
961 #define KASAN_ESR_WRITE 0x10
962 #define KASAN_ESR_SIZE_MASK 0x0f
963 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK))
965 static int kasan_handler(struct pt_regs *regs, unsigned int esr)
967 bool recover = esr & KASAN_ESR_RECOVER;
968 bool write = esr & KASAN_ESR_WRITE;
969 size_t size = KASAN_ESR_SIZE(esr);
970 u64 addr = regs->regs[0];
973 kasan_report(addr, size, write, pc);
976 * The instrumentation allows to control whether we can proceed after
977 * a crash was detected. This is done by passing the -recover flag to
978 * the compiler. Disabling recovery allows to generate more compact
981 * Unfortunately disabling recovery doesn't work for the kernel right
982 * now. KASAN reporting is disabled in some contexts (for example when
983 * the allocator accesses slab object metadata; this is controlled by
984 * current->kasan_depth). All these accesses are detected by the tool,
985 * even though the reports for them are not printed.
987 * This is something that might be fixed at some point in the future.
990 die("Oops - KASAN", regs, 0);
992 /* If thread survives, skip over the brk instruction and continue: */
993 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
994 return DBG_HOOK_HANDLED;
997 static struct break_hook kasan_break_hook = {
999 .imm = KASAN_BRK_IMM,
1000 .mask = KASAN_BRK_MASK,
1005 * Initial handler for AArch64 BRK exceptions
1006 * This handler only used until debug_traps_init().
1008 int __init early_brk64(unsigned long addr, unsigned int esr,
1009 struct pt_regs *regs)
1011 #ifdef CONFIG_KASAN_SW_TAGS
1012 unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
1014 if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
1015 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1017 return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1020 /* This registration must happen early, before debug_traps_init(). */
1021 void __init trap_init(void)
1023 register_kernel_break_hook(&bug_break_hook);
1024 #ifdef CONFIG_KASAN_SW_TAGS
1025 register_kernel_break_hook(&kasan_break_hook);