1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/process.c
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
12 #include <linux/compat.h>
13 #include <linux/efi.h>
14 #include <linux/elf.h>
15 #include <linux/export.h>
16 #include <linux/sched.h>
17 #include <linux/sched/debug.h>
18 #include <linux/sched/task.h>
19 #include <linux/sched/task_stack.h>
20 #include <linux/kernel.h>
21 #include <linux/mman.h>
23 #include <linux/nospec.h>
24 #include <linux/stddef.h>
25 #include <linux/sysctl.h>
26 #include <linux/unistd.h>
27 #include <linux/user.h>
28 #include <linux/delay.h>
29 #include <linux/reboot.h>
30 #include <linux/interrupt.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/elfcore.h>
35 #include <linux/tick.h>
36 #include <linux/utsname.h>
37 #include <linux/uaccess.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/personality.h>
41 #include <linux/notifier.h>
42 #include <trace/events/power.h>
43 #include <linux/percpu.h>
44 #include <linux/thread_info.h>
45 #include <linux/prctl.h>
47 #include <asm/alternative.h>
48 #include <asm/compat.h>
49 #include <asm/cpufeature.h>
50 #include <asm/cacheflush.h>
52 #include <asm/fpsimd.h>
53 #include <asm/mmu_context.h>
55 #include <asm/processor.h>
56 #include <asm/pointer_auth.h>
57 #include <asm/stacktrace.h>
58 #include <asm/switch_to.h>
59 #include <asm/system_misc.h>
61 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
62 #include <linux/stackprotector.h>
63 unsigned long __stack_chk_guard __read_mostly;
64 EXPORT_SYMBOL(__stack_chk_guard);
68 * Function pointers to optional machine specific functions
70 void (*pm_power_off)(void);
71 EXPORT_SYMBOL_GPL(pm_power_off);
73 void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
75 #ifdef CONFIG_HOTPLUG_CPU
76 void arch_cpu_idle_dead(void)
83 * Called by kexec, immediately prior to machine_kexec().
85 * This must completely disable all secondary CPUs; simply causing those CPUs
86 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
87 * kexec'd kernel to use any and all RAM as it sees fit, without having to
88 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
89 * functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this.
91 void machine_shutdown(void)
93 smp_shutdown_nonboot_cpus(reboot_cpu);
97 * Halting simply requires that the secondary CPUs stop performing any
98 * activity (executing tasks, handling interrupts). smp_send_stop()
101 void machine_halt(void)
109 * Power-off simply requires that the secondary CPUs stop performing any
110 * activity (executing tasks, handling interrupts). smp_send_stop()
111 * achieves this. When the system power is turned off, it will take all CPUs
114 void machine_power_off(void)
123 * Restart requires that the secondary CPUs stop performing any activity
124 * while the primary CPU resets the system. Systems with multiple CPUs must
125 * provide a HW restart implementation, to ensure that all CPUs reset at once.
126 * This is required so that any code running after reset on the primary CPU
127 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
128 * executing pre-reset code, and using RAM that the primary CPU's code wishes
129 * to use. Implementing such co-ordination would be essentially impossible.
131 void machine_restart(char *cmd)
133 /* Disable interrupts first */
138 * UpdateCapsule() depends on the system being reset via
141 if (efi_enabled(EFI_RUNTIME_SERVICES))
142 efi_reboot(reboot_mode, NULL);
144 /* Now call the architecture specific reboot code. */
146 arm_pm_restart(reboot_mode, cmd);
148 do_kernel_restart(cmd);
151 * Whoops - the architecture was unable to reboot.
153 printk("Reboot failed -- System halted\n");
157 #define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str
158 static const char *const btypes[] = {
166 static void print_pstate(struct pt_regs *regs)
168 u64 pstate = regs->pstate;
170 if (compat_user_mode(regs)) {
171 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n",
173 pstate & PSR_AA32_N_BIT ? 'N' : 'n',
174 pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
175 pstate & PSR_AA32_C_BIT ? 'C' : 'c',
176 pstate & PSR_AA32_V_BIT ? 'V' : 'v',
177 pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
178 pstate & PSR_AA32_T_BIT ? "T32" : "A32",
179 pstate & PSR_AA32_E_BIT ? "BE" : "LE",
180 pstate & PSR_AA32_A_BIT ? 'A' : 'a',
181 pstate & PSR_AA32_I_BIT ? 'I' : 'i',
182 pstate & PSR_AA32_F_BIT ? 'F' : 'f');
184 const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
187 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO BTYPE=%s)\n",
189 pstate & PSR_N_BIT ? 'N' : 'n',
190 pstate & PSR_Z_BIT ? 'Z' : 'z',
191 pstate & PSR_C_BIT ? 'C' : 'c',
192 pstate & PSR_V_BIT ? 'V' : 'v',
193 pstate & PSR_D_BIT ? 'D' : 'd',
194 pstate & PSR_A_BIT ? 'A' : 'a',
195 pstate & PSR_I_BIT ? 'I' : 'i',
196 pstate & PSR_F_BIT ? 'F' : 'f',
197 pstate & PSR_PAN_BIT ? '+' : '-',
198 pstate & PSR_UAO_BIT ? '+' : '-',
199 pstate & PSR_TCO_BIT ? '+' : '-',
204 void __show_regs(struct pt_regs *regs)
209 if (compat_user_mode(regs)) {
210 lr = regs->compat_lr;
211 sp = regs->compat_sp;
219 show_regs_print_info(KERN_DEFAULT);
222 if (!user_mode(regs)) {
223 printk("pc : %pS\n", (void *)regs->pc);
224 printk("lr : %pS\n", (void *)ptrauth_strip_insn_pac(lr));
226 printk("pc : %016llx\n", regs->pc);
227 printk("lr : %016llx\n", lr);
230 printk("sp : %016llx\n", sp);
232 if (system_uses_irq_prio_masking())
233 printk("pmr_save: %08llx\n", regs->pmr_save);
238 printk("x%-2d: %016llx", i, regs->regs[i]);
241 pr_cont(" x%-2d: %016llx", i, regs->regs[i]);
247 void show_regs(struct pt_regs *regs)
250 dump_backtrace(regs, NULL, KERN_DEFAULT);
253 static void tls_thread_flush(void)
255 write_sysreg(0, tpidr_el0);
257 if (is_compat_task()) {
258 current->thread.uw.tp_value = 0;
261 * We need to ensure ordering between the shadow state and the
262 * hardware state, so that we don't corrupt the hardware state
263 * with a stale shadow state during context switch.
266 write_sysreg(0, tpidrro_el0);
270 static void flush_tagged_addr_state(void)
272 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
273 clear_thread_flag(TIF_TAGGED_ADDR);
276 void flush_thread(void)
278 fpsimd_flush_thread();
280 flush_ptrace_hw_breakpoint(current);
281 flush_tagged_addr_state();
284 void release_thread(struct task_struct *dead_task)
288 void arch_release_task_struct(struct task_struct *tsk)
290 fpsimd_release_task(tsk);
293 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
296 fpsimd_preserve_current_state();
299 /* We rely on the above assignment to initialize dst's thread_flags: */
300 BUILD_BUG_ON(!IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK));
303 * Detach src's sve_state (if any) from dst so that it does not
304 * get erroneously used or freed prematurely. dst's sve_state
305 * will be allocated on demand later on if dst uses SVE.
306 * For consistency, also clear TIF_SVE here: this could be done
307 * later in copy_process(), but to avoid tripping up future
308 * maintainers it is best not to leave TIF_SVE and sve_state in
309 * an inconsistent state, even temporarily.
311 dst->thread.sve_state = NULL;
312 clear_tsk_thread_flag(dst, TIF_SVE);
314 /* clear any pending asynchronous tag fault raised by the parent */
315 clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT);
320 asmlinkage void ret_from_fork(void) asm("ret_from_fork");
322 int copy_thread(unsigned long clone_flags, unsigned long stack_start,
323 unsigned long stk_sz, struct task_struct *p, unsigned long tls)
325 struct pt_regs *childregs = task_pt_regs(p);
327 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
330 * In case p was allocated the same task_struct pointer as some
331 * other recently-exited task, make sure p is disassociated from
332 * any cpu that may have run that now-exited task recently.
333 * Otherwise we could erroneously skip reloading the FPSIMD
336 fpsimd_flush_task_state(p);
338 ptrauth_thread_init_kernel(p);
340 if (likely(!(p->flags & (PF_KTHREAD | PF_IO_WORKER)))) {
341 *childregs = *current_pt_regs();
342 childregs->regs[0] = 0;
345 * Read the current TLS pointer from tpidr_el0 as it may be
346 * out-of-sync with the saved value.
348 *task_user_tls(p) = read_sysreg(tpidr_el0);
351 if (is_compat_thread(task_thread_info(p)))
352 childregs->compat_sp = stack_start;
354 childregs->sp = stack_start;
358 * If a TLS pointer was passed to clone, use it for the new
361 if (clone_flags & CLONE_SETTLS)
362 p->thread.uw.tp_value = tls;
365 * A kthread has no context to ERET to, so ensure any buggy
366 * ERET is treated as an illegal exception return.
368 * When a user task is created from a kthread, childregs will
369 * be initialized by start_thread() or start_compat_thread().
371 memset(childregs, 0, sizeof(struct pt_regs));
372 childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT;
374 p->thread.cpu_context.x19 = stack_start;
375 p->thread.cpu_context.x20 = stk_sz;
377 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
378 p->thread.cpu_context.sp = (unsigned long)childregs;
380 * For the benefit of the unwinder, set up childregs->stackframe
381 * as the final frame for the new task.
383 p->thread.cpu_context.fp = (unsigned long)childregs->stackframe;
385 ptrace_hw_copy_thread(p);
390 void tls_preserve_current_state(void)
392 *task_user_tls(current) = read_sysreg(tpidr_el0);
395 static void tls_thread_switch(struct task_struct *next)
397 tls_preserve_current_state();
399 if (is_compat_thread(task_thread_info(next)))
400 write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
401 else if (!arm64_kernel_unmapped_at_el0())
402 write_sysreg(0, tpidrro_el0);
404 write_sysreg(*task_user_tls(next), tpidr_el0);
408 * Force SSBS state on context-switch, since it may be lost after migrating
409 * from a CPU which treats the bit as RES0 in a heterogeneous system.
411 static void ssbs_thread_switch(struct task_struct *next)
414 * Nothing to do for kernel threads, but 'regs' may be junk
415 * (e.g. idle task) so check the flags and bail early.
417 if (unlikely(next->flags & PF_KTHREAD))
421 * If all CPUs implement the SSBS extension, then we just need to
422 * context-switch the PSTATE field.
424 if (cpus_have_const_cap(ARM64_SSBS))
427 spectre_v4_enable_task_mitigation(next);
431 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
432 * shadow copy so that we can restore this upon entry from userspace.
434 * This is *only* for exception entry from EL0, and is not valid until we
435 * __switch_to() a user task.
437 DEFINE_PER_CPU(struct task_struct *, __entry_task);
439 static void entry_task_switch(struct task_struct *next)
441 __this_cpu_write(__entry_task, next);
445 * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
446 * Assuming the virtual counter is enabled at the beginning of times:
448 * - disable access when switching from a 64bit task to a 32bit task
449 * - enable access when switching from a 32bit task to a 64bit task
451 static void erratum_1418040_thread_switch(struct task_struct *prev,
452 struct task_struct *next)
457 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040))
460 prev32 = is_compat_thread(task_thread_info(prev));
461 next32 = is_compat_thread(task_thread_info(next));
463 if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040))
466 val = read_sysreg(cntkctl_el1);
469 val |= ARCH_TIMER_USR_VCT_ACCESS_EN;
471 val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN;
473 write_sysreg(val, cntkctl_el1);
476 static void compat_thread_switch(struct task_struct *next)
478 if (!is_compat_thread(task_thread_info(next)))
481 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
482 set_tsk_thread_flag(next, TIF_NOTIFY_RESUME);
485 static void update_sctlr_el1(u64 sctlr)
488 * EnIA must not be cleared while in the kernel as this is necessary for
489 * in-kernel PAC. It will be cleared on kernel exit if needed.
491 sysreg_clear_set(sctlr_el1, SCTLR_USER_MASK & ~SCTLR_ELx_ENIA, sctlr);
493 /* ISB required for the kernel uaccess routines when setting TCF0. */
497 void set_task_sctlr_el1(u64 sctlr)
500 * __switch_to() checks current->thread.sctlr as an
501 * optimisation. Disable preemption so that it does not see
502 * the variable update before the SCTLR_EL1 one.
505 current->thread.sctlr_user = sctlr;
506 update_sctlr_el1(sctlr);
513 __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
514 struct task_struct *next)
516 struct task_struct *last;
518 fpsimd_thread_switch(next);
519 tls_thread_switch(next);
520 hw_breakpoint_thread_switch(next);
521 contextidr_thread_switch(next);
522 entry_task_switch(next);
523 ssbs_thread_switch(next);
524 erratum_1418040_thread_switch(prev, next);
525 ptrauth_thread_switch_user(next);
526 compat_thread_switch(next);
529 * Complete any pending TLB or cache maintenance on this CPU in case
530 * the thread migrates to a different CPU.
531 * This full barrier is also required by the membarrier system
537 * MTE thread switching must happen after the DSB above to ensure that
538 * any asynchronous tag check faults have been logged in the TFSR*_EL1
541 mte_thread_switch(next);
542 /* avoid expensive SCTLR_EL1 accesses if no change */
543 if (prev->thread.sctlr_user != next->thread.sctlr_user)
544 update_sctlr_el1(next->thread.sctlr_user);
546 /* the actual thread switch */
547 last = cpu_switch_to(prev, next);
552 unsigned long get_wchan(struct task_struct *p)
554 struct stackframe frame;
555 unsigned long stack_page, ret = 0;
557 if (!p || p == current || p->state == TASK_RUNNING)
560 stack_page = (unsigned long)try_get_task_stack(p);
564 start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p));
567 if (unwind_frame(p, &frame))
569 if (!in_sched_functions(frame.pc)) {
573 } while (count++ < 16);
580 unsigned long arch_align_stack(unsigned long sp)
582 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
583 sp -= get_random_int() & ~PAGE_MASK;
588 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
590 void arch_setup_new_exec(void)
592 unsigned long mmflags = 0;
594 if (is_compat_task()) {
595 mmflags = MMCF_AARCH32;
596 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
597 set_tsk_thread_flag(current, TIF_NOTIFY_RESUME);
600 current->mm->context.flags = mmflags;
601 ptrauth_thread_init_user();
602 mte_thread_init_user();
604 if (task_spec_ssb_noexec(current)) {
605 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
610 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
612 * Control the relaxed ABI allowing tagged user addresses into the kernel.
614 static unsigned int tagged_addr_disabled;
616 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
618 unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
619 struct thread_info *ti = task_thread_info(task);
621 if (is_compat_thread(ti))
624 if (system_supports_mte())
625 valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK;
627 if (arg & ~valid_mask)
631 * Do not allow the enabling of the tagged address ABI if globally
632 * disabled via sysctl abi.tagged_addr_disabled.
634 if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
637 if (set_mte_ctrl(task, arg) != 0)
640 update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
645 long get_tagged_addr_ctrl(struct task_struct *task)
648 struct thread_info *ti = task_thread_info(task);
650 if (is_compat_thread(ti))
653 if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR))
654 ret = PR_TAGGED_ADDR_ENABLE;
656 ret |= get_mte_ctrl(task);
662 * Global sysctl to disable the tagged user addresses support. This control
663 * only prevents the tagged address ABI enabling via prctl() and does not
664 * disable it for tasks that already opted in to the relaxed ABI.
667 static struct ctl_table tagged_addr_sysctl_table[] = {
669 .procname = "tagged_addr_disabled",
671 .data = &tagged_addr_disabled,
672 .maxlen = sizeof(int),
673 .proc_handler = proc_dointvec_minmax,
674 .extra1 = SYSCTL_ZERO,
675 .extra2 = SYSCTL_ONE,
680 static int __init tagged_addr_init(void)
682 if (!register_sysctl("abi", tagged_addr_sysctl_table))
687 core_initcall(tagged_addr_init);
688 #endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
690 #ifdef CONFIG_BINFMT_ELF
691 int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
692 bool has_interp, bool is_interp)
695 * For dynamically linked executables the interpreter is
696 * responsible for setting PROT_BTI on everything except
699 if (is_interp != has_interp)
702 if (!(state->flags & ARM64_ELF_BTI))
705 if (prot & PROT_EXEC)