1 // SPDX-License-Identifier: GPL-2.0-only
3 * AArch64 loadable module support.
5 * Copyright (C) 2012 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
10 #include <linux/bitops.h>
11 #include <linux/elf.h>
12 #include <linux/gfp.h>
13 #include <linux/kasan.h>
14 #include <linux/kernel.h>
16 #include <linux/moduleloader.h>
17 #include <linux/vmalloc.h>
18 #include <asm/alternative.h>
20 #include <asm/sections.h>
22 void *module_alloc(unsigned long size)
24 u64 module_alloc_end = module_alloc_base + MODULES_VSIZE;
25 gfp_t gfp_mask = GFP_KERNEL;
28 /* Silence the initial allocation */
29 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
30 gfp_mask |= __GFP_NOWARN;
32 if (IS_ENABLED(CONFIG_KASAN))
33 /* don't exceed the static module region - see below */
34 module_alloc_end = MODULES_END;
36 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
37 module_alloc_end, gfp_mask, PAGE_KERNEL, 0,
38 NUMA_NO_NODE, __builtin_return_address(0));
40 if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
41 !IS_ENABLED(CONFIG_KASAN))
43 * KASAN can only deal with module allocations being served
44 * from the reserved module region, since the remainder of
45 * the vmalloc region is already backed by zero shadow pages,
46 * and punching holes into it is non-trivial. Since the module
47 * region is not randomized when KASAN is enabled, it is even
48 * less likely that the module region gets exhausted, so we
49 * can simply omit this fallback in that case.
51 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
52 module_alloc_base + SZ_2G, GFP_KERNEL,
53 PAGE_KERNEL, 0, NUMA_NO_NODE,
54 __builtin_return_address(0));
56 if (p && (kasan_module_alloc(p, size) < 0)) {
64 enum aarch64_reloc_op {
71 static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
77 return val - (u64)place;
79 return (val & ~0xfff) - ((u64)place & ~0xfff);
84 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
88 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
90 s64 sval = do_reloc(op, place, val);
93 * The ELF psABI for AArch64 documents the 16-bit and 32-bit place
94 * relative and absolute relocations as having a range of [-2^15, 2^16)
95 * or [-2^31, 2^32), respectively. However, in order to be able to
96 * detect overflows reliably, we have to choose whether we interpret
97 * such quantities as signed or as unsigned, and stick with it.
98 * The way we organize our address space requires a signed
99 * interpretation of 32-bit relative references, so let's use that
100 * for all R_AARCH64_PRELxx relocations. This means our upper
101 * bound for overflow detection should be Sxx_MAX rather than Uxx_MAX.
106 *(s16 *)place = sval;
109 if (sval < 0 || sval > U16_MAX)
113 if (sval < S16_MIN || sval > S16_MAX)
117 pr_err("Invalid 16-bit data relocation (%d)\n", op);
122 *(s32 *)place = sval;
125 if (sval < 0 || sval > U32_MAX)
129 if (sval < S32_MIN || sval > S32_MAX)
133 pr_err("Invalid 32-bit data relocation (%d)\n", op);
138 *(s64 *)place = sval;
141 pr_err("Invalid length (%d) for data relocation\n", len);
147 enum aarch64_insn_movw_imm_type {
148 AARCH64_INSN_IMM_MOVNZ,
149 AARCH64_INSN_IMM_MOVKZ,
152 static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
153 int lsb, enum aarch64_insn_movw_imm_type imm_type)
157 u32 insn = le32_to_cpu(*place);
159 sval = do_reloc(op, place, val);
162 if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
164 * For signed MOVW relocations, we have to manipulate the
165 * instruction encoding depending on whether or not the
166 * immediate is less than zero.
170 /* >=0: Set the instruction to MOVZ (opcode 10b). */
174 * <0: Set the instruction to MOVN (opcode 00b).
175 * Since we've masked the opcode already, we
176 * don't need to do anything other than
177 * inverting the new immediate field.
183 /* Update the instruction with the new encoding. */
184 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
185 *place = cpu_to_le32(insn);
193 static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
194 int lsb, int len, enum aarch64_insn_imm_type imm_type)
198 u32 insn = le32_to_cpu(*place);
200 /* Calculate the relocation value. */
201 sval = do_reloc(op, place, val);
204 /* Extract the value bits and shift them to bit 0. */
205 imm_mask = (BIT(lsb + len) - 1) >> lsb;
206 imm = sval & imm_mask;
208 /* Update the instruction's immediate field. */
209 insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
210 *place = cpu_to_le32(insn);
213 * Extract the upper value bits (including the sign bit) and
214 * shift them to bit 0.
216 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
219 * Overflow has occurred if the upper bits are not all equal to
220 * the sign bit of the value.
222 if ((u64)(sval + 1) >= 2)
228 static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs,
229 __le32 *place, u64 val)
233 if (!is_forbidden_offset_for_adrp(place))
234 return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
235 AARCH64_INSN_IMM_ADR);
237 /* patch ADRP to ADR if it is in range */
238 if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
239 AARCH64_INSN_IMM_ADR)) {
240 insn = le32_to_cpu(*place);
243 /* out of range for ADR -> emit a veneer */
244 val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff);
247 insn = aarch64_insn_gen_branch_imm((u64)place, val,
248 AARCH64_INSN_BRANCH_NOLINK);
251 *place = cpu_to_le32(insn);
255 int apply_relocate_add(Elf64_Shdr *sechdrs,
257 unsigned int symindex,
267 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
269 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
270 /* loc corresponds to P in the AArch64 ELF document. */
271 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
274 /* sym is the ELF symbol we're referring to. */
275 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
276 + ELF64_R_SYM(rel[i].r_info);
278 /* val corresponds to (S + A) in the AArch64 ELF document. */
279 val = sym->st_value + rel[i].r_addend;
281 /* Check for overflow by default. */
282 overflow_check = true;
284 /* Perform the static relocation. */
285 switch (ELF64_R_TYPE(rel[i].r_info)) {
286 /* Null relocations. */
292 /* Data relocations. */
293 case R_AARCH64_ABS64:
294 overflow_check = false;
295 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
297 case R_AARCH64_ABS32:
298 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
300 case R_AARCH64_ABS16:
301 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
303 case R_AARCH64_PREL64:
304 overflow_check = false;
305 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
307 case R_AARCH64_PREL32:
308 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
310 case R_AARCH64_PREL16:
311 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
314 /* MOVW instruction relocations. */
315 case R_AARCH64_MOVW_UABS_G0_NC:
316 overflow_check = false;
317 case R_AARCH64_MOVW_UABS_G0:
318 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
319 AARCH64_INSN_IMM_MOVKZ);
321 case R_AARCH64_MOVW_UABS_G1_NC:
322 overflow_check = false;
323 case R_AARCH64_MOVW_UABS_G1:
324 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
325 AARCH64_INSN_IMM_MOVKZ);
327 case R_AARCH64_MOVW_UABS_G2_NC:
328 overflow_check = false;
329 case R_AARCH64_MOVW_UABS_G2:
330 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
331 AARCH64_INSN_IMM_MOVKZ);
333 case R_AARCH64_MOVW_UABS_G3:
334 /* We're using the top bits so we can't overflow. */
335 overflow_check = false;
336 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
337 AARCH64_INSN_IMM_MOVKZ);
339 case R_AARCH64_MOVW_SABS_G0:
340 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
341 AARCH64_INSN_IMM_MOVNZ);
343 case R_AARCH64_MOVW_SABS_G1:
344 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
345 AARCH64_INSN_IMM_MOVNZ);
347 case R_AARCH64_MOVW_SABS_G2:
348 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
349 AARCH64_INSN_IMM_MOVNZ);
351 case R_AARCH64_MOVW_PREL_G0_NC:
352 overflow_check = false;
353 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
354 AARCH64_INSN_IMM_MOVKZ);
356 case R_AARCH64_MOVW_PREL_G0:
357 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
358 AARCH64_INSN_IMM_MOVNZ);
360 case R_AARCH64_MOVW_PREL_G1_NC:
361 overflow_check = false;
362 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
363 AARCH64_INSN_IMM_MOVKZ);
365 case R_AARCH64_MOVW_PREL_G1:
366 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
367 AARCH64_INSN_IMM_MOVNZ);
369 case R_AARCH64_MOVW_PREL_G2_NC:
370 overflow_check = false;
371 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
372 AARCH64_INSN_IMM_MOVKZ);
374 case R_AARCH64_MOVW_PREL_G2:
375 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
376 AARCH64_INSN_IMM_MOVNZ);
378 case R_AARCH64_MOVW_PREL_G3:
379 /* We're using the top bits so we can't overflow. */
380 overflow_check = false;
381 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
382 AARCH64_INSN_IMM_MOVNZ);
385 /* Immediate instruction relocations. */
386 case R_AARCH64_LD_PREL_LO19:
387 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
388 AARCH64_INSN_IMM_19);
390 case R_AARCH64_ADR_PREL_LO21:
391 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
392 AARCH64_INSN_IMM_ADR);
394 case R_AARCH64_ADR_PREL_PG_HI21_NC:
395 overflow_check = false;
396 case R_AARCH64_ADR_PREL_PG_HI21:
397 ovf = reloc_insn_adrp(me, sechdrs, loc, val);
398 if (ovf && ovf != -ERANGE)
401 case R_AARCH64_ADD_ABS_LO12_NC:
402 case R_AARCH64_LDST8_ABS_LO12_NC:
403 overflow_check = false;
404 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
405 AARCH64_INSN_IMM_12);
407 case R_AARCH64_LDST16_ABS_LO12_NC:
408 overflow_check = false;
409 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
410 AARCH64_INSN_IMM_12);
412 case R_AARCH64_LDST32_ABS_LO12_NC:
413 overflow_check = false;
414 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
415 AARCH64_INSN_IMM_12);
417 case R_AARCH64_LDST64_ABS_LO12_NC:
418 overflow_check = false;
419 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
420 AARCH64_INSN_IMM_12);
422 case R_AARCH64_LDST128_ABS_LO12_NC:
423 overflow_check = false;
424 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
425 AARCH64_INSN_IMM_12);
427 case R_AARCH64_TSTBR14:
428 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
429 AARCH64_INSN_IMM_14);
431 case R_AARCH64_CONDBR19:
432 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
433 AARCH64_INSN_IMM_19);
435 case R_AARCH64_JUMP26:
436 case R_AARCH64_CALL26:
437 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
438 AARCH64_INSN_IMM_26);
440 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
442 val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym);
445 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
446 26, AARCH64_INSN_IMM_26);
451 pr_err("module %s: unsupported RELA relocation: %llu\n",
452 me->name, ELF64_R_TYPE(rel[i].r_info));
456 if (overflow_check && ovf == -ERANGE)
464 pr_err("module %s: overflow in relocation type %d val %Lx\n",
465 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
469 int module_finalize(const Elf_Ehdr *hdr,
470 const Elf_Shdr *sechdrs,
473 const Elf_Shdr *s, *se;
474 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
476 for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
477 if (strcmp(".altinstructions", secstrs + s->sh_name) == 0)
478 apply_alternatives_module((void *)s->sh_addr, s->sh_size);
479 #ifdef CONFIG_ARM64_MODULE_PLTS
480 if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
481 !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
482 me->arch.ftrace_trampoline = (void *)s->sh_addr;