arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/sort.h>
  14 #include <linux/stop_machine.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/cpu.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/cpu_ops.h>
  21 #include <asm/fpsimd.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/processor.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/traps.h>
  26 #include <asm/virt.h>
  27
  28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  29 static unsigned long elf_hwcap __read_mostly;
  30
  31 #ifdef CONFIG_COMPAT
  32 #define COMPAT_ELF_HWCAP_DEFAULT        \
  33                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  34                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  35                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  36                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  37                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  38                                  COMPAT_HWCAP_LPAE)
  39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  40 unsigned int compat_elf_hwcap2 __read_mostly;
  41 #endif
  42
  43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  44 EXPORT_SYMBOL(cpu_hwcaps);
  45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  46
  47 /* Need also bit for ARM64_CB_PATCH */
  48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  49
  50 /*
  51  * Flag to indicate if we have computed the system wide
  52  * capabilities based on the boot time active CPUs. This
  53  * will be used to determine if a new booting CPU should
  54  * go through the verification process to make sure that it
  55  * supports the system capabilities, without using a hotplug
  56  * notifier.
  57  */
  58 static bool sys_caps_initialised;
  59
  60 static inline void set_sys_caps_initialised(void)
  61 {
  62         sys_caps_initialised = true;
  63 }
  64
  65 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  66 {
  67         /* file-wide pr_fmt adds "CPU features: " prefix */
  68         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  69         return 0;
  70 }
  71
  72 static struct notifier_block cpu_hwcaps_notifier = {
  73         .notifier_call = dump_cpu_hwcaps
  74 };
  75
  76 static int __init register_cpu_hwcaps_dumper(void)
  77 {
  78         atomic_notifier_chain_register(&panic_notifier_list,
  79                                        &cpu_hwcaps_notifier);
  80         return 0;
  81 }
  82 __initcall(register_cpu_hwcaps_dumper);
  83
  84 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  85 EXPORT_SYMBOL(cpu_hwcap_keys);
  86
  87 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  88         {                                               \
  89                 .sign = SIGNED,                         \
  90                 .visible = VISIBLE,                     \
  91                 .strict = STRICT,                       \
  92                 .type = TYPE,                           \
  93                 .shift = SHIFT,                         \
  94                 .width = WIDTH,                         \
  95                 .safe_val = SAFE_VAL,                   \
  96         }
  97
  98 /* Define a feature with unsigned values */
  99 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 100         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 101
 102 /* Define a feature with a signed value */
 103 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 104         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 105
 106 #define ARM64_FTR_END                                   \
 107         {                                               \
 108                 .width = 0,                             \
 109         }
 110
 111 /* meta feature for alternatives */
 112 static bool __maybe_unused
 113 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 114
 115 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 116
 117 /*
 118  * NOTE: Any changes to the visibility of features should be kept in
 119  * sync with the documentation of the CPU feature register ABI.
 120  */
 121 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 134         ARM64_FTR_END,
 135 };
 136
 137 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 140                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 142                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 145         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 147                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 149                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 151         ARM64_FTR_END,
 152 };
 153
 154 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 155         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 156         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 157         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 159                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 162         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 163         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 164         /* Linux doesn't care about the EL3 */
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 169         ARM64_FTR_END,
 170 };
 171
 172 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 173         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 174         ARM64_FTR_END,
 175 };
 176
 177 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 178         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 179         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 180         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 181         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 182         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 183         ARM64_FTR_END,
 184 };
 185
 186 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 187         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 188         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 189         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 190         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 191         /* Linux shouldn't care about secure memory */
 192         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 195         /*
 196          * Differing PARange is fine as long as all peripherals and memory are mapped
 197          * within the minimum PARange of all CPUs
 198          */
 199         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 200         ARM64_FTR_END,
 201 };
 202
 203 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 204         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 205         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 210         ARM64_FTR_END,
 211 };
 212
 213 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 214         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 215         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 216         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 217         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 221         ARM64_FTR_END,
 222 };
 223
 224 static const struct arm64_ftr_bits ftr_ctr[] = {
 225         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 226         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 227         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 228         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
 229         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 231         /*
 232          * Linux can handle differing I-cache policies. Userspace JITs will
 233          * make use of *minLine.
 234          * If we have differing I-cache policies, report it as the weakest - VIPT.
 235          */
 236         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 237         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 238         ARM64_FTR_END,
 239 };
 240
 241 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 242         .name           = "SYS_CTR_EL0",
 243         .ftr_bits       = ftr_ctr
 244 };
 245
 246 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 247         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 248         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 249         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 252         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 253         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 254         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 255         ARM64_FTR_END,
 256 };
 257
 258 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 259         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 264         /*
 265          * We can instantiate multiple PMU instances with different levels
 266          * of support.
 267          */
 268         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 269         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 270         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 271         ARM64_FTR_END,
 272 };
 273
 274 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 277         ARM64_FTR_END,
 278 };
 279
 280 static const struct arm64_ftr_bits ftr_dczid[] = {
 281         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 282         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 283         ARM64_FTR_END,
 284 };
 285
 286
 287 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 288         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 289         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 294         ARM64_FTR_END,
 295 };
 296
 297 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 298         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 299         ARM64_FTR_END,
 300 };
 301
 302 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 307         ARM64_FTR_END,
 308 };
 309
 310 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 311         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 312         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 313         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 314         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 319         ARM64_FTR_END,
 320 };
 321
 322 static const struct arm64_ftr_bits ftr_zcr[] = {
 323         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 324                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 325         ARM64_FTR_END,
 326 };
 327
 328 /*
 329  * Common ftr bits for a 32bit register with all hidden, strict
 330  * attributes, with 4bit feature fields and a default safe value of
 331  * 0. Covers the following 32bit registers:
 332  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 333  */
 334 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 335         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 342         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 343         ARM64_FTR_END,
 344 };
 345
 346 /* Table for a single 32bit feature value */
 347 static const struct arm64_ftr_bits ftr_single32[] = {
 348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 349         ARM64_FTR_END,
 350 };
 351
 352 static const struct arm64_ftr_bits ftr_raz[] = {
 353         ARM64_FTR_END,
 354 };
 355
 356 #define ARM64_FTR_REG(id, table) {              \
 357         .sys_id = id,                           \
 358         .reg =  &(struct arm64_ftr_reg){        \
 359                 .name = #id,                    \
 360                 .ftr_bits = &((table)[0]),      \
 361         }}
 362
 363 static const struct __ftr_reg_entry {
 364         u32                     sys_id;
 365         struct arm64_ftr_reg    *reg;
 366 } arm64_ftr_regs[] = {
 367
 368         /* Op1 = 0, CRn = 0, CRm = 1 */
 369         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 370         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 371         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 372         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 373         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 374         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 375         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 376
 377         /* Op1 = 0, CRn = 0, CRm = 2 */
 378         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 379         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 380         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 381         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 382         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 383         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 384         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 385
 386         /* Op1 = 0, CRn = 0, CRm = 3 */
 387         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 388         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 389         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 390
 391         /* Op1 = 0, CRn = 0, CRm = 4 */
 392         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 393         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 394         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 395
 396         /* Op1 = 0, CRn = 0, CRm = 5 */
 397         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 398         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 399
 400         /* Op1 = 0, CRn = 0, CRm = 6 */
 401         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 402         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 403
 404         /* Op1 = 0, CRn = 0, CRm = 7 */
 405         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 406         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 407         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 408
 409         /* Op1 = 0, CRn = 1, CRm = 2 */
 410         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 411
 412         /* Op1 = 3, CRn = 0, CRm = 0 */
 413         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 414         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 415
 416         /* Op1 = 3, CRn = 14, CRm = 0 */
 417         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 418 };
 419
 420 static int search_cmp_ftr_reg(const void *id, const void *regp)
 421 {
 422         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 423 }
 424
 425 /*
 426  * get_arm64_ftr_reg - Lookup a feature register entry using its
 427  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 428  * ascending order of sys_id , we use binary search to find a matching
 429  * entry.
 430  *
 431  * returns - Upon success,  matching ftr_reg entry for id.
 432  *         - NULL on failure. It is upto the caller to decide
 433  *           the impact of a failure.
 434  */
 435 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 436 {
 437         const struct __ftr_reg_entry *ret;
 438
 439         ret = bsearch((const void *)(unsigned long)sys_id,
 440                         arm64_ftr_regs,
 441                         ARRAY_SIZE(arm64_ftr_regs),
 442                         sizeof(arm64_ftr_regs[0]),
 443                         search_cmp_ftr_reg);
 444         if (ret)
 445                 return ret->reg;
 446         return NULL;
 447 }
 448
 449 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 450                                s64 ftr_val)
 451 {
 452         u64 mask = arm64_ftr_mask(ftrp);
 453
 454         reg &= ~mask;
 455         reg |= (ftr_val << ftrp->shift) & mask;
 456         return reg;
 457 }
 458
 459 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 460                                 s64 cur)
 461 {
 462         s64 ret = 0;
 463
 464         switch (ftrp->type) {
 465         case FTR_EXACT:
 466                 ret = ftrp->safe_val;
 467                 break;
 468         case FTR_LOWER_SAFE:
 469                 ret = new < cur ? new : cur;
 470                 break;
 471         case FTR_HIGHER_SAFE:
 472                 ret = new > cur ? new : cur;
 473                 break;
 474         default:
 475                 BUG();
 476         }
 477
 478         return ret;
 479 }
 480
 481 static void __init sort_ftr_regs(void)
 482 {
 483         int i;
 484
 485         /* Check that the array is sorted so that we can do the binary search */
 486         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 487                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 488 }
 489
 490 /*
 491  * Initialise the CPU feature register from Boot CPU values.
 492  * Also initiliases the strict_mask for the register.
 493  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 494  * RES0 for the system-wide value, and must strictly match.
 495  */
 496 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 497 {
 498         u64 val = 0;
 499         u64 strict_mask = ~0x0ULL;
 500         u64 user_mask = 0;
 501         u64 valid_mask = 0;
 502
 503         const struct arm64_ftr_bits *ftrp;
 504         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 505
 506         BUG_ON(!reg);
 507
 508         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 509                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 510                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 511
 512                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 513
 514                 valid_mask |= ftr_mask;
 515                 if (!ftrp->strict)
 516                         strict_mask &= ~ftr_mask;
 517                 if (ftrp->visible)
 518                         user_mask |= ftr_mask;
 519                 else
 520                         reg->user_val = arm64_ftr_set_value(ftrp,
 521                                                             reg->user_val,
 522                                                             ftrp->safe_val);
 523         }
 524
 525         val &= valid_mask;
 526
 527         reg->sys_val = val;
 528         reg->strict_mask = strict_mask;
 529         reg->user_mask = user_mask;
 530 }
 531
 532 extern const struct arm64_cpu_capabilities arm64_errata[];
 533 static const struct arm64_cpu_capabilities arm64_features[];
 534
 535 static void __init
 536 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 537 {
 538         for (; caps->matches; caps++) {
 539                 if (WARN(caps->capability >= ARM64_NCAPS,
 540                         "Invalid capability %d\n", caps->capability))
 541                         continue;
 542                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 543                         "Duplicate entry for capability %d\n",
 544                         caps->capability))
 545                         continue;
 546                 cpu_hwcaps_ptrs[caps->capability] = caps;
 547         }
 548 }
 549
 550 static void __init init_cpu_hwcaps_indirect_list(void)
 551 {
 552         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 553         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 554 }
 555
 556 static void __init setup_boot_cpu_capabilities(void);
 557
 558 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 559 {
 560         /* Before we start using the tables, make sure it is sorted */
 561         sort_ftr_regs();
 562
 563         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 564         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 565         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 566         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 567         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 568         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 569         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 570         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 571         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 572         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 573         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 574         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 575         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 576
 577         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 578                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 579                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 580                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 581                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 582                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 583                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 584                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 585                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 586                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 587                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 588                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 589                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 590                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 591                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 592                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 593                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 594         }
 595
 596         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 597                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 598                 sve_init_vq_map();
 599         }
 600
 601         /*
 602          * Initialize the indirect array of CPU hwcaps capabilities pointers
 603          * before we handle the boot CPU below.
 604          */
 605         init_cpu_hwcaps_indirect_list();
 606
 607         /*
 608          * Detect and enable early CPU capabilities based on the boot CPU,
 609          * after we have initialised the CPU feature infrastructure.
 610          */
 611         setup_boot_cpu_capabilities();
 612 }
 613
 614 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 615 {
 616         const struct arm64_ftr_bits *ftrp;
 617
 618         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 619                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 620                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 621
 622                 if (ftr_cur == ftr_new)
 623                         continue;
 624                 /* Find a safe value */
 625                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 626                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 627         }
 628
 629 }
 630
 631 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 632 {
 633         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 634
 635         BUG_ON(!regp);
 636         update_cpu_ftr_reg(regp, val);
 637         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 638                 return 0;
 639         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 640                         regp->name, boot, cpu, val);
 641         return 1;
 642 }
 643
 644 /*
 645  * Update system wide CPU feature registers with the values from a
 646  * non-boot CPU. Also performs SANITY checks to make sure that there
 647  * aren't any insane variations from that of the boot CPU.
 648  */
 649 void update_cpu_features(int cpu,
 650                          struct cpuinfo_arm64 *info,
 651                          struct cpuinfo_arm64 *boot)
 652 {
 653         int taint = 0;
 654
 655         /*
 656          * The kernel can handle differing I-cache policies, but otherwise
 657          * caches should look identical. Userspace JITs will make use of
 658          * *minLine.
 659          */
 660         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 661                                       info->reg_ctr, boot->reg_ctr);
 662
 663         /*
 664          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 665          * could result in too much or too little memory being zeroed if a
 666          * process is preempted and migrated between CPUs.
 667          */
 668         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 669                                       info->reg_dczid, boot->reg_dczid);
 670
 671         /* If different, timekeeping will be broken (especially with KVM) */
 672         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 673                                       info->reg_cntfrq, boot->reg_cntfrq);
 674
 675         /*
 676          * The kernel uses self-hosted debug features and expects CPUs to
 677          * support identical debug features. We presently need CTX_CMPs, WRPs,
 678          * and BRPs to be identical.
 679          * ID_AA64DFR1 is currently RES0.
 680          */
 681         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 682                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 683         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 684                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 685         /*
 686          * Even in big.LITTLE, processors should be identical instruction-set
 687          * wise.
 688          */
 689         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 690                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 691         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 692                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 693
 694         /*
 695          * Differing PARange support is fine as long as all peripherals and
 696          * memory are mapped within the minimum PARange of all CPUs.
 697          * Linux should not care about secure memory.
 698          */
 699         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 700                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 701         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 702                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 703         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 704                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 705
 706         /*
 707          * EL3 is not our concern.
 708          */
 709         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 710                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 711         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 712                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 713
 714         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 715                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 716
 717         /*
 718          * If we have AArch32, we care about 32-bit features for compat.
 719          * If the system doesn't support AArch32, don't update them.
 720          */
 721         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 722                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 723
 724                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 725                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 726                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 727                                         info->reg_id_isar0, boot->reg_id_isar0);
 728                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 729                                         info->reg_id_isar1, boot->reg_id_isar1);
 730                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 731                                         info->reg_id_isar2, boot->reg_id_isar2);
 732                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 733                                         info->reg_id_isar3, boot->reg_id_isar3);
 734                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 735                                         info->reg_id_isar4, boot->reg_id_isar4);
 736                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 737                                         info->reg_id_isar5, boot->reg_id_isar5);
 738
 739                 /*
 740                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 741                  * ACTLR formats could differ across CPUs and therefore would have to
 742                  * be trapped for virtualization anyway.
 743                  */
 744                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 745                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 746                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 747                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 748                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 749                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 750                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 751                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 752                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 753                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 754                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 755                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 756                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 757                                         info->reg_mvfr0, boot->reg_mvfr0);
 758                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 759                                         info->reg_mvfr1, boot->reg_mvfr1);
 760                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 761                                         info->reg_mvfr2, boot->reg_mvfr2);
 762         }
 763
 764         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 765                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 766                                         info->reg_zcr, boot->reg_zcr);
 767
 768                 /* Probe vector lengths, unless we already gave up on SVE */
 769                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 770                     !sys_caps_initialised)
 771                         sve_update_vq_map();
 772         }
 773
 774         /*
 775          * Mismatched CPU features are a recipe for disaster. Don't even
 776          * pretend to support them.
 777          */
 778         if (taint) {
 779                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 780                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 781         }
 782 }
 783
 784 u64 read_sanitised_ftr_reg(u32 id)
 785 {
 786         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 787
 788         /* We shouldn't get a request for an unsupported register */
 789         BUG_ON(!regp);
 790         return regp->sys_val;
 791 }
 792
 793 #define read_sysreg_case(r)     \
 794         case r:         return read_sysreg_s(r)
 795
 796 /*
 797  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 798  * Read the system register on the current CPU
 799  */
 800 static u64 __read_sysreg_by_encoding(u32 sys_id)
 801 {
 802         switch (sys_id) {
 803         read_sysreg_case(SYS_ID_PFR0_EL1);
 804         read_sysreg_case(SYS_ID_PFR1_EL1);
 805         read_sysreg_case(SYS_ID_DFR0_EL1);
 806         read_sysreg_case(SYS_ID_MMFR0_EL1);
 807         read_sysreg_case(SYS_ID_MMFR1_EL1);
 808         read_sysreg_case(SYS_ID_MMFR2_EL1);
 809         read_sysreg_case(SYS_ID_MMFR3_EL1);
 810         read_sysreg_case(SYS_ID_ISAR0_EL1);
 811         read_sysreg_case(SYS_ID_ISAR1_EL1);
 812         read_sysreg_case(SYS_ID_ISAR2_EL1);
 813         read_sysreg_case(SYS_ID_ISAR3_EL1);
 814         read_sysreg_case(SYS_ID_ISAR4_EL1);
 815         read_sysreg_case(SYS_ID_ISAR5_EL1);
 816         read_sysreg_case(SYS_MVFR0_EL1);
 817         read_sysreg_case(SYS_MVFR1_EL1);
 818         read_sysreg_case(SYS_MVFR2_EL1);
 819
 820         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 821         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 822         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 823         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 824         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 825         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 826         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 827         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 828         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 829         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 830
 831         read_sysreg_case(SYS_CNTFRQ_EL0);
 832         read_sysreg_case(SYS_CTR_EL0);
 833         read_sysreg_case(SYS_DCZID_EL0);
 834
 835         default:
 836                 BUG();
 837                 return 0;
 838         }
 839 }
 840
 841 #include <linux/irqchip/arm-gic-v3.h>
 842
 843 static bool
 844 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 845 {
 846         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 847
 848         return val >= entry->min_field_value;
 849 }
 850
 851 static bool
 852 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 853 {
 854         u64 val;
 855
 856         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 857         if (scope == SCOPE_SYSTEM)
 858                 val = read_sanitised_ftr_reg(entry->sys_reg);
 859         else
 860                 val = __read_sysreg_by_encoding(entry->sys_reg);
 861
 862         return feature_matches(val, entry);
 863 }
 864
 865 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 866 {
 867         bool has_sre;
 868
 869         if (!has_cpuid_feature(entry, scope))
 870                 return false;
 871
 872         has_sre = gic_enable_sre();
 873         if (!has_sre)
 874                 pr_warn_once("%s present but disabled by higher exception level\n",
 875                              entry->desc);
 876
 877         return has_sre;
 878 }
 879
 880 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 881 {
 882         u32 midr = read_cpuid_id();
 883
 884         /* Cavium ThunderX pass 1.x and 2.x */
 885         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 886                 MIDR_CPU_VAR_REV(0, 0),
 887                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 888 }
 889
 890 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 891 {
 892         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 893
 894         return cpuid_feature_extract_signed_field(pfr0,
 895                                         ID_AA64PFR0_FP_SHIFT) < 0;
 896 }
 897
 898 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 899                           int scope)
 900 {
 901         u64 ctr;
 902
 903         if (scope == SCOPE_SYSTEM)
 904                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 905         else
 906                 ctr = read_cpuid_effective_cachetype();
 907
 908         return ctr & BIT(CTR_IDC_SHIFT);
 909 }
 910
 911 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 912 {
 913         /*
 914          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 915          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 916          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 917          * value.
 918          */
 919         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 920                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 921 }
 922
 923 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 924                           int scope)
 925 {
 926         u64 ctr;
 927
 928         if (scope == SCOPE_SYSTEM)
 929                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 930         else
 931                 ctr = read_cpuid_cachetype();
 932
 933         return ctr & BIT(CTR_DIC_SHIFT);
 934 }
 935
 936 static bool __maybe_unused
 937 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 938 {
 939         /*
 940          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 941          * may share TLB entries with a CPU stuck in the crashed
 942          * kernel.
 943          */
 944          if (is_kdump_kernel())
 945                 return false;
 946
 947         return has_cpuid_feature(entry, scope);
 948 }
 949
 950 static bool __meltdown_safe = true;
 951 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 952
 953 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 954                                 int scope)
 955 {
 956         /* List of CPUs that are not vulnerable and don't need KPTI */
 957         static const struct midr_range kpti_safe_list[] = {
 958                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 959                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 960                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 961                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 962                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 963                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 964                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 965                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 966                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 967                 { /* sentinel */ }
 968         };
 969         char const *str = "kpti command line option";
 970         bool meltdown_safe;
 971
 972         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 973
 974         /* Defer to CPU feature registers */
 975         if (has_cpuid_feature(entry, scope))
 976                 meltdown_safe = true;
 977
 978         if (!meltdown_safe)
 979                 __meltdown_safe = false;
 980
 981         /*
 982          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 983          * ThunderX leads to apparent I-cache corruption of kernel text, which
 984          * ends as well as you might imagine. Don't even try.
 985          */
 986         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 987                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 988                 __kpti_forced = -1;
 989         }
 990
 991         /* Useful for KASLR robustness */
 992         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
 993                 if (!__kpti_forced) {
 994                         str = "KASLR";
 995                         __kpti_forced = 1;
 996                 }
 997         }
 998
 999         if (cpu_mitigations_off() && !__kpti_forced) {
1000                 str = "mitigations=off";
1001                 __kpti_forced = -1;
1002         }
1003
1004         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1005                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1006                 return false;
1007         }
1008
1009         /* Forced? */
1010         if (__kpti_forced) {
1011                 pr_info_once("kernel page table isolation forced %s by %s\n",
1012                              __kpti_forced > 0 ? "ON" : "OFF", str);
1013                 return __kpti_forced > 0;
1014         }
1015
1016         return !meltdown_safe;
1017 }
1018
1019 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1020 static void
1021 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1022 {
1023         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1024         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1025         kpti_remap_fn *remap_fn;
1026
1027         static bool kpti_applied = false;
1028         int cpu = smp_processor_id();
1029
1030         /*
1031          * We don't need to rewrite the page-tables if either we've done
1032          * it already or we have KASLR enabled and therefore have not
1033          * created any global mappings at all.
1034          */
1035         if (kpti_applied || kaslr_offset() > 0)
1036                 return;
1037
1038         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1039
1040         cpu_install_idmap();
1041         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1042         cpu_uninstall_idmap();
1043
1044         if (!cpu)
1045                 kpti_applied = true;
1046
1047         return;
1048 }
1049 #else
1050 static void
1051 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1052 {
1053 }
1054 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1055
1056 static int __init parse_kpti(char *str)
1057 {
1058         bool enabled;
1059         int ret = strtobool(str, &enabled);
1060
1061         if (ret)
1062                 return ret;
1063
1064         __kpti_forced = enabled ? 1 : -1;
1065         return 0;
1066 }
1067 early_param("kpti", parse_kpti);
1068
1069 #ifdef CONFIG_ARM64_HW_AFDBM
1070 static inline void __cpu_enable_hw_dbm(void)
1071 {
1072         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1073
1074         write_sysreg(tcr, tcr_el1);
1075         isb();
1076 }
1077
1078 static bool cpu_has_broken_dbm(void)
1079 {
1080         /* List of CPUs which have broken DBM support. */
1081         static const struct midr_range cpus[] = {
1082 #ifdef CONFIG_ARM64_ERRATUM_1024718
1083                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1084 #endif
1085                 {},
1086         };
1087
1088         return is_midr_in_range_list(read_cpuid_id(), cpus);
1089 }
1090
1091 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1092 {
1093         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1094                !cpu_has_broken_dbm();
1095 }
1096
1097 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1098 {
1099         if (cpu_can_use_dbm(cap))
1100                 __cpu_enable_hw_dbm();
1101 }
1102
1103 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1104                        int __unused)
1105 {
1106         static bool detected = false;
1107         /*
1108          * DBM is a non-conflicting feature. i.e, the kernel can safely
1109          * run a mix of CPUs with and without the feature. So, we
1110          * unconditionally enable the capability to allow any late CPU
1111          * to use the feature. We only enable the control bits on the
1112          * CPU, if it actually supports.
1113          *
1114          * We have to make sure we print the "feature" detection only
1115          * when at least one CPU actually uses it. So check if this CPU
1116          * can actually use it and print the message exactly once.
1117          *
1118          * This is safe as all CPUs (including secondary CPUs - due to the
1119          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1120          * goes through the "matches" check exactly once. Also if a CPU
1121          * matches the criteria, it is guaranteed that the CPU will turn
1122          * the DBM on, as the capability is unconditionally enabled.
1123          */
1124         if (!detected && cpu_can_use_dbm(cap)) {
1125                 detected = true;
1126                 pr_info("detected: Hardware dirty bit management\n");
1127         }
1128
1129         return true;
1130 }
1131
1132 #endif
1133
1134 #ifdef CONFIG_ARM64_VHE
1135 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1136 {
1137         return is_kernel_in_hyp_mode();
1138 }
1139
1140 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1141 {
1142         /*
1143          * Copy register values that aren't redirected by hardware.
1144          *
1145          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1146          * this value to tpidr_el2 before we patch the code. Once we've done
1147          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1148          * do anything here.
1149          */
1150         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1151                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1152 }
1153 #endif
1154
1155 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1156 {
1157         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1158
1159         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1160         WARN_ON(val & (7 << 27 | 7 << 21));
1161 }
1162
1163 #ifdef CONFIG_ARM64_SSBD
1164 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1165 {
1166         if (user_mode(regs))
1167                 return 1;
1168
1169         if (instr & BIT(PSTATE_Imm_shift))
1170                 regs->pstate |= PSR_SSBS_BIT;
1171         else
1172                 regs->pstate &= ~PSR_SSBS_BIT;
1173
1174         arm64_skip_faulting_instruction(regs, 4);
1175         return 0;
1176 }
1177
1178 static struct undef_hook ssbs_emulation_hook = {
1179         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1180         .instr_val      = 0xd500401f | PSTATE_SSBS,
1181         .fn             = ssbs_emulation_handler,
1182 };
1183
1184 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1185 {
1186         static bool undef_hook_registered = false;
1187         static DEFINE_RAW_SPINLOCK(hook_lock);
1188
1189         raw_spin_lock(&hook_lock);
1190         if (!undef_hook_registered) {
1191                 register_undef_hook(&ssbs_emulation_hook);
1192                 undef_hook_registered = true;
1193         }
1194         raw_spin_unlock(&hook_lock);
1195
1196         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1197                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1198                 arm64_set_ssbd_mitigation(false);
1199         } else {
1200                 arm64_set_ssbd_mitigation(true);
1201         }
1202 }
1203 #endif /* CONFIG_ARM64_SSBD */
1204
1205 #ifdef CONFIG_ARM64_PAN
1206 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1207 {
1208         /*
1209          * We modify PSTATE. This won't work from irq context as the PSTATE
1210          * is discarded once we return from the exception.
1211          */
1212         WARN_ON_ONCE(in_interrupt());
1213
1214         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1215         asm(SET_PSTATE_PAN(1));
1216 }
1217 #endif /* CONFIG_ARM64_PAN */
1218
1219 #ifdef CONFIG_ARM64_RAS_EXTN
1220 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1221 {
1222         /* Firmware may have left a deferred SError in this register. */
1223         write_sysreg_s(0, SYS_DISR_EL1);
1224 }
1225 #endif /* CONFIG_ARM64_RAS_EXTN */
1226
1227 #ifdef CONFIG_ARM64_PTR_AUTH
1228 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1229 {
1230         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1231                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1232 }
1233 #endif /* CONFIG_ARM64_PTR_AUTH */
1234
1235 #ifdef CONFIG_ARM64_PSEUDO_NMI
1236 static bool enable_pseudo_nmi;
1237
1238 static int __init early_enable_pseudo_nmi(char *p)
1239 {
1240         return strtobool(p, &enable_pseudo_nmi);
1241 }
1242 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1243
1244 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1245                                    int scope)
1246 {
1247         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1248 }
1249 #endif
1250
1251 static const struct arm64_cpu_capabilities arm64_features[] = {
1252         {
1253                 .desc = "GIC system register CPU interface",
1254                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1255                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1256                 .matches = has_useable_gicv3_cpuif,
1257                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1258                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1259                 .sign = FTR_UNSIGNED,
1260                 .min_field_value = 1,
1261         },
1262 #ifdef CONFIG_ARM64_PAN
1263         {
1264                 .desc = "Privileged Access Never",
1265                 .capability = ARM64_HAS_PAN,
1266                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1267                 .matches = has_cpuid_feature,
1268                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1269                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1270                 .sign = FTR_UNSIGNED,
1271                 .min_field_value = 1,
1272                 .cpu_enable = cpu_enable_pan,
1273         },
1274 #endif /* CONFIG_ARM64_PAN */
1275 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1276         {
1277                 .desc = "LSE atomic instructions",
1278                 .capability = ARM64_HAS_LSE_ATOMICS,
1279                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1280                 .matches = has_cpuid_feature,
1281                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1282                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1283                 .sign = FTR_UNSIGNED,
1284                 .min_field_value = 2,
1285         },
1286 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1287         {
1288                 .desc = "Software prefetching using PRFM",
1289                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1290                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1291                 .matches = has_no_hw_prefetch,
1292         },
1293 #ifdef CONFIG_ARM64_UAO
1294         {
1295                 .desc = "User Access Override",
1296                 .capability = ARM64_HAS_UAO,
1297                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1298                 .matches = has_cpuid_feature,
1299                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1300                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1301                 .min_field_value = 1,
1302                 /*
1303                  * We rely on stop_machine() calling uao_thread_switch() to set
1304                  * UAO immediately after patching.
1305                  */
1306         },
1307 #endif /* CONFIG_ARM64_UAO */
1308 #ifdef CONFIG_ARM64_PAN
1309         {
1310                 .capability = ARM64_ALT_PAN_NOT_UAO,
1311                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1312                 .matches = cpufeature_pan_not_uao,
1313         },
1314 #endif /* CONFIG_ARM64_PAN */
1315 #ifdef CONFIG_ARM64_VHE
1316         {
1317                 .desc = "Virtualization Host Extensions",
1318                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1319                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1320                 .matches = runs_at_el2,
1321                 .cpu_enable = cpu_copy_el2regs,
1322         },
1323 #endif  /* CONFIG_ARM64_VHE */
1324         {
1325                 .desc = "32-bit EL0 Support",
1326                 .capability = ARM64_HAS_32BIT_EL0,
1327                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1328                 .matches = has_cpuid_feature,
1329                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1330                 .sign = FTR_UNSIGNED,
1331                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1332                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1333         },
1334         {
1335                 .desc = "Kernel page table isolation (KPTI)",
1336                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1337                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1338                 /*
1339                  * The ID feature fields below are used to indicate that
1340                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1341                  * more details.
1342                  */
1343                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1344                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1345                 .min_field_value = 1,
1346                 .matches = unmap_kernel_at_el0,
1347                 .cpu_enable = kpti_install_ng_mappings,
1348         },
1349         {
1350                 /* FP/SIMD is not implemented */
1351                 .capability = ARM64_HAS_NO_FPSIMD,
1352                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1353                 .min_field_value = 0,
1354                 .matches = has_no_fpsimd,
1355         },
1356 #ifdef CONFIG_ARM64_PMEM
1357         {
1358                 .desc = "Data cache clean to Point of Persistence",
1359                 .capability = ARM64_HAS_DCPOP,
1360                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1361                 .matches = has_cpuid_feature,
1362                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1363                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1364                 .min_field_value = 1,
1365         },
1366         {
1367                 .desc = "Data cache clean to Point of Deep Persistence",
1368                 .capability = ARM64_HAS_DCPODP,
1369                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1370                 .matches = has_cpuid_feature,
1371                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1372                 .sign = FTR_UNSIGNED,
1373                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1374                 .min_field_value = 2,
1375         },
1376 #endif
1377 #ifdef CONFIG_ARM64_SVE
1378         {
1379                 .desc = "Scalable Vector Extension",
1380                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1381                 .capability = ARM64_SVE,
1382                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1383                 .sign = FTR_UNSIGNED,
1384                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1385                 .min_field_value = ID_AA64PFR0_SVE,
1386                 .matches = has_cpuid_feature,
1387                 .cpu_enable = sve_kernel_enable,
1388         },
1389 #endif /* CONFIG_ARM64_SVE */
1390 #ifdef CONFIG_ARM64_RAS_EXTN
1391         {
1392                 .desc = "RAS Extension Support",
1393                 .capability = ARM64_HAS_RAS_EXTN,
1394                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1395                 .matches = has_cpuid_feature,
1396                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1397                 .sign = FTR_UNSIGNED,
1398                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1399                 .min_field_value = ID_AA64PFR0_RAS_V1,
1400                 .cpu_enable = cpu_clear_disr,
1401         },
1402 #endif /* CONFIG_ARM64_RAS_EXTN */
1403         {
1404                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1405                 .capability = ARM64_HAS_CACHE_IDC,
1406                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1407                 .matches = has_cache_idc,
1408                 .cpu_enable = cpu_emulate_effective_ctr,
1409         },
1410         {
1411                 .desc = "Instruction cache invalidation not required for I/D coherence",
1412                 .capability = ARM64_HAS_CACHE_DIC,
1413                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1414                 .matches = has_cache_dic,
1415         },
1416         {
1417                 .desc = "Stage-2 Force Write-Back",
1418                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1419                 .capability = ARM64_HAS_STAGE2_FWB,
1420                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1421                 .sign = FTR_UNSIGNED,
1422                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1423                 .min_field_value = 1,
1424                 .matches = has_cpuid_feature,
1425                 .cpu_enable = cpu_has_fwb,
1426         },
1427 #ifdef CONFIG_ARM64_HW_AFDBM
1428         {
1429                 /*
1430                  * Since we turn this on always, we don't want the user to
1431                  * think that the feature is available when it may not be.
1432                  * So hide the description.
1433                  *
1434                  * .desc = "Hardware pagetable Dirty Bit Management",
1435                  *
1436                  */
1437                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1438                 .capability = ARM64_HW_DBM,
1439                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1440                 .sign = FTR_UNSIGNED,
1441                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1442                 .min_field_value = 2,
1443                 .matches = has_hw_dbm,
1444                 .cpu_enable = cpu_enable_hw_dbm,
1445         },
1446 #endif
1447         {
1448                 .desc = "CRC32 instructions",
1449                 .capability = ARM64_HAS_CRC32,
1450                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1451                 .matches = has_cpuid_feature,
1452                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1453                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1454                 .min_field_value = 1,
1455         },
1456 #ifdef CONFIG_ARM64_SSBD
1457         {
1458                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1459                 .capability = ARM64_SSBS,
1460                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1461                 .matches = has_cpuid_feature,
1462                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1463                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1464                 .sign = FTR_UNSIGNED,
1465                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1466                 .cpu_enable = cpu_enable_ssbs,
1467         },
1468 #endif
1469 #ifdef CONFIG_ARM64_CNP
1470         {
1471                 .desc = "Common not Private translations",
1472                 .capability = ARM64_HAS_CNP,
1473                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1474                 .matches = has_useable_cnp,
1475                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1476                 .sign = FTR_UNSIGNED,
1477                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1478                 .min_field_value = 1,
1479                 .cpu_enable = cpu_enable_cnp,
1480         },
1481 #endif
1482         {
1483                 .desc = "Speculation barrier (SB)",
1484                 .capability = ARM64_HAS_SB,
1485                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1486                 .matches = has_cpuid_feature,
1487                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1488                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1489                 .sign = FTR_UNSIGNED,
1490                 .min_field_value = 1,
1491         },
1492 #ifdef CONFIG_ARM64_PTR_AUTH
1493         {
1494                 .desc = "Address authentication (architected algorithm)",
1495                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1496                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1497                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1498                 .sign = FTR_UNSIGNED,
1499                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1500                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1501                 .matches = has_cpuid_feature,
1502                 .cpu_enable = cpu_enable_address_auth,
1503         },
1504         {
1505                 .desc = "Address authentication (IMP DEF algorithm)",
1506                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1507                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1508                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1509                 .sign = FTR_UNSIGNED,
1510                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1511                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1512                 .matches = has_cpuid_feature,
1513                 .cpu_enable = cpu_enable_address_auth,
1514         },
1515         {
1516                 .desc = "Generic authentication (architected algorithm)",
1517                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1518                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1519                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1520                 .sign = FTR_UNSIGNED,
1521                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1522                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1523                 .matches = has_cpuid_feature,
1524         },
1525         {
1526                 .desc = "Generic authentication (IMP DEF algorithm)",
1527                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1528                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1529                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1530                 .sign = FTR_UNSIGNED,
1531                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1532                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1533                 .matches = has_cpuid_feature,
1534         },
1535 #endif /* CONFIG_ARM64_PTR_AUTH */
1536 #ifdef CONFIG_ARM64_PSEUDO_NMI
1537         {
1538                 /*
1539                  * Depends on having GICv3
1540                  */
1541                 .desc = "IRQ priority masking",
1542                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1543                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1544                 .matches = can_use_gic_priorities,
1545                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1546                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1547                 .sign = FTR_UNSIGNED,
1548                 .min_field_value = 1,
1549         },
1550 #endif
1551         {},
1552 };
1553
1554 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1555                 .matches = has_cpuid_feature,                                   \
1556                 .sys_reg = reg,                                                 \
1557                 .field_pos = field,                                             \
1558                 .sign = s,                                                      \
1559                 .min_field_value = min_value,
1560
1561 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1562                 .desc = name,                                                   \
1563                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1564                 .hwcap_type = cap_type,                                         \
1565                 .hwcap = cap,                                                   \
1566
1567 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1568         {                                                                       \
1569                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1570                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1571         }
1572
1573 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1574         {                                                                       \
1575                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1576                 .matches = cpucap_multi_entry_cap_matches,                      \
1577                 .match_list = list,                                             \
1578         }
1579
1580 #ifdef CONFIG_ARM64_PTR_AUTH
1581 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1582         {
1583                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1584                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1585         },
1586         {
1587                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1588                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1589         },
1590         {},
1591 };
1592
1593 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1594         {
1595                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1596                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1597         },
1598         {
1599                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1600                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1601         },
1602         {},
1603 };
1604 #endif
1605
1606 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1607         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1608         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1609         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1610         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1611         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1612         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1613         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1614         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1615         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1616         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1617         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1618         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1619         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1620         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1621         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1622         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1623         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1624         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1625         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1626         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1627         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1628         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1629         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1630         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1631         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1632         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1633         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1634         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1635         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1636 #ifdef CONFIG_ARM64_SVE
1637         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1638         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1639         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1640         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1641         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1642         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1643         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1644 #endif
1645         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1646 #ifdef CONFIG_ARM64_PTR_AUTH
1647         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1648         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1649 #endif
1650         {},
1651 };
1652
1653 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1654 #ifdef CONFIG_COMPAT
1655         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1656         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1657         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1658         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1659         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1660 #endif
1661         {},
1662 };
1663
1664 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1665 {
1666         switch (cap->hwcap_type) {
1667         case CAP_HWCAP:
1668                 cpu_set_feature(cap->hwcap);
1669                 break;
1670 #ifdef CONFIG_COMPAT
1671         case CAP_COMPAT_HWCAP:
1672                 compat_elf_hwcap |= (u32)cap->hwcap;
1673                 break;
1674         case CAP_COMPAT_HWCAP2:
1675                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1676                 break;
1677 #endif
1678         default:
1679                 WARN_ON(1);
1680                 break;
1681         }
1682 }
1683
1684 /* Check if we have a particular HWCAP enabled */
1685 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1686 {
1687         bool rc;
1688
1689         switch (cap->hwcap_type) {
1690         case CAP_HWCAP:
1691                 rc = cpu_have_feature(cap->hwcap);
1692                 break;
1693 #ifdef CONFIG_COMPAT
1694         case CAP_COMPAT_HWCAP:
1695                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1696                 break;
1697         case CAP_COMPAT_HWCAP2:
1698                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1699                 break;
1700 #endif
1701         default:
1702                 WARN_ON(1);
1703                 rc = false;
1704         }
1705
1706         return rc;
1707 }
1708
1709 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1710 {
1711         /* We support emulation of accesses to CPU ID feature registers */
1712         cpu_set_named_feature(CPUID);
1713         for (; hwcaps->matches; hwcaps++)
1714                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1715                         cap_set_elf_hwcap(hwcaps);
1716 }
1717
1718 static void update_cpu_capabilities(u16 scope_mask)
1719 {
1720         int i;
1721         const struct arm64_cpu_capabilities *caps;
1722
1723         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1724         for (i = 0; i < ARM64_NCAPS; i++) {
1725                 caps = cpu_hwcaps_ptrs[i];
1726                 if (!caps || !(caps->type & scope_mask) ||
1727                     cpus_have_cap(caps->capability) ||
1728                     !caps->matches(caps, cpucap_default_scope(caps)))
1729                         continue;
1730
1731                 if (caps->desc)
1732                         pr_info("detected: %s\n", caps->desc);
1733                 cpus_set_cap(caps->capability);
1734
1735                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1736                         set_bit(caps->capability, boot_capabilities);
1737         }
1738 }
1739
1740 /*
1741  * Enable all the available capabilities on this CPU. The capabilities
1742  * with BOOT_CPU scope are handled separately and hence skipped here.
1743  */
1744 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1745 {
1746         int i;
1747         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1748
1749         for_each_available_cap(i) {
1750                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1751
1752                 if (WARN_ON(!cap))
1753                         continue;
1754
1755                 if (!(cap->type & non_boot_scope))
1756                         continue;
1757
1758                 if (cap->cpu_enable)
1759                         cap->cpu_enable(cap);
1760         }
1761         return 0;
1762 }
1763
1764 /*
1765  * Run through the enabled capabilities and enable() it on all active
1766  * CPUs
1767  */
1768 static void __init enable_cpu_capabilities(u16 scope_mask)
1769 {
1770         int i;
1771         const struct arm64_cpu_capabilities *caps;
1772         bool boot_scope;
1773
1774         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1775         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1776
1777         for (i = 0; i < ARM64_NCAPS; i++) {
1778                 unsigned int num;
1779
1780                 caps = cpu_hwcaps_ptrs[i];
1781                 if (!caps || !(caps->type & scope_mask))
1782                         continue;
1783                 num = caps->capability;
1784                 if (!cpus_have_cap(num))
1785                         continue;
1786
1787                 /* Ensure cpus_have_const_cap(num) works */
1788                 static_branch_enable(&cpu_hwcap_keys[num]);
1789
1790                 if (boot_scope && caps->cpu_enable)
1791                         /*
1792                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1793                          * before any secondary CPU boots. Thus, each secondary
1794                          * will enable the capability as appropriate via
1795                          * check_local_cpu_capabilities(). The only exception is
1796                          * the boot CPU, for which the capability must be
1797                          * enabled here. This approach avoids costly
1798                          * stop_machine() calls for this case.
1799                          */
1800                         caps->cpu_enable(caps);
1801         }
1802
1803         /*
1804          * For all non-boot scope capabilities, use stop_machine()
1805          * as it schedules the work allowing us to modify PSTATE,
1806          * instead of on_each_cpu() which uses an IPI, giving us a
1807          * PSTATE that disappears when we return.
1808          */
1809         if (!boot_scope)
1810                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1811                              NULL, cpu_online_mask);
1812 }
1813
1814 /*
1815  * Run through the list of capabilities to check for conflicts.
1816  * If the system has already detected a capability, take necessary
1817  * action on this CPU.
1818  *
1819  * Returns "false" on conflicts.
1820  */
1821 static bool verify_local_cpu_caps(u16 scope_mask)
1822 {
1823         int i;
1824         bool cpu_has_cap, system_has_cap;
1825         const struct arm64_cpu_capabilities *caps;
1826
1827         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1828
1829         for (i = 0; i < ARM64_NCAPS; i++) {
1830                 caps = cpu_hwcaps_ptrs[i];
1831                 if (!caps || !(caps->type & scope_mask))
1832                         continue;
1833
1834                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1835                 system_has_cap = cpus_have_cap(caps->capability);
1836
1837                 if (system_has_cap) {
1838                         /*
1839                          * Check if the new CPU misses an advertised feature,
1840                          * which is not safe to miss.
1841                          */
1842                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1843                                 break;
1844                         /*
1845                          * We have to issue cpu_enable() irrespective of
1846                          * whether the CPU has it or not, as it is enabeld
1847                          * system wide. It is upto the call back to take
1848                          * appropriate action on this CPU.
1849                          */
1850                         if (caps->cpu_enable)
1851                                 caps->cpu_enable(caps);
1852                 } else {
1853                         /*
1854                          * Check if the CPU has this capability if it isn't
1855                          * safe to have when the system doesn't.
1856                          */
1857                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1858                                 break;
1859                 }
1860         }
1861
1862         if (i < ARM64_NCAPS) {
1863                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1864                         smp_processor_id(), caps->capability,
1865                         caps->desc, system_has_cap, cpu_has_cap);
1866                 return false;
1867         }
1868
1869         return true;
1870 }
1871
1872 /*
1873  * Check for CPU features that are used in early boot
1874  * based on the Boot CPU value.
1875  */
1876 static void check_early_cpu_features(void)
1877 {
1878         verify_cpu_asid_bits();
1879         /*
1880          * Early features are used by the kernel already. If there
1881          * is a conflict, we cannot proceed further.
1882          */
1883         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1884                 cpu_panic_kernel();
1885 }
1886
1887 static void
1888 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1889 {
1890
1891         for (; caps->matches; caps++)
1892                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1893                         pr_crit("CPU%d: missing HWCAP: %s\n",
1894                                         smp_processor_id(), caps->desc);
1895                         cpu_die_early();
1896                 }
1897 }
1898
1899 static void verify_sve_features(void)
1900 {
1901         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1902         u64 zcr = read_zcr_features();
1903
1904         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1905         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1906
1907         if (len < safe_len || sve_verify_vq_map()) {
1908                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1909                         smp_processor_id());
1910                 cpu_die_early();
1911         }
1912
1913         /* Add checks on other ZCR bits here if necessary */
1914 }
1915
1916
1917 /*
1918  * Run through the enabled system capabilities and enable() it on this CPU.
1919  * The capabilities were decided based on the available CPUs at the boot time.
1920  * Any new CPU should match the system wide status of the capability. If the
1921  * new CPU doesn't have a capability which the system now has enabled, we
1922  * cannot do anything to fix it up and could cause unexpected failures. So
1923  * we park the CPU.
1924  */
1925 static void verify_local_cpu_capabilities(void)
1926 {
1927         /*
1928          * The capabilities with SCOPE_BOOT_CPU are checked from
1929          * check_early_cpu_features(), as they need to be verified
1930          * on all secondary CPUs.
1931          */
1932         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1933                 cpu_die_early();
1934
1935         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1936
1937         if (system_supports_32bit_el0())
1938                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1939
1940         if (system_supports_sve())
1941                 verify_sve_features();
1942 }
1943
1944 void check_local_cpu_capabilities(void)
1945 {
1946         /*
1947          * All secondary CPUs should conform to the early CPU features
1948          * in use by the kernel based on boot CPU.
1949          */
1950         check_early_cpu_features();
1951
1952         /*
1953          * If we haven't finalised the system capabilities, this CPU gets
1954          * a chance to update the errata work arounds and local features.
1955          * Otherwise, this CPU should verify that it has all the system
1956          * advertised capabilities.
1957          */
1958         if (!sys_caps_initialised)
1959                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1960         else
1961                 verify_local_cpu_capabilities();
1962 }
1963
1964 static void __init setup_boot_cpu_capabilities(void)
1965 {
1966         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1967         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1968         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1969         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1970 }
1971
1972 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1973 EXPORT_SYMBOL(arm64_const_caps_ready);
1974
1975 static void __init mark_const_caps_ready(void)
1976 {
1977         static_branch_enable(&arm64_const_caps_ready);
1978 }
1979
1980 bool this_cpu_has_cap(unsigned int n)
1981 {
1982         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
1983                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
1984
1985                 if (cap)
1986                         return cap->matches(cap, SCOPE_LOCAL_CPU);
1987         }
1988
1989         return false;
1990 }
1991
1992 void cpu_set_feature(unsigned int num)
1993 {
1994         WARN_ON(num >= MAX_CPU_FEATURES);
1995         elf_hwcap |= BIT(num);
1996 }
1997 EXPORT_SYMBOL_GPL(cpu_set_feature);
1998
1999 bool cpu_have_feature(unsigned int num)
2000 {
2001         WARN_ON(num >= MAX_CPU_FEATURES);
2002         return elf_hwcap & BIT(num);
2003 }
2004 EXPORT_SYMBOL_GPL(cpu_have_feature);
2005
2006 unsigned long cpu_get_elf_hwcap(void)
2007 {
2008         /*
2009          * We currently only populate the first 32 bits of AT_HWCAP. Please
2010          * note that for userspace compatibility we guarantee that bits 62
2011          * and 63 will always be returned as 0.
2012          */
2013         return lower_32_bits(elf_hwcap);
2014 }
2015
2016 unsigned long cpu_get_elf_hwcap2(void)
2017 {
2018         return upper_32_bits(elf_hwcap);
2019 }
2020
2021 static void __init setup_system_capabilities(void)
2022 {
2023         /*
2024          * We have finalised the system-wide safe feature
2025          * registers, finalise the capabilities that depend
2026          * on it. Also enable all the available capabilities,
2027          * that are not enabled already.
2028          */
2029         update_cpu_capabilities(SCOPE_SYSTEM);
2030         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2031 }
2032
2033 void __init setup_cpu_features(void)
2034 {
2035         u32 cwg;
2036
2037         setup_system_capabilities();
2038         mark_const_caps_ready();
2039         setup_elf_hwcaps(arm64_elf_hwcaps);
2040
2041         if (system_supports_32bit_el0())
2042                 setup_elf_hwcaps(compat_elf_hwcaps);
2043
2044         if (system_uses_ttbr0_pan())
2045                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2046
2047         sve_setup();
2048         minsigstksz_setup();
2049
2050         /* Advertise that we have computed the system capabilities */
2051         set_sys_caps_initialised();
2052
2053         /*
2054          * Check for sane CTR_EL0.CWG value.
2055          */
2056         cwg = cache_type_cwg();
2057         if (!cwg)
2058                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2059                         ARCH_DMA_MINALIGN);
2060 }
2061
2062 static bool __maybe_unused
2063 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2064 {
2065         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2066 }
2067
2068 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2069 {
2070         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2071 }
2072
2073 /*
2074  * We emulate only the following system register space.
2075  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2076  * See Table C5-6 System instruction encodings for System register accesses,
2077  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2078  */
2079 static inline bool __attribute_const__ is_emulated(u32 id)
2080 {
2081         return (sys_reg_Op0(id) == 0x3 &&
2082                 sys_reg_CRn(id) == 0x0 &&
2083                 sys_reg_Op1(id) == 0x0 &&
2084                 (sys_reg_CRm(id) == 0 ||
2085                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2086 }
2087
2088 /*
2089  * With CRm == 0, reg should be one of :
2090  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2091  */
2092 static inline int emulate_id_reg(u32 id, u64 *valp)
2093 {
2094         switch (id) {
2095         case SYS_MIDR_EL1:
2096                 *valp = read_cpuid_id();
2097                 break;
2098         case SYS_MPIDR_EL1:
2099                 *valp = SYS_MPIDR_SAFE_VAL;
2100                 break;
2101         case SYS_REVIDR_EL1:
2102                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2103                 *valp = 0;
2104                 break;
2105         default:
2106                 return -EINVAL;
2107         }
2108
2109         return 0;
2110 }
2111
2112 static int emulate_sys_reg(u32 id, u64 *valp)
2113 {
2114         struct arm64_ftr_reg *regp;
2115
2116         if (!is_emulated(id))
2117                 return -EINVAL;
2118
2119         if (sys_reg_CRm(id) == 0)
2120                 return emulate_id_reg(id, valp);
2121
2122         regp = get_arm64_ftr_reg(id);
2123         if (regp)
2124                 *valp = arm64_ftr_reg_user_value(regp);
2125         else
2126                 /*
2127                  * The untracked registers are either IMPLEMENTATION DEFINED
2128                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2129                  */
2130                 *valp = 0;
2131         return 0;
2132 }
2133
2134 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2135 {
2136         int rc;
2137         u64 val;
2138
2139         rc = emulate_sys_reg(sys_reg, &val);
2140         if (!rc) {
2141                 pt_regs_write_reg(regs, rt, val);
2142                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2143         }
2144         return rc;
2145 }
2146
2147 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2148 {
2149         u32 sys_reg, rt;
2150
2151         /*
2152          * sys_reg values are defined as used in mrs/msr instruction.
2153          * shift the imm value to get the encoding.
2154          */
2155         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2156         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2157         return do_emulate_mrs(regs, sys_reg, rt);
2158 }
2159
2160 static struct undef_hook mrs_hook = {
2161         .instr_mask = 0xfff00000,
2162         .instr_val  = 0xd5300000,
2163         .pstate_mask = PSR_AA32_MODE_MASK,
2164         .pstate_val = PSR_MODE_EL0t,
2165         .fn = emulate_mrs,
2166 };
2167
2168 static int __init enable_mrs_emulation(void)
2169 {
2170         register_undef_hook(&mrs_hook);
2171         return 0;
2172 }
2173
2174 core_initcall(enable_mrs_emulation);
2175
2176 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2177                           char *buf)
2178 {
2179         if (__meltdown_safe)
2180                 return sprintf(buf, "Not affected\n");
2181
2182         if (arm64_kernel_unmapped_at_el0())
2183                 return sprintf(buf, "Mitigation: PTI\n");
2184
2185         return sprintf(buf, "Vulnerable\n");
2186 }