2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_CACHETYPE_H
17 #define __ASM_CACHETYPE_H
19 #include <asm/cputype.h>
21 #define CTR_L1IP_SHIFT 14
22 #define CTR_L1IP_MASK 3
24 #define ICACHE_POLICY_RESERVED 0
25 #define ICACHE_POLICY_AIVIVT 1
26 #define ICACHE_POLICY_VIPT 2
27 #define ICACHE_POLICY_PIPT 3
29 static inline u32 icache_policy(void)
31 return (read_cpuid_cachetype() >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK;
35 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
36 * permitted in the I-cache.
38 static inline int icache_is_aliasing(void)
40 return icache_policy() != ICACHE_POLICY_PIPT;
43 static inline int icache_is_aivivt(void)
45 return icache_policy() == ICACHE_POLICY_AIVIVT;
48 #endif /* __ASM_CACHETYPE_H */