1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
8 #define L1_CACHE_SHIFT (6)
9 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
11 #define CLIDR_LOUU_SHIFT 27
12 #define CLIDR_LOC_SHIFT 24
13 #define CLIDR_LOUIS_SHIFT 21
15 #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
16 #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
17 #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
20 * Memory returned by kmalloc() may be used for DMA, so we must make
21 * sure that all such allocations are cache aligned. Otherwise,
22 * unrelated code may cause parts of the buffer to be read into the
23 * cache before the transfer is done, causing old data to be seen by
26 #define ARCH_DMA_MINALIGN (128)
30 #include <linux/bitops.h>
31 #include <linux/kasan-enabled.h>
33 #include <asm/cputype.h>
34 #include <asm/mte-def.h>
35 #include <asm/sysreg.h>
37 #ifdef CONFIG_KASAN_SW_TAGS
38 #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
39 #elif defined(CONFIG_KASAN_HW_TAGS)
40 static inline unsigned int arch_slab_minalign(void)
42 return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
43 __alignof__(unsigned long long);
45 #define arch_slab_minalign() arch_slab_minalign()
48 #define CTR_CACHE_MINLINE_MASK \
49 (0xf << CTR_EL0_DMINLINE_SHIFT | \
50 CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT)
52 #define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
54 #define ICACHEF_ALIASING 0
55 #define ICACHEF_VPIPT 1
56 extern unsigned long __icache_flags;
59 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
60 * permitted in the I-cache.
62 static inline int icache_is_aliasing(void)
64 return test_bit(ICACHEF_ALIASING, &__icache_flags);
67 static __always_inline int icache_is_vpipt(void)
69 return test_bit(ICACHEF_VPIPT, &__icache_flags);
72 static inline u32 cache_type_cwg(void)
74 return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
77 #define __read_mostly __section(".data..read_mostly")
79 static inline int cache_line_size_of_cpu(void)
81 u32 cwg = cache_type_cwg();
83 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
86 int cache_line_size(void);
89 * Read the effective value of CTR_EL0.
91 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
92 * section D10.2.33 "CTR_EL0, Cache Type Register" :
94 * CTR_EL0.IDC reports the data cache clean requirements for
95 * instruction to data coherence.
97 * 0 - dcache clean to PoU is required unless :
98 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
99 * 1 - dcache clean to PoU is not required for i-to-d coherence.
101 * This routine provides the CTR_EL0 with the IDC field updated to the
104 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
106 u32 ctr = read_cpuid_cachetype();
108 if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
109 u64 clidr = read_sysreg(clidr_el1);
111 if (CLIDR_LOC(clidr) == 0 ||
112 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
113 ctr |= BIT(CTR_EL0_IDC_SHIFT);
119 #endif /* __ASSEMBLY__ */