1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
9 #error "Only include this from assembly code"
12 #ifndef __ASM_ASSEMBLER_H
13 #define __ASM_ASSEMBLER_H
15 #include <asm-generic/export.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/alternative.h>
19 #include <asm/asm-bug.h>
20 #include <asm/cpufeature.h>
21 #include <asm/cputype.h>
22 #include <asm/debug-monitors.h>
24 #include <asm/pgtable-hwdef.h>
25 #include <asm/ptrace.h>
26 #include <asm/thread_info.h>
29 * Provide a wxN alias for each wN register so what we can paste a xN
30 * reference after a 'w' to obtain the 32-bit version.
32 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
36 .macro save_and_disable_daif, flags
49 .macro restore_daif, flags:req
53 /* IRQ/FIQ are the lowest priority flags, unconditionally unmask the rest. */
59 * Save/restore interrupts.
61 .macro save_and_disable_irq, flags
66 .macro restore_irq, flags
74 .macro disable_step_tsk, flgs, tmp
75 tbz \flgs, #TIF_SINGLESTEP, 9990f
77 bic \tmp, \tmp, #DBG_MDSCR_SS
79 isb // Synchronise with enable_dbg
83 /* call with daif masked */
84 .macro enable_step_tsk, flgs, tmp
85 tbz \flgs, #TIF_SINGLESTEP, 9990f
87 orr \tmp, \tmp, #DBG_MDSCR_SS
93 * RAS Error Synchronization barrier
96 #ifdef CONFIG_ARM64_RAS_EXTN
104 * Value prediction barrier
111 * Speculation barrier
114 alternative_if_not ARM64_HAS_SB
133 * Create an exception table entry for `insn`, which will branch to `fixup`
134 * when an unhandled fault is taken.
136 .macro _asm_extable, insn, fixup
137 .pushsection __ex_table, "a"
139 .long (\insn - .), (\fixup - .)
144 * Create an exception table entry for `insn` if `fixup` is provided. Otherwise
147 .macro _cond_extable, insn, fixup
149 _asm_extable \insn, \fixup
154 #define USER(l, x...) \
156 _asm_extable 9999b, l
161 lr .req x30 // link register
172 * Select code when configured for BE.
174 #ifdef CONFIG_CPU_BIG_ENDIAN
175 #define CPU_BE(code...) code
177 #define CPU_BE(code...)
181 * Select code when configured for LE.
183 #ifdef CONFIG_CPU_BIG_ENDIAN
184 #define CPU_LE(code...)
186 #define CPU_LE(code...) code
190 * Define a macro that constructs a 64-bit value by concatenating two
191 * 32-bit registers. Note that on big endian systems the order of the
192 * registers is swapped.
194 #ifndef CONFIG_CPU_BIG_ENDIAN
195 .macro regs_to_64, rd, lbits, hbits
197 .macro regs_to_64, rd, hbits, lbits
199 orr \rd, \lbits, \hbits, lsl #32
203 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
204 * <symbol> is within the range +/- 4 GB of the PC.
207 * @dst: destination register (64 bit wide)
208 * @sym: name of the symbol
210 .macro adr_l, dst, sym
212 add \dst, \dst, :lo12:\sym
216 * @dst: destination register (32 or 64 bit wide)
217 * @sym: name of the symbol
218 * @tmp: optional 64-bit scratch register to be used if <dst> is a
219 * 32-bit wide register, in which case it cannot be used to hold
222 .macro ldr_l, dst, sym, tmp=
225 ldr \dst, [\dst, :lo12:\sym]
228 ldr \dst, [\tmp, :lo12:\sym]
233 * @src: source register (32 or 64 bit wide)
234 * @sym: name of the symbol
235 * @tmp: mandatory 64-bit scratch register to calculate the address
236 * while <src> needs to be preserved.
238 .macro str_l, src, sym, tmp
240 str \src, [\tmp, :lo12:\sym]
244 * @dst: destination register
246 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
247 .macro get_this_cpu_offset, dst
251 .macro get_this_cpu_offset, dst
252 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
259 .macro set_this_cpu_offset, src
260 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
269 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
270 * @sym: The name of the per-cpu variable
271 * @tmp: scratch register
273 .macro adr_this_cpu, dst, sym, tmp
275 add \dst, \tmp, #:lo12:\sym
276 get_this_cpu_offset \tmp
281 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
282 * @sym: The name of the per-cpu variable
283 * @tmp: scratch register
285 .macro ldr_this_cpu dst, sym, tmp
287 get_this_cpu_offset \tmp
288 ldr \dst, [\dst, \tmp]
292 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
294 .macro vma_vm_mm, rd, rn
295 ldr \rd, [\rn, #VMA_VM_MM]
299 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
300 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
303 #ifndef __KVM_NVHE_HYPERVISOR__
304 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
305 mrs \reg, ctr_el0 // read CTR
308 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
311 alternative_if_not ARM64_KVM_PROTECTED_MODE
313 alternative_else_nop_endif
314 alternative_cb kvm_compute_final_ctr_el0
316 movk \reg, #0, lsl #16
317 movk \reg, #0, lsl #32
318 movk \reg, #0, lsl #48
325 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
326 * from the CTR register.
328 .macro raw_dcache_line_size, reg, tmp
329 mrs \tmp, ctr_el0 // read CTR
330 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
331 mov \reg, #4 // bytes per word
332 lsl \reg, \reg, \tmp // actual cache line size
336 * dcache_line_size - get the safe D-cache line size across all CPUs
338 .macro dcache_line_size, reg, tmp
340 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
341 mov \reg, #4 // bytes per word
342 lsl \reg, \reg, \tmp // actual cache line size
346 * raw_icache_line_size - get the minimum I-cache line size on this CPU
347 * from the CTR register.
349 .macro raw_icache_line_size, reg, tmp
350 mrs \tmp, ctr_el0 // read CTR
351 and \tmp, \tmp, #0xf // cache line size encoding
352 mov \reg, #4 // bytes per word
353 lsl \reg, \reg, \tmp // actual cache line size
357 * icache_line_size - get the safe I-cache line size across all CPUs
359 .macro icache_line_size, reg, tmp
361 and \tmp, \tmp, #0xf // cache line size encoding
362 mov \reg, #4 // bytes per word
363 lsl \reg, \reg, \tmp // actual cache line size
367 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
369 .macro tcr_set_t0sz, valreg, t0sz
370 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
374 * tcr_set_t1sz - update TCR.T1SZ
376 .macro tcr_set_t1sz, valreg, t1sz
377 bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH
381 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
382 * ID_AA64MMFR0_EL1.PARange value
384 * tcr: register with the TCR_ELx value to be updated
385 * pos: IPS or PS bitfield position
386 * tmp{0,1}: temporary registers
388 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
389 mrs \tmp0, ID_AA64MMFR0_EL1
390 // Narrow PARange to fit the PS field in TCR_ELx
391 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
392 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
394 csel \tmp0, \tmp1, \tmp0, hi
395 bfi \tcr, \tmp0, \pos, #3
398 .macro __dcache_op_workaround_clean_cache, op, addr
399 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
407 * Macro to perform a data cache maintenance for the interval
410 * op: operation passed to dc instruction
411 * domain: domain used in dsb instruciton
412 * start: starting virtual address of the region
413 * end: end virtual address of the region
414 * fixup: optional label to branch to on user fault
415 * Corrupts: start, end, tmp1, tmp2
417 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
418 dcache_line_size \tmp1, \tmp2
420 bic \start, \start, \tmp2
423 __dcache_op_workaround_clean_cache \op, \start
426 __dcache_op_workaround_clean_cache \op, \start
429 sys 3, c7, c12, 1, \start // dc cvap
432 sys 3, c7, c13, 1, \start // dc cvadp
439 add \start, \start, \tmp1
444 _cond_extable .Ldcache_op\@, \fixup
448 * Macro to perform an instruction cache maintenance for the interval
451 * start, end: virtual addresses describing the region
452 * fixup: optional label to branch to on user fault
453 * Corrupts: tmp1, tmp2
455 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
456 icache_line_size \tmp1, \tmp2
458 bic \tmp2, \start, \tmp2
460 ic ivau, \tmp2 // invalidate I line PoU
461 add \tmp2, \tmp2, \tmp1
467 _cond_extable .Licache_op\@, \fixup
471 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
473 .macro reset_pmuserenr_el0, tmpreg
474 mrs \tmpreg, id_aa64dfr0_el1
475 sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
476 cmp \tmpreg, #1 // Skip if no PMU present
478 msr pmuserenr_el0, xzr // Disable PMU access from EL0
483 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present
485 .macro reset_amuserenr_el0, tmpreg
486 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1
487 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4
488 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present
489 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0
493 * copy_page - copy src to dest using temp registers t1-t8
495 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
496 9998: ldp \t1, \t2, [\src]
497 ldp \t3, \t4, [\src, #16]
498 ldp \t5, \t6, [\src, #32]
499 ldp \t7, \t8, [\src, #48]
501 stnp \t1, \t2, [\dest]
502 stnp \t3, \t4, [\dest, #16]
503 stnp \t5, \t6, [\dest, #32]
504 stnp \t7, \t8, [\dest, #48]
505 add \dest, \dest, #64
506 tst \src, #(PAGE_SIZE - 1)
511 * Annotate a function as being unsuitable for kprobes.
513 #ifdef CONFIG_KPROBES
514 #define NOKPROBE(x) \
515 .pushsection "_kprobe_blacklist", "aw"; \
522 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
523 #define EXPORT_SYMBOL_NOKASAN(name)
525 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
529 * Emit a 64-bit absolute little endian symbol reference in a way that
530 * ensures that it will be resolved at build time, even when building a
531 * PIE binary. This requires cooperation from the linker script, which
532 * must emit the lo32/hi32 halves individually.
540 * mov_q - move an immediate constant into a 64-bit register using
541 * between 2 and 4 movz/movk instructions (depending on the
542 * magnitude and sign of the operand)
544 .macro mov_q, reg, val
545 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
546 movz \reg, :abs_g1_s:\val
548 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
549 movz \reg, :abs_g2_s:\val
551 movz \reg, :abs_g3:\val
552 movk \reg, :abs_g2_nc:\val
554 movk \reg, :abs_g1_nc:\val
556 movk \reg, :abs_g0_nc:\val
560 * Return the current task_struct.
562 .macro get_current_task, rd
567 * Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD.
568 * orr is used as it can cover the immediate value (and is idempotent).
569 * In future this may be nop'ed out when dealing with 52-bit kernel VAs.
570 * ttbr: Value of ttbr to set, modified.
572 .macro offset_ttbr1, ttbr, tmp
573 #ifdef CONFIG_ARM64_VA_BITS_52
574 mrs_s \tmp, SYS_ID_AA64MMFR2_EL1
575 and \tmp, \tmp, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
576 cbnz \tmp, .Lskipoffs_\@
577 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
583 * Perform the reverse of offset_ttbr1.
584 * bic is used as it can cover the immediate value and, in future, won't need
585 * to be nop'ed out when dealing with 52-bit kernel VAs.
587 .macro restore_ttbr1, ttbr
588 #ifdef CONFIG_ARM64_VA_BITS_52
589 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
594 * Arrange a physical address in a TTBR register, taking care of 52-bit
597 * phys: physical address, preserved
598 * ttbr: returns the TTBR value
600 .macro phys_to_ttbr, ttbr, phys
601 #ifdef CONFIG_ARM64_PA_BITS_52
602 orr \ttbr, \phys, \phys, lsr #46
603 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
609 .macro phys_to_pte, pte, phys
610 #ifdef CONFIG_ARM64_PA_BITS_52
612 * We assume \phys is 64K aligned and this is guaranteed by only
613 * supporting this configuration with 64K pages.
615 orr \pte, \phys, \phys, lsr #36
616 and \pte, \pte, #PTE_ADDR_MASK
622 .macro pte_to_phys, phys, pte
623 #ifdef CONFIG_ARM64_PA_BITS_52
624 ubfiz \phys, \pte, #(48 - 16 - 12), #16
625 bfxil \phys, \pte, #16, #32
626 lsl \phys, \phys, #16
628 and \phys, \pte, #PTE_ADDR_MASK
633 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
635 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
636 #ifdef CONFIG_FUJITSU_ERRATUM_010001
639 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
640 and \tmp1, \tmp1, \tmp2
641 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
645 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
646 bic \tcr, \tcr, \tmp2
648 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */
652 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
653 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
655 .macro pre_disable_mmu_workaround
656 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
662 * frame_push - Push @regcount callee saved registers to the stack,
663 * starting at x19, as well as x29/x30, and set x29 to
664 * the new value of sp. Add @extra bytes of stack space
667 .macro frame_push, regcount:req, extra
668 __frame st, \regcount, \extra
672 * frame_pop - Pop the callee saved registers from the stack that were
673 * pushed in the most recent call to frame_push, as well
674 * as x29/x30 and any extra stack space that may have been
681 .macro __frame_regs, reg1, reg2, op, num
682 .if .Lframe_regcount == \num
683 \op\()r \reg1, [sp, #(\num + 1) * 8]
684 .elseif .Lframe_regcount > \num
685 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
689 .macro __frame, op, regcount, extra=0
691 .if (\regcount) < 0 || (\regcount) > 10
692 .error "regcount should be in the range [0 ... 10]"
694 .if ((\extra) % 16) != 0
695 .error "extra should be a multiple of 16 bytes"
697 .ifdef .Lframe_regcount
698 .if .Lframe_regcount != -1
699 .error "frame_push/frame_pop may not be nested"
702 .set .Lframe_regcount, \regcount
703 .set .Lframe_extra, \extra
704 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
705 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
709 __frame_regs x19, x20, \op, 1
710 __frame_regs x21, x22, \op, 3
711 __frame_regs x23, x24, \op, 5
712 __frame_regs x25, x26, \op, 7
713 __frame_regs x27, x28, \op, 9
716 .if .Lframe_regcount == -1
717 .error "frame_push/frame_pop may not be nested"
719 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
720 .set .Lframe_regcount, -1
725 * Set SCTLR_ELx to the @reg value, and invalidate the local icache
726 * in the process. This is called when setting the MMU on.
728 .macro set_sctlr, sreg, reg
732 * Invalidate the local I-cache so that any instructions fetched
733 * speculatively from the PoC are discarded, since they may have
734 * been dynamically patched at the PoU.
741 .macro set_sctlr_el1, reg
742 set_sctlr sctlr_el1, \reg
745 .macro set_sctlr_el2, reg
746 set_sctlr sctlr_el2, \reg
750 * Check whether preempt/bh-disabled asm code should yield as soon as
751 * it is able. This is the case if we are currently running in task
752 * context, and either a softirq is pending, or the TIF_NEED_RESCHED
753 * flag is set and re-enabling preemption a single time would result in
754 * a preempt count of zero. (Note that the TIF_NEED_RESCHED flag is
755 * stored negated in the top word of the thread_info::preempt_count
758 .macro cond_yield, lbl:req, tmp:req, tmp2:req
759 get_current_task \tmp
760 ldr \tmp, [\tmp, #TSK_TI_PREEMPT]
762 * If we are serving a softirq, there is no point in yielding: the
763 * softirq will not be preempted no matter what we do, so we should
764 * run to completion as quickly as we can.
766 tbnz \tmp, #SOFTIRQ_SHIFT, .Lnoyield_\@
767 #ifdef CONFIG_PREEMPTION
768 sub \tmp, \tmp, #PREEMPT_DISABLE_OFFSET
771 adr_l \tmp, irq_stat + IRQ_CPUSTAT_SOFTIRQ_PENDING
772 get_this_cpu_offset \tmp2
773 ldr w\tmp, [\tmp, \tmp2]
774 cbnz w\tmp, \lbl // yield on pending softirq in task context
779 * This macro emits a program property note section identifying
780 * architecture features which require special handling, mainly for
781 * use in assembly files included in the VDSO.
784 #define NT_GNU_PROPERTY_TYPE_0 5
785 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
787 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
788 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
790 #ifdef CONFIG_ARM64_BTI_KERNEL
791 #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \
792 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \
793 GNU_PROPERTY_AARCH64_FEATURE_1_PAC))
796 #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
797 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
798 .pushsection .note.gnu.property, "a"
802 .long NT_GNU_PROPERTY_TYPE_0
806 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND
810 * This is described with an array of char in the Linux API
811 * spec but the text and all other usage (including binutils,
812 * clang and GCC) treat this as a 32 bit value so no swizzling
813 * is required for big endian.
823 .macro emit_aarch64_feature_1_and, feat=0
826 #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */
828 #endif /* __ASM_ASSEMBLER_H */