1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
9 #error "Only include this from assembly code"
12 #ifndef __ASM_ASSEMBLER_H
13 #define __ASM_ASSEMBLER_H
15 #include <asm-generic/export.h>
17 #include <asm/alternative.h>
18 #include <asm/asm-bug.h>
19 #include <asm/asm-extable.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/cpufeature.h>
22 #include <asm/cputype.h>
23 #include <asm/debug-monitors.h>
25 #include <asm/pgtable-hwdef.h>
26 #include <asm/ptrace.h>
27 #include <asm/thread_info.h>
30 * Provide a wxN alias for each wN register so what we can paste a xN
31 * reference after a 'w' to obtain the 32-bit version.
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
37 .macro save_and_disable_daif, flags
50 .macro restore_daif, flags:req
54 /* IRQ/FIQ are the lowest priority flags, unconditionally unmask the rest. */
60 * Save/restore interrupts.
62 .macro save_and_disable_irq, flags
67 .macro restore_irq, flags
75 .macro disable_step_tsk, flgs, tmp
76 tbz \flgs, #TIF_SINGLESTEP, 9990f
78 bic \tmp, \tmp, #DBG_MDSCR_SS
80 isb // Synchronise with enable_dbg
84 /* call with daif masked */
85 .macro enable_step_tsk, flgs, tmp
86 tbz \flgs, #TIF_SINGLESTEP, 9990f
88 orr \tmp, \tmp, #DBG_MDSCR_SS
94 * RAS Error Synchronization barrier
97 #ifdef CONFIG_ARM64_RAS_EXTN
105 * Value prediction barrier
112 * Clear Branch History instruction
119 * Speculation barrier
122 alternative_if_not ARM64_HAS_SB
143 lr .req x30 // link register
154 * Select code when configured for BE.
156 #ifdef CONFIG_CPU_BIG_ENDIAN
157 #define CPU_BE(code...) code
159 #define CPU_BE(code...)
163 * Select code when configured for LE.
165 #ifdef CONFIG_CPU_BIG_ENDIAN
166 #define CPU_LE(code...)
168 #define CPU_LE(code...) code
172 * Define a macro that constructs a 64-bit value by concatenating two
173 * 32-bit registers. Note that on big endian systems the order of the
174 * registers is swapped.
176 #ifndef CONFIG_CPU_BIG_ENDIAN
177 .macro regs_to_64, rd, lbits, hbits
179 .macro regs_to_64, rd, hbits, lbits
181 orr \rd, \lbits, \hbits, lsl #32
185 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
186 * <symbol> is within the range +/- 4 GB of the PC.
189 * @dst: destination register (64 bit wide)
190 * @sym: name of the symbol
192 .macro adr_l, dst, sym
194 add \dst, \dst, :lo12:\sym
198 * @dst: destination register (32 or 64 bit wide)
199 * @sym: name of the symbol
200 * @tmp: optional 64-bit scratch register to be used if <dst> is a
201 * 32-bit wide register, in which case it cannot be used to hold
204 .macro ldr_l, dst, sym, tmp=
207 ldr \dst, [\dst, :lo12:\sym]
210 ldr \dst, [\tmp, :lo12:\sym]
215 * @src: source register (32 or 64 bit wide)
216 * @sym: name of the symbol
217 * @tmp: mandatory 64-bit scratch register to calculate the address
218 * while <src> needs to be preserved.
220 .macro str_l, src, sym, tmp
222 str \src, [\tmp, :lo12:\sym]
226 * @dst: destination register
228 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
229 .macro get_this_cpu_offset, dst
233 .macro get_this_cpu_offset, dst
234 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
241 .macro set_this_cpu_offset, src
242 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
251 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
252 * @sym: The name of the per-cpu variable
253 * @tmp: scratch register
255 .macro adr_this_cpu, dst, sym, tmp
257 add \dst, \tmp, #:lo12:\sym
258 get_this_cpu_offset \tmp
263 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
264 * @sym: The name of the per-cpu variable
265 * @tmp: scratch register
267 .macro ldr_this_cpu dst, sym, tmp
269 get_this_cpu_offset \tmp
270 ldr \dst, [\dst, \tmp]
274 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
276 .macro vma_vm_mm, rd, rn
277 ldr \rd, [\rn, #VMA_VM_MM]
281 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
282 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
285 #ifndef __KVM_NVHE_HYPERVISOR__
286 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
287 mrs \reg, ctr_el0 // read CTR
290 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
293 alternative_if_not ARM64_KVM_PROTECTED_MODE
295 alternative_else_nop_endif
296 alternative_cb kvm_compute_final_ctr_el0
298 movk \reg, #0, lsl #16
299 movk \reg, #0, lsl #32
300 movk \reg, #0, lsl #48
307 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
308 * from the CTR register.
310 .macro raw_dcache_line_size, reg, tmp
311 mrs \tmp, ctr_el0 // read CTR
312 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
313 mov \reg, #4 // bytes per word
314 lsl \reg, \reg, \tmp // actual cache line size
318 * dcache_line_size - get the safe D-cache line size across all CPUs
320 .macro dcache_line_size, reg, tmp
322 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
323 mov \reg, #4 // bytes per word
324 lsl \reg, \reg, \tmp // actual cache line size
328 * raw_icache_line_size - get the minimum I-cache line size on this CPU
329 * from the CTR register.
331 .macro raw_icache_line_size, reg, tmp
332 mrs \tmp, ctr_el0 // read CTR
333 and \tmp, \tmp, #0xf // cache line size encoding
334 mov \reg, #4 // bytes per word
335 lsl \reg, \reg, \tmp // actual cache line size
339 * icache_line_size - get the safe I-cache line size across all CPUs
341 .macro icache_line_size, reg, tmp
343 and \tmp, \tmp, #0xf // cache line size encoding
344 mov \reg, #4 // bytes per word
345 lsl \reg, \reg, \tmp // actual cache line size
349 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
351 .macro tcr_set_t0sz, valreg, t0sz
352 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
356 * tcr_set_t1sz - update TCR.T1SZ
358 .macro tcr_set_t1sz, valreg, t1sz
359 bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH
363 * idmap_get_t0sz - get the T0SZ value needed to cover the ID map
365 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
366 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
367 * this number conveniently equals the number of leading zeroes in
368 * the physical address of _end.
370 .macro idmap_get_t0sz, reg
372 orr \reg, \reg, #(1 << VA_BITS_MIN) - 1
377 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
378 * ID_AA64MMFR0_EL1.PARange value
380 * tcr: register with the TCR_ELx value to be updated
381 * pos: IPS or PS bitfield position
382 * tmp{0,1}: temporary registers
384 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
385 mrs \tmp0, ID_AA64MMFR0_EL1
386 // Narrow PARange to fit the PS field in TCR_ELx
387 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
388 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
390 csel \tmp0, \tmp1, \tmp0, hi
391 bfi \tcr, \tmp0, \pos, #3
394 .macro __dcache_op_workaround_clean_cache, op, addr
395 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
403 * Macro to perform a data cache maintenance for the interval
404 * [start, end) with dcache line size explicitly provided.
406 * op: operation passed to dc instruction
407 * domain: domain used in dsb instruciton
408 * start: starting virtual address of the region
409 * end: end virtual address of the region
410 * linesz: dcache line size
411 * fixup: optional label to branch to on user fault
412 * Corrupts: start, end, tmp
414 .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
415 sub \tmp, \linesz, #1
416 bic \start, \start, \tmp
419 __dcache_op_workaround_clean_cache \op, \start
422 __dcache_op_workaround_clean_cache \op, \start
425 sys 3, c7, c12, 1, \start // dc cvap
428 sys 3, c7, c13, 1, \start // dc cvadp
435 add \start, \start, \linesz
440 _cond_extable .Ldcache_op\@, \fixup
444 * Macro to perform a data cache maintenance for the interval
447 * op: operation passed to dc instruction
448 * domain: domain used in dsb instruciton
449 * start: starting virtual address of the region
450 * end: end virtual address of the region
451 * fixup: optional label to branch to on user fault
452 * Corrupts: start, end, tmp1, tmp2
454 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
455 dcache_line_size \tmp1, \tmp2
456 dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
460 * Macro to perform an instruction cache maintenance for the interval
463 * start, end: virtual addresses describing the region
464 * fixup: optional label to branch to on user fault
465 * Corrupts: tmp1, tmp2
467 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
468 icache_line_size \tmp1, \tmp2
470 bic \tmp2, \start, \tmp2
472 ic ivau, \tmp2 // invalidate I line PoU
473 add \tmp2, \tmp2, \tmp1
479 _cond_extable .Licache_op\@, \fixup
483 * load_ttbr1 - install @pgtbl as a TTBR1 page table
485 * tmp1/tmp2 clobbered, either may overlap with pgtbl
487 .macro load_ttbr1, pgtbl, tmp1, tmp2
488 phys_to_ttbr \tmp1, \pgtbl
489 offset_ttbr1 \tmp1, \tmp2
495 * To prevent the possibility of old and new partial table walks being visible
496 * in the tlb, switch the ttbr to a zero page when we invalidate the old
497 * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
498 * Even switching to our copied tables will cause a changed output address at
499 * each stage of the walk.
501 .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
502 phys_to_ttbr \tmp, \zero_page
507 load_ttbr1 \page_table, \tmp, \tmp2
511 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
513 .macro reset_pmuserenr_el0, tmpreg
514 mrs \tmpreg, id_aa64dfr0_el1
515 sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
516 cmp \tmpreg, #1 // Skip if no PMU present
518 msr pmuserenr_el0, xzr // Disable PMU access from EL0
523 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present
525 .macro reset_amuserenr_el0, tmpreg
526 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1
527 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4
528 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present
529 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0
533 * copy_page - copy src to dest using temp registers t1-t8
535 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
536 9998: ldp \t1, \t2, [\src]
537 ldp \t3, \t4, [\src, #16]
538 ldp \t5, \t6, [\src, #32]
539 ldp \t7, \t8, [\src, #48]
541 stnp \t1, \t2, [\dest]
542 stnp \t3, \t4, [\dest, #16]
543 stnp \t5, \t6, [\dest, #32]
544 stnp \t7, \t8, [\dest, #48]
545 add \dest, \dest, #64
546 tst \src, #(PAGE_SIZE - 1)
551 * Annotate a function as being unsuitable for kprobes.
553 #ifdef CONFIG_KPROBES
554 #define NOKPROBE(x) \
555 .pushsection "_kprobe_blacklist", "aw"; \
562 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
563 #define EXPORT_SYMBOL_NOKASAN(name)
565 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
569 * Emit a 64-bit absolute little endian symbol reference in a way that
570 * ensures that it will be resolved at build time, even when building a
571 * PIE binary. This requires cooperation from the linker script, which
572 * must emit the lo32/hi32 halves individually.
580 * mov_q - move an immediate constant into a 64-bit register using
581 * between 2 and 4 movz/movk instructions (depending on the
582 * magnitude and sign of the operand)
584 .macro mov_q, reg, val
585 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
586 movz \reg, :abs_g1_s:\val
588 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
589 movz \reg, :abs_g2_s:\val
591 movz \reg, :abs_g3:\val
592 movk \reg, :abs_g2_nc:\val
594 movk \reg, :abs_g1_nc:\val
596 movk \reg, :abs_g0_nc:\val
600 * Return the current task_struct.
602 .macro get_current_task, rd
607 * Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD.
608 * orr is used as it can cover the immediate value (and is idempotent).
609 * In future this may be nop'ed out when dealing with 52-bit kernel VAs.
610 * ttbr: Value of ttbr to set, modified.
612 .macro offset_ttbr1, ttbr, tmp
613 #ifdef CONFIG_ARM64_VA_BITS_52
614 mrs_s \tmp, SYS_ID_AA64MMFR2_EL1
615 and \tmp, \tmp, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
616 cbnz \tmp, .Lskipoffs_\@
617 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
623 * Perform the reverse of offset_ttbr1.
624 * bic is used as it can cover the immediate value and, in future, won't need
625 * to be nop'ed out when dealing with 52-bit kernel VAs.
627 .macro restore_ttbr1, ttbr
628 #ifdef CONFIG_ARM64_VA_BITS_52
629 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
634 * Arrange a physical address in a TTBR register, taking care of 52-bit
637 * phys: physical address, preserved
638 * ttbr: returns the TTBR value
640 .macro phys_to_ttbr, ttbr, phys
641 #ifdef CONFIG_ARM64_PA_BITS_52
642 orr \ttbr, \phys, \phys, lsr #46
643 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
649 .macro phys_to_pte, pte, phys
650 #ifdef CONFIG_ARM64_PA_BITS_52
652 * We assume \phys is 64K aligned and this is guaranteed by only
653 * supporting this configuration with 64K pages.
655 orr \pte, \phys, \phys, lsr #36
656 and \pte, \pte, #PTE_ADDR_MASK
662 .macro pte_to_phys, phys, pte
663 #ifdef CONFIG_ARM64_PA_BITS_52
664 ubfiz \phys, \pte, #(48 - 16 - 12), #16
665 bfxil \phys, \pte, #16, #32
666 lsl \phys, \phys, #16
668 and \phys, \pte, #PTE_ADDR_MASK
673 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
675 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
676 #ifdef CONFIG_FUJITSU_ERRATUM_010001
679 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
680 and \tmp1, \tmp1, \tmp2
681 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
685 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
686 bic \tcr, \tcr, \tmp2
688 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */
692 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
693 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
695 .macro pre_disable_mmu_workaround
696 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
702 * frame_push - Push @regcount callee saved registers to the stack,
703 * starting at x19, as well as x29/x30, and set x29 to
704 * the new value of sp. Add @extra bytes of stack space
707 .macro frame_push, regcount:req, extra
708 __frame st, \regcount, \extra
712 * frame_pop - Pop the callee saved registers from the stack that were
713 * pushed in the most recent call to frame_push, as well
714 * as x29/x30 and any extra stack space that may have been
721 .macro __frame_regs, reg1, reg2, op, num
722 .if .Lframe_regcount == \num
723 \op\()r \reg1, [sp, #(\num + 1) * 8]
724 .elseif .Lframe_regcount > \num
725 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
729 .macro __frame, op, regcount, extra=0
731 .if (\regcount) < 0 || (\regcount) > 10
732 .error "regcount should be in the range [0 ... 10]"
734 .if ((\extra) % 16) != 0
735 .error "extra should be a multiple of 16 bytes"
737 .ifdef .Lframe_regcount
738 .if .Lframe_regcount != -1
739 .error "frame_push/frame_pop may not be nested"
742 .set .Lframe_regcount, \regcount
743 .set .Lframe_extra, \extra
744 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
745 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
749 __frame_regs x19, x20, \op, 1
750 __frame_regs x21, x22, \op, 3
751 __frame_regs x23, x24, \op, 5
752 __frame_regs x25, x26, \op, 7
753 __frame_regs x27, x28, \op, 9
756 .if .Lframe_regcount == -1
757 .error "frame_push/frame_pop may not be nested"
759 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
760 .set .Lframe_regcount, -1
765 * Set SCTLR_ELx to the @reg value, and invalidate the local icache
766 * in the process. This is called when setting the MMU on.
768 .macro set_sctlr, sreg, reg
772 * Invalidate the local I-cache so that any instructions fetched
773 * speculatively from the PoC are discarded, since they may have
774 * been dynamically patched at the PoU.
781 .macro set_sctlr_el1, reg
782 set_sctlr sctlr_el1, \reg
785 .macro set_sctlr_el2, reg
786 set_sctlr sctlr_el2, \reg
790 * Check whether preempt/bh-disabled asm code should yield as soon as
791 * it is able. This is the case if we are currently running in task
792 * context, and either a softirq is pending, or the TIF_NEED_RESCHED
793 * flag is set and re-enabling preemption a single time would result in
794 * a preempt count of zero. (Note that the TIF_NEED_RESCHED flag is
795 * stored negated in the top word of the thread_info::preempt_count
798 .macro cond_yield, lbl:req, tmp:req, tmp2:req
799 get_current_task \tmp
800 ldr \tmp, [\tmp, #TSK_TI_PREEMPT]
802 * If we are serving a softirq, there is no point in yielding: the
803 * softirq will not be preempted no matter what we do, so we should
804 * run to completion as quickly as we can.
806 tbnz \tmp, #SOFTIRQ_SHIFT, .Lnoyield_\@
807 #ifdef CONFIG_PREEMPTION
808 sub \tmp, \tmp, #PREEMPT_DISABLE_OFFSET
811 adr_l \tmp, irq_stat + IRQ_CPUSTAT_SOFTIRQ_PENDING
812 get_this_cpu_offset \tmp2
813 ldr w\tmp, [\tmp, \tmp2]
814 cbnz w\tmp, \lbl // yield on pending softirq in task context
819 * Branch Target Identifier (BTI)
822 .equ .L__bti_targets_c, 34
823 .equ .L__bti_targets_j, 36
824 .equ .L__bti_targets_jc,38
825 hint #.L__bti_targets_\targets
829 * This macro emits a program property note section identifying
830 * architecture features which require special handling, mainly for
831 * use in assembly files included in the VDSO.
834 #define NT_GNU_PROPERTY_TYPE_0 5
835 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
837 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
838 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
840 #ifdef CONFIG_ARM64_BTI_KERNEL
841 #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \
842 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \
843 GNU_PROPERTY_AARCH64_FEATURE_1_PAC))
846 #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
847 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
848 .pushsection .note.gnu.property, "a"
852 .long NT_GNU_PROPERTY_TYPE_0
856 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND
860 * This is described with an array of char in the Linux API
861 * spec but the text and all other usage (including binutils,
862 * clang and GCC) treat this as a 32 bit value so no swizzling
863 * is required for big endian.
873 .macro emit_aarch64_feature_1_and, feat=0
876 #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */
878 .macro __mitigate_spectre_bhb_loop tmp
879 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
880 alternative_cb spectre_bhb_patch_loop_iter
881 mov \tmp, #32 // Patched to correct the immediate
883 .Lspectre_bhb_loop\@:
886 b.ne .Lspectre_bhb_loop\@
888 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
891 .macro mitigate_spectre_bhb_loop tmp
892 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
893 alternative_cb spectre_bhb_patch_loop_mitigation_enable
894 b .L_spectre_bhb_loop_done\@ // Patched to NOP
896 __mitigate_spectre_bhb_loop \tmp
897 .L_spectre_bhb_loop_done\@:
898 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
901 /* Save/restores x0-x3 to the stack */
902 .macro __mitigate_spectre_bhb_fw
903 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
904 stp x0, x1, [sp, #-16]!
905 stp x2, x3, [sp, #-16]!
906 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3
907 alternative_cb smccc_patch_fw_mitigation_conduit
908 nop // Patched to SMC/HVC #0
910 ldp x2, x3, [sp], #16
911 ldp x0, x1, [sp], #16
912 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
915 .macro mitigate_spectre_bhb_clear_insn
916 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
917 alternative_cb spectre_bhb_patch_clearbhb
918 /* Patched to NOP when not supported */
922 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
924 #endif /* __ASM_ASSEMBLER_H */