arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Device Tree Source for J7200 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 / {
   9         serdes_refclk: serdes-refclk {
  10                 #clock-cells = <0>;
  11                 compatible = "fixed-clock";
  12         };
  13 };
  14
  15 &cbass_main {
  16         msmc_ram: sram@70000000 {
  17                 compatible = "mmio-sram";
  18                 reg = <0x00 0x70000000 0x00 0x100000>;
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x00 0x00 0x70000000 0x100000>;
  22
  23                 atf-sram@0 {
  24                         reg = <0x00 0x20000>;
  25                 };
  26         };
  27
  28         scm_conf: scm-conf@100000 {
  29                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  30                 reg = <0x00 0x00100000 0x00 0x1c000>;
  31                 #address-cells = <1>;
  32                 #size-cells = <1>;
  33                 ranges = <0x00 0x00 0x00100000 0x1c000>;
  34
  35                 serdes_ln_ctrl: mux-controller@4080 {
  36                         compatible = "reg-mux";
  37                         reg = <0x4080 0x20>;
  38                         #mux-control-cells = <1>;
  39                         mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
  40                                         <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
  41                 };
  42
  43                 cpsw0_phy_gmii_sel: phy@4044 {
  44                         compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
  45                         ti,qsgmii-main-ports = <1>;
  46                         reg = <0x4044 0x10>;
  47                         #phy-cells = <1>;
  48                 };
  49
  50                 usb_serdes_mux: mux-controller@4000 {
  51                         compatible = "reg-mux";
  52                         reg = <0x4000 0x4>;
  53                         #mux-control-cells = <1>;
  54                         mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
  55                 };
  56         };
  57
  58         gic500: interrupt-controller@1800000 {
  59                 compatible = "arm,gic-v3";
  60                 #address-cells = <2>;
  61                 #size-cells = <2>;
  62                 ranges;
  63                 #interrupt-cells = <3>;
  64                 interrupt-controller;
  65                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  66                       <0x00 0x01900000 0x00 0x100000>,  /* GICR */
  67                       <0x00 0x6f000000 0x00 0x2000>,    /* GICC */
  68                       <0x00 0x6f010000 0x00 0x1000>,    /* GICH */
  69                       <0x00 0x6f020000 0x00 0x2000>;    /* GICV */
  70
  71                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  72                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  73
  74                 gic_its: msi-controller@1820000 {
  75                         compatible = "arm,gic-v3-its";
  76                         reg = <0x00 0x01820000 0x00 0x10000>;
  77                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  78                         msi-controller;
  79                         #msi-cells = <1>;
  80                 };
  81         };
  82
  83         main_gpio_intr: interrupt-controller@a00000 {
  84                 compatible = "ti,sci-intr";
  85                 reg = <0x00 0x00a00000 0x00 0x800>;
  86                 ti,intr-trigger-type = <1>;
  87                 interrupt-controller;
  88                 interrupt-parent = <&gic500>;
  89                 #interrupt-cells = <1>;
  90                 ti,sci = <&dmsc>;
  91                 ti,sci-dev-id = <131>;
  92                 ti,interrupt-ranges = <8 392 56>;
  93         };
  94
  95         main_navss: bus@30000000 {
  96                 compatible = "simple-bus";
  97                 #address-cells = <2>;
  98                 #size-cells = <2>;
  99                 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 100                 ti,sci-dev-id = <199>;
 101                 dma-coherent;
 102                 dma-ranges;
 103
 104                 main_navss_intr: interrupt-controller@310e0000 {
 105                         compatible = "ti,sci-intr";
 106                         reg = <0x00 0x310e0000 0x00 0x4000>;
 107                         ti,intr-trigger-type = <4>;
 108                         interrupt-controller;
 109                         interrupt-parent = <&gic500>;
 110                         #interrupt-cells = <1>;
 111                         ti,sci = <&dmsc>;
 112                         ti,sci-dev-id = <213>;
 113                         ti,interrupt-ranges = <0 64 64>,
 114                                               <64 448 64>,
 115                                               <128 672 64>;
 116                 };
 117
 118                 main_udmass_inta: msi-controller@33d00000 {
 119                         compatible = "ti,sci-inta";
 120                         reg = <0x00 0x33d00000 0x00 0x100000>;
 121                         interrupt-controller;
 122                         #interrupt-cells = <0>;
 123                         interrupt-parent = <&main_navss_intr>;
 124                         msi-controller;
 125                         ti,sci = <&dmsc>;
 126                         ti,sci-dev-id = <209>;
 127                         ti,interrupt-ranges = <0 0 256>;
 128                 };
 129
 130                 secure_proxy_main: mailbox@32c00000 {
 131                         compatible = "ti,am654-secure-proxy";
 132                         #mbox-cells = <1>;
 133                         reg-names = "target_data", "rt", "scfg";
 134                         reg = <0x00 0x32c00000 0x00 0x100000>,
 135                               <0x00 0x32400000 0x00 0x100000>,
 136                               <0x00 0x32800000 0x00 0x100000>;
 137                         interrupt-names = "rx_011";
 138                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 139                 };
 140
 141                 hwspinlock: spinlock@30e00000 {
 142                         compatible = "ti,am654-hwspinlock";
 143                         reg = <0x00 0x30e00000 0x00 0x1000>;
 144                         #hwlock-cells = <1>;
 145                 };
 146
 147                 mailbox0_cluster0: mailbox@31f80000 {
 148                         compatible = "ti,am654-mailbox";
 149                         reg = <0x00 0x31f80000 0x00 0x200>;
 150                         #mbox-cells = <1>;
 151                         ti,mbox-num-users = <4>;
 152                         ti,mbox-num-fifos = <16>;
 153                         interrupt-parent = <&main_navss_intr>;
 154                         status = "disabled";
 155                 };
 156
 157                 mailbox0_cluster1: mailbox@31f81000 {
 158                         compatible = "ti,am654-mailbox";
 159                         reg = <0x00 0x31f81000 0x00 0x200>;
 160                         #mbox-cells = <1>;
 161                         ti,mbox-num-users = <4>;
 162                         ti,mbox-num-fifos = <16>;
 163                         interrupt-parent = <&main_navss_intr>;
 164                         status = "disabled";
 165                 };
 166
 167                 mailbox0_cluster2: mailbox@31f82000 {
 168                         compatible = "ti,am654-mailbox";
 169                         reg = <0x00 0x31f82000 0x00 0x200>;
 170                         #mbox-cells = <1>;
 171                         ti,mbox-num-users = <4>;
 172                         ti,mbox-num-fifos = <16>;
 173                         interrupt-parent = <&main_navss_intr>;
 174                         status = "disabled";
 175                 };
 176
 177                 mailbox0_cluster3: mailbox@31f83000 {
 178                         compatible = "ti,am654-mailbox";
 179                         reg = <0x00 0x31f83000 0x00 0x200>;
 180                         #mbox-cells = <1>;
 181                         ti,mbox-num-users = <4>;
 182                         ti,mbox-num-fifos = <16>;
 183                         interrupt-parent = <&main_navss_intr>;
 184                         status = "disabled";
 185                 };
 186
 187                 mailbox0_cluster4: mailbox@31f84000 {
 188                         compatible = "ti,am654-mailbox";
 189                         reg = <0x00 0x31f84000 0x00 0x200>;
 190                         #mbox-cells = <1>;
 191                         ti,mbox-num-users = <4>;
 192                         ti,mbox-num-fifos = <16>;
 193                         interrupt-parent = <&main_navss_intr>;
 194                         status = "disabled";
 195                 };
 196
 197                 mailbox0_cluster5: mailbox@31f85000 {
 198                         compatible = "ti,am654-mailbox";
 199                         reg = <0x00 0x31f85000 0x00 0x200>;
 200                         #mbox-cells = <1>;
 201                         ti,mbox-num-users = <4>;
 202                         ti,mbox-num-fifos = <16>;
 203                         interrupt-parent = <&main_navss_intr>;
 204                         status = "disabled";
 205                 };
 206
 207                 mailbox0_cluster6: mailbox@31f86000 {
 208                         compatible = "ti,am654-mailbox";
 209                         reg = <0x00 0x31f86000 0x00 0x200>;
 210                         #mbox-cells = <1>;
 211                         ti,mbox-num-users = <4>;
 212                         ti,mbox-num-fifos = <16>;
 213                         interrupt-parent = <&main_navss_intr>;
 214                         status = "disabled";
 215                 };
 216
 217                 mailbox0_cluster7: mailbox@31f87000 {
 218                         compatible = "ti,am654-mailbox";
 219                         reg = <0x00 0x31f87000 0x00 0x200>;
 220                         #mbox-cells = <1>;
 221                         ti,mbox-num-users = <4>;
 222                         ti,mbox-num-fifos = <16>;
 223                         interrupt-parent = <&main_navss_intr>;
 224                         status = "disabled";
 225                 };
 226
 227                 mailbox0_cluster8: mailbox@31f88000 {
 228                         compatible = "ti,am654-mailbox";
 229                         reg = <0x00 0x31f88000 0x00 0x200>;
 230                         #mbox-cells = <1>;
 231                         ti,mbox-num-users = <4>;
 232                         ti,mbox-num-fifos = <16>;
 233                         interrupt-parent = <&main_navss_intr>;
 234                         status = "disabled";
 235                 };
 236
 237                 mailbox0_cluster9: mailbox@31f89000 {
 238                         compatible = "ti,am654-mailbox";
 239                         reg = <0x00 0x31f89000 0x00 0x200>;
 240                         #mbox-cells = <1>;
 241                         ti,mbox-num-users = <4>;
 242                         ti,mbox-num-fifos = <16>;
 243                         interrupt-parent = <&main_navss_intr>;
 244                         status = "disabled";
 245                 };
 246
 247                 mailbox0_cluster10: mailbox@31f8a000 {
 248                         compatible = "ti,am654-mailbox";
 249                         reg = <0x00 0x31f8a000 0x00 0x200>;
 250                         #mbox-cells = <1>;
 251                         ti,mbox-num-users = <4>;
 252                         ti,mbox-num-fifos = <16>;
 253                         interrupt-parent = <&main_navss_intr>;
 254                         status = "disabled";
 255                 };
 256
 257                 mailbox0_cluster11: mailbox@31f8b000 {
 258                         compatible = "ti,am654-mailbox";
 259                         reg = <0x00 0x31f8b000 0x00 0x200>;
 260                         #mbox-cells = <1>;
 261                         ti,mbox-num-users = <4>;
 262                         ti,mbox-num-fifos = <16>;
 263                         interrupt-parent = <&main_navss_intr>;
 264                         status = "disabled";
 265                 };
 266
 267                 main_ringacc: ringacc@3c000000 {
 268                         compatible = "ti,am654-navss-ringacc";
 269                         reg = <0x00 0x3c000000 0x00 0x400000>,
 270                               <0x00 0x38000000 0x00 0x400000>,
 271                               <0x00 0x31120000 0x00 0x100>,
 272                               <0x00 0x33000000 0x00 0x40000>,
 273                               <0x00 0x31080000 0x00 0x40000>;
 274                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
 275                         ti,num-rings = <1024>;
 276                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 277                         ti,sci = <&dmsc>;
 278                         ti,sci-dev-id = <211>;
 279                         msi-parent = <&main_udmass_inta>;
 280                 };
 281
 282                 main_udmap: dma-controller@31150000 {
 283                         compatible = "ti,j721e-navss-main-udmap";
 284                         reg = <0x00 0x31150000 0x00 0x100>,
 285                               <0x00 0x34000000 0x00 0x100000>,
 286                               <0x00 0x35000000 0x00 0x100000>,
 287                               <0x00 0x30b00000 0x00 0x4000>,
 288                               <0x00 0x30c00000 0x00 0x4000>,
 289                               <0x00 0x30d00000 0x00 0x4000>;
 290                         reg-names = "gcfg", "rchanrt", "tchanrt",
 291                                     "tchan", "rchan", "rflow";
 292                         msi-parent = <&main_udmass_inta>;
 293                         #dma-cells = <1>;
 294
 295                         ti,sci = <&dmsc>;
 296                         ti,sci-dev-id = <212>;
 297                         ti,ringacc = <&main_ringacc>;
 298
 299                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 300                                                 <0x0f>, /* TX_HCHAN */
 301                                                 <0x10>; /* TX_UHCHAN */
 302                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 303                                                 <0x0b>, /* RX_HCHAN */
 304                                                 <0x0c>; /* RX_UHCHAN */
 305                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 306                 };
 307
 308                 cpts@310d0000 {
 309                         compatible = "ti,j721e-cpts";
 310                         reg = <0x00 0x310d0000 0x00 0x400>;
 311                         reg-names = "cpts";
 312                         clocks = <&k3_clks 201 1>;
 313                         clock-names = "cpts";
 314                         interrupts-extended = <&main_navss_intr 391>;
 315                         interrupt-names = "cpts";
 316                         ti,cpts-periodic-outputs = <6>;
 317                         ti,cpts-ext-ts-inputs = <8>;
 318                 };
 319         };
 320
 321         cpsw0: ethernet@c000000 {
 322                 compatible = "ti,j7200-cpswxg-nuss";
 323                 #address-cells = <2>;
 324                 #size-cells = <2>;
 325                 reg = <0x00 0xc000000 0x00 0x200000>;
 326                 reg-names = "cpsw_nuss";
 327                 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
 328                 clocks = <&k3_clks 19 33>;
 329                 clock-names = "fck";
 330                 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
 331
 332                 dmas = <&main_udmap 0xca00>,
 333                        <&main_udmap 0xca01>,
 334                        <&main_udmap 0xca02>,
 335                        <&main_udmap 0xca03>,
 336                        <&main_udmap 0xca04>,
 337                        <&main_udmap 0xca05>,
 338                        <&main_udmap 0xca06>,
 339                        <&main_udmap 0xca07>,
 340                        <&main_udmap 0x4a00>;
 341                 dma-names = "tx0", "tx1", "tx2", "tx3",
 342                             "tx4", "tx5", "tx6", "tx7",
 343                             "rx";
 344
 345                 status = "disabled";
 346
 347                 ethernet-ports {
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         cpsw0_port1: port@1 {
 351                                 reg = <1>;
 352                                 ti,mac-only;
 353                                 label = "port1";
 354                                 status = "disabled";
 355                         };
 356
 357                         cpsw0_port2: port@2 {
 358                                 reg = <2>;
 359                                 ti,mac-only;
 360                                 label = "port2";
 361                                 status = "disabled";
 362                         };
 363
 364                         cpsw0_port3: port@3 {
 365                                 reg = <3>;
 366                                 ti,mac-only;
 367                                 label = "port3";
 368                                 status = "disabled";
 369                         };
 370
 371                         cpsw0_port4: port@4 {
 372                                 reg = <4>;
 373                                 ti,mac-only;
 374                                 label = "port4";
 375                                 status = "disabled";
 376                         };
 377                 };
 378
 379                 cpsw5g_mdio: mdio@f00 {
 380                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 381                         reg = <0x00 0xf00 0x00 0x100>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         clocks = <&k3_clks 19 33>;
 385                         clock-names = "fck";
 386                         bus_freq = <1000000>;
 387                         status = "disabled";
 388                 };
 389
 390                 cpts@3d000 {
 391                         compatible = "ti,j721e-cpts";
 392                         reg = <0x00 0x3d000 0x00 0x400>;
 393                         clocks = <&k3_clks 19 16>;
 394                         clock-names = "cpts";
 395                         interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 396                         interrupt-names = "cpts";
 397                         ti,cpts-ext-ts-inputs = <4>;
 398                         ti,cpts-periodic-outputs = <2>;
 399                 };
 400         };
 401
 402         /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
 403         main_timerio_input: pinctrl@104200 {
 404                 compatible = "ti,j7200-padconf", "pinctrl-single";
 405                 reg = <0x0 0x104200 0x0 0x50>;
 406                 #pinctrl-cells = <1>;
 407                 pinctrl-single,register-width = <32>;
 408                 pinctrl-single,function-mask = <0x000001ff>;
 409         };
 410
 411         /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
 412         main_timerio_output: pinctrl@104280 {
 413                 compatible = "ti,j7200-padconf", "pinctrl-single";
 414                 reg = <0x0 0x104280 0x0 0x20>;
 415                 #pinctrl-cells = <1>;
 416                 pinctrl-single,register-width = <32>;
 417                 pinctrl-single,function-mask = <0x0000001f>;
 418         };
 419
 420         main_pmx0: pinctrl@11c000 {
 421                 compatible = "ti,j7200-padconf", "pinctrl-single";
 422                 /* Proxy 0 addressing */
 423                 reg = <0x00 0x11c000 0x00 0x10c>;
 424                 #pinctrl-cells = <1>;
 425                 pinctrl-single,register-width = <32>;
 426                 pinctrl-single,function-mask = <0xffffffff>;
 427         };
 428
 429         main_pmx1: pinctrl@11c11c {
 430                 compatible = "ti,j7200-padconf", "pinctrl-single";
 431                 /* Proxy 0 addressing */
 432                 reg = <0x00 0x11c11c 0x00 0xc>;
 433                 #pinctrl-cells = <1>;
 434                 pinctrl-single,register-width = <32>;
 435                 pinctrl-single,function-mask = <0xffffffff>;
 436         };
 437
 438         main_uart0: serial@2800000 {
 439                 compatible = "ti,j721e-uart", "ti,am654-uart";
 440                 reg = <0x00 0x02800000 0x00 0x100>;
 441                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 442                 clock-frequency = <48000000>;
 443                 current-speed = <115200>;
 444                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 445                 clocks = <&k3_clks 146 2>;
 446                 clock-names = "fclk";
 447                 status = "disabled";
 448         };
 449
 450         main_uart1: serial@2810000 {
 451                 compatible = "ti,j721e-uart", "ti,am654-uart";
 452                 reg = <0x00 0x02810000 0x00 0x100>;
 453                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 454                 clock-frequency = <48000000>;
 455                 current-speed = <115200>;
 456                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
 457                 clocks = <&k3_clks 278 2>;
 458                 clock-names = "fclk";
 459                 status = "disabled";
 460         };
 461
 462         main_uart2: serial@2820000 {
 463                 compatible = "ti,j721e-uart", "ti,am654-uart";
 464                 reg = <0x00 0x02820000 0x00 0x100>;
 465                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 466                 clock-frequency = <48000000>;
 467                 current-speed = <115200>;
 468                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 469                 clocks = <&k3_clks 279 2>;
 470                 clock-names = "fclk";
 471                 status = "disabled";
 472         };
 473
 474         main_uart3: serial@2830000 {
 475                 compatible = "ti,j721e-uart", "ti,am654-uart";
 476                 reg = <0x00 0x02830000 0x00 0x100>;
 477                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 478                 clock-frequency = <48000000>;
 479                 current-speed = <115200>;
 480                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 481                 clocks = <&k3_clks 280 2>;
 482                 clock-names = "fclk";
 483                 status = "disabled";
 484         };
 485
 486         main_uart4: serial@2840000 {
 487                 compatible = "ti,j721e-uart", "ti,am654-uart";
 488                 reg = <0x00 0x02840000 0x00 0x100>;
 489                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 490                 clock-frequency = <48000000>;
 491                 current-speed = <115200>;
 492                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 493                 clocks = <&k3_clks 281 2>;
 494                 clock-names = "fclk";
 495                 status = "disabled";
 496         };
 497
 498         main_uart5: serial@2850000 {
 499                 compatible = "ti,j721e-uart", "ti,am654-uart";
 500                 reg = <0x00 0x02850000 0x00 0x100>;
 501                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 502                 clock-frequency = <48000000>;
 503                 current-speed = <115200>;
 504                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 505                 clocks = <&k3_clks 282 2>;
 506                 clock-names = "fclk";
 507                 status = "disabled";
 508         };
 509
 510         main_uart6: serial@2860000 {
 511                 compatible = "ti,j721e-uart", "ti,am654-uart";
 512                 reg = <0x00 0x02860000 0x00 0x100>;
 513                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 514                 clock-frequency = <48000000>;
 515                 current-speed = <115200>;
 516                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 517                 clocks = <&k3_clks 283 2>;
 518                 clock-names = "fclk";
 519                 status = "disabled";
 520         };
 521
 522         main_uart7: serial@2870000 {
 523                 compatible = "ti,j721e-uart", "ti,am654-uart";
 524                 reg = <0x00 0x02870000 0x00 0x100>;
 525                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 526                 clock-frequency = <48000000>;
 527                 current-speed = <115200>;
 528                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 529                 clocks = <&k3_clks 284 2>;
 530                 clock-names = "fclk";
 531                 status = "disabled";
 532         };
 533
 534         main_uart8: serial@2880000 {
 535                 compatible = "ti,j721e-uart", "ti,am654-uart";
 536                 reg = <0x00 0x02880000 0x00 0x100>;
 537                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 538                 clock-frequency = <48000000>;
 539                 current-speed = <115200>;
 540                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 541                 clocks = <&k3_clks 285 2>;
 542                 clock-names = "fclk";
 543                 status = "disabled";
 544         };
 545
 546         main_uart9: serial@2890000 {
 547                 compatible = "ti,j721e-uart", "ti,am654-uart";
 548                 reg = <0x00 0x02890000 0x00 0x100>;
 549                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 550                 clock-frequency = <48000000>;
 551                 current-speed = <115200>;
 552                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 553                 clocks = <&k3_clks 286 2>;
 554                 clock-names = "fclk";
 555                 status = "disabled";
 556         };
 557
 558         main_i2c0: i2c@2000000 {
 559                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 560                 reg = <0x00 0x2000000 0x00 0x100>;
 561                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 clock-names = "fck";
 565                 clocks = <&k3_clks 187 1>;
 566                 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
 567                 status = "disabled";
 568         };
 569
 570         main_i2c1: i2c@2010000 {
 571                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 572                 reg = <0x00 0x2010000 0x00 0x100>;
 573                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 clock-names = "fck";
 577                 clocks = <&k3_clks 188 1>;
 578                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 579                 status = "disabled";
 580         };
 581
 582         main_i2c2: i2c@2020000 {
 583                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 584                 reg = <0x00 0x2020000 0x00 0x100>;
 585                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 clock-names = "fck";
 589                 clocks = <&k3_clks 189 1>;
 590                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 591                 status = "disabled";
 592         };
 593
 594         main_i2c3: i2c@2030000 {
 595                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 596                 reg = <0x00 0x2030000 0x00 0x100>;
 597                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 clock-names = "fck";
 601                 clocks = <&k3_clks 190 1>;
 602                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 603                 status = "disabled";
 604         };
 605
 606         main_i2c4: i2c@2040000 {
 607                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 608                 reg = <0x00 0x2040000 0x00 0x100>;
 609                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 clock-names = "fck";
 613                 clocks = <&k3_clks 191 1>;
 614                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 615                 status = "disabled";
 616         };
 617
 618         main_i2c5: i2c@2050000 {
 619                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 620                 reg = <0x00 0x2050000 0x00 0x100>;
 621                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 clock-names = "fck";
 625                 clocks = <&k3_clks 192 1>;
 626                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 627                 status = "disabled";
 628         };
 629
 630         main_i2c6: i2c@2060000 {
 631                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 632                 reg = <0x00 0x2060000 0x00 0x100>;
 633                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 634                 #address-cells = <1>;
 635                 #size-cells = <0>;
 636                 clock-names = "fck";
 637                 clocks = <&k3_clks 193 1>;
 638                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
 639                 status = "disabled";
 640         };
 641
 642         main_sdhci0: mmc@4f80000 {
 643                 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
 644                 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
 645                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 646                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 647                 clock-names = "clk_ahb", "clk_xin";
 648                 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
 649                 ti,otap-del-sel-legacy = <0x0>;
 650                 ti,otap-del-sel-mmc-hs = <0x0>;
 651                 ti,otap-del-sel-ddr52 = <0x6>;
 652                 ti,otap-del-sel-hs200 = <0x8>;
 653                 ti,otap-del-sel-hs400 = <0x5>;
 654                 ti,itap-del-sel-legacy = <0x10>;
 655                 ti,itap-del-sel-mmc-hs = <0xa>;
 656                 ti,itap-del-sel-ddr52 = <0x3>;
 657                 ti,strobe-sel = <0x77>;
 658                 ti,clkbuf-sel = <0x7>;
 659                 ti,trm-icp = <0x8>;
 660                 bus-width = <8>;
 661                 mmc-ddr-1_8v;
 662                 mmc-hs200-1_8v;
 663                 mmc-hs400-1_8v;
 664                 dma-coherent;
 665                 status = "disabled";
 666         };
 667
 668         main_sdhci1: mmc@4fb0000 {
 669                 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
 670                 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
 671                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 672                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 673                 clock-names = "clk_ahb", "clk_xin";
 674                 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
 675                 ti,otap-del-sel-legacy = <0x0>;
 676                 ti,otap-del-sel-sd-hs = <0x0>;
 677                 ti,otap-del-sel-sdr12 = <0xf>;
 678                 ti,otap-del-sel-sdr25 = <0xf>;
 679                 ti,otap-del-sel-sdr50 = <0xc>;
 680                 ti,otap-del-sel-sdr104 = <0x5>;
 681                 ti,otap-del-sel-ddr50 = <0xc>;
 682                 ti,itap-del-sel-legacy = <0x0>;
 683                 ti,itap-del-sel-sd-hs = <0x0>;
 684                 ti,itap-del-sel-sdr12 = <0x0>;
 685                 ti,itap-del-sel-sdr25 = <0x0>;
 686                 ti,clkbuf-sel = <0x7>;
 687                 ti,trm-icp = <0x8>;
 688                 dma-coherent;
 689                 status = "disabled";
 690         };
 691
 692         serdes_wiz0: wiz@5060000 {
 693                 compatible = "ti,j721e-wiz-10g";
 694                 #address-cells = <1>;
 695                 #size-cells = <1>;
 696                 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
 697                 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
 698                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 699                 num-lanes = <4>;
 700                 #reset-cells = <1>;
 701                 ranges = <0x5060000 0x0 0x5060000 0x10000>;
 702
 703                 assigned-clocks = <&k3_clks 292 85>;
 704                 assigned-clock-parents = <&k3_clks 292 89>;
 705
 706                 wiz0_pll0_refclk: pll0-refclk {
 707                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 708                         clock-output-names = "wiz0_pll0_refclk";
 709                         #clock-cells = <0>;
 710                         assigned-clocks = <&wiz0_pll0_refclk>;
 711                         assigned-clock-parents = <&k3_clks 292 85>;
 712                 };
 713
 714                 wiz0_pll1_refclk: pll1-refclk {
 715                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 716                         clock-output-names = "wiz0_pll1_refclk";
 717                         #clock-cells = <0>;
 718                         assigned-clocks = <&wiz0_pll1_refclk>;
 719                         assigned-clock-parents = <&k3_clks 292 85>;
 720                 };
 721
 722                 wiz0_refclk_dig: refclk-dig {
 723                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 724                         clock-output-names = "wiz0_refclk_dig";
 725                         #clock-cells = <0>;
 726                         assigned-clocks = <&wiz0_refclk_dig>;
 727                         assigned-clock-parents = <&k3_clks 292 85>;
 728                 };
 729
 730                 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
 731                         clocks = <&wiz0_refclk_dig>;
 732                         #clock-cells = <0>;
 733                 };
 734
 735                 serdes0: serdes@5060000 {
 736                         compatible = "ti,j721e-serdes-10g";
 737                         reg = <0x05060000 0x00010000>;
 738                         reg-names = "torrent_phy";
 739                         resets = <&serdes_wiz0 0>;
 740                         reset-names = "torrent_reset";
 741                         clocks = <&wiz0_pll0_refclk>;
 742                         clock-names = "refclk";
 743                         #address-cells = <1>;
 744                         #size-cells = <0>;
 745                 };
 746         };
 747
 748         pcie1_rc: pcie@2910000 {
 749                 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
 750                 reg = <0x00 0x02910000 0x00 0x1000>,
 751                       <0x00 0x02917000 0x00 0x400>,
 752                       <0x00 0x0d800000 0x00 0x00800000>,
 753                       <0x00 0x18000000 0x00 0x00001000>;
 754                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 755                 interrupt-names = "link_state";
 756                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 757                 device_type = "pci";
 758                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 759                 max-link-speed = <3>;
 760                 num-lanes = <4>;
 761                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 762                 clocks = <&k3_clks 240 6>;
 763                 clock-names = "fck";
 764                 #address-cells = <3>;
 765                 #size-cells = <2>;
 766                 bus-range = <0x0 0xff>;
 767                 cdns,no-bar-match-nbits = <64>;
 768                 vendor-id = <0x104c>;
 769                 device-id = <0xb00f>;
 770                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 771                 dma-coherent;
 772                 ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
 773                          <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
 774                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 775                 status = "disabled";
 776         };
 777
 778         usbss0: cdns-usb@4104000 {
 779                 compatible = "ti,j721e-usb";
 780                 reg = <0x00 0x4104000 0x00 0x100>;
 781                 dma-coherent;
 782                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
 783                 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
 784                 clock-names = "ref", "lpm";
 785                 assigned-clocks = <&k3_clks 288 12>;    /* USB2_REFCLK */
 786                 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
 787                 #address-cells = <2>;
 788                 #size-cells = <2>;
 789                 ranges;
 790
 791                 usb0: usb@6000000 {
 792                         compatible = "cdns,usb3";
 793                         reg = <0x00 0x6000000 0x00 0x10000>,
 794                               <0x00 0x6010000 0x00 0x10000>,
 795                               <0x00 0x6020000 0x00 0x10000>;
 796                         reg-names = "otg", "xhci", "dev";
 797                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
 798                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 799                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 800                         interrupt-names = "host",
 801                                           "peripheral",
 802                                           "otg";
 803                         maximum-speed = "super-speed";
 804                         dr_mode = "otg";
 805                         cdns,phyrst-a-enable;
 806                 };
 807         };
 808
 809         main_gpio0: gpio@600000 {
 810                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 811                 reg = <0x00 0x00600000 0x00 0x100>;
 812                 gpio-controller;
 813                 #gpio-cells = <2>;
 814                 interrupt-parent = <&main_gpio_intr>;
 815                 interrupts = <145>, <146>, <147>, <148>,
 816                              <149>;
 817                 interrupt-controller;
 818                 #interrupt-cells = <2>;
 819                 ti,ngpio = <69>;
 820                 ti,davinci-gpio-unbanked = <0>;
 821                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 822                 clocks = <&k3_clks 105 0>;
 823                 clock-names = "gpio";
 824                 status = "disabled";
 825         };
 826
 827         main_gpio2: gpio@610000 {
 828                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 829                 reg = <0x00 0x00610000 0x00 0x100>;
 830                 gpio-controller;
 831                 #gpio-cells = <2>;
 832                 interrupt-parent = <&main_gpio_intr>;
 833                 interrupts = <154>, <155>, <156>, <157>,
 834                              <158>;
 835                 interrupt-controller;
 836                 #interrupt-cells = <2>;
 837                 ti,ngpio = <69>;
 838                 ti,davinci-gpio-unbanked = <0>;
 839                 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 840                 clocks = <&k3_clks 107 0>;
 841                 clock-names = "gpio";
 842                 status = "disabled";
 843         };
 844
 845         main_gpio4: gpio@620000 {
 846                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 847                 reg = <0x00 0x00620000 0x00 0x100>;
 848                 gpio-controller;
 849                 #gpio-cells = <2>;
 850                 interrupt-parent = <&main_gpio_intr>;
 851                 interrupts = <163>, <164>, <165>, <166>,
 852                              <167>;
 853                 interrupt-controller;
 854                 #interrupt-cells = <2>;
 855                 ti,ngpio = <69>;
 856                 ti,davinci-gpio-unbanked = <0>;
 857                 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
 858                 clocks = <&k3_clks 109 0>;
 859                 clock-names = "gpio";
 860                 status = "disabled";
 861         };
 862
 863         main_gpio6: gpio@630000 {
 864                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 865                 reg = <0x00 0x00630000 0x00 0x100>;
 866                 gpio-controller;
 867                 #gpio-cells = <2>;
 868                 interrupt-parent = <&main_gpio_intr>;
 869                 interrupts = <172>, <173>, <174>, <175>,
 870                              <176>;
 871                 interrupt-controller;
 872                 #interrupt-cells = <2>;
 873                 ti,ngpio = <69>;
 874                 ti,davinci-gpio-unbanked = <0>;
 875                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 876                 clocks = <&k3_clks 111 0>;
 877                 clock-names = "gpio";
 878                 status = "disabled";
 879         };
 880
 881         main_mcan0: can@2701000 {
 882                 compatible = "bosch,m_can";
 883                 reg = <0x00 0x02701000 0x00 0x200>,
 884                       <0x00 0x02708000 0x00 0x8000>;
 885                 reg-names = "m_can", "message_ram";
 886                 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 887                 clocks = <&k3_clks 156 0>, <&k3_clks 156 2>;
 888                 clock-names = "hclk", "cclk";
 889                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 890                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 891                 interrupt-names = "int0", "int1";
 892                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 893                 status = "disabled";
 894         };
 895
 896         main_mcan1: can@2711000 {
 897                 compatible = "bosch,m_can";
 898                 reg = <0x00 0x02711000 0x00 0x200>,
 899                       <0x00 0x02718000 0x00 0x8000>;
 900                 reg-names = "m_can", "message_ram";
 901                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 902                 clocks = <&k3_clks 158 0>, <&k3_clks 158 2>;
 903                 clock-names = "hclk", "cclk";
 904                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 905                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 906                 interrupt-names = "int0", "int1";
 907                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 908                 status = "disabled";
 909         };
 910
 911         main_mcan2: can@2721000 {
 912                 compatible = "bosch,m_can";
 913                 reg = <0x00 0x02721000 0x00 0x200>,
 914                       <0x00 0x02728000 0x00 0x8000>;
 915                 reg-names = "m_can", "message_ram";
 916                 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
 917                 clocks = <&k3_clks 160 0>, <&k3_clks 160 2>;
 918                 clock-names = "hclk", "cclk";
 919                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 920                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 921                 interrupt-names = "int0", "int1";
 922                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 923                 status = "disabled";
 924         };
 925
 926         main_mcan3: can@2731000 {
 927                 compatible = "bosch,m_can";
 928                 reg = <0x00 0x02731000 0x00 0x200>,
 929                       <0x00 0x02738000 0x00 0x8000>;
 930                 reg-names = "m_can", "message_ram";
 931                 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
 932                 clocks = <&k3_clks 161 0>, <&k3_clks 161 2>;
 933                 clock-names = "hclk", "cclk";
 934                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 935                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 936                 interrupt-names = "int0", "int1";
 937                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 938                 status = "disabled";
 939         };
 940
 941         main_mcan4: can@2741000 {
 942                 compatible = "bosch,m_can";
 943                 reg = <0x00 0x02741000 0x00 0x200>,
 944                       <0x00 0x02748000 0x00 0x8000>;
 945                 reg-names = "m_can", "message_ram";
 946                 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
 947                 clocks = <&k3_clks 162 0>, <&k3_clks 162 2>;
 948                 clock-names = "hclk", "cclk";
 949                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 950                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 951                 interrupt-names = "int0", "int1";
 952                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 953                 status = "disabled";
 954         };
 955
 956         main_mcan5: can@2751000 {
 957                 compatible = "bosch,m_can";
 958                 reg = <0x00 0x02751000 0x00 0x200>,
 959                       <0x00 0x02758000 0x00 0x8000>;
 960                 reg-names = "m_can", "message_ram";
 961                 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
 962                 clocks = <&k3_clks 163 0>, <&k3_clks 163 2>;
 963                 clock-names = "hclk", "cclk";
 964                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 965                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 966                 interrupt-names = "int0", "int1";
 967                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 968                 status = "disabled";
 969         };
 970
 971         main_mcan6: can@2761000 {
 972                 compatible = "bosch,m_can";
 973                 reg = <0x00 0x02761000 0x00 0x200>,
 974                       <0x00 0x02768000 0x00 0x8000>;
 975                 reg-names = "m_can", "message_ram";
 976                 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
 977                 clocks = <&k3_clks 164 0>, <&k3_clks 164 2>;
 978                 clock-names = "hclk", "cclk";
 979                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 980                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 981                 interrupt-names = "int0", "int1";
 982                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 983                 status = "disabled";
 984         };
 985
 986         main_mcan7: can@2771000 {
 987                 compatible = "bosch,m_can";
 988                 reg = <0x00 0x02771000 0x00 0x200>,
 989                       <0x00 0x02778000 0x00 0x8000>;
 990                 reg-names = "m_can", "message_ram";
 991                 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
 992                 clocks = <&k3_clks 165 0>, <&k3_clks 165 2>;
 993                 clock-names = "hclk", "cclk";
 994                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 995                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 996                 interrupt-names = "int0", "int1";
 997                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 998                 status = "disabled";
 999         };
1000
1001         main_mcan8: can@2781000 {
1002                 compatible = "bosch,m_can";
1003                 reg = <0x00 0x02781000 0x00 0x200>,
1004                       <0x00 0x02788000 0x00 0x8000>;
1005                 reg-names = "m_can", "message_ram";
1006                 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
1007                 clocks = <&k3_clks 166 0>, <&k3_clks 166 2>;
1008                 clock-names = "hclk", "cclk";
1009                 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1010                              <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1011                 interrupt-names = "int0", "int1";
1012                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1013                 status = "disabled";
1014         };
1015
1016         main_mcan9: can@2791000 {
1017                 compatible = "bosch,m_can";
1018                 reg = <0x00 0x02791000 0x00 0x200>,
1019                       <0x00 0x02798000 0x00 0x8000>;
1020                 reg-names = "m_can", "message_ram";
1021                 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
1022                 clocks = <&k3_clks 167 0>, <&k3_clks 167 2>;
1023                 clock-names = "hclk", "cclk";
1024                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1025                              <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1026                 interrupt-names = "int0", "int1";
1027                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1028                 status = "disabled";
1029         };
1030
1031         main_mcan10: can@27a1000 {
1032                 compatible = "bosch,m_can";
1033                 reg = <0x00 0x027a1000 0x00 0x200>,
1034                       <0x00 0x027a8000 0x00 0x8000>;
1035                 reg-names = "m_can", "message_ram";
1036                 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
1037                 clocks = <&k3_clks 168 0>, <&k3_clks 168 2>;
1038                 clock-names = "hclk", "cclk";
1039                 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1040                              <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1041                 interrupt-names = "int0", "int1";
1042                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1043                 status = "disabled";
1044         };
1045
1046         main_mcan11: can@27b1000 {
1047                 compatible = "bosch,m_can";
1048                 reg = <0x00 0x027b1000 0x00 0x200>,
1049                       <0x00 0x027b8000 0x00 0x8000>;
1050                 reg-names = "m_can", "message_ram";
1051                 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
1052                 clocks = <&k3_clks 169 0>, <&k3_clks 169 2>;
1053                 clock-names = "hclk", "cclk";
1054                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1055                              <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "int0", "int1";
1057                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1058                 status = "disabled";
1059         };
1060
1061         main_mcan12: can@27c1000 {
1062                 compatible = "bosch,m_can";
1063                 reg = <0x00 0x027c1000 0x00 0x200>,
1064                       <0x00 0x027c8000 0x00 0x8000>;
1065                 reg-names = "m_can", "message_ram";
1066                 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
1067                 clocks = <&k3_clks 170 0>, <&k3_clks 170 2>;
1068                 clock-names = "hclk", "cclk";
1069                 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1070                              <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1071                 interrupt-names = "int0", "int1";
1072                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1073                 status = "disabled";
1074         };
1075
1076         main_mcan13: can@27d1000 {
1077                 compatible = "bosch,m_can";
1078                 reg = <0x00 0x027d1000 0x00 0x200>,
1079                       <0x00 0x027d8000 0x00 0x8000>;
1080                 reg-names = "m_can", "message_ram";
1081                 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
1082                 clocks = <&k3_clks 171 0>, <&k3_clks 171 2>;
1083                 clock-names = "hclk", "cclk";
1084                 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1085                              <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1086                 interrupt-names = "int0", "int1";
1087                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1088                 status = "disabled";
1089         };
1090
1091         main_mcan14: can@2681000 {
1092                 compatible = "bosch,m_can";
1093                 reg = <0x00 0x02681000 0x00 0x200>,
1094                       <0x00 0x02688000 0x00 0x8000>;
1095                 reg-names = "m_can", "message_ram";
1096                 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
1097                 clocks = <&k3_clks 150 0>, <&k3_clks 150 2>;
1098                 clock-names = "hclk", "cclk";
1099                 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1100                              <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1101                 interrupt-names = "int0", "int1";
1102                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1103                 status = "disabled";
1104         };
1105
1106         main_mcan15: can@2691000 {
1107                 compatible = "bosch,m_can";
1108                 reg = <0x00 0x02691000 0x00 0x200>,
1109                       <0x00 0x02698000 0x00 0x8000>;
1110                 reg-names = "m_can", "message_ram";
1111                 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1112                 clocks = <&k3_clks 151 0>, <&k3_clks 151 2>;
1113                 clock-names = "hclk", "cclk";
1114                 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1115                              <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1116                 interrupt-names = "int0", "int1";
1117                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1118                 status = "disabled";
1119         };
1120
1121         main_mcan16: can@26a1000 {
1122                 compatible = "bosch,m_can";
1123                 reg = <0x00 0x026a1000 0x00 0x200>,
1124                       <0x00 0x026a8000 0x00 0x8000>;
1125                 reg-names = "m_can", "message_ram";
1126                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1127                 clocks = <&k3_clks 152 0>, <&k3_clks 152 2>;
1128                 clock-names = "hclk", "cclk";
1129                 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1130                              <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1131                 interrupt-names = "int0", "int1";
1132                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1133                 status = "disabled";
1134         };
1135
1136         main_mcan17: can@26b1000 {
1137                 compatible = "bosch,m_can";
1138                 reg = <0x00 0x026b1000 0x00 0x200>,
1139                       <0x00 0x026b8000 0x00 0x8000>;
1140                 reg-names = "m_can", "message_ram";
1141                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1142                 clocks = <&k3_clks 153 0>, <&k3_clks 153 2>;
1143                 clock-names = "hclk", "cclk";
1144                 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1145                              <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1146                 interrupt-names = "int0", "int1";
1147                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1148                 status = "disabled";
1149         };
1150
1151         main_spi0: spi@2100000 {
1152                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1153                 reg = <0x00 0x02100000 0x00 0x400>;
1154                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1155                 #address-cells = <1>;
1156                 #size-cells = <0>;
1157                 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
1158                 clocks = <&k3_clks 266 1>;
1159                 status = "disabled";
1160         };
1161
1162         main_spi1: spi@2110000 {
1163                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1164                 reg = <0x00 0x02110000 0x00 0x400>;
1165                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1166                 #address-cells = <1>;
1167                 #size-cells = <0>;
1168                 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
1169                 clocks = <&k3_clks 267 1>;
1170                 status = "disabled";
1171         };
1172
1173         main_spi2: spi@2120000 {
1174                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1175                 reg = <0x00 0x02120000 0x00 0x400>;
1176                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1177                 #address-cells = <1>;
1178                 #size-cells = <0>;
1179                 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
1180                 clocks = <&k3_clks 268 1>;
1181                 status = "disabled";
1182         };
1183
1184         main_spi3: spi@2130000 {
1185                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1186                 reg = <0x00 0x02130000 0x00 0x400>;
1187                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1188                 #address-cells = <1>;
1189                 #size-cells = <0>;
1190                 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
1191                 clocks = <&k3_clks 269 1>;
1192                 status = "disabled";
1193         };
1194
1195         main_spi4: spi@2140000 {
1196                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1197                 reg = <0x00 0x02140000 0x00 0x400>;
1198                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1199                 #address-cells = <1>;
1200                 #size-cells = <0>;
1201                 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
1202                 clocks = <&k3_clks 270 1>;
1203                 status = "disabled";
1204         };
1205
1206         main_spi5: spi@2150000 {
1207                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1208                 reg = <0x00 0x02150000 0x00 0x400>;
1209                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1210                 #address-cells = <1>;
1211                 #size-cells = <0>;
1212                 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
1213                 clocks = <&k3_clks 271 1>;
1214                 status = "disabled";
1215         };
1216
1217         main_spi6: spi@2160000 {
1218                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1219                 reg = <0x00 0x02160000 0x00 0x400>;
1220                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1221                 #address-cells = <1>;
1222                 #size-cells = <0>;
1223                 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
1224                 clocks = <&k3_clks 272 1>;
1225                 status = "disabled";
1226         };
1227
1228         main_spi7: spi@2170000 {
1229                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1230                 reg = <0x00 0x02170000 0x00 0x400>;
1231                 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1232                 #address-cells = <1>;
1233                 #size-cells = <0>;
1234                 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1235                 clocks = <&k3_clks 273 1>;
1236                 status = "disabled";
1237         };
1238
1239         watchdog0: watchdog@2200000 {
1240                 compatible = "ti,j7-rti-wdt";
1241                 reg = <0x0 0x2200000 0x0 0x100>;
1242                 clocks = <&k3_clks 252 1>;
1243                 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1244                 assigned-clocks = <&k3_clks 252 1>;
1245                 assigned-clock-parents = <&k3_clks 252 5>;
1246         };
1247
1248         watchdog1: watchdog@2210000 {
1249                 compatible = "ti,j7-rti-wdt";
1250                 reg = <0x0 0x2210000 0x0 0x100>;
1251                 clocks = <&k3_clks 253 1>;
1252                 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1253                 assigned-clocks = <&k3_clks 253 1>;
1254                 assigned-clock-parents = <&k3_clks 253 5>;
1255         };
1256
1257         main_timer0: timer@2400000 {
1258                 compatible = "ti,am654-timer";
1259                 reg = <0x00 0x2400000 0x00 0x400>;
1260                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1261                 clocks = <&k3_clks 49 1>;
1262                 clock-names = "fck";
1263                 assigned-clocks = <&k3_clks 49 1>;
1264                 assigned-clock-parents = <&k3_clks 49 2>;
1265                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1266                 ti,timer-pwm;
1267         };
1268
1269         main_timer1: timer@2410000 {
1270                 compatible = "ti,am654-timer";
1271                 reg = <0x00 0x2410000 0x00 0x400>;
1272                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1273                 clocks = <&k3_clks 50 1>;
1274                 clock-names = "fck";
1275                 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1276                 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1277                 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1278                 ti,timer-pwm;
1279         };
1280
1281         main_timer2: timer@2420000 {
1282                 compatible = "ti,am654-timer";
1283                 reg = <0x00 0x2420000 0x00 0x400>;
1284                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1285                 clocks = <&k3_clks 51 1>;
1286                 clock-names = "fck";
1287                 assigned-clocks = <&k3_clks 51 1>;
1288                 assigned-clock-parents = <&k3_clks 51 2>;
1289                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1290                 ti,timer-pwm;
1291         };
1292
1293         main_timer3: timer@2430000 {
1294                 compatible = "ti,am654-timer";
1295                 reg = <0x00 0x2430000 0x00 0x400>;
1296                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1297                 clocks = <&k3_clks 52 1>;
1298                 clock-names = "fck";
1299                 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1300                 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1301                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1302                 ti,timer-pwm;
1303         };
1304
1305         main_timer4: timer@2440000 {
1306                 compatible = "ti,am654-timer";
1307                 reg = <0x00 0x2440000 0x00 0x400>;
1308                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1309                 clocks = <&k3_clks 53 1>;
1310                 clock-names = "fck";
1311                 assigned-clocks = <&k3_clks 53 1>;
1312                 assigned-clock-parents = <&k3_clks 53 2>;
1313                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1314                 ti,timer-pwm;
1315         };
1316
1317         main_timer5: timer@2450000 {
1318                 compatible = "ti,am654-timer";
1319                 reg = <0x00 0x2450000 0x00 0x400>;
1320                 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1321                 clocks = <&k3_clks 54 1>;
1322                 clock-names = "fck";
1323                 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1324                 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1325                 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1326                 ti,timer-pwm;
1327         };
1328
1329         main_timer6: timer@2460000 {
1330                 compatible = "ti,am654-timer";
1331                 reg = <0x00 0x2460000 0x00 0x400>;
1332                 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1333                 clocks = <&k3_clks 55 1>;
1334                 clock-names = "fck";
1335                 assigned-clocks = <&k3_clks 55 1>;
1336                 assigned-clock-parents = <&k3_clks 55 2>;
1337                 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1338                 ti,timer-pwm;
1339         };
1340
1341         main_timer7: timer@2470000 {
1342                 compatible = "ti,am654-timer";
1343                 reg = <0x00 0x2470000 0x00 0x400>;
1344                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1345                 clocks = <&k3_clks 57 1>;
1346                 clock-names = "fck";
1347                 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1348                 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1349                 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1350                 ti,timer-pwm;
1351         };
1352
1353         main_timer8: timer@2480000 {
1354                 compatible = "ti,am654-timer";
1355                 reg = <0x00 0x2480000 0x00 0x400>;
1356                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1357                 clocks = <&k3_clks 58 1>;
1358                 clock-names = "fck";
1359                 assigned-clocks = <&k3_clks 58 1>;
1360                 assigned-clock-parents = <&k3_clks 58 2>;
1361                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1362                 ti,timer-pwm;
1363         };
1364
1365         main_timer9: timer@2490000 {
1366                 compatible = "ti,am654-timer";
1367                 reg = <0x00 0x2490000 0x00 0x400>;
1368                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1369                 clocks = <&k3_clks 59 1>;
1370                 clock-names = "fck";
1371                 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1372                 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1373                 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1374                 ti,timer-pwm;
1375         };
1376
1377         main_timer10: timer@24a0000 {
1378                 compatible = "ti,am654-timer";
1379                 reg = <0x00 0x24a0000 0x00 0x400>;
1380                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1381                 clocks = <&k3_clks 60 1>;
1382                 clock-names = "fck";
1383                 assigned-clocks = <&k3_clks 60 1>;
1384                 assigned-clock-parents = <&k3_clks 60 2>;
1385                 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1386                 ti,timer-pwm;
1387         };
1388
1389         main_timer11: timer@24b0000 {
1390                 compatible = "ti,am654-timer";
1391                 reg = <0x00 0x24b0000 0x00 0x400>;
1392                 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1393                 clocks = <&k3_clks 62 1>;
1394                 clock-names = "fck";
1395                 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1396                 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1397                 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1398                 ti,timer-pwm;
1399         };
1400
1401         main_timer12: timer@24c0000 {
1402                 compatible = "ti,am654-timer";
1403                 reg = <0x00 0x24c0000 0x00 0x400>;
1404                 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1405                 clocks = <&k3_clks 63 1>;
1406                 clock-names = "fck";
1407                 assigned-clocks = <&k3_clks 63 1>;
1408                 assigned-clock-parents = <&k3_clks 63 2>;
1409                 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1410                 ti,timer-pwm;
1411         };
1412
1413         main_timer13: timer@24d0000 {
1414                 compatible = "ti,am654-timer";
1415                 reg = <0x00 0x24d0000 0x00 0x400>;
1416                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1417                 clocks = <&k3_clks 64 1>;
1418                 clock-names = "fck";
1419                 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1420                 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1421                 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1422                 ti,timer-pwm;
1423         };
1424
1425         main_timer14: timer@24e0000 {
1426                 compatible = "ti,am654-timer";
1427                 reg = <0x00 0x24e0000 0x00 0x400>;
1428                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1429                 clocks = <&k3_clks 65 1>;
1430                 clock-names = "fck";
1431                 assigned-clocks = <&k3_clks 65 1>;
1432                 assigned-clock-parents = <&k3_clks 65 2>;
1433                 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1434                 ti,timer-pwm;
1435         };
1436
1437         main_timer15: timer@24f0000 {
1438                 compatible = "ti,am654-timer";
1439                 reg = <0x00 0x24f0000 0x00 0x400>;
1440                 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1441                 clocks = <&k3_clks 66 1>;
1442                 clock-names = "fck";
1443                 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1444                 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1445                 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1446                 ti,timer-pwm;
1447         };
1448
1449         main_timer16: timer@2500000 {
1450                 compatible = "ti,am654-timer";
1451                 reg = <0x00 0x2500000 0x00 0x400>;
1452                 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1453                 clocks = <&k3_clks 67 1>;
1454                 clock-names = "fck";
1455                 assigned-clocks = <&k3_clks 67 1>;
1456                 assigned-clock-parents = <&k3_clks 67 2>;
1457                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1458                 ti,timer-pwm;
1459         };
1460
1461         main_timer17: timer@2510000 {
1462                 compatible = "ti,am654-timer";
1463                 reg = <0x00 0x2510000 0x00 0x400>;
1464                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1465                 clocks = <&k3_clks 68 1>;
1466                 clock-names = "fck";
1467                 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1468                 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1469                 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1470                 ti,timer-pwm;
1471         };
1472
1473         main_timer18: timer@2520000 {
1474                 compatible = "ti,am654-timer";
1475                 reg = <0x00 0x2520000 0x00 0x400>;
1476                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1477                 clocks = <&k3_clks 69 1>;
1478                 clock-names = "fck";
1479                 assigned-clocks = <&k3_clks 69 1>;
1480                 assigned-clock-parents = <&k3_clks 69 2>;
1481                 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1482                 ti,timer-pwm;
1483         };
1484
1485         main_timer19: timer@2530000 {
1486                 compatible = "ti,am654-timer";
1487                 reg = <0x00 0x2530000 0x00 0x400>;
1488                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1489                 clocks = <&k3_clks 70 1>;
1490                 clock-names = "fck";
1491                 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1492                 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1493                 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1494                 ti,timer-pwm;
1495         };
1496
1497         main_r5fss0: r5fss@5c00000 {
1498                 compatible = "ti,j7200-r5fss";
1499                 ti,cluster-mode = <1>;
1500                 #address-cells = <1>;
1501                 #size-cells = <1>;
1502                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1503                          <0x5d00000 0x00 0x5d00000 0x20000>;
1504                 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1505
1506                 main_r5fss0_core0: r5f@5c00000 {
1507                         compatible = "ti,j7200-r5f";
1508                         reg = <0x5c00000 0x00010000>,
1509                               <0x5c10000 0x00010000>;
1510                         reg-names = "atcm", "btcm";
1511                         ti,sci = <&dmsc>;
1512                         ti,sci-dev-id = <245>;
1513                         ti,sci-proc-ids = <0x06 0xff>;
1514                         resets = <&k3_reset 245 1>;
1515                         firmware-name = "j7200-main-r5f0_0-fw";
1516                         ti,atcm-enable = <1>;
1517                         ti,btcm-enable = <1>;
1518                         ti,loczrama = <1>;
1519                 };
1520
1521                 main_r5fss0_core1: r5f@5d00000 {
1522                         compatible = "ti,j7200-r5f";
1523                         reg = <0x5d00000 0x00008000>,
1524                               <0x5d10000 0x00008000>;
1525                         reg-names = "atcm", "btcm";
1526                         ti,sci = <&dmsc>;
1527                         ti,sci-dev-id = <246>;
1528                         ti,sci-proc-ids = <0x07 0xff>;
1529                         resets = <&k3_reset 246 1>;
1530                         firmware-name = "j7200-main-r5f0_1-fw";
1531                         ti,atcm-enable = <1>;
1532                         ti,btcm-enable = <1>;
1533                         ti,loczrama = <1>;
1534                 };
1535         };
1536
1537         main_esm: esm@700000 {
1538                 compatible = "ti,j721e-esm";
1539                 reg = <0x0 0x700000 0x0 0x1000>;
1540                 ti,esm-pins = <656>, <657>;
1541         };
1542 };