arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 / {
   9         serdes_refclk: serdes-refclk {
  10                 #clock-cells = <0>;
  11                 compatible = "fixed-clock";
  12         };
  13 };
  14
  15 &cbass_main {
  16         msmc_ram: sram@70000000 {
  17                 compatible = "mmio-sram";
  18                 reg = <0x00 0x70000000 0x00 0x100000>;
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x00 0x00 0x70000000 0x100000>;
  22
  23                 atf-sram@0 {
  24                         reg = <0x00 0x20000>;
  25                 };
  26         };
  27
  28         scm_conf: scm-conf@100000 {
  29                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  30                 reg = <0x00 0x00100000 0x00 0x1c000>;
  31                 #address-cells = <1>;
  32                 #size-cells = <1>;
  33                 ranges = <0x00 0x00 0x00100000 0x1c000>;
  34
  35                 serdes_ln_ctrl: mux-controller@4080 {
  36                         compatible = "mmio-mux";
  37                         #mux-control-cells = <1>;
  38                         mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
  39                                         <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
  40                 };
  41
  42                 cpsw0_phy_gmii_sel: phy@4044 {
  43                         compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
  44                         ti,qsgmii-main-ports = <1>;
  45                         reg = <0x4044 0x10>;
  46                         #phy-cells = <1>;
  47                 };
  48
  49                 usb_serdes_mux: mux-controller@4000 {
  50                         compatible = "mmio-mux";
  51                         #mux-control-cells = <1>;
  52                         mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
  53                 };
  54         };
  55
  56         gic500: interrupt-controller@1800000 {
  57                 compatible = "arm,gic-v3";
  58                 #address-cells = <2>;
  59                 #size-cells = <2>;
  60                 ranges;
  61                 #interrupt-cells = <3>;
  62                 interrupt-controller;
  63                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  64                       <0x00 0x01900000 0x00 0x100000>,  /* GICR */
  65                       <0x00 0x6f000000 0x00 0x2000>,    /* GICC */
  66                       <0x00 0x6f010000 0x00 0x1000>,    /* GICH */
  67                       <0x00 0x6f020000 0x00 0x2000>;    /* GICV */
  68
  69                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  70                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  71
  72                 gic_its: msi-controller@1820000 {
  73                         compatible = "arm,gic-v3-its";
  74                         reg = <0x00 0x01820000 0x00 0x10000>;
  75                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  76                         msi-controller;
  77                         #msi-cells = <1>;
  78                 };
  79         };
  80
  81         main_gpio_intr: interrupt-controller@a00000 {
  82                 compatible = "ti,sci-intr";
  83                 reg = <0x00 0x00a00000 0x00 0x800>;
  84                 ti,intr-trigger-type = <1>;
  85                 interrupt-controller;
  86                 interrupt-parent = <&gic500>;
  87                 #interrupt-cells = <1>;
  88                 ti,sci = <&dmsc>;
  89                 ti,sci-dev-id = <131>;
  90                 ti,interrupt-ranges = <8 392 56>;
  91         };
  92
  93         main_navss: bus@30000000 {
  94                 compatible = "simple-bus";
  95                 #address-cells = <2>;
  96                 #size-cells = <2>;
  97                 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
  98                 ti,sci-dev-id = <199>;
  99                 dma-coherent;
 100                 dma-ranges;
 101
 102                 main_navss_intr: interrupt-controller@310e0000 {
 103                         compatible = "ti,sci-intr";
 104                         reg = <0x00 0x310e0000 0x00 0x4000>;
 105                         ti,intr-trigger-type = <4>;
 106                         interrupt-controller;
 107                         interrupt-parent = <&gic500>;
 108                         #interrupt-cells = <1>;
 109                         ti,sci = <&dmsc>;
 110                         ti,sci-dev-id = <213>;
 111                         ti,interrupt-ranges = <0 64 64>,
 112                                               <64 448 64>,
 113                                               <128 672 64>;
 114                 };
 115
 116                 main_udmass_inta: msi-controller@33d00000 {
 117                         compatible = "ti,sci-inta";
 118                         reg = <0x00 0x33d00000 0x00 0x100000>;
 119                         interrupt-controller;
 120                         #interrupt-cells = <0>;
 121                         interrupt-parent = <&main_navss_intr>;
 122                         msi-controller;
 123                         ti,sci = <&dmsc>;
 124                         ti,sci-dev-id = <209>;
 125                         ti,interrupt-ranges = <0 0 256>;
 126                 };
 127
 128                 secure_proxy_main: mailbox@32c00000 {
 129                         compatible = "ti,am654-secure-proxy";
 130                         #mbox-cells = <1>;
 131                         reg-names = "target_data", "rt", "scfg";
 132                         reg = <0x00 0x32c00000 0x00 0x100000>,
 133                               <0x00 0x32400000 0x00 0x100000>,
 134                               <0x00 0x32800000 0x00 0x100000>;
 135                         interrupt-names = "rx_011";
 136                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 137                 };
 138
 139                 hwspinlock: spinlock@30e00000 {
 140                         compatible = "ti,am654-hwspinlock";
 141                         reg = <0x00 0x30e00000 0x00 0x1000>;
 142                         #hwlock-cells = <1>;
 143                 };
 144
 145                 mailbox0_cluster0: mailbox@31f80000 {
 146                         compatible = "ti,am654-mailbox";
 147                         reg = <0x00 0x31f80000 0x00 0x200>;
 148                         #mbox-cells = <1>;
 149                         ti,mbox-num-users = <4>;
 150                         ti,mbox-num-fifos = <16>;
 151                         interrupt-parent = <&main_navss_intr>;
 152                         status = "disabled";
 153                 };
 154
 155                 mailbox0_cluster1: mailbox@31f81000 {
 156                         compatible = "ti,am654-mailbox";
 157                         reg = <0x00 0x31f81000 0x00 0x200>;
 158                         #mbox-cells = <1>;
 159                         ti,mbox-num-users = <4>;
 160                         ti,mbox-num-fifos = <16>;
 161                         interrupt-parent = <&main_navss_intr>;
 162                         status = "disabled";
 163                 };
 164
 165                 mailbox0_cluster2: mailbox@31f82000 {
 166                         compatible = "ti,am654-mailbox";
 167                         reg = <0x00 0x31f82000 0x00 0x200>;
 168                         #mbox-cells = <1>;
 169                         ti,mbox-num-users = <4>;
 170                         ti,mbox-num-fifos = <16>;
 171                         interrupt-parent = <&main_navss_intr>;
 172                         status = "disabled";
 173                 };
 174
 175                 mailbox0_cluster3: mailbox@31f83000 {
 176                         compatible = "ti,am654-mailbox";
 177                         reg = <0x00 0x31f83000 0x00 0x200>;
 178                         #mbox-cells = <1>;
 179                         ti,mbox-num-users = <4>;
 180                         ti,mbox-num-fifos = <16>;
 181                         interrupt-parent = <&main_navss_intr>;
 182                         status = "disabled";
 183                 };
 184
 185                 mailbox0_cluster4: mailbox@31f84000 {
 186                         compatible = "ti,am654-mailbox";
 187                         reg = <0x00 0x31f84000 0x00 0x200>;
 188                         #mbox-cells = <1>;
 189                         ti,mbox-num-users = <4>;
 190                         ti,mbox-num-fifos = <16>;
 191                         interrupt-parent = <&main_navss_intr>;
 192                         status = "disabled";
 193                 };
 194
 195                 mailbox0_cluster5: mailbox@31f85000 {
 196                         compatible = "ti,am654-mailbox";
 197                         reg = <0x00 0x31f85000 0x00 0x200>;
 198                         #mbox-cells = <1>;
 199                         ti,mbox-num-users = <4>;
 200                         ti,mbox-num-fifos = <16>;
 201                         interrupt-parent = <&main_navss_intr>;
 202                         status = "disabled";
 203                 };
 204
 205                 mailbox0_cluster6: mailbox@31f86000 {
 206                         compatible = "ti,am654-mailbox";
 207                         reg = <0x00 0x31f86000 0x00 0x200>;
 208                         #mbox-cells = <1>;
 209                         ti,mbox-num-users = <4>;
 210                         ti,mbox-num-fifos = <16>;
 211                         interrupt-parent = <&main_navss_intr>;
 212                         status = "disabled";
 213                 };
 214
 215                 mailbox0_cluster7: mailbox@31f87000 {
 216                         compatible = "ti,am654-mailbox";
 217                         reg = <0x00 0x31f87000 0x00 0x200>;
 218                         #mbox-cells = <1>;
 219                         ti,mbox-num-users = <4>;
 220                         ti,mbox-num-fifos = <16>;
 221                         interrupt-parent = <&main_navss_intr>;
 222                         status = "disabled";
 223                 };
 224
 225                 mailbox0_cluster8: mailbox@31f88000 {
 226                         compatible = "ti,am654-mailbox";
 227                         reg = <0x00 0x31f88000 0x00 0x200>;
 228                         #mbox-cells = <1>;
 229                         ti,mbox-num-users = <4>;
 230                         ti,mbox-num-fifos = <16>;
 231                         interrupt-parent = <&main_navss_intr>;
 232                         status = "disabled";
 233                 };
 234
 235                 mailbox0_cluster9: mailbox@31f89000 {
 236                         compatible = "ti,am654-mailbox";
 237                         reg = <0x00 0x31f89000 0x00 0x200>;
 238                         #mbox-cells = <1>;
 239                         ti,mbox-num-users = <4>;
 240                         ti,mbox-num-fifos = <16>;
 241                         interrupt-parent = <&main_navss_intr>;
 242                         status = "disabled";
 243                 };
 244
 245                 mailbox0_cluster10: mailbox@31f8a000 {
 246                         compatible = "ti,am654-mailbox";
 247                         reg = <0x00 0x31f8a000 0x00 0x200>;
 248                         #mbox-cells = <1>;
 249                         ti,mbox-num-users = <4>;
 250                         ti,mbox-num-fifos = <16>;
 251                         interrupt-parent = <&main_navss_intr>;
 252                         status = "disabled";
 253                 };
 254
 255                 mailbox0_cluster11: mailbox@31f8b000 {
 256                         compatible = "ti,am654-mailbox";
 257                         reg = <0x00 0x31f8b000 0x00 0x200>;
 258                         #mbox-cells = <1>;
 259                         ti,mbox-num-users = <4>;
 260                         ti,mbox-num-fifos = <16>;
 261                         interrupt-parent = <&main_navss_intr>;
 262                         status = "disabled";
 263                 };
 264
 265                 main_ringacc: ringacc@3c000000 {
 266                         compatible = "ti,am654-navss-ringacc";
 267                         reg = <0x00 0x3c000000 0x00 0x400000>,
 268                               <0x00 0x38000000 0x00 0x400000>,
 269                               <0x00 0x31120000 0x00 0x100>,
 270                               <0x00 0x33000000 0x00 0x40000>,
 271                               <0x00 0x31080000 0x00 0x40000>;
 272                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
 273                         ti,num-rings = <1024>;
 274                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 275                         ti,sci = <&dmsc>;
 276                         ti,sci-dev-id = <211>;
 277                         msi-parent = <&main_udmass_inta>;
 278                 };
 279
 280                 main_udmap: dma-controller@31150000 {
 281                         compatible = "ti,j721e-navss-main-udmap";
 282                         reg = <0x00 0x31150000 0x00 0x100>,
 283                               <0x00 0x34000000 0x00 0x100000>,
 284                               <0x00 0x35000000 0x00 0x100000>,
 285                               <0x00 0x30b00000 0x00 0x4000>,
 286                               <0x00 0x30c00000 0x00 0x4000>,
 287                               <0x00 0x30d00000 0x00 0x4000>;
 288                         reg-names = "gcfg", "rchanrt", "tchanrt",
 289                                     "tchan", "rchan", "rflow";
 290                         msi-parent = <&main_udmass_inta>;
 291                         #dma-cells = <1>;
 292
 293                         ti,sci = <&dmsc>;
 294                         ti,sci-dev-id = <212>;
 295                         ti,ringacc = <&main_ringacc>;
 296
 297                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 298                                                 <0x0f>, /* TX_HCHAN */
 299                                                 <0x10>; /* TX_UHCHAN */
 300                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 301                                                 <0x0b>, /* RX_HCHAN */
 302                                                 <0x0c>; /* RX_UHCHAN */
 303                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 304                 };
 305
 306                 cpts@310d0000 {
 307                         compatible = "ti,j721e-cpts";
 308                         reg = <0x00 0x310d0000 0x00 0x400>;
 309                         reg-names = "cpts";
 310                         clocks = <&k3_clks 201 1>;
 311                         clock-names = "cpts";
 312                         interrupts-extended = <&main_navss_intr 391>;
 313                         interrupt-names = "cpts";
 314                         ti,cpts-periodic-outputs = <6>;
 315                         ti,cpts-ext-ts-inputs = <8>;
 316                 };
 317         };
 318
 319         cpsw0: ethernet@c000000 {
 320                 compatible = "ti,j7200-cpswxg-nuss";
 321                 #address-cells = <2>;
 322                 #size-cells = <2>;
 323                 reg = <0x00 0xc000000 0x00 0x200000>;
 324                 reg-names = "cpsw_nuss";
 325                 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
 326                 clocks = <&k3_clks 19 33>;
 327                 clock-names = "fck";
 328                 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
 329
 330                 dmas = <&main_udmap 0xca00>,
 331                        <&main_udmap 0xca01>,
 332                        <&main_udmap 0xca02>,
 333                        <&main_udmap 0xca03>,
 334                        <&main_udmap 0xca04>,
 335                        <&main_udmap 0xca05>,
 336                        <&main_udmap 0xca06>,
 337                        <&main_udmap 0xca07>,
 338                        <&main_udmap 0x4a00>;
 339                 dma-names = "tx0", "tx1", "tx2", "tx3",
 340                             "tx4", "tx5", "tx6", "tx7",
 341                             "rx";
 342
 343                 status = "disabled";
 344
 345                 ethernet-ports {
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         cpsw0_port1: port@1 {
 349                                 reg = <1>;
 350                                 ti,mac-only;
 351                                 label = "port1";
 352                                 status = "disabled";
 353                         };
 354
 355                         cpsw0_port2: port@2 {
 356                                 reg = <2>;
 357                                 ti,mac-only;
 358                                 label = "port2";
 359                                 status = "disabled";
 360                         };
 361
 362                         cpsw0_port3: port@3 {
 363                                 reg = <3>;
 364                                 ti,mac-only;
 365                                 label = "port3";
 366                                 status = "disabled";
 367                         };
 368
 369                         cpsw0_port4: port@4 {
 370                                 reg = <4>;
 371                                 ti,mac-only;
 372                                 label = "port4";
 373                                 status = "disabled";
 374                         };
 375                 };
 376
 377                 cpsw5g_mdio: mdio@f00 {
 378                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 379                         reg = <0x00 0xf00 0x00 0x100>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         clocks = <&k3_clks 19 33>;
 383                         clock-names = "fck";
 384                         bus_freq = <1000000>;
 385                         status = "disabled";
 386                 };
 387
 388                 cpts@3d000 {
 389                         compatible = "ti,j721e-cpts";
 390                         reg = <0x00 0x3d000 0x00 0x400>;
 391                         clocks = <&k3_clks 19 16>;
 392                         clock-names = "cpts";
 393                         interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 394                         interrupt-names = "cpts";
 395                         ti,cpts-ext-ts-inputs = <4>;
 396                         ti,cpts-periodic-outputs = <2>;
 397                 };
 398         };
 399
 400         /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
 401         main_timerio_input: pinctrl@104200 {
 402                 compatible = "ti,j7200-padconf", "pinctrl-single";
 403                 reg = <0x0 0x104200 0x0 0x50>;
 404                 #pinctrl-cells = <1>;
 405                 pinctrl-single,register-width = <32>;
 406                 pinctrl-single,function-mask = <0x000001ff>;
 407         };
 408
 409         /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
 410         main_timerio_output: pinctrl@104280 {
 411                 compatible = "ti,j7200-padconf", "pinctrl-single";
 412                 reg = <0x0 0x104280 0x0 0x20>;
 413                 #pinctrl-cells = <1>;
 414                 pinctrl-single,register-width = <32>;
 415                 pinctrl-single,function-mask = <0x0000001f>;
 416         };
 417
 418         main_pmx0: pinctrl@11c000 {
 419                 compatible = "ti,j7200-padconf", "pinctrl-single";
 420                 /* Proxy 0 addressing */
 421                 reg = <0x00 0x11c000 0x00 0x10c>;
 422                 #pinctrl-cells = <1>;
 423                 pinctrl-single,register-width = <32>;
 424                 pinctrl-single,function-mask = <0xffffffff>;
 425         };
 426
 427         main_pmx1: pinctrl@11c11c {
 428                 compatible = "ti,j7200-padconf", "pinctrl-single";
 429                 /* Proxy 0 addressing */
 430                 reg = <0x00 0x11c11c 0x00 0xc>;
 431                 #pinctrl-cells = <1>;
 432                 pinctrl-single,register-width = <32>;
 433                 pinctrl-single,function-mask = <0xffffffff>;
 434         };
 435
 436         main_uart0: serial@2800000 {
 437                 compatible = "ti,j721e-uart", "ti,am654-uart";
 438                 reg = <0x00 0x02800000 0x00 0x100>;
 439                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 440                 clock-frequency = <48000000>;
 441                 current-speed = <115200>;
 442                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 443                 clocks = <&k3_clks 146 2>;
 444                 clock-names = "fclk";
 445                 status = "disabled";
 446         };
 447
 448         main_uart1: serial@2810000 {
 449                 compatible = "ti,j721e-uart", "ti,am654-uart";
 450                 reg = <0x00 0x02810000 0x00 0x100>;
 451                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 452                 clock-frequency = <48000000>;
 453                 current-speed = <115200>;
 454                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
 455                 clocks = <&k3_clks 278 2>;
 456                 clock-names = "fclk";
 457                 status = "disabled";
 458         };
 459
 460         main_uart2: serial@2820000 {
 461                 compatible = "ti,j721e-uart", "ti,am654-uart";
 462                 reg = <0x00 0x02820000 0x00 0x100>;
 463                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 464                 clock-frequency = <48000000>;
 465                 current-speed = <115200>;
 466                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 467                 clocks = <&k3_clks 279 2>;
 468                 clock-names = "fclk";
 469                 status = "disabled";
 470         };
 471
 472         main_uart3: serial@2830000 {
 473                 compatible = "ti,j721e-uart", "ti,am654-uart";
 474                 reg = <0x00 0x02830000 0x00 0x100>;
 475                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 476                 clock-frequency = <48000000>;
 477                 current-speed = <115200>;
 478                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 479                 clocks = <&k3_clks 280 2>;
 480                 clock-names = "fclk";
 481                 status = "disabled";
 482         };
 483
 484         main_uart4: serial@2840000 {
 485                 compatible = "ti,j721e-uart", "ti,am654-uart";
 486                 reg = <0x00 0x02840000 0x00 0x100>;
 487                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 488                 clock-frequency = <48000000>;
 489                 current-speed = <115200>;
 490                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 491                 clocks = <&k3_clks 281 2>;
 492                 clock-names = "fclk";
 493                 status = "disabled";
 494         };
 495
 496         main_uart5: serial@2850000 {
 497                 compatible = "ti,j721e-uart", "ti,am654-uart";
 498                 reg = <0x00 0x02850000 0x00 0x100>;
 499                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 500                 clock-frequency = <48000000>;
 501                 current-speed = <115200>;
 502                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 503                 clocks = <&k3_clks 282 2>;
 504                 clock-names = "fclk";
 505                 status = "disabled";
 506         };
 507
 508         main_uart6: serial@2860000 {
 509                 compatible = "ti,j721e-uart", "ti,am654-uart";
 510                 reg = <0x00 0x02860000 0x00 0x100>;
 511                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 512                 clock-frequency = <48000000>;
 513                 current-speed = <115200>;
 514                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 515                 clocks = <&k3_clks 283 2>;
 516                 clock-names = "fclk";
 517                 status = "disabled";
 518         };
 519
 520         main_uart7: serial@2870000 {
 521                 compatible = "ti,j721e-uart", "ti,am654-uart";
 522                 reg = <0x00 0x02870000 0x00 0x100>;
 523                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 524                 clock-frequency = <48000000>;
 525                 current-speed = <115200>;
 526                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 527                 clocks = <&k3_clks 284 2>;
 528                 clock-names = "fclk";
 529                 status = "disabled";
 530         };
 531
 532         main_uart8: serial@2880000 {
 533                 compatible = "ti,j721e-uart", "ti,am654-uart";
 534                 reg = <0x00 0x02880000 0x00 0x100>;
 535                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 536                 clock-frequency = <48000000>;
 537                 current-speed = <115200>;
 538                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 539                 clocks = <&k3_clks 285 2>;
 540                 clock-names = "fclk";
 541                 status = "disabled";
 542         };
 543
 544         main_uart9: serial@2890000 {
 545                 compatible = "ti,j721e-uart", "ti,am654-uart";
 546                 reg = <0x00 0x02890000 0x00 0x100>;
 547                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 548                 clock-frequency = <48000000>;
 549                 current-speed = <115200>;
 550                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 551                 clocks = <&k3_clks 286 2>;
 552                 clock-names = "fclk";
 553                 status = "disabled";
 554         };
 555
 556         main_i2c0: i2c@2000000 {
 557                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 558                 reg = <0x00 0x2000000 0x00 0x100>;
 559                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 clock-names = "fck";
 563                 clocks = <&k3_clks 187 1>;
 564                 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
 565                 status = "disabled";
 566         };
 567
 568         main_i2c1: i2c@2010000 {
 569                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 570                 reg = <0x00 0x2010000 0x00 0x100>;
 571                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 clock-names = "fck";
 575                 clocks = <&k3_clks 188 1>;
 576                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 577                 status = "disabled";
 578         };
 579
 580         main_i2c2: i2c@2020000 {
 581                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 582                 reg = <0x00 0x2020000 0x00 0x100>;
 583                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 584                 #address-cells = <1>;
 585                 #size-cells = <0>;
 586                 clock-names = "fck";
 587                 clocks = <&k3_clks 189 1>;
 588                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 589                 status = "disabled";
 590         };
 591
 592         main_i2c3: i2c@2030000 {
 593                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 594                 reg = <0x00 0x2030000 0x00 0x100>;
 595                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 clock-names = "fck";
 599                 clocks = <&k3_clks 190 1>;
 600                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 601                 status = "disabled";
 602         };
 603
 604         main_i2c4: i2c@2040000 {
 605                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 606                 reg = <0x00 0x2040000 0x00 0x100>;
 607                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 clock-names = "fck";
 611                 clocks = <&k3_clks 191 1>;
 612                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 613                 status = "disabled";
 614         };
 615
 616         main_i2c5: i2c@2050000 {
 617                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 618                 reg = <0x00 0x2050000 0x00 0x100>;
 619                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 620                 #address-cells = <1>;
 621                 #size-cells = <0>;
 622                 clock-names = "fck";
 623                 clocks = <&k3_clks 192 1>;
 624                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 625                 status = "disabled";
 626         };
 627
 628         main_i2c6: i2c@2060000 {
 629                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 630                 reg = <0x00 0x2060000 0x00 0x100>;
 631                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 clock-names = "fck";
 635                 clocks = <&k3_clks 193 1>;
 636                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
 637                 status = "disabled";
 638         };
 639
 640         main_sdhci0: mmc@4f80000 {
 641                 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
 642                 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
 643                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 644                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 645                 clock-names = "clk_ahb", "clk_xin";
 646                 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
 647                 ti,otap-del-sel-legacy = <0x0>;
 648                 ti,otap-del-sel-mmc-hs = <0x0>;
 649                 ti,otap-del-sel-ddr52 = <0x6>;
 650                 ti,otap-del-sel-hs200 = <0x8>;
 651                 ti,otap-del-sel-hs400 = <0x5>;
 652                 ti,itap-del-sel-legacy = <0x10>;
 653                 ti,itap-del-sel-mmc-hs = <0xa>;
 654                 ti,itap-del-sel-ddr52 = <0x3>;
 655                 ti,strobe-sel = <0x77>;
 656                 ti,clkbuf-sel = <0x7>;
 657                 ti,trm-icp = <0x8>;
 658                 bus-width = <8>;
 659                 mmc-ddr-1_8v;
 660                 mmc-hs200-1_8v;
 661                 mmc-hs400-1_8v;
 662                 dma-coherent;
 663                 status = "disabled";
 664         };
 665
 666         main_sdhci1: mmc@4fb0000 {
 667                 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
 668                 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
 669                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 670                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 671                 clock-names = "clk_ahb", "clk_xin";
 672                 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
 673                 ti,otap-del-sel-legacy = <0x0>;
 674                 ti,otap-del-sel-sd-hs = <0x0>;
 675                 ti,otap-del-sel-sdr12 = <0xf>;
 676                 ti,otap-del-sel-sdr25 = <0xf>;
 677                 ti,otap-del-sel-sdr50 = <0xc>;
 678                 ti,otap-del-sel-sdr104 = <0x5>;
 679                 ti,otap-del-sel-ddr50 = <0xc>;
 680                 ti,itap-del-sel-legacy = <0x0>;
 681                 ti,itap-del-sel-sd-hs = <0x0>;
 682                 ti,itap-del-sel-sdr12 = <0x0>;
 683                 ti,itap-del-sel-sdr25 = <0x0>;
 684                 ti,clkbuf-sel = <0x7>;
 685                 ti,trm-icp = <0x8>;
 686                 dma-coherent;
 687                 status = "disabled";
 688         };
 689
 690         serdes_wiz0: wiz@5060000 {
 691                 compatible = "ti,j721e-wiz-10g";
 692                 #address-cells = <1>;
 693                 #size-cells = <1>;
 694                 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
 695                 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
 696                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 697                 num-lanes = <4>;
 698                 #reset-cells = <1>;
 699                 ranges = <0x5060000 0x0 0x5060000 0x10000>;
 700
 701                 assigned-clocks = <&k3_clks 292 85>;
 702                 assigned-clock-parents = <&k3_clks 292 89>;
 703
 704                 wiz0_pll0_refclk: pll0-refclk {
 705                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 706                         clock-output-names = "wiz0_pll0_refclk";
 707                         #clock-cells = <0>;
 708                         assigned-clocks = <&wiz0_pll0_refclk>;
 709                         assigned-clock-parents = <&k3_clks 292 85>;
 710                 };
 711
 712                 wiz0_pll1_refclk: pll1-refclk {
 713                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 714                         clock-output-names = "wiz0_pll1_refclk";
 715                         #clock-cells = <0>;
 716                         assigned-clocks = <&wiz0_pll1_refclk>;
 717                         assigned-clock-parents = <&k3_clks 292 85>;
 718                 };
 719
 720                 wiz0_refclk_dig: refclk-dig {
 721                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 722                         clock-output-names = "wiz0_refclk_dig";
 723                         #clock-cells = <0>;
 724                         assigned-clocks = <&wiz0_refclk_dig>;
 725                         assigned-clock-parents = <&k3_clks 292 85>;
 726                 };
 727
 728                 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
 729                         clocks = <&wiz0_refclk_dig>;
 730                         #clock-cells = <0>;
 731                 };
 732
 733                 serdes0: serdes@5060000 {
 734                         compatible = "ti,j721e-serdes-10g";
 735                         reg = <0x05060000 0x00010000>;
 736                         reg-names = "torrent_phy";
 737                         resets = <&serdes_wiz0 0>;
 738                         reset-names = "torrent_reset";
 739                         clocks = <&wiz0_pll0_refclk>;
 740                         clock-names = "refclk";
 741                         #address-cells = <1>;
 742                         #size-cells = <0>;
 743                 };
 744         };
 745
 746         pcie1_rc: pcie@2910000 {
 747                 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
 748                 reg = <0x00 0x02910000 0x00 0x1000>,
 749                       <0x00 0x02917000 0x00 0x400>,
 750                       <0x00 0x0d800000 0x00 0x00800000>,
 751                       <0x00 0x18000000 0x00 0x00001000>;
 752                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 753                 interrupt-names = "link_state";
 754                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 755                 device_type = "pci";
 756                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 757                 max-link-speed = <3>;
 758                 num-lanes = <4>;
 759                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 760                 clocks = <&k3_clks 240 6>;
 761                 clock-names = "fck";
 762                 #address-cells = <3>;
 763                 #size-cells = <2>;
 764                 bus-range = <0x0 0xff>;
 765                 cdns,no-bar-match-nbits = <64>;
 766                 vendor-id = <0x104c>;
 767                 device-id = <0xb00f>;
 768                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 769                 dma-coherent;
 770                 ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
 771                          <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
 772                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 773                 status = "disabled";
 774         };
 775
 776         usbss0: cdns-usb@4104000 {
 777                 compatible = "ti,j721e-usb";
 778                 reg = <0x00 0x4104000 0x00 0x100>;
 779                 dma-coherent;
 780                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
 781                 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
 782                 clock-names = "ref", "lpm";
 783                 assigned-clocks = <&k3_clks 288 12>;    /* USB2_REFCLK */
 784                 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
 785                 #address-cells = <2>;
 786                 #size-cells = <2>;
 787                 ranges;
 788
 789                 usb0: usb@6000000 {
 790                         compatible = "cdns,usb3";
 791                         reg = <0x00 0x6000000 0x00 0x10000>,
 792                               <0x00 0x6010000 0x00 0x10000>,
 793                               <0x00 0x6020000 0x00 0x10000>;
 794                         reg-names = "otg", "xhci", "dev";
 795                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
 796                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 797                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 798                         interrupt-names = "host",
 799                                           "peripheral",
 800                                           "otg";
 801                         maximum-speed = "super-speed";
 802                         dr_mode = "otg";
 803                         cdns,phyrst-a-enable;
 804                 };
 805         };
 806
 807         main_gpio0: gpio@600000 {
 808                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 809                 reg = <0x00 0x00600000 0x00 0x100>;
 810                 gpio-controller;
 811                 #gpio-cells = <2>;
 812                 interrupt-parent = <&main_gpio_intr>;
 813                 interrupts = <145>, <146>, <147>, <148>,
 814                              <149>;
 815                 interrupt-controller;
 816                 #interrupt-cells = <2>;
 817                 ti,ngpio = <69>;
 818                 ti,davinci-gpio-unbanked = <0>;
 819                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 820                 clocks = <&k3_clks 105 0>;
 821                 clock-names = "gpio";
 822                 status = "disabled";
 823         };
 824
 825         main_gpio2: gpio@610000 {
 826                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 827                 reg = <0x00 0x00610000 0x00 0x100>;
 828                 gpio-controller;
 829                 #gpio-cells = <2>;
 830                 interrupt-parent = <&main_gpio_intr>;
 831                 interrupts = <154>, <155>, <156>, <157>,
 832                              <158>;
 833                 interrupt-controller;
 834                 #interrupt-cells = <2>;
 835                 ti,ngpio = <69>;
 836                 ti,davinci-gpio-unbanked = <0>;
 837                 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 838                 clocks = <&k3_clks 107 0>;
 839                 clock-names = "gpio";
 840                 status = "disabled";
 841         };
 842
 843         main_gpio4: gpio@620000 {
 844                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 845                 reg = <0x00 0x00620000 0x00 0x100>;
 846                 gpio-controller;
 847                 #gpio-cells = <2>;
 848                 interrupt-parent = <&main_gpio_intr>;
 849                 interrupts = <163>, <164>, <165>, <166>,
 850                              <167>;
 851                 interrupt-controller;
 852                 #interrupt-cells = <2>;
 853                 ti,ngpio = <69>;
 854                 ti,davinci-gpio-unbanked = <0>;
 855                 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
 856                 clocks = <&k3_clks 109 0>;
 857                 clock-names = "gpio";
 858                 status = "disabled";
 859         };
 860
 861         main_gpio6: gpio@630000 {
 862                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 863                 reg = <0x00 0x00630000 0x00 0x100>;
 864                 gpio-controller;
 865                 #gpio-cells = <2>;
 866                 interrupt-parent = <&main_gpio_intr>;
 867                 interrupts = <172>, <173>, <174>, <175>,
 868                              <176>;
 869                 interrupt-controller;
 870                 #interrupt-cells = <2>;
 871                 ti,ngpio = <69>;
 872                 ti,davinci-gpio-unbanked = <0>;
 873                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 874                 clocks = <&k3_clks 111 0>;
 875                 clock-names = "gpio";
 876                 status = "disabled";
 877         };
 878
 879         main_mcan0: can@2701000 {
 880                 compatible = "bosch,m_can";
 881                 reg = <0x00 0x02701000 0x00 0x200>,
 882                       <0x00 0x02708000 0x00 0x8000>;
 883                 reg-names = "m_can", "message_ram";
 884                 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 885                 clocks = <&k3_clks 156 0>, <&k3_clks 156 2>;
 886                 clock-names = "hclk", "cclk";
 887                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 888                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 889                 interrupt-names = "int0", "int1";
 890                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 891                 status = "disabled";
 892         };
 893
 894         main_mcan1: can@2711000 {
 895                 compatible = "bosch,m_can";
 896                 reg = <0x00 0x02711000 0x00 0x200>,
 897                       <0x00 0x02718000 0x00 0x8000>;
 898                 reg-names = "m_can", "message_ram";
 899                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 900                 clocks = <&k3_clks 158 0>, <&k3_clks 158 2>;
 901                 clock-names = "hclk", "cclk";
 902                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 903                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 904                 interrupt-names = "int0", "int1";
 905                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 906                 status = "disabled";
 907         };
 908
 909         main_mcan2: can@2721000 {
 910                 compatible = "bosch,m_can";
 911                 reg = <0x00 0x02721000 0x00 0x200>,
 912                       <0x00 0x02728000 0x00 0x8000>;
 913                 reg-names = "m_can", "message_ram";
 914                 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
 915                 clocks = <&k3_clks 160 0>, <&k3_clks 160 2>;
 916                 clock-names = "hclk", "cclk";
 917                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 918                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 919                 interrupt-names = "int0", "int1";
 920                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 921                 status = "disabled";
 922         };
 923
 924         main_mcan3: can@2731000 {
 925                 compatible = "bosch,m_can";
 926                 reg = <0x00 0x02731000 0x00 0x200>,
 927                       <0x00 0x02738000 0x00 0x8000>;
 928                 reg-names = "m_can", "message_ram";
 929                 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
 930                 clocks = <&k3_clks 161 0>, <&k3_clks 161 2>;
 931                 clock-names = "hclk", "cclk";
 932                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 933                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 934                 interrupt-names = "int0", "int1";
 935                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 936                 status = "disabled";
 937         };
 938
 939         main_mcan4: can@2741000 {
 940                 compatible = "bosch,m_can";
 941                 reg = <0x00 0x02741000 0x00 0x200>,
 942                       <0x00 0x02748000 0x00 0x8000>;
 943                 reg-names = "m_can", "message_ram";
 944                 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
 945                 clocks = <&k3_clks 162 0>, <&k3_clks 162 2>;
 946                 clock-names = "hclk", "cclk";
 947                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 948                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 949                 interrupt-names = "int0", "int1";
 950                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 951                 status = "disabled";
 952         };
 953
 954         main_mcan5: can@2751000 {
 955                 compatible = "bosch,m_can";
 956                 reg = <0x00 0x02751000 0x00 0x200>,
 957                       <0x00 0x02758000 0x00 0x8000>;
 958                 reg-names = "m_can", "message_ram";
 959                 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
 960                 clocks = <&k3_clks 163 0>, <&k3_clks 163 2>;
 961                 clock-names = "hclk", "cclk";
 962                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 963                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 964                 interrupt-names = "int0", "int1";
 965                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 966                 status = "disabled";
 967         };
 968
 969         main_mcan6: can@2761000 {
 970                 compatible = "bosch,m_can";
 971                 reg = <0x00 0x02761000 0x00 0x200>,
 972                       <0x00 0x02768000 0x00 0x8000>;
 973                 reg-names = "m_can", "message_ram";
 974                 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
 975                 clocks = <&k3_clks 164 0>, <&k3_clks 164 2>;
 976                 clock-names = "hclk", "cclk";
 977                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 978                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 979                 interrupt-names = "int0", "int1";
 980                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 981                 status = "disabled";
 982         };
 983
 984         main_mcan7: can@2771000 {
 985                 compatible = "bosch,m_can";
 986                 reg = <0x00 0x02771000 0x00 0x200>,
 987                       <0x00 0x02778000 0x00 0x8000>;
 988                 reg-names = "m_can", "message_ram";
 989                 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
 990                 clocks = <&k3_clks 165 0>, <&k3_clks 165 2>;
 991                 clock-names = "hclk", "cclk";
 992                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 993                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 994                 interrupt-names = "int0", "int1";
 995                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 996                 status = "disabled";
 997         };
 998
 999         main_mcan8: can@2781000 {
1000                 compatible = "bosch,m_can";
1001                 reg = <0x00 0x02781000 0x00 0x200>,
1002                       <0x00 0x02788000 0x00 0x8000>;
1003                 reg-names = "m_can", "message_ram";
1004                 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
1005                 clocks = <&k3_clks 166 0>, <&k3_clks 166 2>;
1006                 clock-names = "hclk", "cclk";
1007                 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1008                              <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1009                 interrupt-names = "int0", "int1";
1010                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1011                 status = "disabled";
1012         };
1013
1014         main_mcan9: can@2791000 {
1015                 compatible = "bosch,m_can";
1016                 reg = <0x00 0x02791000 0x00 0x200>,
1017                       <0x00 0x02798000 0x00 0x8000>;
1018                 reg-names = "m_can", "message_ram";
1019                 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
1020                 clocks = <&k3_clks 167 0>, <&k3_clks 167 2>;
1021                 clock-names = "hclk", "cclk";
1022                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1023                              <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1024                 interrupt-names = "int0", "int1";
1025                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1026                 status = "disabled";
1027         };
1028
1029         main_mcan10: can@27a1000 {
1030                 compatible = "bosch,m_can";
1031                 reg = <0x00 0x027a1000 0x00 0x200>,
1032                       <0x00 0x027a8000 0x00 0x8000>;
1033                 reg-names = "m_can", "message_ram";
1034                 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
1035                 clocks = <&k3_clks 168 0>, <&k3_clks 168 2>;
1036                 clock-names = "hclk", "cclk";
1037                 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1038                              <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1039                 interrupt-names = "int0", "int1";
1040                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1041                 status = "disabled";
1042         };
1043
1044         main_mcan11: can@27b1000 {
1045                 compatible = "bosch,m_can";
1046                 reg = <0x00 0x027b1000 0x00 0x200>,
1047                       <0x00 0x027b8000 0x00 0x8000>;
1048                 reg-names = "m_can", "message_ram";
1049                 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
1050                 clocks = <&k3_clks 169 0>, <&k3_clks 169 2>;
1051                 clock-names = "hclk", "cclk";
1052                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1053                              <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1054                 interrupt-names = "int0", "int1";
1055                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1056                 status = "disabled";
1057         };
1058
1059         main_mcan12: can@27c1000 {
1060                 compatible = "bosch,m_can";
1061                 reg = <0x00 0x027c1000 0x00 0x200>,
1062                       <0x00 0x027c8000 0x00 0x8000>;
1063                 reg-names = "m_can", "message_ram";
1064                 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
1065                 clocks = <&k3_clks 170 0>, <&k3_clks 170 2>;
1066                 clock-names = "hclk", "cclk";
1067                 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1068                              <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1069                 interrupt-names = "int0", "int1";
1070                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1071                 status = "disabled";
1072         };
1073
1074         main_mcan13: can@27d1000 {
1075                 compatible = "bosch,m_can";
1076                 reg = <0x00 0x027d1000 0x00 0x200>,
1077                       <0x00 0x027d8000 0x00 0x8000>;
1078                 reg-names = "m_can", "message_ram";
1079                 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
1080                 clocks = <&k3_clks 171 0>, <&k3_clks 171 2>;
1081                 clock-names = "hclk", "cclk";
1082                 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1083                              <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1084                 interrupt-names = "int0", "int1";
1085                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1086                 status = "disabled";
1087         };
1088
1089         main_mcan14: can@2681000 {
1090                 compatible = "bosch,m_can";
1091                 reg = <0x00 0x02681000 0x00 0x200>,
1092                       <0x00 0x02688000 0x00 0x8000>;
1093                 reg-names = "m_can", "message_ram";
1094                 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
1095                 clocks = <&k3_clks 150 0>, <&k3_clks 150 2>;
1096                 clock-names = "hclk", "cclk";
1097                 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1098                              <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1099                 interrupt-names = "int0", "int1";
1100                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1101                 status = "disabled";
1102         };
1103
1104         main_mcan15: can@2691000 {
1105                 compatible = "bosch,m_can";
1106                 reg = <0x00 0x02691000 0x00 0x200>,
1107                       <0x00 0x02698000 0x00 0x8000>;
1108                 reg-names = "m_can", "message_ram";
1109                 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1110                 clocks = <&k3_clks 151 0>, <&k3_clks 151 2>;
1111                 clock-names = "hclk", "cclk";
1112                 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1113                              <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1114                 interrupt-names = "int0", "int1";
1115                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1116                 status = "disabled";
1117         };
1118
1119         main_mcan16: can@26a1000 {
1120                 compatible = "bosch,m_can";
1121                 reg = <0x00 0x026a1000 0x00 0x200>,
1122                       <0x00 0x026a8000 0x00 0x8000>;
1123                 reg-names = "m_can", "message_ram";
1124                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1125                 clocks = <&k3_clks 152 0>, <&k3_clks 152 2>;
1126                 clock-names = "hclk", "cclk";
1127                 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1128                              <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1129                 interrupt-names = "int0", "int1";
1130                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1131                 status = "disabled";
1132         };
1133
1134         main_mcan17: can@26b1000 {
1135                 compatible = "bosch,m_can";
1136                 reg = <0x00 0x026b1000 0x00 0x200>,
1137                       <0x00 0x026b8000 0x00 0x8000>;
1138                 reg-names = "m_can", "message_ram";
1139                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1140                 clocks = <&k3_clks 153 0>, <&k3_clks 153 2>;
1141                 clock-names = "hclk", "cclk";
1142                 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1143                              <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1144                 interrupt-names = "int0", "int1";
1145                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1146                 status = "disabled";
1147         };
1148
1149         main_spi0: spi@2100000 {
1150                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1151                 reg = <0x00 0x02100000 0x00 0x400>;
1152                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1153                 #address-cells = <1>;
1154                 #size-cells = <0>;
1155                 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
1156                 clocks = <&k3_clks 266 1>;
1157                 status = "disabled";
1158         };
1159
1160         main_spi1: spi@2110000 {
1161                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1162                 reg = <0x00 0x02110000 0x00 0x400>;
1163                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1164                 #address-cells = <1>;
1165                 #size-cells = <0>;
1166                 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
1167                 clocks = <&k3_clks 267 1>;
1168                 status = "disabled";
1169         };
1170
1171         main_spi2: spi@2120000 {
1172                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1173                 reg = <0x00 0x02120000 0x00 0x400>;
1174                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1175                 #address-cells = <1>;
1176                 #size-cells = <0>;
1177                 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
1178                 clocks = <&k3_clks 268 1>;
1179                 status = "disabled";
1180         };
1181
1182         main_spi3: spi@2130000 {
1183                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1184                 reg = <0x00 0x02130000 0x00 0x400>;
1185                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1186                 #address-cells = <1>;
1187                 #size-cells = <0>;
1188                 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
1189                 clocks = <&k3_clks 269 1>;
1190                 status = "disabled";
1191         };
1192
1193         main_spi4: spi@2140000 {
1194                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1195                 reg = <0x00 0x02140000 0x00 0x400>;
1196                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1197                 #address-cells = <1>;
1198                 #size-cells = <0>;
1199                 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
1200                 clocks = <&k3_clks 270 1>;
1201                 status = "disabled";
1202         };
1203
1204         main_spi5: spi@2150000 {
1205                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1206                 reg = <0x00 0x02150000 0x00 0x400>;
1207                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1208                 #address-cells = <1>;
1209                 #size-cells = <0>;
1210                 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
1211                 clocks = <&k3_clks 271 1>;
1212                 status = "disabled";
1213         };
1214
1215         main_spi6: spi@2160000 {
1216                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1217                 reg = <0x00 0x02160000 0x00 0x400>;
1218                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1219                 #address-cells = <1>;
1220                 #size-cells = <0>;
1221                 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
1222                 clocks = <&k3_clks 272 1>;
1223                 status = "disabled";
1224         };
1225
1226         main_spi7: spi@2170000 {
1227                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1228                 reg = <0x00 0x02170000 0x00 0x400>;
1229                 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1230                 #address-cells = <1>;
1231                 #size-cells = <0>;
1232                 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1233                 clocks = <&k3_clks 273 1>;
1234                 status = "disabled";
1235         };
1236
1237         watchdog0: watchdog@2200000 {
1238                 compatible = "ti,j7-rti-wdt";
1239                 reg = <0x0 0x2200000 0x0 0x100>;
1240                 clocks = <&k3_clks 252 1>;
1241                 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1242                 assigned-clocks = <&k3_clks 252 1>;
1243                 assigned-clock-parents = <&k3_clks 252 5>;
1244         };
1245
1246         watchdog1: watchdog@2210000 {
1247                 compatible = "ti,j7-rti-wdt";
1248                 reg = <0x0 0x2210000 0x0 0x100>;
1249                 clocks = <&k3_clks 253 1>;
1250                 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1251                 assigned-clocks = <&k3_clks 253 1>;
1252                 assigned-clock-parents = <&k3_clks 253 5>;
1253         };
1254
1255         main_timer0: timer@2400000 {
1256                 compatible = "ti,am654-timer";
1257                 reg = <0x00 0x2400000 0x00 0x400>;
1258                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1259                 clocks = <&k3_clks 49 1>;
1260                 clock-names = "fck";
1261                 assigned-clocks = <&k3_clks 49 1>;
1262                 assigned-clock-parents = <&k3_clks 49 2>;
1263                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1264                 ti,timer-pwm;
1265         };
1266
1267         main_timer1: timer@2410000 {
1268                 compatible = "ti,am654-timer";
1269                 reg = <0x00 0x2410000 0x00 0x400>;
1270                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1271                 clocks = <&k3_clks 50 1>;
1272                 clock-names = "fck";
1273                 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1274                 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1275                 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1276                 ti,timer-pwm;
1277         };
1278
1279         main_timer2: timer@2420000 {
1280                 compatible = "ti,am654-timer";
1281                 reg = <0x00 0x2420000 0x00 0x400>;
1282                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1283                 clocks = <&k3_clks 51 1>;
1284                 clock-names = "fck";
1285                 assigned-clocks = <&k3_clks 51 1>;
1286                 assigned-clock-parents = <&k3_clks 51 2>;
1287                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1288                 ti,timer-pwm;
1289         };
1290
1291         main_timer3: timer@2430000 {
1292                 compatible = "ti,am654-timer";
1293                 reg = <0x00 0x2430000 0x00 0x400>;
1294                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1295                 clocks = <&k3_clks 52 1>;
1296                 clock-names = "fck";
1297                 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1298                 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1299                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1300                 ti,timer-pwm;
1301         };
1302
1303         main_timer4: timer@2440000 {
1304                 compatible = "ti,am654-timer";
1305                 reg = <0x00 0x2440000 0x00 0x400>;
1306                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1307                 clocks = <&k3_clks 53 1>;
1308                 clock-names = "fck";
1309                 assigned-clocks = <&k3_clks 53 1>;
1310                 assigned-clock-parents = <&k3_clks 53 2>;
1311                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1312                 ti,timer-pwm;
1313         };
1314
1315         main_timer5: timer@2450000 {
1316                 compatible = "ti,am654-timer";
1317                 reg = <0x00 0x2450000 0x00 0x400>;
1318                 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1319                 clocks = <&k3_clks 54 1>;
1320                 clock-names = "fck";
1321                 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1322                 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1323                 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1324                 ti,timer-pwm;
1325         };
1326
1327         main_timer6: timer@2460000 {
1328                 compatible = "ti,am654-timer";
1329                 reg = <0x00 0x2460000 0x00 0x400>;
1330                 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1331                 clocks = <&k3_clks 55 1>;
1332                 clock-names = "fck";
1333                 assigned-clocks = <&k3_clks 55 1>;
1334                 assigned-clock-parents = <&k3_clks 55 2>;
1335                 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1336                 ti,timer-pwm;
1337         };
1338
1339         main_timer7: timer@2470000 {
1340                 compatible = "ti,am654-timer";
1341                 reg = <0x00 0x2470000 0x00 0x400>;
1342                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1343                 clocks = <&k3_clks 57 1>;
1344                 clock-names = "fck";
1345                 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1346                 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1347                 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1348                 ti,timer-pwm;
1349         };
1350
1351         main_timer8: timer@2480000 {
1352                 compatible = "ti,am654-timer";
1353                 reg = <0x00 0x2480000 0x00 0x400>;
1354                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1355                 clocks = <&k3_clks 58 1>;
1356                 clock-names = "fck";
1357                 assigned-clocks = <&k3_clks 58 1>;
1358                 assigned-clock-parents = <&k3_clks 58 2>;
1359                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1360                 ti,timer-pwm;
1361         };
1362
1363         main_timer9: timer@2490000 {
1364                 compatible = "ti,am654-timer";
1365                 reg = <0x00 0x2490000 0x00 0x400>;
1366                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1367                 clocks = <&k3_clks 59 1>;
1368                 clock-names = "fck";
1369                 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1370                 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1371                 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1372                 ti,timer-pwm;
1373         };
1374
1375         main_timer10: timer@24a0000 {
1376                 compatible = "ti,am654-timer";
1377                 reg = <0x00 0x24a0000 0x00 0x400>;
1378                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1379                 clocks = <&k3_clks 60 1>;
1380                 clock-names = "fck";
1381                 assigned-clocks = <&k3_clks 60 1>;
1382                 assigned-clock-parents = <&k3_clks 60 2>;
1383                 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1384                 ti,timer-pwm;
1385         };
1386
1387         main_timer11: timer@24b0000 {
1388                 compatible = "ti,am654-timer";
1389                 reg = <0x00 0x24b0000 0x00 0x400>;
1390                 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1391                 clocks = <&k3_clks 62 1>;
1392                 clock-names = "fck";
1393                 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1394                 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1395                 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1396                 ti,timer-pwm;
1397         };
1398
1399         main_timer12: timer@24c0000 {
1400                 compatible = "ti,am654-timer";
1401                 reg = <0x00 0x24c0000 0x00 0x400>;
1402                 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1403                 clocks = <&k3_clks 63 1>;
1404                 clock-names = "fck";
1405                 assigned-clocks = <&k3_clks 63 1>;
1406                 assigned-clock-parents = <&k3_clks 63 2>;
1407                 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1408                 ti,timer-pwm;
1409         };
1410
1411         main_timer13: timer@24d0000 {
1412                 compatible = "ti,am654-timer";
1413                 reg = <0x00 0x24d0000 0x00 0x400>;
1414                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1415                 clocks = <&k3_clks 64 1>;
1416                 clock-names = "fck";
1417                 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1418                 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1419                 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1420                 ti,timer-pwm;
1421         };
1422
1423         main_timer14: timer@24e0000 {
1424                 compatible = "ti,am654-timer";
1425                 reg = <0x00 0x24e0000 0x00 0x400>;
1426                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1427                 clocks = <&k3_clks 65 1>;
1428                 clock-names = "fck";
1429                 assigned-clocks = <&k3_clks 65 1>;
1430                 assigned-clock-parents = <&k3_clks 65 2>;
1431                 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1432                 ti,timer-pwm;
1433         };
1434
1435         main_timer15: timer@24f0000 {
1436                 compatible = "ti,am654-timer";
1437                 reg = <0x00 0x24f0000 0x00 0x400>;
1438                 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1439                 clocks = <&k3_clks 66 1>;
1440                 clock-names = "fck";
1441                 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1442                 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1443                 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1444                 ti,timer-pwm;
1445         };
1446
1447         main_timer16: timer@2500000 {
1448                 compatible = "ti,am654-timer";
1449                 reg = <0x00 0x2500000 0x00 0x400>;
1450                 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1451                 clocks = <&k3_clks 67 1>;
1452                 clock-names = "fck";
1453                 assigned-clocks = <&k3_clks 67 1>;
1454                 assigned-clock-parents = <&k3_clks 67 2>;
1455                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1456                 ti,timer-pwm;
1457         };
1458
1459         main_timer17: timer@2510000 {
1460                 compatible = "ti,am654-timer";
1461                 reg = <0x00 0x2510000 0x00 0x400>;
1462                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1463                 clocks = <&k3_clks 68 1>;
1464                 clock-names = "fck";
1465                 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1466                 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1467                 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1468                 ti,timer-pwm;
1469         };
1470
1471         main_timer18: timer@2520000 {
1472                 compatible = "ti,am654-timer";
1473                 reg = <0x00 0x2520000 0x00 0x400>;
1474                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1475                 clocks = <&k3_clks 69 1>;
1476                 clock-names = "fck";
1477                 assigned-clocks = <&k3_clks 69 1>;
1478                 assigned-clock-parents = <&k3_clks 69 2>;
1479                 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1480                 ti,timer-pwm;
1481         };
1482
1483         main_timer19: timer@2530000 {
1484                 compatible = "ti,am654-timer";
1485                 reg = <0x00 0x2530000 0x00 0x400>;
1486                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1487                 clocks = <&k3_clks 70 1>;
1488                 clock-names = "fck";
1489                 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1490                 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1491                 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1492                 ti,timer-pwm;
1493         };
1494
1495         main_r5fss0: r5fss@5c00000 {
1496                 compatible = "ti,j7200-r5fss";
1497                 ti,cluster-mode = <1>;
1498                 #address-cells = <1>;
1499                 #size-cells = <1>;
1500                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1501                          <0x5d00000 0x00 0x5d00000 0x20000>;
1502                 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1503
1504                 main_r5fss0_core0: r5f@5c00000 {
1505                         compatible = "ti,j7200-r5f";
1506                         reg = <0x5c00000 0x00010000>,
1507                               <0x5c10000 0x00010000>;
1508                         reg-names = "atcm", "btcm";
1509                         ti,sci = <&dmsc>;
1510                         ti,sci-dev-id = <245>;
1511                         ti,sci-proc-ids = <0x06 0xff>;
1512                         resets = <&k3_reset 245 1>;
1513                         firmware-name = "j7200-main-r5f0_0-fw";
1514                         ti,atcm-enable = <1>;
1515                         ti,btcm-enable = <1>;
1516                         ti,loczrama = <1>;
1517                 };
1518
1519                 main_r5fss0_core1: r5f@5d00000 {
1520                         compatible = "ti,j7200-r5f";
1521                         reg = <0x5d00000 0x00008000>,
1522                               <0x5d10000 0x00008000>;
1523                         reg-names = "atcm", "btcm";
1524                         ti,sci = <&dmsc>;
1525                         ti,sci-dev-id = <246>;
1526                         ti,sci-proc-ids = <0x07 0xff>;
1527                         resets = <&k3_reset 246 1>;
1528                         firmware-name = "j7200-main-r5f0_1-fw";
1529                         ti,atcm-enable = <1>;
1530                         ti,btcm-enable = <1>;
1531                         ti,loczrama = <1>;
1532                 };
1533         };
1534
1535         main_esm: esm@700000 {
1536                 compatible = "ti,j721e-esm";
1537                 reg = <0x0 0x700000 0x0 0x1000>;
1538                 ti,esm-pins = <656>, <657>;
1539         };
1540 };