arch/arm64/boot/dts/ti/k3-am69-sk.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
   4  *
   5  * Design Files: https://www.ti.com/lit/zip/SPRR466
   6  * TRM: https://www.ti.com/lit/zip/spruj52
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include "k3-j784s4.dtsi"
  14
  15 / {
  16         compatible = "ti,am69-sk", "ti,j784s4";
  17         model = "Texas Instruments AM69 SK";
  18
  19         chosen {
  20                 stdout-path = "serial2:115200n8";
  21         };
  22
  23         aliases {
  24                 serial0 = &wkup_uart0;
  25                 serial1 = &mcu_uart0;
  26                 serial2 = &main_uart8;
  27                 mmc0 = &main_sdhci0;
  28                 mmc1 = &main_sdhci1;
  29                 i2c0 = &wkup_i2c0;
  30                 i2c3 = &main_i2c0;
  31                 ethernet0 = &mcu_cpsw_port1;
  32         };
  33
  34         memory@80000000 {
  35                 device_type = "memory";
  36                 bootph-all;
  37                 /* 32G RAM */
  38                 reg = <0x00 0x80000000 0x00 0x80000000>,
  39                       <0x08 0x80000000 0x07 0x80000000>;
  40         };
  41
  42         reserved_memory: reserved-memory {
  43                 #address-cells = <2>;
  44                 #size-cells = <2>;
  45                 ranges;
  46
  47                 secure_ddr: optee@9e800000 {
  48                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  49                         no-map;
  50                 };
  51
  52                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  53                         compatible = "shared-dma-pool";
  54                         reg = <0x00 0xa0000000 0x00 0x100000>;
  55                         no-map;
  56                 };
  57
  58                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  59                         compatible = "shared-dma-pool";
  60                         reg = <0x00 0xa0100000 0x00 0xf00000>;
  61                         no-map;
  62                 };
  63
  64                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  65                         compatible = "shared-dma-pool";
  66                         reg = <0x00 0xa1000000 0x00 0x100000>;
  67                         no-map;
  68                 };
  69
  70                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  71                         compatible = "shared-dma-pool";
  72                         reg = <0x00 0xa1100000 0x00 0xf00000>;
  73                         no-map;
  74                 };
  75
  76                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
  77                         compatible = "shared-dma-pool";
  78                         reg = <0x00 0xa2000000 0x00 0x100000>;
  79                         no-map;
  80                 };
  81
  82                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
  83                         compatible = "shared-dma-pool";
  84                         reg = <0x00 0xa2100000 0x00 0xf00000>;
  85                         no-map;
  86                 };
  87
  88                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
  89                         compatible = "shared-dma-pool";
  90                         reg = <0x00 0xa3000000 0x00 0x100000>;
  91                         no-map;
  92                 };
  93
  94                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
  95                         compatible = "shared-dma-pool";
  96                         reg = <0x00 0xa3100000 0x00 0xf00000>;
  97                         no-map;
  98                 };
  99
 100                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
 101                         compatible = "shared-dma-pool";
 102                         reg = <0x00 0xa4000000 0x00 0x100000>;
 103                         no-map;
 104                 };
 105
 106                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
 107                         compatible = "shared-dma-pool";
 108                         reg = <0x00 0xa4100000 0x00 0xf00000>;
 109                         no-map;
 110                 };
 111
 112                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
 113                         compatible = "shared-dma-pool";
 114                         reg = <0x00 0xa5000000 0x00 0x100000>;
 115                         no-map;
 116                 };
 117
 118                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
 119                         compatible = "shared-dma-pool";
 120                         reg = <0x00 0xa5100000 0x00 0xf00000>;
 121                         no-map;
 122                 };
 123
 124                 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
 125                         compatible = "shared-dma-pool";
 126                         reg = <0x00 0xa6000000 0x00 0x100000>;
 127                         no-map;
 128                 };
 129
 130                 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
 131                         compatible = "shared-dma-pool";
 132                         reg = <0x00 0xa6100000 0x00 0xf00000>;
 133                         no-map;
 134                 };
 135
 136                 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
 137                         compatible = "shared-dma-pool";
 138                         reg = <0x00 0xa7000000 0x00 0x100000>;
 139                         no-map;
 140                 };
 141
 142                 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
 143                         compatible = "shared-dma-pool";
 144                         reg = <0x00 0xa7100000 0x00 0xf00000>;
 145                         no-map;
 146                 };
 147
 148                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
 149                         compatible = "shared-dma-pool";
 150                         reg = <0x00 0xa8000000 0x00 0x100000>;
 151                         no-map;
 152                 };
 153
 154                 c71_0_memory_region: c71-memory@a8100000 {
 155                         compatible = "shared-dma-pool";
 156                         reg = <0x00 0xa8100000 0x00 0xf00000>;
 157                         no-map;
 158                 };
 159
 160                 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
 161                         compatible = "shared-dma-pool";
 162                         reg = <0x00 0xa9000000 0x00 0x100000>;
 163                         no-map;
 164                 };
 165
 166                 c71_1_memory_region: c71-memory@a9100000 {
 167                         compatible = "shared-dma-pool";
 168                         reg = <0x00 0xa9100000 0x00 0xf00000>;
 169                         no-map;
 170                 };
 171
 172                 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
 173                         compatible = "shared-dma-pool";
 174                         reg = <0x00 0xaa000000 0x00 0x100000>;
 175                         no-map;
 176                 };
 177
 178                 c71_2_memory_region: c71-memory@aa100000 {
 179                         compatible = "shared-dma-pool";
 180                         reg = <0x00 0xaa100000 0x00 0xf00000>;
 181                         no-map;
 182                 };
 183
 184                 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
 185                         compatible = "shared-dma-pool";
 186                         reg = <0x00 0xab000000 0x00 0x100000>;
 187                         no-map;
 188                 };
 189
 190                 c71_3_memory_region: c71-memory@ab100000 {
 191                         compatible = "shared-dma-pool";
 192                         reg = <0x00 0xab100000 0x00 0xf00000>;
 193                         no-map;
 194                 };
 195         };
 196
 197         vusb_main: regulator-vusb-main5v0 {
 198                 /* USB MAIN INPUT 5V DC */
 199                 compatible = "regulator-fixed";
 200                 regulator-name = "vusb-main5v0";
 201                 regulator-min-microvolt = <5000000>;
 202                 regulator-max-microvolt = <5000000>;
 203                 regulator-always-on;
 204                 regulator-boot-on;
 205         };
 206
 207         vsys_5v0: regulator-vsys5v0 {
 208                 /* Output of LM61460 */
 209                 compatible = "regulator-fixed";
 210                 regulator-name = "vsys_5v0";
 211                 regulator-min-microvolt = <5000000>;
 212                 regulator-max-microvolt = <5000000>;
 213                 vin-supply = <&vusb_main>;
 214                 regulator-always-on;
 215                 regulator-boot-on;
 216         };
 217
 218         vsys_3v3: regulator-vsys3v3 {
 219                 /* Output of LM5143 */
 220                 compatible = "regulator-fixed";
 221                 regulator-name = "vsys_3v3";
 222                 regulator-min-microvolt = <3300000>;
 223                 regulator-max-microvolt = <3300000>;
 224                 vin-supply = <&vusb_main>;
 225                 regulator-always-on;
 226                 regulator-boot-on;
 227         };
 228
 229         vdd_mmc1: regulator-sd {
 230                 /* Output of TPS22918 */
 231                 compatible = "regulator-fixed";
 232                 regulator-name = "vdd_mmc1";
 233                 regulator-min-microvolt = <3300000>;
 234                 regulator-max-microvolt = <3300000>;
 235                 regulator-boot-on;
 236                 enable-active-high;
 237                 vin-supply = <&vsys_3v3>;
 238                 gpio = <&exp1 2 GPIO_ACTIVE_HIGH>;
 239         };
 240
 241         vdd_sd_dv: regulator-tlv71033 {
 242                 /* Output of TLV71033 */
 243                 compatible = "regulator-gpio";
 244                 regulator-name = "tlv71033";
 245                 pinctrl-names = "default";
 246                 pinctrl-0 = <&vdd_sd_dv_pins_default>;
 247                 regulator-min-microvolt = <1800000>;
 248                 regulator-max-microvolt = <3300000>;
 249                 regulator-boot-on;
 250                 vin-supply = <&vsys_5v0>;
 251                 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
 252                 states = <1800000 0x0>,
 253                          <3300000 0x1>;
 254         };
 255
 256         dp0_pwr_3v3: regulator-dp0-pwr {
 257                 compatible = "regulator-fixed";
 258                 regulator-name = "dp0-pwr";
 259                 regulator-min-microvolt = <3300000>;
 260                 regulator-max-microvolt = <3300000>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&dp_pwr_en_pins_default>;
 263                 gpio = <&main_gpio0 4 0>;       /* DP0_3V3 _EN */
 264                 enable-active-high;
 265         };
 266
 267         dp0: connector-dp0 {
 268                 compatible = "dp-connector";
 269                 label = "DP0";
 270                 type = "full-size";
 271                 dp-pwr-supply = <&dp0_pwr_3v3>;
 272
 273                 port {
 274                         dp0_connector_in: endpoint {
 275                                 remote-endpoint = <&dp0_out>;
 276                         };
 277                 };
 278         };
 279
 280         connector-hdmi {
 281                 compatible = "hdmi-connector";
 282                 label = "hdmi";
 283                 type = "a";
 284                 pinctrl-names = "default";
 285                 pinctrl-0 = <&hdmi_hpd_pins_default>;
 286                 ddc-i2c-bus = <&mcu_i2c1>;
 287                 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;   /* HDMI_HPD */
 288
 289                 port {
 290                         hdmi_connector_in: endpoint {
 291                                 remote-endpoint = <&tfp410_out>;
 292                         };
 293                 };
 294         };
 295
 296         bridge-dvi {
 297                 compatible = "ti,tfp410";
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&hdmi_pdn_pins_default>;
 300                 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>;     /* HDMI_PDn */
 301                 ti,deskew = <0>;
 302
 303                 ports {
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306
 307                         port@0 {
 308                                 reg = <0>;
 309
 310                                 tfp410_in: endpoint {
 311                                         remote-endpoint = <&dpi1_out0>;
 312                                         pclk-sample = <1>;
 313                                 };
 314                         };
 315
 316                         port@1 {
 317                                 reg = <1>;
 318
 319                                 tfp410_out: endpoint {
 320                                         remote-endpoint = <&hdmi_connector_in>;
 321                                 };
 322                         };
 323                 };
 324         };
 325
 326         csi_mux: mux-controller {
 327                 compatible = "gpio-mux";
 328                 #mux-state-cells = <1>;
 329                 mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
 330                 idle-state = <0>;
 331         };
 332
 333         transceiver1: can-phy0 {
 334                 compatible = "ti,tcan1042";
 335                 #phy-cells = <0>;
 336                 max-bitrate = <5000000>;
 337         };
 338
 339         transceiver2: can-phy1 {
 340                 compatible = "ti,tcan1042";
 341                 #phy-cells = <0>;
 342                 max-bitrate = <5000000>;
 343         };
 344
 345         transceiver3: can-phy2 {
 346                 compatible = "ti,tcan1042";
 347                 #phy-cells = <0>;
 348                 max-bitrate = <5000000>;
 349         };
 350
 351         transceiver4: can-phy3 {
 352                 compatible = "ti,tcan1042";
 353                 #phy-cells = <0>;
 354                 max-bitrate = <5000000>;
 355         };
 356
 357 };
 358
 359 &main_pmx0 {
 360         bootph-all;
 361         main_uart8_pins_default: main-uart8-default-pins {
 362                 bootph-all;
 363                 pinctrl-single,pins = <
 364                         J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
 365                         J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
 366                 >;
 367         };
 368
 369         main_i2c0_pins_default: main-i2c0-default-pins {
 370                 pinctrl-single,pins = <
 371                         J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
 372                         J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
 373                 >;
 374         };
 375
 376         main_i2c1_pins_default: main-i2c1-default-pins {
 377                 pinctrl-single,pins = <
 378                         J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */
 379                         J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */
 380                 >;
 381         };
 382
 383         main_mmc1_pins_default: main-mmc1-default-pins {
 384                 bootph-all;
 385                 pinctrl-single,pins = <
 386                         J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
 387                         J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
 388                         J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
 389                         J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
 390                         J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
 391                         J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
 392                         J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
 393                         J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
 394                 >;
 395         };
 396
 397         vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
 398                 pinctrl-single,pins = <
 399                         J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
 400                 >;
 401         };
 402
 403         rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
 404                 pinctrl-single,pins = <
 405                         J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
 406                         J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
 407                         J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
 408                         J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
 409                         J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
 410                         J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
 411                         J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
 412                         J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
 413                         J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
 414                         J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
 415                         J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
 416                         J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
 417                         J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
 418                         J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
 419                 >;
 420         };
 421
 422         dp0_pins_default: dp0-default-pins {
 423                 pinctrl-single,pins = <
 424                         J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */
 425                 >;
 426         };
 427
 428         dp_pwr_en_pins_default: dp-pwr-en-default-pins {
 429                 pinctrl-single,pins = <
 430                         J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */
 431                 >;
 432         };
 433
 434         dss_vout0_pins_default: dss-vout0-default-pins {
 435                 pinctrl-single,pins = <
 436                         J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */
 437                         J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */
 438                         J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */
 439                         J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */
 440                         J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */
 441                         J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */
 442                         J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */
 443                         J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */
 444                         J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */
 445                         J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */
 446                         J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */
 447                         J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */
 448                         J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */
 449                         J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */
 450                         J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */
 451                         J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */
 452                         J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */
 453                         J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */
 454                         J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */
 455                         J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */
 456                         J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */
 457                         J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */
 458                         J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */
 459                         J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */
 460                         J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */
 461                         J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */
 462                         J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */
 463                         J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */
 464                 >;
 465         };
 466
 467         hdmi_hpd_pins_default: hdmi-hpd-default-pins {
 468                 pinctrl-single,pins = <
 469                         J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
 470                 >;
 471         };
 472
 473         main_mcan6_pins_default: main-mcan6-default-pins {
 474                 pinctrl-single,pins = <
 475                         J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */
 476                         J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */
 477                 >;
 478         };
 479
 480         main_mcan7_pins_default: main-mcan7-default-pins {
 481                 pinctrl-single,pins = <
 482                         J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
 483                         J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
 484                 >;
 485         };
 486
 487 };
 488
 489 &wkup_pmx0 {
 490         bootph-all;
 491         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
 492                 pinctrl-single,pins = <
 493                         J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
 494                         J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
 495                         J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
 496                         J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
 497                         J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
 498                         J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
 499                         J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
 500                         J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
 501                         J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
 502                         J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
 503                         J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
 504                 >;
 505         };
 506 };
 507
 508 &wkup_pmx2 {
 509         bootph-all;
 510         pmic_irq_pins_default: pmic-irq-default-pins {
 511                 pinctrl-single,pins = <
 512                         /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */
 513                         J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7)
 514                 >;
 515         };
 516
 517         wkup_uart0_pins_default: wkup-uart0-default-pins {
 518                 bootph-all;
 519                 pinctrl-single,pins = <
 520                         J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
 521                         J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
 522                         J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
 523                         J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
 524                 >;
 525         };
 526
 527         wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 528                 bootph-all;
 529                 pinctrl-single,pins = <
 530                         J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
 531                         J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
 532                 >;
 533         };
 534
 535         mcu_uart0_pins_default: mcu-uart0-default-pins {
 536                 bootph-all;
 537                 pinctrl-single,pins = <
 538                         J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
 539                         J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
 540                 >;
 541         };
 542
 543         mcu_i2c0_pins_default: mcu-i2c0-default-pins {
 544                 pinctrl-single,pins = <
 545                         J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */
 546                         J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */
 547                 >;
 548         };
 549
 550         mcu_cpsw_pins_default: mcu-cpsw-default-pins {
 551                 pinctrl-single,pins = <
 552                         J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
 553                         J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
 554                         J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
 555                         J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
 556                         J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
 557                         J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
 558                         J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
 559                         J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
 560                         J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
 561                         J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
 562                         J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
 563                         J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
 564                 >;
 565         };
 566
 567         mcu_mdio_pins_default: mcu-mdio-default-pins {
 568                 pinctrl-single,pins = <
 569                         J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
 570                         J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
 571                 >;
 572         };
 573
 574         mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
 575                 pinctrl-single,pins = <
 576                         J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */
 577                         J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */
 578                         J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
 579                         J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */
 580                         J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */
 581                         J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */
 582                         J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */
 583                         J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
 584                         J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
 585                 >;
 586         };
 587
 588         mcu_i2c1_pins_default: mcu-i2c1-default-pins {
 589                 pinctrl-single,pins = <
 590                         /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */
 591                         J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0)
 592                         /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */
 593                         J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0)
 594                 >;
 595         };
 596
 597         hdmi_pdn_pins_default: hdmi-pdn-default-pins {
 598                 pinctrl-single,pins = <
 599                         J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
 600                 >;
 601         };
 602
 603         mcu_mcan0_pins_default: mcu-mcan0-default-pins {
 604                 pinctrl-single,pins = <
 605                         J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */
 606                         J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */
 607                 >;
 608         };
 609
 610         mcu_mcan1_pins_default: mcu-mcan1-default-pins {
 611                 pinctrl-single,pins = <
 612                         J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */
 613                         J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */
 614                 >;
 615         };
 616
 617 };
 618
 619 &wkup_pmx3 {
 620         mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
 621                 pinctrl-single,pins = <
 622                         J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */
 623                 >;
 624         };
 625 };
 626
 627 &mailbox0_cluster0 {
 628         status = "okay";
 629         interrupts = <436>;
 630         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 631                 ti,mbox-rx = <0 0 0>;
 632                 ti,mbox-tx = <1 0 0>;
 633         };
 634
 635         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 636                 ti,mbox-rx = <2 0 0>;
 637                 ti,mbox-tx = <3 0 0>;
 638         };
 639 };
 640
 641 &mailbox0_cluster1 {
 642         status = "okay";
 643         interrupts = <432>;
 644         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 645                 ti,mbox-rx = <0 0 0>;
 646                 ti,mbox-tx = <1 0 0>;
 647         };
 648
 649         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 650                 ti,mbox-rx = <2 0 0>;
 651                 ti,mbox-tx = <3 0 0>;
 652         };
 653 };
 654
 655 &mailbox0_cluster2 {
 656         status = "okay";
 657         interrupts = <428>;
 658         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 659                 ti,mbox-rx = <0 0 0>;
 660                 ti,mbox-tx = <1 0 0>;
 661         };
 662
 663         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 664                 ti,mbox-rx = <2 0 0>;
 665                 ti,mbox-tx = <3 0 0>;
 666         };
 667 };
 668
 669 &mailbox0_cluster3 {
 670         status = "okay";
 671         interrupts = <424>;
 672         mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
 673                 ti,mbox-rx = <0 0 0>;
 674                 ti,mbox-tx = <1 0 0>;
 675         };
 676
 677         mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
 678                 ti,mbox-rx = <2 0 0>;
 679                 ti,mbox-tx = <3 0 0>;
 680         };
 681 };
 682
 683 &mailbox0_cluster4 {
 684         status = "okay";
 685         interrupts = <420>;
 686         mbox_c71_0: mbox-c71-0 {
 687                 ti,mbox-rx = <0 0 0>;
 688                 ti,mbox-tx = <1 0 0>;
 689         };
 690
 691         mbox_c71_1: mbox-c71-1 {
 692                 ti,mbox-rx = <2 0 0>;
 693                 ti,mbox-tx = <3 0 0>;
 694         };
 695 };
 696
 697 &mailbox0_cluster5 {
 698         status = "okay";
 699         interrupts = <416>;
 700         mbox_c71_2: mbox-c71-2 {
 701                 ti,mbox-rx = <0 0 0>;
 702                 ti,mbox-tx = <1 0 0>;
 703         };
 704
 705         mbox_c71_3: mbox-c71-3 {
 706                 ti,mbox-rx = <2 0 0>;
 707                 ti,mbox-tx = <3 0 0>;
 708         };
 709 };
 710
 711 &wkup_uart0 {
 712         /* Firmware usage */
 713         status = "reserved";
 714         pinctrl-names = "default";
 715         pinctrl-0 = <&wkup_uart0_pins_default>;
 716 };
 717
 718 &wkup_i2c0 {
 719         bootph-all;
 720         status = "okay";
 721         pinctrl-names = "default";
 722         pinctrl-0 = <&wkup_i2c0_pins_default>;
 723         clock-frequency = <400000>;
 724
 725         eeprom@51 {
 726                 /* AT24C512C-MAHM-T */
 727                 compatible = "atmel,24c512";
 728                 reg = <0x51>;
 729         };
 730
 731         tps659413: pmic@48 {
 732                 compatible = "ti,tps6594-q1";
 733                 reg = <0x48>;
 734                 system-power-controller;
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&pmic_irq_pins_default>;
 737                 interrupt-parent = <&wkup_gpio0>;
 738                 interrupts = <83 IRQ_TYPE_EDGE_FALLING>;
 739                 gpio-controller;
 740                 #gpio-cells = <2>;
 741                 ti,primary-pmic;
 742                 buck12-supply = <&vsys_3v3>;
 743                 buck3-supply = <&vsys_3v3>;
 744                 buck4-supply = <&vsys_3v3>;
 745                 buck5-supply = <&vsys_3v3>;
 746                 ldo1-supply = <&vsys_3v3>;
 747                 ldo2-supply = <&vsys_3v3>;
 748                 ldo3-supply = <&vsys_3v3>;
 749                 ldo4-supply = <&vsys_3v3>;
 750
 751                 regulators {
 752                         bucka12: buck12 {
 753                                 regulator-name = "vdd_ddr_1v1";
 754                                 regulator-min-microvolt = <1100000>;
 755                                 regulator-max-microvolt = <1100000>;
 756                                 regulator-boot-on;
 757                                 regulator-always-on;
 758                         };
 759
 760                         bucka3: buck3 {
 761                                 regulator-name = "vdd_ram_0v85";
 762                                 regulator-min-microvolt = <850000>;
 763                                 regulator-max-microvolt = <850000>;
 764                                 regulator-boot-on;
 765                                 regulator-always-on;
 766                         };
 767
 768                         bucka4: buck4 {
 769                                 regulator-name = "vdd_io_1v8";
 770                                 regulator-min-microvolt = <1800000>;
 771                                 regulator-max-microvolt = <1800000>;
 772                                 regulator-boot-on;
 773                                 regulator-always-on;
 774                         };
 775
 776                         bucka5: buck5 {
 777                                 regulator-name = "vdd_mcu_0v85";
 778                                 regulator-min-microvolt = <850000>;
 779                                 regulator-max-microvolt = <850000>;
 780                                 regulator-boot-on;
 781                                 regulator-always-on;
 782                         };
 783
 784                         ldoa1: ldo1 {
 785                                 regulator-name = "vdd_mcuio_1v8";
 786                                 regulator-min-microvolt = <1800000>;
 787                                 regulator-max-microvolt = <1800000>;
 788                                 regulator-boot-on;
 789                                 regulator-always-on;
 790                         };
 791
 792                         ldoa2: ldo2 {
 793                                 regulator-name = "vdd_mcuio_3v3";
 794                                 regulator-min-microvolt = <3300000>;
 795                                 regulator-max-microvolt = <3300000>;
 796                                 regulator-boot-on;
 797                                 regulator-always-on;
 798                         };
 799
 800                         ldoa3: ldo3 {
 801                                 regulator-name = "vds_dll_0v8";
 802                                 regulator-min-microvolt = <800000>;
 803                                 regulator-max-microvolt = <800000>;
 804                                 regulator-boot-on;
 805                                 regulator-always-on;
 806                         };
 807
 808                         ldoa4: ldo4 {
 809                                 regulator-name = "vda_mcu_1v8";
 810                                 regulator-min-microvolt = <1800000>;
 811                                 regulator-max-microvolt = <1800000>;
 812                                 regulator-boot-on;
 813                                 regulator-always-on;
 814                         };
 815                 };
 816         };
 817 };
 818
 819 &wkup_gpio0 {
 820         status = "okay";
 821         pinctrl-names = "default";
 822         pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
 823 };
 824
 825 &mcu_uart0 {
 826         bootph-all;
 827         status = "okay";
 828         pinctrl-names = "default";
 829         pinctrl-0 = <&mcu_uart0_pins_default>;
 830 };
 831
 832 &mcu_i2c0 {
 833         status = "okay";
 834         pinctrl-names = "default";
 835         pinctrl-0 = <&mcu_i2c0_pins_default>;
 836         clock-frequency = <400000>;
 837 };
 838
 839 &main_uart8 {
 840         bootph-all;
 841         status = "okay";
 842         pinctrl-names = "default";
 843         pinctrl-0 = <&main_uart8_pins_default>;
 844 };
 845
 846 &main_i2c0 {
 847         status = "okay";
 848         pinctrl-names = "default";
 849         pinctrl-0 = <&main_i2c0_pins_default>;
 850         clock-frequency = <400000>;
 851
 852         exp1: gpio@21 {
 853                 compatible = "ti,tca6416";
 854                 reg = <0x21>;
 855                 gpio-controller;
 856                 #gpio-cells = <2>;
 857                 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
 858                                 "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#",
 859                                 "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz",
 860                                 "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz",
 861                                 "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#",
 862                                 "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2";
 863         };
 864 };
 865
 866 &main_i2c1 {
 867         pinctrl-names = "default";
 868         pinctrl-0 = <&main_i2c1_pins_default>;
 869         clock-frequency = <400000>;
 870         status = "okay";
 871
 872         exp2: gpio@21 {
 873                 compatible = "ti,tca6408";
 874                 reg = <0x21>;
 875                 gpio-controller;
 876                 #gpio-cells = <2>;
 877                 gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz",
 878                                   "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1";
 879         };
 880
 881         i2c-mux@70 {
 882                 compatible = "nxp,pca9543";
 883                 #address-cells = <1>;
 884                 #size-cells = <0>;
 885                 reg = <0x70>;
 886
 887                 cam0_i2c: i2c@0 {
 888                         #address-cells = <1>;
 889                         #size-cells = <0>;
 890                         reg = <0>;
 891                 };
 892
 893                 cam1_i2c: i2c@1 {
 894                         #address-cells = <1>;
 895                         #size-cells = <0>;
 896                         reg = <1>;
 897                 };
 898
 899         };
 900 };
 901
 902 &main_sdhci0 {
 903         bootph-all;
 904         /* eMMC */
 905         status = "okay";
 906         non-removable;
 907         ti,driver-strength-ohm = <50>;
 908         disable-wp;
 909 };
 910
 911 &main_sdhci1 {
 912         bootph-all;
 913         /* SD card */
 914         status = "okay";
 915         pinctrl-0 = <&main_mmc1_pins_default>;
 916         pinctrl-names = "default";
 917         disable-wp;
 918         vmmc-supply = <&vdd_mmc1>;
 919         vqmmc-supply = <&vdd_sd_dv>;
 920 };
 921
 922 &main_gpio0 {
 923         status = "okay";
 924         pinctrl-names = "default";
 925         pinctrl-0 = <&rpi_header_gpio0_pins_default>;
 926 };
 927
 928 &mcu_cpsw {
 929         status = "okay";
 930         pinctrl-names = "default";
 931         pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 932 };
 933
 934 &davinci_mdio {
 935         mcu_phy0: ethernet-phy@0 {
 936                 reg = <0>;
 937                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 938                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 939                 ti,min-output-impedance;
 940         };
 941 };
 942
 943 &mcu_cpsw_port1 {
 944         status = "okay";
 945         phy-mode = "rgmii-rxid";
 946         phy-handle = <&mcu_phy0>;
 947 };
 948
 949 &mcu_r5fss0_core0 {
 950         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 951         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 952                         <&mcu_r5fss0_core0_memory_region>;
 953 };
 954
 955 &mcu_r5fss0_core1 {
 956         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
 957         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 958                         <&mcu_r5fss0_core1_memory_region>;
 959 };
 960
 961 &main_r5fss0_core0 {
 962         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
 963         memory-region = <&main_r5fss0_core0_dma_memory_region>,
 964                         <&main_r5fss0_core0_memory_region>;
 965 };
 966
 967 &main_r5fss0_core1 {
 968         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
 969         memory-region = <&main_r5fss0_core1_dma_memory_region>,
 970                         <&main_r5fss0_core1_memory_region>;
 971 };
 972
 973 &main_r5fss1_core0 {
 974         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
 975         memory-region = <&main_r5fss1_core0_dma_memory_region>,
 976                         <&main_r5fss1_core0_memory_region>;
 977 };
 978
 979 &main_r5fss1_core1 {
 980         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
 981         memory-region = <&main_r5fss1_core1_dma_memory_region>,
 982                         <&main_r5fss1_core1_memory_region>;
 983 };
 984
 985 &main_r5fss2_core0 {
 986         mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
 987         memory-region = <&main_r5fss2_core0_dma_memory_region>,
 988                         <&main_r5fss2_core0_memory_region>;
 989 };
 990
 991 &main_r5fss2_core1 {
 992         mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
 993         memory-region = <&main_r5fss2_core1_dma_memory_region>,
 994                         <&main_r5fss2_core1_memory_region>;
 995 };
 996
 997 &c71_0 {
 998         status = "okay";
 999         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
1000         memory-region = <&c71_0_dma_memory_region>,
1001                         <&c71_0_memory_region>;
1002 };
1003
1004 &c71_1 {
1005         status = "okay";
1006         mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
1007         memory-region = <&c71_1_dma_memory_region>,
1008                         <&c71_1_memory_region>;
1009 };
1010
1011 &c71_2 {
1012         status = "okay";
1013         mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
1014         memory-region = <&c71_2_dma_memory_region>,
1015                         <&c71_2_memory_region>;
1016 };
1017
1018 &c71_3 {
1019         status = "okay";
1020         mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
1021         memory-region = <&c71_3_dma_memory_region>,
1022                         <&c71_3_memory_region>;
1023 };
1024
1025 &wkup_gpio_intr {
1026         status = "okay";
1027 };
1028
1029 &mcu_i2c1 {
1030         status = "okay";
1031         pinctrl-names = "default";
1032         pinctrl-0 = <&mcu_i2c1_pins_default>;
1033         clock-frequency = <100000>;
1034 };
1035
1036 &serdes_refclk {
1037         status = "okay";
1038         clock-frequency = <100000000>;
1039 };
1040
1041 &dss {
1042         status = "okay";
1043         pinctrl-names = "default";
1044         pinctrl-0 = <&dss_vout0_pins_default>;
1045         assigned-clocks = <&k3_clks 218 2>,
1046                           <&k3_clks 218 5>;
1047         assigned-clock-parents = <&k3_clks 218 3>,
1048                                  <&k3_clks 218 7>;
1049 };
1050
1051 &serdes_wiz4 {
1052         status = "okay";
1053 };
1054
1055 &serdes4 {
1056         status = "okay";
1057         serdes4_dp_link: phy@0 {
1058                 reg = <0>;
1059                 cdns,num-lanes = <4>;
1060                 #phy-cells = <0>;
1061                 cdns,phy-type = <PHY_TYPE_DP>;
1062                 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
1063                          <&serdes_wiz4 3>, <&serdes_wiz4 4>;
1064         };
1065 };
1066
1067 &mhdp {
1068         status = "okay";
1069         pinctrl-names = "default";
1070         pinctrl-0 = <&dp0_pins_default>;
1071         phys = <&serdes4_dp_link>;
1072         phy-names = "dpphy";
1073 };
1074
1075 &dss_ports {
1076         #address-cells = <1>;
1077         #size-cells = <0>;
1078
1079         /* DP */
1080         port@0 {
1081                 reg = <0>;
1082
1083                 dpi0_out: endpoint {
1084                         remote-endpoint = <&dp0_in>;
1085                 };
1086         };
1087
1088         /* HDMI */
1089         port@1 {
1090                 reg = <1>;
1091
1092                 dpi1_out0: endpoint {
1093                         remote-endpoint = <&tfp410_in>;
1094                 };
1095         };
1096 };
1097
1098 &dp0_ports {
1099
1100         port@0 {
1101                 reg = <0>;
1102
1103                 dp0_in: endpoint {
1104                         remote-endpoint = <&dpi0_out>;
1105                 };
1106         };
1107
1108         port@4 {
1109                 reg = <4>;
1110
1111                 dp0_out: endpoint {
1112                         remote-endpoint = <&dp0_connector_in>;
1113                 };
1114         };
1115 };
1116
1117 &mcu_mcan0 {
1118         status = "okay";
1119         pinctrl-names = "default";
1120         pinctrl-0 = <&mcu_mcan0_pins_default>;
1121         phys = <&transceiver1>;
1122 };
1123
1124 &mcu_mcan1 {
1125         status = "okay";
1126         pinctrl-names = "default";
1127         pinctrl-0 = <&mcu_mcan1_pins_default>;
1128         phys = <&transceiver2>;
1129 };
1130
1131 &main_mcan6 {
1132         status = "okay";
1133         pinctrl-names = "default";
1134         pinctrl-0 = <&main_mcan6_pins_default>;
1135         phys = <&transceiver3>;
1136 };
1137
1138 &main_mcan7 {
1139         status = "okay";
1140         pinctrl-names = "default";
1141         pinctrl-0 = <&main_mcan7_pins_default>;
1142         phys = <&transceiver4>;
1143 };
1144
1145 &ospi0 {
1146         status = "okay";
1147         pinctrl-names = "default";
1148         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
1149
1150         flash@0 {
1151                 compatible = "jedec,spi-nor";
1152                 reg = <0x0>;
1153                 spi-tx-bus-width = <8>;
1154                 spi-rx-bus-width = <8>;
1155                 spi-max-frequency = <25000000>;
1156                 cdns,tshsl-ns = <60>;
1157                 cdns,tsd2d-ns = <60>;
1158                 cdns,tchsh-ns = <60>;
1159                 cdns,tslch-ns = <60>;
1160                 cdns,read-delay = <4>;
1161
1162                 partitions {
1163                         bootph-all;
1164                         compatible = "fixed-partitions";
1165                         #address-cells = <1>;
1166                         #size-cells = <1>;
1167
1168                         partition@0 {
1169                                 label = "ospi.tiboot3";
1170                                 reg = <0x0 0x100000>;
1171                         };
1172
1173                         partition@100000 {
1174                                 label = "ospi.tispl";
1175                                 reg = <0x100000 0x200000>;
1176                         };
1177
1178                         partition@300000 {
1179                                 label = "ospi.u-boot";
1180                                 reg = <0x300000 0x400000>;
1181                         };
1182
1183                         partition@700000 {
1184                                 label = "ospi.env";
1185                                 reg = <0x700000 0x40000>;
1186                         };
1187
1188                         partition@740000 {
1189                                 label = "ospi.env.backup";
1190                                 reg = <0x740000 0x40000>;
1191                         };
1192
1193                         partition@800000 {
1194                                 label = "ospi.rootfs";
1195                                 reg = <0x800000 0x37c0000>;
1196                         };
1197
1198                         partition@3fc0000 {
1199                                 bootph-pre-ram;
1200                                 label = "ospi.phypattern";
1201                                 reg = <0x3fc0000 0x40000>;
1202                         };
1203                 };
1204         };
1205 };