arch/arm64/boot/dts/ti/k3-am69-sk.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
   4  *
   5  * Design Files: https://www.ti.com/lit/zip/SPRR466
   6  * TRM: https://www.ti.com/lit/zip/spruj52
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include "k3-j784s4.dtsi"
  14
  15 / {
  16         compatible = "ti,am69-sk", "ti,j784s4";
  17         model = "Texas Instruments AM69 SK";
  18
  19         chosen {
  20                 stdout-path = "serial2:115200n8";
  21         };
  22
  23         aliases {
  24                 serial0 = &wkup_uart0;
  25                 serial1 = &mcu_uart0;
  26                 serial2 = &main_uart8;
  27                 mmc0 = &main_sdhci0;
  28                 mmc1 = &main_sdhci1;
  29                 i2c0 = &wkup_i2c0;
  30                 i2c3 = &main_i2c0;
  31                 ethernet0 = &mcu_cpsw_port1;
  32         };
  33
  34         memory@80000000 {
  35                 device_type = "memory";
  36                 /* 32G RAM */
  37                 reg = <0x00 0x80000000 0x00 0x80000000>,
  38                       <0x08 0x80000000 0x07 0x80000000>;
  39         };
  40
  41         reserved_memory: reserved-memory {
  42                 #address-cells = <2>;
  43                 #size-cells = <2>;
  44                 ranges;
  45
  46                 secure_ddr: optee@9e800000 {
  47                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  48                         no-map;
  49                 };
  50
  51                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  52                         compatible = "shared-dma-pool";
  53                         reg = <0x00 0xa0000000 0x00 0x100000>;
  54                         no-map;
  55                 };
  56
  57                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  58                         compatible = "shared-dma-pool";
  59                         reg = <0x00 0xa0100000 0x00 0xf00000>;
  60                         no-map;
  61                 };
  62
  63                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  64                         compatible = "shared-dma-pool";
  65                         reg = <0x00 0xa1000000 0x00 0x100000>;
  66                         no-map;
  67                 };
  68
  69                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  70                         compatible = "shared-dma-pool";
  71                         reg = <0x00 0xa1100000 0x00 0xf00000>;
  72                         no-map;
  73                 };
  74
  75                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
  76                         compatible = "shared-dma-pool";
  77                         reg = <0x00 0xa2000000 0x00 0x100000>;
  78                         no-map;
  79                 };
  80
  81                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
  82                         compatible = "shared-dma-pool";
  83                         reg = <0x00 0xa2100000 0x00 0xf00000>;
  84                         no-map;
  85                 };
  86
  87                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
  88                         compatible = "shared-dma-pool";
  89                         reg = <0x00 0xa3000000 0x00 0x100000>;
  90                         no-map;
  91                 };
  92
  93                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
  94                         compatible = "shared-dma-pool";
  95                         reg = <0x00 0xa3100000 0x00 0xf00000>;
  96                         no-map;
  97                 };
  98
  99                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
 100                         compatible = "shared-dma-pool";
 101                         reg = <0x00 0xa4000000 0x00 0x100000>;
 102                         no-map;
 103                 };
 104
 105                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
 106                         compatible = "shared-dma-pool";
 107                         reg = <0x00 0xa4100000 0x00 0xf00000>;
 108                         no-map;
 109                 };
 110
 111                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
 112                         compatible = "shared-dma-pool";
 113                         reg = <0x00 0xa5000000 0x00 0x100000>;
 114                         no-map;
 115                 };
 116
 117                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
 118                         compatible = "shared-dma-pool";
 119                         reg = <0x00 0xa5100000 0x00 0xf00000>;
 120                         no-map;
 121                 };
 122
 123                 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
 124                         compatible = "shared-dma-pool";
 125                         reg = <0x00 0xa6000000 0x00 0x100000>;
 126                         no-map;
 127                 };
 128
 129                 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
 130                         compatible = "shared-dma-pool";
 131                         reg = <0x00 0xa6100000 0x00 0xf00000>;
 132                         no-map;
 133                 };
 134
 135                 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
 136                         compatible = "shared-dma-pool";
 137                         reg = <0x00 0xa7000000 0x00 0x100000>;
 138                         no-map;
 139                 };
 140
 141                 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
 142                         compatible = "shared-dma-pool";
 143                         reg = <0x00 0xa7100000 0x00 0xf00000>;
 144                         no-map;
 145                 };
 146
 147                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
 148                         compatible = "shared-dma-pool";
 149                         reg = <0x00 0xa8000000 0x00 0x100000>;
 150                         no-map;
 151                 };
 152
 153                 c71_0_memory_region: c71-memory@a8100000 {
 154                         compatible = "shared-dma-pool";
 155                         reg = <0x00 0xa8100000 0x00 0xf00000>;
 156                         no-map;
 157                 };
 158
 159                 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
 160                         compatible = "shared-dma-pool";
 161                         reg = <0x00 0xa9000000 0x00 0x100000>;
 162                         no-map;
 163                 };
 164
 165                 c71_1_memory_region: c71-memory@a9100000 {
 166                         compatible = "shared-dma-pool";
 167                         reg = <0x00 0xa9100000 0x00 0xf00000>;
 168                         no-map;
 169                 };
 170
 171                 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
 172                         compatible = "shared-dma-pool";
 173                         reg = <0x00 0xaa000000 0x00 0x100000>;
 174                         no-map;
 175                 };
 176
 177                 c71_2_memory_region: c71-memory@aa100000 {
 178                         compatible = "shared-dma-pool";
 179                         reg = <0x00 0xaa100000 0x00 0xf00000>;
 180                         no-map;
 181                 };
 182
 183                 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
 184                         compatible = "shared-dma-pool";
 185                         reg = <0x00 0xab000000 0x00 0x100000>;
 186                         no-map;
 187                 };
 188
 189                 c71_3_memory_region: c71-memory@ab100000 {
 190                         compatible = "shared-dma-pool";
 191                         reg = <0x00 0xab100000 0x00 0xf00000>;
 192                         no-map;
 193                 };
 194         };
 195
 196         vusb_main: regulator-vusb-main5v0 {
 197                 /* USB MAIN INPUT 5V DC */
 198                 compatible = "regulator-fixed";
 199                 regulator-name = "vusb-main5v0";
 200                 regulator-min-microvolt = <5000000>;
 201                 regulator-max-microvolt = <5000000>;
 202                 regulator-always-on;
 203                 regulator-boot-on;
 204         };
 205
 206         vsys_5v0: regulator-vsys5v0 {
 207                 /* Output of LM61460 */
 208                 compatible = "regulator-fixed";
 209                 regulator-name = "vsys_5v0";
 210                 regulator-min-microvolt = <5000000>;
 211                 regulator-max-microvolt = <5000000>;
 212                 vin-supply = <&vusb_main>;
 213                 regulator-always-on;
 214                 regulator-boot-on;
 215         };
 216
 217         vsys_3v3: regulator-vsys3v3 {
 218                 /* Output of LM5143 */
 219                 compatible = "regulator-fixed";
 220                 regulator-name = "vsys_3v3";
 221                 regulator-min-microvolt = <3300000>;
 222                 regulator-max-microvolt = <3300000>;
 223                 vin-supply = <&vusb_main>;
 224                 regulator-always-on;
 225                 regulator-boot-on;
 226         };
 227
 228         vdd_mmc1: regulator-sd {
 229                 /* Output of TPS22918 */
 230                 compatible = "regulator-fixed";
 231                 regulator-name = "vdd_mmc1";
 232                 regulator-min-microvolt = <3300000>;
 233                 regulator-max-microvolt = <3300000>;
 234                 regulator-boot-on;
 235                 enable-active-high;
 236                 vin-supply = <&vsys_3v3>;
 237                 gpio = <&exp1 2 GPIO_ACTIVE_HIGH>;
 238         };
 239
 240         vdd_sd_dv: regulator-tlv71033 {
 241                 /* Output of TLV71033 */
 242                 compatible = "regulator-gpio";
 243                 regulator-name = "tlv71033";
 244                 pinctrl-names = "default";
 245                 pinctrl-0 = <&vdd_sd_dv_pins_default>;
 246                 regulator-min-microvolt = <1800000>;
 247                 regulator-max-microvolt = <3300000>;
 248                 regulator-boot-on;
 249                 vin-supply = <&vsys_5v0>;
 250                 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
 251                 states = <1800000 0x0>,
 252                          <3300000 0x1>;
 253         };
 254
 255         dp0_pwr_3v3: regulator-dp0-pwr {
 256                 compatible = "regulator-fixed";
 257                 regulator-name = "dp0-pwr";
 258                 regulator-min-microvolt = <3300000>;
 259                 regulator-max-microvolt = <3300000>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&dp_pwr_en_pins_default>;
 262                 gpio = <&main_gpio0 4 0>;       /* DP0_3V3 _EN */
 263                 enable-active-high;
 264         };
 265
 266         dp0: connector-dp0 {
 267                 compatible = "dp-connector";
 268                 label = "DP0";
 269                 type = "full-size";
 270                 dp-pwr-supply = <&dp0_pwr_3v3>;
 271
 272                 port {
 273                         dp0_connector_in: endpoint {
 274                                 remote-endpoint = <&dp0_out>;
 275                         };
 276                 };
 277         };
 278
 279         connector-hdmi {
 280                 compatible = "hdmi-connector";
 281                 label = "hdmi";
 282                 type = "a";
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&hdmi_hpd_pins_default>;
 285                 ddc-i2c-bus = <&mcu_i2c1>;
 286                 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;   /* HDMI_HPD */
 287
 288                 port {
 289                         hdmi_connector_in: endpoint {
 290                                 remote-endpoint = <&tfp410_out>;
 291                         };
 292                 };
 293         };
 294
 295         bridge-dvi {
 296                 compatible = "ti,tfp410";
 297                 pinctrl-names = "default";
 298                 pinctrl-0 = <&hdmi_pdn_pins_default>;
 299                 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>;     /* HDMI_PDn */
 300                 ti,deskew = <0>;
 301
 302                 ports {
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305
 306                         port@0 {
 307                                 reg = <0>;
 308
 309                                 tfp410_in: endpoint {
 310                                         remote-endpoint = <&dpi1_out0>;
 311                                         pclk-sample = <1>;
 312                                 };
 313                         };
 314
 315                         port@1 {
 316                                 reg = <1>;
 317
 318                                 tfp410_out: endpoint {
 319                                         remote-endpoint = <&hdmi_connector_in>;
 320                                 };
 321                         };
 322                 };
 323         };
 324 };
 325
 326 &main_pmx0 {
 327         bootph-all;
 328         main_uart8_pins_default: main-uart8-default-pins {
 329                 bootph-all;
 330                 pinctrl-single,pins = <
 331                         J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
 332                         J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
 333                 >;
 334         };
 335
 336         main_i2c0_pins_default: main-i2c0-default-pins {
 337                 pinctrl-single,pins = <
 338                         J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
 339                         J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
 340                 >;
 341         };
 342
 343         main_mmc1_pins_default: main-mmc1-default-pins {
 344                 bootph-all;
 345                 pinctrl-single,pins = <
 346                         J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
 347                         J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
 348                         J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
 349                         J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
 350                         J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
 351                         J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
 352                         J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
 353                         J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
 354                 >;
 355         };
 356
 357         vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
 358                 pinctrl-single,pins = <
 359                         J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
 360                 >;
 361         };
 362
 363         rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
 364                 pinctrl-single,pins = <
 365                         J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
 366                         J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
 367                         J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
 368                         J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
 369                         J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
 370                         J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
 371                         J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
 372                         J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
 373                         J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
 374                         J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
 375                         J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
 376                         J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
 377                         J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
 378                         J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
 379                 >;
 380         };
 381
 382         dp0_pins_default: dp0-default-pins {
 383                 pinctrl-single,pins = <
 384                         J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */
 385                 >;
 386         };
 387
 388         dp_pwr_en_pins_default: dp-pwr-en-default-pins {
 389                 pinctrl-single,pins = <
 390                         J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */
 391                 >;
 392         };
 393
 394         dss_vout0_pins_default: dss-vout0-default-pins {
 395                 pinctrl-single,pins = <
 396                         J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */
 397                         J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */
 398                         J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */
 399                         J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */
 400                         J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */
 401                         J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */
 402                         J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */
 403                         J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */
 404                         J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */
 405                         J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */
 406                         J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */
 407                         J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */
 408                         J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */
 409                         J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */
 410                         J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */
 411                         J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */
 412                         J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */
 413                         J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */
 414                         J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */
 415                         J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */
 416                         J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */
 417                         J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */
 418                         J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */
 419                         J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */
 420                         J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */
 421                         J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */
 422                         J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */
 423                         J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */
 424                 >;
 425         };
 426
 427         hdmi_hpd_pins_default: hdmi-hpd-default-pins {
 428                 pinctrl-single,pins = <
 429                         J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
 430                 >;
 431         };
 432 };
 433
 434 &wkup_pmx2 {
 435         bootph-all;
 436         pmic_irq_pins_default: pmic-irq-default-pins {
 437                 pinctrl-single,pins = <
 438                         /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */
 439                         J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7)
 440                 >;
 441         };
 442
 443         wkup_uart0_pins_default: wkup-uart0-default-pins {
 444                 bootph-all;
 445                 pinctrl-single,pins = <
 446                         J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
 447                         J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
 448                         J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
 449                         J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
 450                 >;
 451         };
 452
 453         wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 454                 bootph-all;
 455                 pinctrl-single,pins = <
 456                         J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
 457                         J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
 458                 >;
 459         };
 460
 461         mcu_uart0_pins_default: mcu-uart0-default-pins {
 462                 bootph-all;
 463                 pinctrl-single,pins = <
 464                         J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
 465                         J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
 466                 >;
 467         };
 468
 469         mcu_i2c0_pins_default: mcu-i2c0-default-pins {
 470                 pinctrl-single,pins = <
 471                         J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */
 472                         J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */
 473                 >;
 474         };
 475
 476         mcu_cpsw_pins_default: mcu-cpsw-default-pins {
 477                 pinctrl-single,pins = <
 478                         J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
 479                         J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
 480                         J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
 481                         J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
 482                         J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
 483                         J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
 484                         J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
 485                         J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
 486                         J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
 487                         J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
 488                         J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
 489                         J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
 490                 >;
 491         };
 492
 493         mcu_mdio_pins_default: mcu-mdio-default-pins {
 494                 pinctrl-single,pins = <
 495                         J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
 496                         J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
 497                 >;
 498         };
 499
 500         mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
 501                 pinctrl-single,pins = <
 502                         J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */
 503                         J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */
 504                         J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
 505                         J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */
 506                         J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */
 507                         J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */
 508                         J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */
 509                         J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
 510                         J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
 511                 >;
 512         };
 513
 514         mcu_i2c1_pins_default: mcu-i2c1-default-pins {
 515                 pinctrl-single,pins = <
 516                         /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */
 517                         J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0)
 518                         /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */
 519                         J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0)
 520                 >;
 521         };
 522
 523         hdmi_pdn_pins_default: hdmi-pdn-default-pins {
 524                 pinctrl-single,pins = <
 525                         J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
 526                 >;
 527         };
 528 };
 529
 530 &wkup_pmx3 {
 531         mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
 532                 pinctrl-single,pins = <
 533                         J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */
 534                 >;
 535         };
 536 };
 537
 538 &mailbox0_cluster0 {
 539         status = "okay";
 540         interrupts = <436>;
 541         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 542                 ti,mbox-rx = <0 0 0>;
 543                 ti,mbox-tx = <1 0 0>;
 544         };
 545
 546         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 547                 ti,mbox-rx = <2 0 0>;
 548                 ti,mbox-tx = <3 0 0>;
 549         };
 550 };
 551
 552 &mailbox0_cluster1 {
 553         status = "okay";
 554         interrupts = <432>;
 555         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 556                 ti,mbox-rx = <0 0 0>;
 557                 ti,mbox-tx = <1 0 0>;
 558         };
 559
 560         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 561                 ti,mbox-rx = <2 0 0>;
 562                 ti,mbox-tx = <3 0 0>;
 563         };
 564 };
 565
 566 &mailbox0_cluster2 {
 567         status = "okay";
 568         interrupts = <428>;
 569         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 570                 ti,mbox-rx = <0 0 0>;
 571                 ti,mbox-tx = <1 0 0>;
 572         };
 573
 574         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 575                 ti,mbox-rx = <2 0 0>;
 576                 ti,mbox-tx = <3 0 0>;
 577         };
 578 };
 579
 580 &mailbox0_cluster3 {
 581         status = "okay";
 582         interrupts = <424>;
 583         mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
 584                 ti,mbox-rx = <0 0 0>;
 585                 ti,mbox-tx = <1 0 0>;
 586         };
 587
 588         mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
 589                 ti,mbox-rx = <2 0 0>;
 590                 ti,mbox-tx = <3 0 0>;
 591         };
 592 };
 593
 594 &mailbox0_cluster4 {
 595         status = "okay";
 596         interrupts = <420>;
 597         mbox_c71_0: mbox-c71-0 {
 598                 ti,mbox-rx = <0 0 0>;
 599                 ti,mbox-tx = <1 0 0>;
 600         };
 601
 602         mbox_c71_1: mbox-c71-1 {
 603                 ti,mbox-rx = <2 0 0>;
 604                 ti,mbox-tx = <3 0 0>;
 605         };
 606 };
 607
 608 &mailbox0_cluster5 {
 609         status = "okay";
 610         interrupts = <416>;
 611         mbox_c71_2: mbox-c71-2 {
 612                 ti,mbox-rx = <0 0 0>;
 613                 ti,mbox-tx = <1 0 0>;
 614         };
 615
 616         mbox_c71_3: mbox-c71-3 {
 617                 ti,mbox-rx = <2 0 0>;
 618                 ti,mbox-tx = <3 0 0>;
 619         };
 620 };
 621
 622 &wkup_uart0 {
 623         /* Firmware usage */
 624         status = "reserved";
 625         pinctrl-names = "default";
 626         pinctrl-0 = <&wkup_uart0_pins_default>;
 627 };
 628
 629 &wkup_i2c0 {
 630         bootph-all;
 631         status = "okay";
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&wkup_i2c0_pins_default>;
 634         clock-frequency = <400000>;
 635
 636         eeprom@51 {
 637                 /* AT24C512C-MAHM-T */
 638                 compatible = "atmel,24c512";
 639                 reg = <0x51>;
 640         };
 641
 642         tps659413: pmic@48 {
 643                 compatible = "ti,tps6594-q1";
 644                 reg = <0x48>;
 645                 system-power-controller;
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&pmic_irq_pins_default>;
 648                 interrupt-parent = <&wkup_gpio0>;
 649                 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
 650                 gpio-controller;
 651                 #gpio-cells = <2>;
 652                 ti,primary-pmic;
 653                 buck12-supply = <&vsys_3v3>;
 654                 buck3-supply = <&vsys_3v3>;
 655                 buck4-supply = <&vsys_3v3>;
 656                 buck5-supply = <&vsys_3v3>;
 657                 ldo1-supply = <&vsys_3v3>;
 658                 ldo2-supply = <&vsys_3v3>;
 659                 ldo3-supply = <&vsys_3v3>;
 660                 ldo4-supply = <&vsys_3v3>;
 661
 662                 regulators {
 663                         bucka12: buck12 {
 664                                 regulator-name = "vdd_ddr_1v1";
 665                                 regulator-min-microvolt = <1100000>;
 666                                 regulator-max-microvolt = <1100000>;
 667                                 regulator-boot-on;
 668                                 regulator-always-on;
 669                         };
 670
 671                         bucka3: buck3 {
 672                                 regulator-name = "vdd_ram_0v85";
 673                                 regulator-min-microvolt = <850000>;
 674                                 regulator-max-microvolt = <850000>;
 675                                 regulator-boot-on;
 676                                 regulator-always-on;
 677                         };
 678
 679                         bucka4: buck4 {
 680                                 regulator-name = "vdd_io_1v8";
 681                                 regulator-min-microvolt = <1800000>;
 682                                 regulator-max-microvolt = <1800000>;
 683                                 regulator-boot-on;
 684                                 regulator-always-on;
 685                         };
 686
 687                         bucka5: buck5 {
 688                                 regulator-name = "vdd_mcu_0v85";
 689                                 regulator-min-microvolt = <850000>;
 690                                 regulator-max-microvolt = <850000>;
 691                                 regulator-boot-on;
 692                                 regulator-always-on;
 693                         };
 694
 695                         ldoa1: ldo1 {
 696                                 regulator-name = "vdd_mcuio_1v8";
 697                                 regulator-min-microvolt = <1800000>;
 698                                 regulator-max-microvolt = <1800000>;
 699                                 regulator-boot-on;
 700                                 regulator-always-on;
 701                         };
 702
 703                         ldoa2: ldo2 {
 704                                 regulator-name = "vdd_mcuio_3v3";
 705                                 regulator-min-microvolt = <3300000>;
 706                                 regulator-max-microvolt = <3300000>;
 707                                 regulator-boot-on;
 708                                 regulator-always-on;
 709                         };
 710
 711                         ldoa3: ldo3 {
 712                                 regulator-name = "vds_dll_0v8";
 713                                 regulator-min-microvolt = <800000>;
 714                                 regulator-max-microvolt = <800000>;
 715                                 regulator-boot-on;
 716                                 regulator-always-on;
 717                         };
 718
 719                         ldoa4: ldo4 {
 720                                 regulator-name = "vda_mcu_1v8";
 721                                 regulator-min-microvolt = <1800000>;
 722                                 regulator-max-microvolt = <1800000>;
 723                                 regulator-boot-on;
 724                                 regulator-always-on;
 725                         };
 726                 };
 727         };
 728 };
 729
 730 &wkup_gpio0 {
 731         status = "okay";
 732         pinctrl-names = "default";
 733         pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
 734 };
 735
 736 &mcu_uart0 {
 737         bootph-all;
 738         status = "okay";
 739         pinctrl-names = "default";
 740         pinctrl-0 = <&mcu_uart0_pins_default>;
 741 };
 742
 743 &mcu_i2c0 {
 744         status = "okay";
 745         pinctrl-names = "default";
 746         pinctrl-0 = <&mcu_i2c0_pins_default>;
 747         clock-frequency = <400000>;
 748 };
 749
 750 &main_uart8 {
 751         bootph-all;
 752         status = "okay";
 753         pinctrl-names = "default";
 754         pinctrl-0 = <&main_uart8_pins_default>;
 755 };
 756
 757 &main_i2c0 {
 758         status = "okay";
 759         pinctrl-names = "default";
 760         pinctrl-0 = <&main_i2c0_pins_default>;
 761         clock-frequency = <400000>;
 762
 763         exp1: gpio@21 {
 764                 compatible = "ti,tca6416";
 765                 reg = <0x21>;
 766                 gpio-controller;
 767                 #gpio-cells = <2>;
 768                 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
 769                                 "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#",
 770                                 "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz",
 771                                 "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz",
 772                                 "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#",
 773                                 "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2";
 774         };
 775 };
 776
 777 &main_sdhci0 {
 778         bootph-all;
 779         /* eMMC */
 780         status = "okay";
 781         non-removable;
 782         ti,driver-strength-ohm = <50>;
 783         disable-wp;
 784 };
 785
 786 &main_sdhci1 {
 787         bootph-all;
 788         /* SD card */
 789         status = "okay";
 790         pinctrl-0 = <&main_mmc1_pins_default>;
 791         pinctrl-names = "default";
 792         disable-wp;
 793         vmmc-supply = <&vdd_mmc1>;
 794         vqmmc-supply = <&vdd_sd_dv>;
 795 };
 796
 797 &main_gpio0 {
 798         status = "okay";
 799         pinctrl-names = "default";
 800         pinctrl-0 = <&rpi_header_gpio0_pins_default>;
 801 };
 802
 803 &mcu_cpsw {
 804         status = "okay";
 805         pinctrl-names = "default";
 806         pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 807 };
 808
 809 &davinci_mdio {
 810         mcu_phy0: ethernet-phy@0 {
 811                 reg = <0>;
 812                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 813                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 814                 ti,min-output-impedance;
 815         };
 816 };
 817
 818 &mcu_cpsw_port1 {
 819         status = "okay";
 820         phy-mode = "rgmii-rxid";
 821         phy-handle = <&mcu_phy0>;
 822 };
 823
 824 &mcu_r5fss0_core0 {
 825         mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 826         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 827                         <&mcu_r5fss0_core0_memory_region>;
 828 };
 829
 830 &mcu_r5fss0_core1 {
 831         mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 832         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 833                         <&mcu_r5fss0_core1_memory_region>;
 834 };
 835
 836 &main_r5fss0_core0 {
 837         mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 838         memory-region = <&main_r5fss0_core0_dma_memory_region>,
 839                         <&main_r5fss0_core0_memory_region>;
 840 };
 841
 842 &main_r5fss0_core1 {
 843         mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 844         memory-region = <&main_r5fss0_core1_dma_memory_region>,
 845                         <&main_r5fss0_core1_memory_region>;
 846 };
 847
 848 &main_r5fss1_core0 {
 849         mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
 850         memory-region = <&main_r5fss1_core0_dma_memory_region>,
 851                         <&main_r5fss1_core0_memory_region>;
 852 };
 853
 854 &main_r5fss1_core1 {
 855         mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
 856         memory-region = <&main_r5fss1_core1_dma_memory_region>,
 857                         <&main_r5fss1_core1_memory_region>;
 858 };
 859
 860 &main_r5fss2_core0 {
 861         mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core0>;
 862         memory-region = <&main_r5fss2_core0_dma_memory_region>,
 863                         <&main_r5fss2_core0_memory_region>;
 864 };
 865
 866 &main_r5fss2_core1 {
 867         mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core1>;
 868         memory-region = <&main_r5fss2_core1_dma_memory_region>,
 869                         <&main_r5fss2_core1_memory_region>;
 870 };
 871
 872 &c71_0 {
 873         status = "okay";
 874         mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
 875         memory-region = <&c71_0_dma_memory_region>,
 876                         <&c71_0_memory_region>;
 877 };
 878
 879 &c71_1 {
 880         status = "okay";
 881         mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
 882         memory-region = <&c71_1_dma_memory_region>,
 883                         <&c71_1_memory_region>;
 884 };
 885
 886 &c71_2 {
 887         status = "okay";
 888         mboxes = <&mailbox0_cluster5>, <&mbox_c71_2>;
 889         memory-region = <&c71_2_dma_memory_region>,
 890                         <&c71_2_memory_region>;
 891 };
 892
 893 &c71_3 {
 894         status = "okay";
 895         mboxes = <&mailbox0_cluster5>, <&mbox_c71_3>;
 896         memory-region = <&c71_3_dma_memory_region>,
 897                         <&c71_3_memory_region>;
 898 };
 899
 900 &wkup_gpio_intr {
 901         status = "okay";
 902 };
 903
 904 &mcu_i2c1 {
 905         status = "okay";
 906         pinctrl-names = "default";
 907         pinctrl-0 = <&mcu_i2c1_pins_default>;
 908         clock-frequency = <100000>;
 909 };
 910
 911 &serdes_refclk {
 912         status = "okay";
 913         clock-frequency = <100000000>;
 914 };
 915
 916 &dss {
 917         status = "okay";
 918         pinctrl-names = "default";
 919         pinctrl-0 = <&dss_vout0_pins_default>;
 920         assigned-clocks = <&k3_clks 218 2>,
 921                           <&k3_clks 218 5>,
 922                           <&k3_clks 218 14>,
 923                           <&k3_clks 218 18>;
 924         assigned-clock-parents = <&k3_clks 218 3>,
 925                                  <&k3_clks 218 7>,
 926                                  <&k3_clks 218 16>,
 927                                  <&k3_clks 218 22>;
 928 };
 929
 930 &serdes_wiz4 {
 931         status = "okay";
 932 };
 933
 934 &serdes4 {
 935         status = "okay";
 936         serdes4_dp_link: phy@0 {
 937                 reg = <0>;
 938                 cdns,num-lanes = <4>;
 939                 #phy-cells = <0>;
 940                 cdns,phy-type = <PHY_TYPE_DP>;
 941                 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
 942                          <&serdes_wiz4 3>, <&serdes_wiz4 4>;
 943         };
 944 };
 945
 946 &mhdp {
 947         status = "okay";
 948         pinctrl-names = "default";
 949         pinctrl-0 = <&dp0_pins_default>;
 950         phys = <&serdes4_dp_link>;
 951         phy-names = "dpphy";
 952 };
 953
 954 &dss_ports {
 955         #address-cells = <1>;
 956         #size-cells = <0>;
 957
 958         /* DP */
 959         port@0 {
 960                 reg = <0>;
 961
 962                 dpi0_out: endpoint {
 963                         remote-endpoint = <&dp0_in>;
 964                 };
 965         };
 966
 967         /* HDMI */
 968         port@1 {
 969                 reg = <1>;
 970
 971                 dpi1_out0: endpoint {
 972                         remote-endpoint = <&tfp410_in>;
 973                 };
 974         };
 975 };
 976
 977 &dp0_ports {
 978
 979         port@0 {
 980                 reg = <0>;
 981
 982                 dp0_in: endpoint {
 983                         remote-endpoint = <&dpi0_out>;
 984                 };
 985         };
 986
 987         port@4 {
 988                 reg = <4>;
 989
 990                 dp0_out: endpoint {
 991                         remote-endpoint = <&dp0_connector_in>;
 992                 };
 993         };
 994 };