arch/arm64/boot/dts/ti/k3-am69-sk.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
   4  *
   5  * Design Files: https://www.ti.com/lit/zip/SPRR466
   6  * TRM: https://www.ti.com/lit/zip/spruj52
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include "k3-j784s4.dtsi"
  14
  15 / {
  16         compatible = "ti,am69-sk", "ti,j784s4";
  17         model = "Texas Instruments AM69 SK";
  18
  19         chosen {
  20                 stdout-path = "serial2:115200n8";
  21         };
  22
  23         aliases {
  24                 serial0 = &wkup_uart0;
  25                 serial1 = &mcu_uart0;
  26                 serial2 = &main_uart8;
  27                 mmc0 = &main_sdhci0;
  28                 mmc1 = &main_sdhci1;
  29                 i2c0 = &wkup_i2c0;
  30                 i2c3 = &main_i2c0;
  31                 ethernet0 = &mcu_cpsw_port1;
  32         };
  33
  34         memory@80000000 {
  35                 device_type = "memory";
  36                 bootph-all;
  37                 /* 32G RAM */
  38                 reg = <0x00 0x80000000 0x00 0x80000000>,
  39                       <0x08 0x80000000 0x07 0x80000000>;
  40         };
  41
  42         reserved_memory: reserved-memory {
  43                 #address-cells = <2>;
  44                 #size-cells = <2>;
  45                 ranges;
  46
  47                 secure_ddr: optee@9e800000 {
  48                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  49                         no-map;
  50                 };
  51
  52                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  53                         compatible = "shared-dma-pool";
  54                         reg = <0x00 0xa0000000 0x00 0x100000>;
  55                         no-map;
  56                 };
  57
  58                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  59                         compatible = "shared-dma-pool";
  60                         reg = <0x00 0xa0100000 0x00 0xf00000>;
  61                         no-map;
  62                 };
  63
  64                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  65                         compatible = "shared-dma-pool";
  66                         reg = <0x00 0xa1000000 0x00 0x100000>;
  67                         no-map;
  68                 };
  69
  70                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  71                         compatible = "shared-dma-pool";
  72                         reg = <0x00 0xa1100000 0x00 0xf00000>;
  73                         no-map;
  74                 };
  75
  76                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
  77                         compatible = "shared-dma-pool";
  78                         reg = <0x00 0xa2000000 0x00 0x100000>;
  79                         no-map;
  80                 };
  81
  82                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
  83                         compatible = "shared-dma-pool";
  84                         reg = <0x00 0xa2100000 0x00 0xf00000>;
  85                         no-map;
  86                 };
  87
  88                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
  89                         compatible = "shared-dma-pool";
  90                         reg = <0x00 0xa3000000 0x00 0x100000>;
  91                         no-map;
  92                 };
  93
  94                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
  95                         compatible = "shared-dma-pool";
  96                         reg = <0x00 0xa3100000 0x00 0xf00000>;
  97                         no-map;
  98                 };
  99
 100                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
 101                         compatible = "shared-dma-pool";
 102                         reg = <0x00 0xa4000000 0x00 0x100000>;
 103                         no-map;
 104                 };
 105
 106                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
 107                         compatible = "shared-dma-pool";
 108                         reg = <0x00 0xa4100000 0x00 0xf00000>;
 109                         no-map;
 110                 };
 111
 112                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
 113                         compatible = "shared-dma-pool";
 114                         reg = <0x00 0xa5000000 0x00 0x100000>;
 115                         no-map;
 116                 };
 117
 118                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
 119                         compatible = "shared-dma-pool";
 120                         reg = <0x00 0xa5100000 0x00 0xf00000>;
 121                         no-map;
 122                 };
 123
 124                 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
 125                         compatible = "shared-dma-pool";
 126                         reg = <0x00 0xa6000000 0x00 0x100000>;
 127                         no-map;
 128                 };
 129
 130                 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
 131                         compatible = "shared-dma-pool";
 132                         reg = <0x00 0xa6100000 0x00 0xf00000>;
 133                         no-map;
 134                 };
 135
 136                 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
 137                         compatible = "shared-dma-pool";
 138                         reg = <0x00 0xa7000000 0x00 0x100000>;
 139                         no-map;
 140                 };
 141
 142                 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
 143                         compatible = "shared-dma-pool";
 144                         reg = <0x00 0xa7100000 0x00 0xf00000>;
 145                         no-map;
 146                 };
 147
 148                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
 149                         compatible = "shared-dma-pool";
 150                         reg = <0x00 0xa8000000 0x00 0x100000>;
 151                         no-map;
 152                 };
 153
 154                 c71_0_memory_region: c71-memory@a8100000 {
 155                         compatible = "shared-dma-pool";
 156                         reg = <0x00 0xa8100000 0x00 0xf00000>;
 157                         no-map;
 158                 };
 159
 160                 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
 161                         compatible = "shared-dma-pool";
 162                         reg = <0x00 0xa9000000 0x00 0x100000>;
 163                         no-map;
 164                 };
 165
 166                 c71_1_memory_region: c71-memory@a9100000 {
 167                         compatible = "shared-dma-pool";
 168                         reg = <0x00 0xa9100000 0x00 0xf00000>;
 169                         no-map;
 170                 };
 171
 172                 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
 173                         compatible = "shared-dma-pool";
 174                         reg = <0x00 0xaa000000 0x00 0x100000>;
 175                         no-map;
 176                 };
 177
 178                 c71_2_memory_region: c71-memory@aa100000 {
 179                         compatible = "shared-dma-pool";
 180                         reg = <0x00 0xaa100000 0x00 0xf00000>;
 181                         no-map;
 182                 };
 183
 184                 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
 185                         compatible = "shared-dma-pool";
 186                         reg = <0x00 0xab000000 0x00 0x100000>;
 187                         no-map;
 188                 };
 189
 190                 c71_3_memory_region: c71-memory@ab100000 {
 191                         compatible = "shared-dma-pool";
 192                         reg = <0x00 0xab100000 0x00 0xf00000>;
 193                         no-map;
 194                 };
 195         };
 196
 197         vusb_main: regulator-vusb-main5v0 {
 198                 /* USB MAIN INPUT 5V DC */
 199                 compatible = "regulator-fixed";
 200                 regulator-name = "vusb-main5v0";
 201                 regulator-min-microvolt = <5000000>;
 202                 regulator-max-microvolt = <5000000>;
 203                 regulator-always-on;
 204                 regulator-boot-on;
 205         };
 206
 207         vsys_5v0: regulator-vsys5v0 {
 208                 /* Output of LM61460 */
 209                 compatible = "regulator-fixed";
 210                 regulator-name = "vsys_5v0";
 211                 regulator-min-microvolt = <5000000>;
 212                 regulator-max-microvolt = <5000000>;
 213                 vin-supply = <&vusb_main>;
 214                 regulator-always-on;
 215                 regulator-boot-on;
 216         };
 217
 218         vsys_3v3: regulator-vsys3v3 {
 219                 /* Output of LM5143 */
 220                 compatible = "regulator-fixed";
 221                 regulator-name = "vsys_3v3";
 222                 regulator-min-microvolt = <3300000>;
 223                 regulator-max-microvolt = <3300000>;
 224                 vin-supply = <&vusb_main>;
 225                 regulator-always-on;
 226                 regulator-boot-on;
 227         };
 228
 229         vdd_mmc1: regulator-sd {
 230                 /* Output of TPS22918 */
 231                 compatible = "regulator-fixed";
 232                 regulator-name = "vdd_mmc1";
 233                 regulator-min-microvolt = <3300000>;
 234                 regulator-max-microvolt = <3300000>;
 235                 regulator-boot-on;
 236                 enable-active-high;
 237                 vin-supply = <&vsys_3v3>;
 238                 gpio = <&exp1 2 GPIO_ACTIVE_HIGH>;
 239         };
 240
 241         vdd_sd_dv: regulator-tlv71033 {
 242                 /* Output of TLV71033 */
 243                 compatible = "regulator-gpio";
 244                 regulator-name = "tlv71033";
 245                 pinctrl-names = "default";
 246                 pinctrl-0 = <&vdd_sd_dv_pins_default>;
 247                 regulator-min-microvolt = <1800000>;
 248                 regulator-max-microvolt = <3300000>;
 249                 regulator-boot-on;
 250                 vin-supply = <&vsys_5v0>;
 251                 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
 252                 states = <1800000 0x0>,
 253                          <3300000 0x1>;
 254         };
 255
 256         dp0_pwr_3v3: regulator-dp0-pwr {
 257                 compatible = "regulator-fixed";
 258                 regulator-name = "dp0-pwr";
 259                 regulator-min-microvolt = <3300000>;
 260                 regulator-max-microvolt = <3300000>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&dp_pwr_en_pins_default>;
 263                 gpio = <&main_gpio0 4 0>;       /* DP0_3V3 _EN */
 264                 enable-active-high;
 265         };
 266
 267         dp0: connector-dp0 {
 268                 compatible = "dp-connector";
 269                 label = "DP0";
 270                 type = "full-size";
 271                 dp-pwr-supply = <&dp0_pwr_3v3>;
 272
 273                 port {
 274                         dp0_connector_in: endpoint {
 275                                 remote-endpoint = <&dp0_out>;
 276                         };
 277                 };
 278         };
 279
 280         connector-hdmi {
 281                 compatible = "hdmi-connector";
 282                 label = "hdmi";
 283                 type = "a";
 284                 pinctrl-names = "default";
 285                 pinctrl-0 = <&hdmi_hpd_pins_default>;
 286                 ddc-i2c-bus = <&mcu_i2c1>;
 287                 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;   /* HDMI_HPD */
 288
 289                 port {
 290                         hdmi_connector_in: endpoint {
 291                                 remote-endpoint = <&tfp410_out>;
 292                         };
 293                 };
 294         };
 295
 296         bridge-dvi {
 297                 compatible = "ti,tfp410";
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&hdmi_pdn_pins_default>;
 300                 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>;     /* HDMI_PDn */
 301                 ti,deskew = <0>;
 302
 303                 ports {
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306
 307                         port@0 {
 308                                 reg = <0>;
 309
 310                                 tfp410_in: endpoint {
 311                                         remote-endpoint = <&dpi1_out0>;
 312                                         pclk-sample = <1>;
 313                                 };
 314                         };
 315
 316                         port@1 {
 317                                 reg = <1>;
 318
 319                                 tfp410_out: endpoint {
 320                                         remote-endpoint = <&hdmi_connector_in>;
 321                                 };
 322                         };
 323                 };
 324         };
 325
 326         csi_mux: mux-controller {
 327                 compatible = "gpio-mux";
 328                 #mux-state-cells = <1>;
 329                 mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
 330                 idle-state = <0>;
 331         };
 332
 333 };
 334
 335 &main_pmx0 {
 336         bootph-all;
 337         main_uart8_pins_default: main-uart8-default-pins {
 338                 bootph-all;
 339                 pinctrl-single,pins = <
 340                         J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
 341                         J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
 342                 >;
 343         };
 344
 345         main_i2c0_pins_default: main-i2c0-default-pins {
 346                 pinctrl-single,pins = <
 347                         J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
 348                         J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
 349                 >;
 350         };
 351
 352         main_i2c1_pins_default: main-i2c1-default-pins {
 353                 pinctrl-single,pins = <
 354                         J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */
 355                         J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */
 356                 >;
 357         };
 358
 359         main_mmc1_pins_default: main-mmc1-default-pins {
 360                 bootph-all;
 361                 pinctrl-single,pins = <
 362                         J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
 363                         J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
 364                         J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
 365                         J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
 366                         J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
 367                         J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
 368                         J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
 369                         J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
 370                 >;
 371         };
 372
 373         vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
 374                 pinctrl-single,pins = <
 375                         J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
 376                 >;
 377         };
 378
 379         rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
 380                 pinctrl-single,pins = <
 381                         J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
 382                         J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
 383                         J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
 384                         J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
 385                         J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
 386                         J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
 387                         J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
 388                         J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
 389                         J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
 390                         J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
 391                         J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
 392                         J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
 393                         J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
 394                         J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
 395                 >;
 396         };
 397
 398         dp0_pins_default: dp0-default-pins {
 399                 pinctrl-single,pins = <
 400                         J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */
 401                 >;
 402         };
 403
 404         dp_pwr_en_pins_default: dp-pwr-en-default-pins {
 405                 pinctrl-single,pins = <
 406                         J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */
 407                 >;
 408         };
 409
 410         dss_vout0_pins_default: dss-vout0-default-pins {
 411                 pinctrl-single,pins = <
 412                         J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */
 413                         J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */
 414                         J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */
 415                         J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */
 416                         J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */
 417                         J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */
 418                         J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */
 419                         J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */
 420                         J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */
 421                         J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */
 422                         J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */
 423                         J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */
 424                         J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */
 425                         J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */
 426                         J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */
 427                         J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */
 428                         J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */
 429                         J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */
 430                         J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */
 431                         J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */
 432                         J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */
 433                         J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */
 434                         J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */
 435                         J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */
 436                         J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */
 437                         J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */
 438                         J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */
 439                         J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */
 440                 >;
 441         };
 442
 443         hdmi_hpd_pins_default: hdmi-hpd-default-pins {
 444                 pinctrl-single,pins = <
 445                         J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
 446                 >;
 447         };
 448 };
 449
 450 &wkup_pmx2 {
 451         bootph-all;
 452         pmic_irq_pins_default: pmic-irq-default-pins {
 453                 pinctrl-single,pins = <
 454                         /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */
 455                         J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7)
 456                 >;
 457         };
 458
 459         wkup_uart0_pins_default: wkup-uart0-default-pins {
 460                 bootph-all;
 461                 pinctrl-single,pins = <
 462                         J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
 463                         J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
 464                         J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
 465                         J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
 466                 >;
 467         };
 468
 469         wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 470                 bootph-all;
 471                 pinctrl-single,pins = <
 472                         J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
 473                         J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
 474                 >;
 475         };
 476
 477         mcu_uart0_pins_default: mcu-uart0-default-pins {
 478                 bootph-all;
 479                 pinctrl-single,pins = <
 480                         J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
 481                         J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
 482                 >;
 483         };
 484
 485         mcu_i2c0_pins_default: mcu-i2c0-default-pins {
 486                 pinctrl-single,pins = <
 487                         J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */
 488                         J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */
 489                 >;
 490         };
 491
 492         mcu_cpsw_pins_default: mcu-cpsw-default-pins {
 493                 pinctrl-single,pins = <
 494                         J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
 495                         J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
 496                         J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
 497                         J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
 498                         J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
 499                         J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
 500                         J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
 501                         J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
 502                         J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
 503                         J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
 504                         J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
 505                         J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
 506                 >;
 507         };
 508
 509         mcu_mdio_pins_default: mcu-mdio-default-pins {
 510                 pinctrl-single,pins = <
 511                         J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
 512                         J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
 513                 >;
 514         };
 515
 516         mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
 517                 pinctrl-single,pins = <
 518                         J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */
 519                         J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */
 520                         J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
 521                         J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */
 522                         J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */
 523                         J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */
 524                         J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */
 525                         J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
 526                         J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
 527                 >;
 528         };
 529
 530         mcu_i2c1_pins_default: mcu-i2c1-default-pins {
 531                 pinctrl-single,pins = <
 532                         /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */
 533                         J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0)
 534                         /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */
 535                         J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0)
 536                 >;
 537         };
 538
 539         hdmi_pdn_pins_default: hdmi-pdn-default-pins {
 540                 pinctrl-single,pins = <
 541                         J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
 542                 >;
 543         };
 544 };
 545
 546 &wkup_pmx3 {
 547         mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
 548                 pinctrl-single,pins = <
 549                         J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */
 550                 >;
 551         };
 552 };
 553
 554 &mailbox0_cluster0 {
 555         status = "okay";
 556         interrupts = <436>;
 557         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 558                 ti,mbox-rx = <0 0 0>;
 559                 ti,mbox-tx = <1 0 0>;
 560         };
 561
 562         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 563                 ti,mbox-rx = <2 0 0>;
 564                 ti,mbox-tx = <3 0 0>;
 565         };
 566 };
 567
 568 &mailbox0_cluster1 {
 569         status = "okay";
 570         interrupts = <432>;
 571         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 572                 ti,mbox-rx = <0 0 0>;
 573                 ti,mbox-tx = <1 0 0>;
 574         };
 575
 576         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 577                 ti,mbox-rx = <2 0 0>;
 578                 ti,mbox-tx = <3 0 0>;
 579         };
 580 };
 581
 582 &mailbox0_cluster2 {
 583         status = "okay";
 584         interrupts = <428>;
 585         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 586                 ti,mbox-rx = <0 0 0>;
 587                 ti,mbox-tx = <1 0 0>;
 588         };
 589
 590         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 591                 ti,mbox-rx = <2 0 0>;
 592                 ti,mbox-tx = <3 0 0>;
 593         };
 594 };
 595
 596 &mailbox0_cluster3 {
 597         status = "okay";
 598         interrupts = <424>;
 599         mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
 600                 ti,mbox-rx = <0 0 0>;
 601                 ti,mbox-tx = <1 0 0>;
 602         };
 603
 604         mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
 605                 ti,mbox-rx = <2 0 0>;
 606                 ti,mbox-tx = <3 0 0>;
 607         };
 608 };
 609
 610 &mailbox0_cluster4 {
 611         status = "okay";
 612         interrupts = <420>;
 613         mbox_c71_0: mbox-c71-0 {
 614                 ti,mbox-rx = <0 0 0>;
 615                 ti,mbox-tx = <1 0 0>;
 616         };
 617
 618         mbox_c71_1: mbox-c71-1 {
 619                 ti,mbox-rx = <2 0 0>;
 620                 ti,mbox-tx = <3 0 0>;
 621         };
 622 };
 623
 624 &mailbox0_cluster5 {
 625         status = "okay";
 626         interrupts = <416>;
 627         mbox_c71_2: mbox-c71-2 {
 628                 ti,mbox-rx = <0 0 0>;
 629                 ti,mbox-tx = <1 0 0>;
 630         };
 631
 632         mbox_c71_3: mbox-c71-3 {
 633                 ti,mbox-rx = <2 0 0>;
 634                 ti,mbox-tx = <3 0 0>;
 635         };
 636 };
 637
 638 &wkup_uart0 {
 639         /* Firmware usage */
 640         status = "reserved";
 641         pinctrl-names = "default";
 642         pinctrl-0 = <&wkup_uart0_pins_default>;
 643 };
 644
 645 &wkup_i2c0 {
 646         bootph-all;
 647         status = "okay";
 648         pinctrl-names = "default";
 649         pinctrl-0 = <&wkup_i2c0_pins_default>;
 650         clock-frequency = <400000>;
 651
 652         eeprom@51 {
 653                 /* AT24C512C-MAHM-T */
 654                 compatible = "atmel,24c512";
 655                 reg = <0x51>;
 656         };
 657
 658         tps659413: pmic@48 {
 659                 compatible = "ti,tps6594-q1";
 660                 reg = <0x48>;
 661                 system-power-controller;
 662                 pinctrl-names = "default";
 663                 pinctrl-0 = <&pmic_irq_pins_default>;
 664                 interrupt-parent = <&wkup_gpio0>;
 665                 interrupts = <83 IRQ_TYPE_EDGE_FALLING>;
 666                 gpio-controller;
 667                 #gpio-cells = <2>;
 668                 ti,primary-pmic;
 669                 buck12-supply = <&vsys_3v3>;
 670                 buck3-supply = <&vsys_3v3>;
 671                 buck4-supply = <&vsys_3v3>;
 672                 buck5-supply = <&vsys_3v3>;
 673                 ldo1-supply = <&vsys_3v3>;
 674                 ldo2-supply = <&vsys_3v3>;
 675                 ldo3-supply = <&vsys_3v3>;
 676                 ldo4-supply = <&vsys_3v3>;
 677
 678                 regulators {
 679                         bucka12: buck12 {
 680                                 regulator-name = "vdd_ddr_1v1";
 681                                 regulator-min-microvolt = <1100000>;
 682                                 regulator-max-microvolt = <1100000>;
 683                                 regulator-boot-on;
 684                                 regulator-always-on;
 685                         };
 686
 687                         bucka3: buck3 {
 688                                 regulator-name = "vdd_ram_0v85";
 689                                 regulator-min-microvolt = <850000>;
 690                                 regulator-max-microvolt = <850000>;
 691                                 regulator-boot-on;
 692                                 regulator-always-on;
 693                         };
 694
 695                         bucka4: buck4 {
 696                                 regulator-name = "vdd_io_1v8";
 697                                 regulator-min-microvolt = <1800000>;
 698                                 regulator-max-microvolt = <1800000>;
 699                                 regulator-boot-on;
 700                                 regulator-always-on;
 701                         };
 702
 703                         bucka5: buck5 {
 704                                 regulator-name = "vdd_mcu_0v85";
 705                                 regulator-min-microvolt = <850000>;
 706                                 regulator-max-microvolt = <850000>;
 707                                 regulator-boot-on;
 708                                 regulator-always-on;
 709                         };
 710
 711                         ldoa1: ldo1 {
 712                                 regulator-name = "vdd_mcuio_1v8";
 713                                 regulator-min-microvolt = <1800000>;
 714                                 regulator-max-microvolt = <1800000>;
 715                                 regulator-boot-on;
 716                                 regulator-always-on;
 717                         };
 718
 719                         ldoa2: ldo2 {
 720                                 regulator-name = "vdd_mcuio_3v3";
 721                                 regulator-min-microvolt = <3300000>;
 722                                 regulator-max-microvolt = <3300000>;
 723                                 regulator-boot-on;
 724                                 regulator-always-on;
 725                         };
 726
 727                         ldoa3: ldo3 {
 728                                 regulator-name = "vds_dll_0v8";
 729                                 regulator-min-microvolt = <800000>;
 730                                 regulator-max-microvolt = <800000>;
 731                                 regulator-boot-on;
 732                                 regulator-always-on;
 733                         };
 734
 735                         ldoa4: ldo4 {
 736                                 regulator-name = "vda_mcu_1v8";
 737                                 regulator-min-microvolt = <1800000>;
 738                                 regulator-max-microvolt = <1800000>;
 739                                 regulator-boot-on;
 740                                 regulator-always-on;
 741                         };
 742                 };
 743         };
 744 };
 745
 746 &wkup_gpio0 {
 747         status = "okay";
 748         pinctrl-names = "default";
 749         pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
 750 };
 751
 752 &mcu_uart0 {
 753         bootph-all;
 754         status = "okay";
 755         pinctrl-names = "default";
 756         pinctrl-0 = <&mcu_uart0_pins_default>;
 757 };
 758
 759 &mcu_i2c0 {
 760         status = "okay";
 761         pinctrl-names = "default";
 762         pinctrl-0 = <&mcu_i2c0_pins_default>;
 763         clock-frequency = <400000>;
 764 };
 765
 766 &main_uart8 {
 767         bootph-all;
 768         status = "okay";
 769         pinctrl-names = "default";
 770         pinctrl-0 = <&main_uart8_pins_default>;
 771 };
 772
 773 &main_i2c0 {
 774         status = "okay";
 775         pinctrl-names = "default";
 776         pinctrl-0 = <&main_i2c0_pins_default>;
 777         clock-frequency = <400000>;
 778
 779         exp1: gpio@21 {
 780                 compatible = "ti,tca6416";
 781                 reg = <0x21>;
 782                 gpio-controller;
 783                 #gpio-cells = <2>;
 784                 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
 785                                 "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#",
 786                                 "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz",
 787                                 "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz",
 788                                 "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#",
 789                                 "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2";
 790         };
 791 };
 792
 793 &main_i2c1 {
 794         pinctrl-names = "default";
 795         pinctrl-0 = <&main_i2c1_pins_default>;
 796         clock-frequency = <400000>;
 797         status = "okay";
 798
 799         exp2: gpio@21 {
 800                 compatible = "ti,tca6408";
 801                 reg = <0x21>;
 802                 gpio-controller;
 803                 #gpio-cells = <2>;
 804                 gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz",
 805                                   "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1";
 806         };
 807
 808         i2c-mux@70 {
 809                 compatible = "nxp,pca9543";
 810                 #address-cells = <1>;
 811                 #size-cells = <0>;
 812                 reg = <0x70>;
 813
 814                 cam0_i2c: i2c@0 {
 815                         #address-cells = <1>;
 816                         #size-cells = <0>;
 817                         reg = <0>;
 818                 };
 819
 820                 cam1_i2c: i2c@1 {
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                         reg = <1>;
 824                 };
 825
 826         };
 827 };
 828
 829 &main_sdhci0 {
 830         bootph-all;
 831         /* eMMC */
 832         status = "okay";
 833         non-removable;
 834         ti,driver-strength-ohm = <50>;
 835         disable-wp;
 836 };
 837
 838 &main_sdhci1 {
 839         bootph-all;
 840         /* SD card */
 841         status = "okay";
 842         pinctrl-0 = <&main_mmc1_pins_default>;
 843         pinctrl-names = "default";
 844         disable-wp;
 845         vmmc-supply = <&vdd_mmc1>;
 846         vqmmc-supply = <&vdd_sd_dv>;
 847 };
 848
 849 &main_gpio0 {
 850         status = "okay";
 851         pinctrl-names = "default";
 852         pinctrl-0 = <&rpi_header_gpio0_pins_default>;
 853 };
 854
 855 &mcu_cpsw {
 856         status = "okay";
 857         pinctrl-names = "default";
 858         pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 859 };
 860
 861 &davinci_mdio {
 862         mcu_phy0: ethernet-phy@0 {
 863                 reg = <0>;
 864                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 865                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 866                 ti,min-output-impedance;
 867         };
 868 };
 869
 870 &mcu_cpsw_port1 {
 871         status = "okay";
 872         phy-mode = "rgmii-rxid";
 873         phy-handle = <&mcu_phy0>;
 874 };
 875
 876 &mcu_r5fss0_core0 {
 877         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 878         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 879                         <&mcu_r5fss0_core0_memory_region>;
 880 };
 881
 882 &mcu_r5fss0_core1 {
 883         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
 884         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 885                         <&mcu_r5fss0_core1_memory_region>;
 886 };
 887
 888 &main_r5fss0_core0 {
 889         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
 890         memory-region = <&main_r5fss0_core0_dma_memory_region>,
 891                         <&main_r5fss0_core0_memory_region>;
 892 };
 893
 894 &main_r5fss0_core1 {
 895         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
 896         memory-region = <&main_r5fss0_core1_dma_memory_region>,
 897                         <&main_r5fss0_core1_memory_region>;
 898 };
 899
 900 &main_r5fss1_core0 {
 901         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
 902         memory-region = <&main_r5fss1_core0_dma_memory_region>,
 903                         <&main_r5fss1_core0_memory_region>;
 904 };
 905
 906 &main_r5fss1_core1 {
 907         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
 908         memory-region = <&main_r5fss1_core1_dma_memory_region>,
 909                         <&main_r5fss1_core1_memory_region>;
 910 };
 911
 912 &main_r5fss2_core0 {
 913         mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
 914         memory-region = <&main_r5fss2_core0_dma_memory_region>,
 915                         <&main_r5fss2_core0_memory_region>;
 916 };
 917
 918 &main_r5fss2_core1 {
 919         mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
 920         memory-region = <&main_r5fss2_core1_dma_memory_region>,
 921                         <&main_r5fss2_core1_memory_region>;
 922 };
 923
 924 &c71_0 {
 925         status = "okay";
 926         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 927         memory-region = <&c71_0_dma_memory_region>,
 928                         <&c71_0_memory_region>;
 929 };
 930
 931 &c71_1 {
 932         status = "okay";
 933         mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
 934         memory-region = <&c71_1_dma_memory_region>,
 935                         <&c71_1_memory_region>;
 936 };
 937
 938 &c71_2 {
 939         status = "okay";
 940         mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
 941         memory-region = <&c71_2_dma_memory_region>,
 942                         <&c71_2_memory_region>;
 943 };
 944
 945 &c71_3 {
 946         status = "okay";
 947         mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
 948         memory-region = <&c71_3_dma_memory_region>,
 949                         <&c71_3_memory_region>;
 950 };
 951
 952 &wkup_gpio_intr {
 953         status = "okay";
 954 };
 955
 956 &mcu_i2c1 {
 957         status = "okay";
 958         pinctrl-names = "default";
 959         pinctrl-0 = <&mcu_i2c1_pins_default>;
 960         clock-frequency = <100000>;
 961 };
 962
 963 &serdes_refclk {
 964         status = "okay";
 965         clock-frequency = <100000000>;
 966 };
 967
 968 &dss {
 969         status = "okay";
 970         pinctrl-names = "default";
 971         pinctrl-0 = <&dss_vout0_pins_default>;
 972         assigned-clocks = <&k3_clks 218 2>,
 973                           <&k3_clks 218 5>;
 974         assigned-clock-parents = <&k3_clks 218 3>,
 975                                  <&k3_clks 218 7>;
 976 };
 977
 978 &serdes_wiz4 {
 979         status = "okay";
 980 };
 981
 982 &serdes4 {
 983         status = "okay";
 984         serdes4_dp_link: phy@0 {
 985                 reg = <0>;
 986                 cdns,num-lanes = <4>;
 987                 #phy-cells = <0>;
 988                 cdns,phy-type = <PHY_TYPE_DP>;
 989                 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
 990                          <&serdes_wiz4 3>, <&serdes_wiz4 4>;
 991         };
 992 };
 993
 994 &mhdp {
 995         status = "okay";
 996         pinctrl-names = "default";
 997         pinctrl-0 = <&dp0_pins_default>;
 998         phys = <&serdes4_dp_link>;
 999         phy-names = "dpphy";
1000 };
1001
1002 &dss_ports {
1003         #address-cells = <1>;
1004         #size-cells = <0>;
1005
1006         /* DP */
1007         port@0 {
1008                 reg = <0>;
1009
1010                 dpi0_out: endpoint {
1011                         remote-endpoint = <&dp0_in>;
1012                 };
1013         };
1014
1015         /* HDMI */
1016         port@1 {
1017                 reg = <1>;
1018
1019                 dpi1_out0: endpoint {
1020                         remote-endpoint = <&tfp410_in>;
1021                 };
1022         };
1023 };
1024
1025 &dp0_ports {
1026
1027         port@0 {
1028                 reg = <0>;
1029
1030                 dp0_in: endpoint {
1031                         remote-endpoint = <&dpi0_out>;
1032                 };
1033         };
1034
1035         port@4 {
1036                 reg = <4>;
1037
1038                 dp0_out: endpoint {
1039                         remote-endpoint = <&dp0_connector_in>;
1040                 };
1041         };
1042 };