2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /memreserve/ 0x80000000 0x00080000;
49 compatible = "socionext,uniphier-ld11";
52 interrupt-parent = <&gic>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 clocks = <&sys_clk 33>;
74 enable-method = "psci";
75 operating-points-v2 = <&cluster0_opp>;
80 compatible = "arm,cortex-a53", "arm,armv8";
82 clocks = <&sys_clk 33>;
83 enable-method = "psci";
84 operating-points-v2 = <&cluster0_opp>;
88 cluster0_opp: opp_table {
89 compatible = "operating-points-v2";
93 opp-hz = /bits/ 64 <245000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <250000000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <490000000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <500000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <653334000>;
110 clock-latency-ns = <300>;
113 opp-hz = /bits/ 64 <666667000>;
114 clock-latency-ns = <300>;
117 opp-hz = /bits/ 64 <980000000>;
118 clock-latency-ns = <300>;
123 compatible = "arm,psci-1.0";
129 compatible = "fixed-clock";
131 clock-frequency = <25000000>;
136 compatible = "arm,armv8-timer";
137 interrupts = <1 13 4>,
144 compatible = "simple-bus";
145 #address-cells = <1>;
147 ranges = <0 0 0 0xffffffff>;
149 serial0: serial@54006800 {
150 compatible = "socionext,uniphier-uart";
152 reg = <0x54006800 0x40>;
153 interrupts = <0 33 4>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_uart0>;
156 clocks = <&peri_clk 0>;
159 serial1: serial@54006900 {
160 compatible = "socionext,uniphier-uart";
162 reg = <0x54006900 0x40>;
163 interrupts = <0 35 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_uart1>;
166 clocks = <&peri_clk 1>;
169 serial2: serial@54006a00 {
170 compatible = "socionext,uniphier-uart";
172 reg = <0x54006a00 0x40>;
173 interrupts = <0 37 4>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart2>;
176 clocks = <&peri_clk 2>;
179 serial3: serial@54006b00 {
180 compatible = "socionext,uniphier-uart";
182 reg = <0x54006b00 0x40>;
183 interrupts = <0 177 4>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_uart3>;
186 clocks = <&peri_clk 3>;
190 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58780000 0x80>;
193 #address-cells = <1>;
195 interrupts = <0 41 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c0>;
198 clocks = <&peri_clk 4>;
199 clock-frequency = <100000>;
203 compatible = "socionext,uniphier-fi2c";
205 reg = <0x58781000 0x80>;
206 #address-cells = <1>;
208 interrupts = <0 42 4>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_i2c1>;
211 clocks = <&peri_clk 5>;
212 clock-frequency = <100000>;
216 compatible = "socionext,uniphier-fi2c";
217 reg = <0x58782000 0x80>;
218 #address-cells = <1>;
220 interrupts = <0 43 4>;
221 clocks = <&peri_clk 6>;
222 clock-frequency = <400000>;
226 compatible = "socionext,uniphier-fi2c";
228 reg = <0x58783000 0x80>;
229 #address-cells = <1>;
231 interrupts = <0 44 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_i2c3>;
234 clocks = <&peri_clk 7>;
235 clock-frequency = <100000>;
239 compatible = "socionext,uniphier-fi2c";
241 reg = <0x58784000 0x80>;
242 #address-cells = <1>;
244 interrupts = <0 45 4>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c4>;
247 clocks = <&peri_clk 8>;
248 clock-frequency = <100000>;
252 compatible = "socionext,uniphier-fi2c";
253 reg = <0x58785000 0x80>;
254 #address-cells = <1>;
256 interrupts = <0 25 4>;
257 clocks = <&peri_clk 9>;
258 clock-frequency = <400000>;
261 system_bus: system-bus@58c00000 {
262 compatible = "socionext,uniphier-system-bus";
264 reg = <0x58c00000 0x400>;
265 #address-cells = <2>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_system_bus>;
272 compatible = "socionext,uniphier-smpctrl";
273 reg = <0x59801000 0x400>;
277 compatible = "socionext,uniphier-ld11-sdctrl",
278 "simple-mfd", "syscon";
279 reg = <0x59810000 0x400>;
282 compatible = "socionext,uniphier-ld11-sd-reset";
288 compatible = "socionext,uniphier-ld11-perictrl",
289 "simple-mfd", "syscon";
290 reg = <0x59820000 0x200>;
293 compatible = "socionext,uniphier-ld11-peri-clock";
298 compatible = "socionext,uniphier-ld11-peri-reset";
303 emmc: sdhc@5a000000 {
304 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
305 reg = <0x5a000000 0x400>;
306 interrupts = <0 78 4>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_emmc>;
309 clocks = <&sys_clk 4>;
316 compatible = "socionext,uniphier-ehci", "generic-ehci";
318 reg = <0x5a800100 0x100>;
319 interrupts = <0 243 4>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_usb0>;
322 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
323 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
328 compatible = "socionext,uniphier-ehci", "generic-ehci";
330 reg = <0x5a810100 0x100>;
331 interrupts = <0 244 4>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_usb1>;
334 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
335 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
340 compatible = "socionext,uniphier-ehci", "generic-ehci";
342 reg = <0x5a820100 0x100>;
343 interrupts = <0 245 4>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_usb2>;
346 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
347 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
352 compatible = "socionext,uniphier-ld11-mioctrl",
353 "simple-mfd", "syscon";
354 reg = <0x5b3e0000 0x800>;
357 compatible = "socionext,uniphier-ld11-mio-clock";
362 compatible = "socionext,uniphier-ld11-mio-reset";
364 resets = <&sys_rst 7>;
369 compatible = "socionext,uniphier-ld11-soc-glue",
370 "simple-mfd", "syscon";
371 reg = <0x5f800000 0x2000>;
374 compatible = "socionext,uniphier-ld11-pinctrl";
378 gic: interrupt-controller@5fe00000 {
379 compatible = "arm,gic-v3";
380 reg = <0x5fe00000 0x10000>, /* GICD */
381 <0x5fe40000 0x80000>; /* GICR */
382 interrupt-controller;
383 #interrupt-cells = <3>;
384 interrupts = <1 9 4>;
388 compatible = "socionext,uniphier-ld11-sysctrl",
389 "simple-mfd", "syscon";
390 reg = <0x61840000 0x10000>;
393 compatible = "socionext,uniphier-ld11-clock";
398 compatible = "socionext,uniphier-ld11-reset";
405 /include/ "uniphier-pinctrl.dtsi"