arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2LC SMARC EVK parts
   4  *
   5  * Copyright (C) 2022 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  10
  11 #include "rzg2lc-smarc-pinfunction.dtsi"
  12 #include "rz-smarc-common.dtsi"
  13
  14 / {
  15         aliases {
  16                 serial1 = &scif1;
  17                 i2c2 = &i2c2;
  18         };
  19
  20         osc1: cec-clock {
  21                 compatible = "fixed-clock";
  22                 #clock-cells = <0>;
  23                 clock-frequency = <12000000>;
  24         };
  25
  26         hdmi-out {
  27                 compatible = "hdmi-connector";
  28                 type = "d";
  29
  30                 port {
  31                         hdmi_con_out: endpoint {
  32                                 remote-endpoint = <&adv7535_out>;
  33                         };
  34                 };
  35         };
  36 };
  37
  38 #if (SW_SCIF_CAN || SW_RSPI_CAN)
  39 &canfd {
  40         pinctrl-0 = <&can1_pins>;
  41         /delete-node/ channel@0;
  42 };
  43 #else
  44 &canfd {
  45         /delete-property/ pinctrl-0;
  46         /delete-property/ pinctrl-names;
  47         status = "disabled";
  48 };
  49 #endif
  50
  51 &cpu_dai {
  52         sound-dai = <&ssi0>;
  53 };
  54
  55 &dsi {
  56         status = "okay";
  57
  58         ports {
  59                 port@1 {
  60                         dsi0_out: endpoint {
  61                                 data-lanes = <1 2 3 4>;
  62                                 remote-endpoint = <&adv7535_in>;
  63                         };
  64                 };
  65         };
  66 };
  67
  68 &du {
  69         status = "okay";
  70 };
  71
  72 &i2c1 {
  73         adv7535: hdmi@3d {
  74                 compatible = "adi,adv7535";
  75                 reg = <0x3d>;
  76
  77                 interrupt-parent = <&pinctrl>;
  78                 interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>;
  79                 clocks = <&osc1>;
  80                 clock-names = "cec";
  81                 avdd-supply = <&reg_1p8v>;
  82                 dvdd-supply = <&reg_1p8v>;
  83                 pvdd-supply = <&reg_1p8v>;
  84                 a2vdd-supply = <&reg_1p8v>;
  85                 v3p3-supply = <&reg_3p3v>;
  86                 v1p2-supply = <&reg_1p8v>;
  87
  88                 adi,dsi-lanes = <4>;
  89
  90                 ports {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93
  94                         port@0 {
  95                                 reg = <0>;
  96                                 adv7535_in: endpoint {
  97                                         remote-endpoint = <&dsi0_out>;
  98                                 };
  99                         };
 100
 101                         port@1 {
 102                                 reg = <1>;
 103                                 adv7535_out: endpoint {
 104                                         remote-endpoint = <&hdmi_con_out>;
 105                                 };
 106                         };
 107                 };
 108         };
 109 };
 110
 111 &i2c2 {
 112         pinctrl-0 = <&i2c2_pins>;
 113         pinctrl-names = "default";
 114         clock-frequency = <400000>;
 115
 116         status = "okay";
 117
 118         wm8978: codec@1a {
 119                 compatible = "wlf,wm8978";
 120                 #sound-dai-cells = <0>;
 121                 reg = <0x1a>;
 122         };
 123
 124         versa3: clock-generator@68 {
 125                 compatible = "renesas,5p35023";
 126                 reg = <0x68>;
 127                 #clock-cells = <1>;
 128                 clocks = <&x1>;
 129
 130                 renesas,settings = [
 131                         80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
 132                         00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
 133                         80 b0 45 c4 95
 134                 ];
 135
 136                 assigned-clocks = <&versa3 0>, <&versa3 1>,
 137                                   <&versa3 2>, <&versa3 3>,
 138                                   <&versa3 4>, <&versa3 5>;
 139                 assigned-clock-rates = <24000000>, <11289600>,
 140                                        <11289600>, <12000000>,
 141                                        <25000000>, <12288000>;
 142         };
 143 };
 144
 145 #if PMOD_MTU3
 146 &mtu3 {
 147         pinctrl-0 = <&mtu3_pins>;
 148         pinctrl-names = "default";
 149
 150         status = "okay";
 151 };
 152
 153 &spi1 {
 154         status = "disabled";
 155 };
 156 #endif
 157
 158 /*
 159  * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
 160  * SW1 should be at position 2->3 so that SER0_CTS# line is activated
 161  * SW2 should be at position 2->3 so that SER0_TX line is activated
 162  * SW3 should be at position 2->3 so that SER0_RX line is activated
 163  * SW4 should be at position 2->3 so that SER0_RTS# line is activated
 164  */
 165 #if (!SW_SCIF_CAN && PMOD1_SER0)
 166 &scif1 {
 167         pinctrl-0 = <&scif1_pins>;
 168         pinctrl-names = "default";
 169
 170         uart-has-rtscts;
 171         status = "okay";
 172 };
 173 #endif
 174
 175 &ssi0 {
 176         pinctrl-0 = <&ssi0_pins>;
 177         pinctrl-names = "default";
 178
 179         status = "okay";
 180 };
 181
 182 #if (SW_RSPI_CAN)
 183 &spi1 {
 184         /delete-property/ pinctrl-0;
 185         /delete-property/ pinctrl-names;
 186         status = "disabled";
 187 };
 188 #endif
 189
 190 &vccq_sdhi1 {
 191         gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
 192 };