arch/arm64/boot/dts/renesas/r8a77995.dtsi

   1 /*
   2  * Device Tree Source for the r8a77995 SoC
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Glider bvba
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/r8a77995-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a77995";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         psci {
  22                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  23                 method = "smc";
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 a53_0: cpu@0 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         reg = <0x0>;
  33                         device_type = "cpu";
  34                         power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
  35                         next-level-cache = <&L2_CA53>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 L2_CA53: cache-controller-1 {
  40                         compatible = "cache";
  41                         power-domains = <&sysc R8A77995_PD_CA53_SCU>;
  42                         cache-unified;
  43                         cache-level = <2>;
  44                 };
  45         };
  46
  47         extal_clk: extal {
  48                 compatible = "fixed-clock";
  49                 #clock-cells = <0>;
  50                 /* This value must be overridden by the board */
  51                 clock-frequency = <0>;
  52         };
  53
  54         /* External CAN clock - to be overridden by boards that provide it */
  55         can_clk: can {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <0>;
  59         };
  60
  61         scif_clk: scif {
  62                 compatible = "fixed-clock";
  63                 #clock-cells = <0>;
  64                 clock-frequency = <0>;
  65         };
  66
  67         soc {
  68                 compatible = "simple-bus";
  69                 interrupt-parent = <&gic>;
  70                 #address-cells = <2>;
  71                 #size-cells = <2>;
  72                 ranges;
  73
  74                 gic: interrupt-controller@f1010000 {
  75                         compatible = "arm,gic-400";
  76                         #interrupt-cells = <3>;
  77                         #address-cells = <0>;
  78                         interrupt-controller;
  79                         reg = <0x0 0xf1010000 0 0x1000>,
  80                               <0x0 0xf1020000 0 0x20000>,
  81                               <0x0 0xf1040000 0 0x20000>,
  82                               <0x0 0xf1060000 0 0x20000>;
  83                         interrupts = <GIC_PPI 9
  84                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  85                         clocks = <&cpg CPG_MOD 408>;
  86                         clock-names = "clk";
  87                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
  88                         resets = <&cpg 408>;
  89                 };
  90
  91                 timer {
  92                         compatible = "arm,armv8-timer";
  93                         interrupts = <GIC_PPI 13
  94                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  95                                      <GIC_PPI 14
  96                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  97                                      <GIC_PPI 11
  98                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  99                                      <GIC_PPI 10
 100                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 101                 };
 102
 103                 rwdt: watchdog@e6020000 {
 104                         compatible = "renesas,r8a77995-wdt",
 105                                      "renesas,rcar-gen3-wdt";
 106                         reg = <0 0xe6020000 0 0x0c>;
 107                         clocks = <&cpg CPG_MOD 402>;
 108                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 109                         resets = <&cpg 402>;
 110                         status = "disabled";
 111                 };
 112
 113                 pmu_a53 {
 114                         compatible = "arm,cortex-a53-pmu";
 115                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 116                 };
 117
 118                 ipmmu_vi0: mmu@febd0000 {
 119                         compatible = "renesas,ipmmu-r8a77995";
 120                         reg = <0 0xfebd0000 0 0x1000>;
 121                         renesas,ipmmu-main = <&ipmmu_mm 14>;
 122                         #iommu-cells = <1>;
 123                         status = "disabled";
 124                 };
 125
 126                 ipmmu_vp0: mmu@fe990000 {
 127                         compatible = "renesas,ipmmu-r8a77995";
 128                         reg = <0 0xfe990000 0 0x1000>;
 129                         renesas,ipmmu-main = <&ipmmu_mm 16>;
 130                         #iommu-cells = <1>;
 131                         status = "disabled";
 132                 };
 133
 134                 ipmmu_vc0: mmu@fe6b0000 {
 135                         compatible = "renesas,ipmmu-r8a77995";
 136                         reg = <0 0xfe6b0000 0 0x1000>;
 137                         renesas,ipmmu-main = <&ipmmu_mm 12>;
 138                         #iommu-cells = <1>;
 139                         status = "disabled";
 140                 };
 141
 142                 ipmmu_pv0: mmu@fd800000 {
 143                         compatible = "renesas,ipmmu-r8a77995";
 144                         reg = <0 0xfd800000 0 0x1000>;
 145                         renesas,ipmmu-main = <&ipmmu_mm 6>;
 146                         #iommu-cells = <1>;
 147                         status = "disabled";
 148                 };
 149
 150                 ipmmu_hc: mmu@e6570000 {
 151                         compatible = "renesas,ipmmu-r8a77995";
 152                         reg = <0 0xe6570000 0 0x1000>;
 153                         renesas,ipmmu-main = <&ipmmu_mm 2>;
 154                         #iommu-cells = <1>;
 155                         status = "disabled";
 156                 };
 157
 158                 ipmmu_rt: mmu@ffc80000 {
 159                         compatible = "renesas,ipmmu-r8a77995";
 160                         reg = <0 0xffc80000 0 0x1000>;
 161                         renesas,ipmmu-main = <&ipmmu_mm 10>;
 162                         #iommu-cells = <1>;
 163                         status = "disabled";
 164                 };
 165
 166                 ipmmu_mp: mmu@ec670000 {
 167                         compatible = "renesas,ipmmu-r8a77995";
 168                         reg = <0 0xec670000 0 0x1000>;
 169                         renesas,ipmmu-main = <&ipmmu_mm 4>;
 170                         #iommu-cells = <1>;
 171                         status = "disabled";
 172                 };
 173
 174                 ipmmu_ds0: mmu@e6740000 {
 175                         compatible = "renesas,ipmmu-r8a77995";
 176                         reg = <0 0xe6740000 0 0x1000>;
 177                         renesas,ipmmu-main = <&ipmmu_mm 0>;
 178                         #iommu-cells = <1>;
 179                         status = "disabled";
 180                 };
 181
 182                 ipmmu_ds1: mmu@e7740000 {
 183                         compatible = "renesas,ipmmu-r8a77995";
 184                         reg = <0 0xe7740000 0 0x1000>;
 185                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 186                         #iommu-cells = <1>;
 187                         status = "disabled";
 188                 };
 189
 190                 ipmmu_mm: mmu@e67b0000 {
 191                         compatible = "renesas,ipmmu-r8a77995";
 192                         reg = <0 0xe67b0000 0 0x1000>;
 193                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 195                         #iommu-cells = <1>;
 196                         status = "disabled";
 197                 };
 198
 199
 200                 cpg: clock-controller@e6150000 {
 201                         compatible = "renesas,r8a77995-cpg-mssr";
 202                         reg = <0 0xe6150000 0 0x1000>;
 203                         clocks = <&extal_clk>;
 204                         clock-names = "extal";
 205                         #clock-cells = <2>;
 206                         #power-domain-cells = <0>;
 207                         #reset-cells = <1>;
 208                 };
 209
 210                 rst: reset-controller@e6160000 {
 211                         compatible = "renesas,r8a77995-rst";
 212                         reg = <0 0xe6160000 0 0x0200>;
 213                 };
 214
 215                 pfc: pin-controller@e6060000 {
 216                         compatible = "renesas,pfc-r8a77995";
 217                         reg = <0 0xe6060000 0 0x508>;
 218                 };
 219
 220                 prr: chipid@fff00044 {
 221                         compatible = "renesas,prr";
 222                         reg = <0 0xfff00044 0 4>;
 223                 };
 224
 225                 sysc: system-controller@e6180000 {
 226                         compatible = "renesas,r8a77995-sysc";
 227                         reg = <0 0xe6180000 0 0x0400>;
 228                         #power-domain-cells = <1>;
 229                 };
 230
 231                 intc_ex: interrupt-controller@e61c0000 {
 232                         compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
 233                         #interrupt-cells = <2>;
 234                         interrupt-controller;
 235                         reg = <0 0xe61c0000 0 0x200>;
 236                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 237                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 238                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 239                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 240                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 241                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&cpg CPG_MOD 407>;
 243                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 244                         resets = <&cpg 407>;
 245                 };
 246
 247                 dmac0: dma-controller@e6700000 {
 248                         compatible = "renesas,dmac-r8a77995",
 249                                      "renesas,rcar-dmac";
 250                         reg = <0 0xe6700000 0 0x10000>;
 251                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
 252                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 253                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 254                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 255                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 256                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 257                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 258                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 259                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 260                         interrupt-names = "error",
 261                                         "ch0", "ch1", "ch2", "ch3",
 262                                         "ch4", "ch5", "ch6", "ch7";
 263                         clocks = <&cpg CPG_MOD 219>;
 264                         clock-names = "fck";
 265                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 266                         resets = <&cpg 219>;
 267                         #dma-cells = <1>;
 268                         dma-channels = <8>;
 269                 };
 270
 271                 dmac1: dma-controller@e7300000 {
 272                         compatible = "renesas,dmac-r8a77995",
 273                                      "renesas,rcar-dmac";
 274                         reg = <0 0xe7300000 0 0x10000>;
 275                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 276                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 277                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 278                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 279                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 280                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 281                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 282                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 283                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 284                         interrupt-names = "error",
 285                                         "ch0", "ch1", "ch2", "ch3",
 286                                         "ch4", "ch5", "ch6", "ch7";
 287                         clocks = <&cpg CPG_MOD 218>;
 288                         clock-names = "fck";
 289                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 290                         resets = <&cpg 218>;
 291                         #dma-cells = <1>;
 292                         dma-channels = <8>;
 293                 };
 294
 295                 dmac2: dma-controller@e7310000 {
 296                         compatible = "renesas,dmac-r8a77995",
 297                                      "renesas,rcar-dmac";
 298                         reg = <0 0xe7310000 0 0x10000>;
 299                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
 300                                       GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
 301                                       GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
 302                                       GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
 303                                       GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
 304                                       GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
 305                                       GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
 306                                       GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
 307                                       GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
 308                         interrupt-names = "error",
 309                                         "ch0", "ch1", "ch2", "ch3",
 310                                         "ch4", "ch5", "ch6", "ch7";
 311                         clocks = <&cpg CPG_MOD 217>;
 312                         clock-names = "fck";
 313                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 314                         resets = <&cpg 217>;
 315                         #dma-cells = <1>;
 316                         dma-channels = <8>;
 317                 };
 318
 319                 gpio0: gpio@e6050000 {
 320                         compatible = "renesas,gpio-r8a77995",
 321                                      "renesas,rcar-gen3-gpio",
 322                                      "renesas,gpio-rcar";
 323                         reg = <0 0xe6050000 0 0x50>;
 324                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 325                         #gpio-cells = <2>;
 326                         gpio-controller;
 327                         gpio-ranges = <&pfc 0 0 9>;
 328                         #interrupt-cells = <2>;
 329                         interrupt-controller;
 330                         clocks = <&cpg CPG_MOD 912>;
 331                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 332                         resets = <&cpg 912>;
 333                 };
 334
 335                 gpio1: gpio@e6051000 {
 336                         compatible = "renesas,gpio-r8a77995",
 337                                      "renesas,rcar-gen3-gpio",
 338                                      "renesas,gpio-rcar";
 339                         reg = <0 0xe6051000 0 0x50>;
 340                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 341                         #gpio-cells = <2>;
 342                         gpio-controller;
 343                         gpio-ranges = <&pfc 0 32 32>;
 344                         #interrupt-cells = <2>;
 345                         interrupt-controller;
 346                         clocks = <&cpg CPG_MOD 911>;
 347                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 348                         resets = <&cpg 911>;
 349                 };
 350
 351                 gpio2: gpio@e6052000 {
 352                         compatible = "renesas,gpio-r8a77995",
 353                                      "renesas,rcar-gen3-gpio",
 354                                      "renesas,gpio-rcar";
 355                         reg = <0 0xe6052000 0 0x50>;
 356                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 357                         #gpio-cells = <2>;
 358                         gpio-controller;
 359                         gpio-ranges = <&pfc 0 64 32>;
 360                         #interrupt-cells = <2>;
 361                         interrupt-controller;
 362                         clocks = <&cpg CPG_MOD 910>;
 363                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 364                         resets = <&cpg 910>;
 365                 };
 366
 367                 gpio3: gpio@e6053000 {
 368                         compatible = "renesas,gpio-r8a77995",
 369                                      "renesas,rcar-gen3-gpio",
 370                                      "renesas,gpio-rcar";
 371                         reg = <0 0xe6053000 0 0x50>;
 372                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 373                         #gpio-cells = <2>;
 374                         gpio-controller;
 375                         gpio-ranges = <&pfc 0 96 10>;
 376                         #interrupt-cells = <2>;
 377                         interrupt-controller;
 378                         clocks = <&cpg CPG_MOD 909>;
 379                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 380                         resets = <&cpg 909>;
 381                 };
 382
 383                 gpio4: gpio@e6054000 {
 384                         compatible = "renesas,gpio-r8a77995",
 385                                      "renesas,rcar-gen3-gpio",
 386                                      "renesas,gpio-rcar";
 387                         reg = <0 0xe6054000 0 0x50>;
 388                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 389                         #gpio-cells = <2>;
 390                         gpio-controller;
 391                         gpio-ranges = <&pfc 0 128 32>;
 392                         #interrupt-cells = <2>;
 393                         interrupt-controller;
 394                         clocks = <&cpg CPG_MOD 908>;
 395                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 396                         resets = <&cpg 908>;
 397                 };
 398
 399                 gpio5: gpio@e6055000 {
 400                         compatible = "renesas,gpio-r8a77995",
 401                                      "renesas,rcar-gen3-gpio",
 402                                      "renesas,gpio-rcar";
 403                         reg = <0 0xe6055000 0 0x50>;
 404                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 405                         #gpio-cells = <2>;
 406                         gpio-controller;
 407                         gpio-ranges = <&pfc 0 160 21>;
 408                         #interrupt-cells = <2>;
 409                         interrupt-controller;
 410                         clocks = <&cpg CPG_MOD 907>;
 411                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 412                         resets = <&cpg 907>;
 413                 };
 414
 415                 gpio6: gpio@e6055400 {
 416                         compatible = "renesas,gpio-r8a77995",
 417                                      "renesas,rcar-gen3-gpio",
 418                                      "renesas,gpio-rcar";
 419                         reg = <0 0xe6055400 0 0x50>;
 420                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 421                         #gpio-cells = <2>;
 422                         gpio-controller;
 423                         gpio-ranges = <&pfc 0 192 14>;
 424                         #interrupt-cells = <2>;
 425                         interrupt-controller;
 426                         clocks = <&cpg CPG_MOD 906>;
 427                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 428                         resets = <&cpg 906>;
 429                 };
 430
 431                 can0: can@e6c30000 {
 432                         compatible = "renesas,can-r8a77995",
 433                                      "renesas,rcar-gen3-can";
 434                         reg = <0 0xe6c30000 0 0x1000>;
 435                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&cpg CPG_MOD 916>,
 437                                <&cpg CPG_CORE R8A77995_CLK_CANFD>,
 438                                <&can_clk>;
 439                         clock-names = "clkp1", "clkp2", "can_clk";
 440                         assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
 441                         assigned-clock-rates = <40000000>;
 442                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 443                         resets = <&cpg 916>;
 444                         status = "disabled";
 445                 };
 446
 447                 can1: can@e6c38000 {
 448                         compatible = "renesas,can-r8a77995",
 449                                      "renesas,rcar-gen3-can";
 450                         reg = <0 0xe6c38000 0 0x1000>;
 451                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 452                         clocks = <&cpg CPG_MOD 915>,
 453                                <&cpg CPG_CORE R8A77995_CLK_CANFD>,
 454                                <&can_clk>;
 455                         clock-names = "clkp1", "clkp2", "can_clk";
 456                         assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
 457                         assigned-clock-rates = <40000000>;
 458                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 459                         resets = <&cpg 915>;
 460                         status = "disabled";
 461                 };
 462
 463                 canfd: can@e66c0000 {
 464                         compatible = "renesas,r8a77995-canfd",
 465                                      "renesas,rcar-gen3-canfd";
 466                         reg = <0 0xe66c0000 0 0x8000>;
 467                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 468                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 469                         clocks = <&cpg CPG_MOD 914>,
 470                                <&cpg CPG_CORE R8A77995_CLK_CANFD>,
 471                                <&can_clk>;
 472                         clock-names = "fck", "canfd", "can_clk";
 473                         assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
 474                         assigned-clock-rates = <40000000>;
 475                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 476                         resets = <&cpg 914>;
 477                         status = "disabled";
 478
 479                         channel0 {
 480                                 status = "disabled";
 481                         };
 482
 483                         channel1 {
 484                                 status = "disabled";
 485                         };
 486                 };
 487
 488                 avb: ethernet@e6800000 {
 489                         compatible = "renesas,etheravb-r8a77995",
 490                                      "renesas,etheravb-rcar-gen3";
 491                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 492                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 493                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 494                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 495                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 497                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 498                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 499                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 500                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 501                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 502                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 503                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 504                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 506                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 507                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 508                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 509                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 510                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 511                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 512                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 513                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 514                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 515                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 516                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 517                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 518                                           "ch4", "ch5", "ch6", "ch7",
 519                                           "ch8", "ch9", "ch10", "ch11",
 520                                           "ch12", "ch13", "ch14", "ch15",
 521                                           "ch16", "ch17", "ch18", "ch19",
 522                                           "ch20", "ch21", "ch22", "ch23",
 523                                           "ch24";
 524                         clocks = <&cpg CPG_MOD 812>;
 525                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 526                         resets = <&cpg 812>;
 527                         phy-mode = "rgmii-txid";
 528                         iommus = <&ipmmu_ds0 16>;
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         status = "disabled";
 532                 };
 533
 534                 scif2: serial@e6e88000 {
 535                         compatible = "renesas,scif-r8a77995",
 536                                      "renesas,rcar-gen3-scif", "renesas,scif";
 537                         reg = <0 0xe6e88000 0 64>;
 538                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&cpg CPG_MOD 310>,
 540                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 541                                  <&scif_clk>;
 542                         clock-names = "fck", "brg_int", "scif_clk";
 543                         dmas = <&dmac1 0x13>, <&dmac1 0x12>,
 544                                <&dmac2 0x13>, <&dmac2 0x12>;
 545                         dma-names = "tx", "rx", "tx", "rx";
 546                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 547                         resets = <&cpg 310>;
 548                         status = "disabled";
 549                 };
 550
 551                 pwm0: pwm@e6e30000 {
 552                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 553                         reg = <0 0xe6e30000 0 0x8>;
 554                         #pwm-cells = <2>;
 555                         clocks = <&cpg CPG_MOD 523>;
 556                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 557                         resets = <&cpg 523>;
 558                         status = "disabled";
 559                 };
 560
 561                 pwm1: pwm@e6e31000 {
 562                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 563                         reg = <0 0xe6e31000 0 0x8>;
 564                         #pwm-cells = <2>;
 565                         clocks = <&cpg CPG_MOD 523>;
 566                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 567                         resets = <&cpg 523>;
 568                         status = "disabled";
 569                 };
 570
 571                 pwm2: pwm@e6e32000 {
 572                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 573                         reg = <0 0xe6e32000 0 0x8>;
 574                         #pwm-cells = <2>;
 575                         clocks = <&cpg CPG_MOD 523>;
 576                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 577                         resets = <&cpg 523>;
 578                         status = "disabled";
 579                 };
 580
 581                 pwm3: pwm@e6e33000 {
 582                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 583                         reg = <0 0xe6e33000 0 0x8>;
 584                         #pwm-cells = <2>;
 585                         clocks = <&cpg CPG_MOD 523>;
 586                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 587                         resets = <&cpg 523>;
 588                         status = "disabled";
 589                 };
 590
 591                 sdhi2: sd@ee140000 {
 592                         compatible = "renesas,sdhi-r8a77995",
 593                                      "renesas,rcar-gen3-sdhi";
 594                         reg = <0 0xee140000 0 0x2000>;
 595                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 596                         clocks = <&cpg CPG_MOD 312>;
 597                         max-frequency = <200000000>;
 598                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 599                         resets = <&cpg 312>;
 600                         status = "disabled";
 601                 };
 602
 603                 ehci0: usb@ee080100 {
 604                         compatible = "generic-ehci";
 605                         reg = <0 0xee080100 0 0x100>;
 606                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 607                         clocks = <&cpg CPG_MOD 703>;
 608                         phys = <&usb2_phy0>;
 609                         phy-names = "usb";
 610                         companion = <&ohci0>;
 611                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 612                         resets = <&cpg 703>;
 613                         status = "disabled";
 614                 };
 615
 616                 ohci0: usb@ee080000 {
 617                         compatible = "generic-ohci";
 618                         reg = <0 0xee080000 0 0x100>;
 619                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 620                         clocks = <&cpg CPG_MOD 703>;
 621                         phys = <&usb2_phy0>;
 622                         phy-names = "usb";
 623                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 624                         resets = <&cpg 703>;
 625                         status = "disabled";
 626                 };
 627
 628                 usb2_phy0: usb-phy@ee080200 {
 629                         compatible = "renesas,usb2-phy-r8a77995",
 630                                      "renesas,rcar-gen3-usb2-phy";
 631                         reg = <0 0xee080200 0 0x700>;
 632                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 633                         clocks = <&cpg CPG_MOD 703>;
 634                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 635                         resets = <&cpg 703>;
 636                         #phy-cells = <0>;
 637                         status = "disabled";
 638                 };
 639         };
 640 };